ADA4932-1_09 [ADI]
Low Power Differential ADC Driver; 低功耗差分ADC驱动器
| 型号： | ADA4932-1_09 |
| 厂家： | 
ADI |
| 描述： | Low Power Differential ADC Driver |
| 文件： | 总28页 (文件大小：477K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power
Differential ADC Driver
ADA4932-1/ADA4932-2
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
High performance at low power
High speed
−3 dB bandwidth of 560 MHz, G = 1
0.1 dB gain flatness to 300 MHz
Slew rate: 2800 V/μs, 25% to 75%
Fast 0.1% settling time of 9 ns
Low power: 9.6 mA per amplifier
Low harmonic distortion
ADA4932-1
12 PD
–FB
+IN
–IN
1
2
3
4
11 –OUT
10 +OUT
+FB
9
V
OCM
100 dB SFDR @ 10 MHz
90 dB SFDR @ 20 MHz
Figure 1. ADA4932-1
Low input voltage noise: 3.6 nV/√Hz
0.5 mV typical input offset voltage
Externally adjustable gain
Can be used with fractional differential gains
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Input common-mode range shifted down by 1 VBE
Wide supply range: +3 V to 5 V
Available in 16-lead and 24-lead LFCSP packages
–IN1
+FB1
1
18 +OUT1
17 V
2
3
4
5
6
OCM1
16 –V
+V
S2
S2
S1
ADA4932-2
–V
15
14
+V
S1
–FB2
+IN2
PD2
13 –OUT2
APPLICATIONS
ADC drivers
Figure 2. ADA4932-2
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
–40
–50
V
= 2V p-p
OUT, dm
HD2, G = 1
HD3, G = 1
HD2, G = 2
HD3, G = 2
–60
Line drivers
–70
GENERAL DESCRIPTION
–80
The ADA4932-x is the next generation AD8132 with higher
performance, and lower noise and power consumption. It is an
ideal choice for driving high performance ADCs as a single-ended-
to-differential or differential-to-differential amplifier. The output
common-mode voltage is user adjustable by means of an internal
common-mode feedback loop, allowing the ADA4932-x output
to match the input of the ADC. The internal feedback loop also
provides exceptional output balance as well as suppression of
even-order harmonic distortion products.
–90
–100
–110
–120
–130
–140
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 3. Harmonic Distortion vs. Frequency at Various Gains
With the ADA4932-x, differential gain configurations are easily
realized with a simple external four-resistor feedback network that
determines the closed-loop gain of the amplifier.
The ADA4932-x is available in a Pb-free, 3 mm × 3 mm 16-lead
LFCSP (ADA4932-1, single) or a Pb-free, 4 mm × 4 mm 24-lead
LFCSP (ADA4932-2, dual). The pinout has been optimized to
facilitate PCB layout and minimize distortion. The ADA4932-1
and the ADA4932-2 are specified to operate over the −40°C to
+105°C temperature range; both operate on supplies between
+3 V and 5 V.
The ADA4932-x is fabricated using the Analog Devices, Inc.,
proprietary silicon-germanium (SiGe) complementary bipolar
process, enabling it to achieve low levels of distortion and noise
at low power consumption. The low offset and excellent dynamic
performance of the ADA4932-x make it well suited for a wide
variety of data acquisition and signal processing applications.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.
ADA4932-1/ADA4932-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of ꢀperation ...................................................................... 19
Applications Information.............................................................. 20
Analyzing an Application Circuit ............................................ 20
Setting the Closed-Loop Gain .................................................. 20
Estimating the ꢀutput Noise Voltage...................................... 20
Impact of Mismatches in the Feedback Networks................. 21
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V ꢀperation............................................................................. 3
5 V ꢀperation ............................................................................... 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
Maximum Power Dissipation ..................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Circuits..................................................................................... 17
Terminology .................................................................................... 18
Calculating the Input Impedance for an Application
Circuit .......................................................................................... 21
Input Common-Mode Voltage Range..................................... 23
Input and ꢀutput Capacitive AC Coupling............................ 23
Setting the ꢀutput Common-Mode Voltage.......................... 23
Layout, Grounding, and Bypassing.............................................. 24
High Performance ADC Driving ................................................. 25
ꢀutline Dimensions....................................................................... 26
ꢀrdering Guide .......................................................................... 26
REVISION HISTORY
8/09—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Figure 11........................................................................ 9
Changes to Figure 43 and Figure 45............................................. 15
Changes to Figure 52, Figure 53, and Figure 54 ......................... 17
10/08—Revision 0: Initial Version
Rev. A | Page 2 of 28
ADA4932-1/ADA4932-2
SPECIFICATIONS
5 V OPERATION
TA = 25°C, +VS = 5 V, −VS = −5 V, VꢀCM = 0 V, RF = 499 Ω, RG = 499 Ω, RT = 53.6 Ω (when used), RL, dm = 1 kꢁ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 55 for signal definitions.
±±IN to VOUT, dm Performance
Table 1.
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
VOUT, dm = 0.1 V p-p
VOUT, dm = 0.1 V p-p, RF = RG = 205 Ω
VOUT, dm = 2.0 V p-p
560
1000
360
360
300
100
2800
9
MHz
MHz
MHz
MHz
MHz
MHz
V/μs
ns
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
VOUT, dm = 2.0 V p-p, RF = RG = 205 Ω
VOUT, dm = 2.0 V p-p, ADA4932-1, RL = 200 Ω
VOUT, dm = 2.0 V p-p, ADA4932-2, RL = 200 Ω
VOUT, dm = 2 V p-p, 25% to 75%
VOUT, dm = 2 V step
VIN = 0 V to 5 V ramp, G = 2
See Figure 54 for distortion test circuit
VOUT, dm = 2 V p-p, 1 MHz
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 20 MHz
VOUT, dm = 2 V p-p, 50 MHz
VOUT, dm = 2 V p-p, 1 MHz
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 20 MHz
VOUT, dm = 2 V p-p, 50 MHz
f1 = 30 MHz, f2 = 30.1 MHz, VOUT, dm = 2 V p-p
f = 1 MHz
Slew Rate
Settling Time to 0.1%
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
20
ns
−110
−100
−90
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−72
Third Harmonic
−130
−120
−105
−80
−91
3.6
IMD
Voltage Noise (RTI)
Input Current Noise
Crosstalk
nV/√Hz
pA/√Hz
dB
f = 1 MHz
f = 10 MHz, ADA4932-2
1.0
−100
INPUT CHARACTERISTICS
Offset Voltage
V+DIN = V−DIN = VOCM = 0 V
TMIN to TMAX variation
−2.2
−5.2
−0.2
0.5
−3.7
−2.5
−9.5
+2.2 mV
μV/°C
−0.1 μA
nA/°C
+0.2 μA
Input Bias Current
TMIN to TMAX variation
Input Offset Current
Input Resistance
0.025
Differential
Common mode
11
16
0.5
−VS + 0.2 to
+VS − 1.8
MΩ
MΩ
pF
V
Input Capacitance
Input Common-Mode Voltage Range
CMRR
Open-Loop Gain
∆VOUT, dm/∆VIN, cm, ∆VIN, cm = 1 V
−100
66
−87 dB
64
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Maximum ∆VOUT, single-ended output,
RF = RG = 10 kΩ, RL = 1 kΩ
−VS + 1.4 to
+VS − 1.4
−VS + 1.2 to
+VS − 1.2
V
Linear Output Current
Output Balance Error
200 kHz, RL, dm = 10 Ω, SFDR = 68 dB
∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 2 V p-p, 1 MHz,
see Figure 53 for output balance test circuit
80
−64
mA rms
−60 dB
Rev. A | Page 3 of 28
ADA4932-1/ADA4932-2
VOCM to VOUT, cm Performance
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
VOUT, cm = 100 mV p-p
VOUT, cm = 2 V p-p
VIN = 1.5 V to 3.5 V, 25% to 75%
f = 1 MHz
270
105
410
9.6
MHz
MHz
V/μs
nV/√Hz
−VS + 1.2 to +VS − 1.2
25
1
−100
0.998
V
22
−5.1
29
kΩ
mV
dB
V/V
Input Offset Voltage
VOCM CMRR
Gain
V+DIN = V−DIN = 0 V
ΔVOUT, dm/ΔVOCM, ΔVOCM = 1 V
ΔVOUT, cm/ΔVOCM, ΔVOCM = 1 V
+5.1
−86
1.000
0.995
General Performance
Table 3.
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
3.0
9.0
11
10.1
V
9.6
35
0.9
−96
mA
μA/°C
mA
dB
TMIN to TMAX variation
Powered down
ΔVOUT, dm/ΔVS, ΔVS = 1 V p-p
1.0
−84
Power Supply Rejection Ratio
POWER-DOWN (PD)
PD Input Voltage
Powered down
Enabled
≤(+VS − 2.5)
≥(+VS − 1.8)
1100
V
V
ns
ns
Turn-Off Time
Turn-On Time
16
PD Pin Bias Current per Amplifier
Enabled
PD = 5 V
PD = 0 V
−10
+0.7
+10
μA
μA
°C
Disabled
−240
−40
−195
−140
+105
OPERATING TEMPERATURE RANGE
Rev. A | Page 4 of 28
ADA4932-1/ADA4932-2
5 V OPERATION
TA = 25°C, +VS = 5 V, −VS = 0 V, VꢀCM = 2.5 V, RF = 499 Ω, RG = 499 Ω, RT = 53.6 Ω (when used), RL, dm = 1 kꢁ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 55 for signal definitions.
±±IN to VOUT, dm Performance
Table 4.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
VOUT, dm = 0.1 V p-p
VOUT, dm = 0.1 V p-p, RF = RG = 205 Ω
VOUT, dm = 2.0 V p-p
560
990
315
320
120
200
2200
10
MHz
MHz
MHz
MHz
MHz
MHz
V/μs
ns
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
VOUT, dm = 2.0 V p-p, RF = RG = 205 Ω
VOUT, dm = 2.0 V p-p, ADA4932-1, RL = 200 Ω
VOUT, dm = 2.0 V p-p, ADA4932-2, RL = 200 Ω
VOUT, dm = 2 V p-p, 25% to 75%
VOUT, dm = 2 V step
VIN = 0 V to 2.5 V ramp, G = 2
See Figure 54 for distortion test circuit
VOUT, dm = 2 V p-p, 1 MHz
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 20 MHz
VOUT, dm = 2 V p-p, 50 MHz
VOUT, dm = 2 V p-p, 1 MHz
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 20 MHz
VOUT, dm = 2 V p-p, 50 MHz
f1 = 30 MHz, f2 = 30.1 MHz, VOUT, dm = 2 V p-p
f = 1 MHz
Slew Rate
Settling Time to 0.1%
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
20
ns
−110
−100
−90
−72
−120
−100
−87
−70
−91
3.6
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Third Harmonic
IMD
dBc
Voltage Noise (RTI)
Input Current Noise
Crosstalk
nV/√Hz
pA/√Hz
dB
f = 1 MHz
f = 10 MHz, ADA4932-2
1.0
−100
INPUT CHARACTERISTICS
Offset Voltage
V+DIN = V−DIN = VOCM = 2.5 V
TMIN to TMAX variation
−2.2
−5.3
−0.25
0.5
−3.7
−3.0
−9.5
+2.2
mV
μV/°C
Input Bias Current
−0.23 μA
nA/°C
+0.25 μA
TMIN to TMAX variation
Input Offset Current
Input Resistance
0.025
Differential
Common mode
11
16
0.5
−VS + 0.2 to
+VS − 1.8
MΩ
MΩ
pF
V
Input Capacitance
Input Common-Mode Voltage Range
CMRR
Open-Loop Gain
∆VOUT, dm/∆VIN, cm, ∆VIN, cm = 1 V
−100
66
−87
−60
dB
dB
64
OUTPUT CHARACTERISTICS
Output Voltage Swing
Maximum ∆VOUT, single-ended output,
RF = RG = 10 kΩ, RL = 1 kΩ
200 kHz, RL, dm = 10 Ω, SFDR = 67 dB
∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V p-p, 1 MHz,
see Figure 53 for output balance test circuit
−VS + 1.15 to
+VS − 1.15
−VS + 1.02 to
+VS − 1.02
53
V
Linear Output Current
Output Balance Error
mA rms
dB
−64
Rev. A | Page 5 of 28
ADA4932-1/ADA4932-2
VOCM to VOUT, cm Performance
Table 5.
Parameter
Conditions
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
VOUT, cm = 100 mV p-p
VOUT, cm = 2 V p-p
VIN = 1.5 V to 3.5 V, 25% to 75%
f = 1 MHz
260
90
360
9.6
MHz
MHz
V/μs
nV/√Hz
−VS + 1.2 to +VS − 1.2
25
−3.0
−100
0.998
V
22
−6.5
29
kΩ
mV
dB
V/V
Input Offset Voltage
VOCM CMRR
Gain
V+DIN = V−DIN = 2.5 V
ΔVOUT, dm/ΔVOCM, ΔVOCM = 1 V
ΔVOUT, cm/ΔVOCM, ΔVOCM = 1 V
+6.5
−86
1.000
0.995
General Performance
Table 6.
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
3.0
8.2
11
9.5
V
8.8
35
0.7
−96
mA
μA/°C
mA
dB
TMIN to TMAX variation
Powered down
ΔVOUT, dm/ΔVS, ΔVS = 1 V p-p
0.8
−84
Power Supply Rejection Ratio
POWER-DOWN (PD)
PD Input Voltage
Powered down
Enabled
≤(+VS − 2.5)
≥(+VS − 1.8)
1100
V
V
ns
ns
Turn-Off Time
Turn-On Time
16
PD Pin Bias Current per Amplifier
Enabled
PD = 5 V
PD = 0 V
−10
+0.7
−70
+10
μA
μA
°C
Disabled
−100
−40
−40
OPERATING TEMPERATURE RANGE
+105
Rev. A | Page 6 of 28
ADA4932-1/ADA4932-2
ABSOLUTE MAXIMUM RATINGS
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Table 7.
Parameter
Rating
Supply Voltage
11 V
Power Dissipation
See Figure 4
5 mA
Input Current, +IN, −IN, PD
Storage Temperature Range
Operating Temperature Range
ADA4932-1
ADA4932-2
Lead Temperature (Soldering, 10 sec)
Junction Temperature
−65°C to +125°C
−40°C to +105°C
−40°C to +105°C
300°C
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads/
exposed pad from metal traces, through holes, ground, and power
planes reduces θJA.
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the single 16-lead
LFCSP (91°C/W) and the dual 24-lead LFCSP (65°C/W) on a
JEDEC standard 4-layer board with the exposed pad soldered to
a PCB pad that is connected to a solid plane.
3.5
THERMAL RESISTANCE
3.0
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p circuit board, as described
in EIA/JESD 51-7.
2.5
ADA4932-2
2.0
Table 8. Thermal Resistance
Package Type
1.5
θJA
91
65
Unit
°C/W
°C/W
ADA4932-1
ADA4932-1, 16-Lead LFCSP (Exposed Pad)
ADA4932-2, 24-Lead LFCSP (Exposed Pad)
1.0
0.5
0
MAXIMUM POWER DISSIPATION
–40
–20
0
20
40
60
80
100
The maximum safe power dissipation in the ADA4932-x
AMBIENT TEMPERATURE (°C)
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4932-x. Exceeding a
junction temperature of 150°C for an extended period can result
in changes in the silicon devices, potentially causing failure.
Figure 4. Maximum Power Dissipation vs. Ambient Temperature for
a 4-Layer Board
ESD CAUTION
Rev. A | Page 7 of 28
ADA4932-1/ADA4932-2
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
–IN1
+FB1
1
2
3
4
5
6
18
17 V
16 –V
15
14
+OUT1
PIN 1
OCM1
INDICATOR
12 PD
–FB
+IN
–IN
1
2
3
4
+V
ADA4932-2
TOP VIEW
(Not to Scale)
S2
S2
S1
–V
+V
S1
–FB2
+IN2
11 –OUT
10 +OUT
ADA4932-1
TOP VIEW
(Not to Scale)
PD2
13 –OUT2
+FB
9 V
OCM
NOTES
NOTES
1. SOLDER EXPOSED PADDLE ON BACK OF PACKAGE
TO GROUND PLANE OR TO A POWER PLANE.
1. SOLDER EXPOSED PADDLE ON BACK OF PACKAGE
TO GROUND PLANE OR TO A POWER PLANE.
Figure 5. ADA4932-1 Pin Configuration
Figure 6. ADA4932-2 Pin Configuration
Table 9. ADA4932-1 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
−FB
+IN
Negative Output for Feedback Component Connection.
Positive Input Summing Node.
3
−IN
Negative Input Summing Node.
4
+FB
+VS
Positive Output for Feedback Component Connection.
Positive Supply Voltage.
5 to 8
9
VOCM
Output Common-Mode Voltage.
10
11
12
+OUT
−OUT
PD
Positive Output for Load Connection.
Negative Output for Load Connection.
Power-Down Pin.
13 to 16
17 (EPAD)
−VS
Negative Supply Voltage.
Solder the exposed paddle on the back of the package to a ground plane or to a power plane.
Exposed Paddle (EPAD)
Table 10. ADA4932-2 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3, 4
−IN1
+FB1
+VS1
Negative Input Summing Node 1.
Positive Output Feedback 1.
Positive Supply Voltage 1.
5
6
7
8
9, 10
11
12
13
14
−FB2
+IN2
−IN2
+FB2
+VS2
VOCM2
+OUT2
−OUT2
PD2
Negative Output Feedback 2.
Positive Input Summing Node 2.
Negative Input Summing Node 2.
Positive Output Feedback 2.
Positive Supply Voltage 2.
Output Common-Mode Voltage 2.
Positive Output 2.
Negative Output 2.
Power-Down Pin 2.
15, 16
17
18
19
20
−VS2
VOCM1
+OUT1
−OUT1
PD1
Negative Supply Voltage 2.
Output Common-Mode Voltage 1.
Positive Output 1.
Negative Output 1.
Power-Down Pin 1.
21, 22
23
24
−VS1
−FB1
+IN1
Negative Supply Voltage 1.
Negative Output Feedback 1.
Positive Input Summing Node 1.
Solder the exposed paddle on the back of the package to a ground plane or to a power plane.
25 (EPAD)
Exposed Paddle (EPAD)
Rev. A | Page 8 of 28
ADA4932-1/ADA4932-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, −VS = −5 V, VꢀCM = 0 V, RG = 499 Ω, RF = 499 Ω, RT = 53.6 ꢁ (when used), RL, dm = 1 kꢁ, unless otherwise noted.
Refer to Figure 52 for test setup. Refer to Figure 55 for signal definitions.
2
2
V
R
R
= 100mV p-p
= 499Ω
= 499Ω, 249Ω
V
R
R
= 2V p-p
= 499Ω
= 499Ω, 249Ω
IN
GAIN = 1
GAIN = 2
IN
GAIN = 1
GAIN = 2
1
1
F
F
G
G
0
0
–1
–2
–3
–4
–5
–6
–7
–8
–1
–2
–3
–4
–5
–6
–7
–8
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. Small Signal Frequency Response for Various Gains
Figure 10. Large Signal Frequency Response for Various Gains
2
2
V
= 100mV p-p
V = 2V p-p
OUT, dm
OUT, dm
R
R
= R = 499Ω
F
F
G
R
= R = 499Ω
G
F
1
0
1
0
= R = 205Ω
G
–1
–2
–3
–4
–5
–6
–7
–8
R = R = 205Ω
F G
–1
–2
–3
–4
–5
–6
–7
–8
1M
10M
100M
FREQUENCY (Hz)
1G
10G
1
10
100
1k
FREQUENCY (MHz)
Figure 11. Large Signal Frequency Response for Various RF and RG
Figure 8. Small Signal Frequency Response for Various RF and RG
2
2
V
= 100mV p-p
V
= 2V p-p
OUT, dm
OUT, dm
1
0
1
0
V
V
= ±5V
= ±2.5V
V
V
= ±5V
= ±2.5V
S
S
S
S
–1
–2
–3
–4
–5
–6
–7
–8
–1
–2
–3
–4
–5
–6
–7
–8
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 9. Small Signal Frequency Response for Various Supplies
Figure 12. Large Signal Frequency Response for Various Supplies
Rev. A | Page 9 of 28
ADA4932-1/ADA4932-2
2
2
1
V
= 100mV p-p
V
= 2V p-p
OUT, dm
OUT, dm
1
0
0
–1
–2
–3
–4
–5
–6
–7
–8
–1
–2
–3
–4
–5
–6
–7
–8
T
T
T
= –40°C
= +25°C
= +105°C
T
T
T
= –40°C
= +25°C
= +105°C
A
A
A
A
A
A
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. Small Signal Frequency Response for Various Temperatures
Figure 16. Large Signal Frequency Response for Various Temperatures
2
2
V
= 100mV p-p
V
= 2V p-p
OUT, dm
OUT, dm
R
R
= 1kΩ
= 200Ω
R
R
= 1kΩ
= 200Ω
L
L
L
L
1
0
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–1
–2
–3
–4
–5
–6
–7
–8
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14. Small Signal Frequency Response at Various Loads
Figure 17. Large Signal Frequency Response at Various Loads
2
2
V
= 100mV p-p
V
= 2V p-p
OUT, dm
OUT, dm
1
0
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–1
–2
–3
–4
–5
–6
–7
–8
V
V
V
= 0V
V
V
V
= 0V
OCM
OCM
OCM
OCM
OCM
OCM
= +2.5V
= –2.5V
= +2.5V
= –2.5V
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15. Small Signal Frequency Response for Various VOCM Levels
Figure 18. Large Signal Frequency Response for Various VOCM Levels
Rev. A | Page 10 of 28
ADA4932-1/ADA4932-2
4
2
4
2
V
= 100mV p-p
V
= 2V p-p
OUT, dm
OUT, dm
C
C
C
= 0pF
= 0.9pF
= 1.8pF
L
L
L
0
0
C
= 0pF
L
C
C
= 0.9pF
= 1.8pF
–2
–4
–6
–8
–10
L
L
–2
–4
–6
–8
10M
100M
1G
1M
10M
100M
FREQUENCY (Hz)
1G
10G
FREQUENCY (Hz)
Figure 19. Small Signal Frequency Response at Various Capacitive Loads
Figure 22. Large Signal Frequency Response at Various Capacitive Loads
0.5
0.5
V
= 100mV p-p
V
= 2V p-p
OUT, dm
OUT, dm
0.4
0.3
0.4
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
ADA4932-1, R = 1kΩ
L
ADA4932-1, R = 1kΩ
L
ADA4932-1, R = 200Ω
L
ADA4932-1, R = 200Ω
L
ADA4932-2, CH 1, R = 1kΩ
L
ADA4932-2, CH 1, R = 1kΩ
L
ADA4932-2, CH 1, R = 200Ω
L
ADA4932-2, CH 1, R = 200Ω
L
ADA4932-2, CH 2, R = 1kΩ
L
ADA4932-2, CH 2, R = 1kΩ
L
ADA4932-2, CH 2, R = 200Ω
L
ADA4932-2, CH 2, R = 200Ω
L
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20. 0.1 dB Flatness Small Signal Frequency Response for Various Loads
Figure 23. 0.1 dB Flatness Large Signal Frequency Response for Various Loads
2
2
V
= 2V p-p
V
= 100mV p-p
OUT, cm
OUT, cm
1
0
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–1
–2
–3
–4
–5
–6
–7
–8
V
V
V
(DC) = 0V
OCM
OCM
OCM
(DC) = +2.5V
(DC) = –2.5V
V
V
V
(DC) = 0V
OCM
OCM
OCM
(DC) = +2.5V
(DC) = –2.5V
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 24. VOCM Large Signal Frequency Response at Various DC Levels
Figure 21. VOCM Small Signal Frequency Response at Various DC Levels
Rev. A | Page 11 of 28
ADA4932-1/ADA4932-2
–40
–40
–50
V
= 2V p-p
V
= 2V p-p
OUT, dm
OUT, dm
–50
–60
HD2, R = 1kΩ
HD2, G = 1
HD3, G = 1
HD2, G = 2
HD3, G = 2
L
HD3, R = 1kΩ
–60
L
HD2, R = 200Ω
L
–70
–70
HD3, R = 200Ω
L
–80
–80
–90
–90
–100
–110
–120
–130
–140
–100
–110
–120
–130
–140
100k
1M
10M
FREQUENCY (Hz)
100M
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 25. Harmonic Distortion vs. Frequency at Various Loads
Figure 28. Harmonic Distortion vs. Frequency at Various Gains
–40
–40
V
V
= 2V p-p
= 0V
V
= 0V
OUT, dm
OCM
–50
–60
–50
–60
OCM
HD2, ±5.0V
HD3, ±5.0V
HD2, ±2.5V
HD3, ±2.5V
HD2, ±5.0V
HD3, ±5.0V
HD2, ±2.5V
HD3, ±2.5V
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–100
–110
–120
–130
–140
100k
1M
10M
FREQUENCY (Hz)
100M
0
1
2
3
4
5
6
7
8
9
10
V
(V p-p)
OUT, dm
Figure 26. Harmonic Distortion vs. Frequency at Various Supplies
Figure 29. Harmonic Distortion vs. VOUT, dm and Supply Voltage, f = 10 MHz
–30
–20
V
= 2V p-p
V
= 2V p-p
OUT
OUT
–40
–50
–30
–40
HD2 AT 10MHz
HD3 AT 10MHz
HD2 AT 30MHz
HD3 AT 30MHz
HD2 AT 10MHz
HD3 AT 10MHz
HD2 AT 30MHz
HD3 AT 30MHz
–60
–50
–70
–60
–80
–70
–90
–80
–100
–110
–120
–130
–90
–100
–110
–120
–4
–3
–2
–1
0
1
2
3
4
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
V
(V p-p)
V
(V)
OCM
OCM
Figure 27. Harmonic Distortion vs. VOCM at Various Frequencies, 5 V Supplies
Figure 30. Harmonic Distortion vs. VOCM at Various Frequencies, +5 V Supply
Rev. A | Page 12 of 28
ADA4932-1/ADA4932-2
–40
–50
–40
–50
V
= 2V p-p
OUT, dm
HD2, 2V p-p
HD3, 2V p-p
HD2, 4V p-p
HD3, 4V p-p
HD2, R = R = 499Ω
F
G
–60
–60
HD3, R = R = 499Ω
F G
HD2, R = R = 200Ω
F
G
–70
–70
HD3, R = R = 200Ω
F
G
–80
–80
–90
–90
–100
–110
–120
–130
–140
–100
–110
–120
–130
–140
100k
1M
10M
FREQUENCY (Hz)
100M
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 31. Harmonic Distortion vs. Frequency at Various VOUT, dm
Figure 34. Harmonic Distortion vs. Frequency at Various RF and RG
–40
10
V
= 2V p-p
V
= 2V p-p
OUT, dm
OUT, dm
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–50
–60
–70
–80
R
R
= 200Ω
= 1kΩ
L
–90
–100
–110
–120
–130
–140
L
100k
1M
10M
FREQUENCY (Hz)
100M
29.6 29.7 29.8 29.9 30.0 30.1 30.2 30.3 30.4 30.5
FREQUENCY (MHz)
Figure 32. Spurious-Free Dynamic Range vs. Frequency at Various Loads
Figure 35. 30 MHz Intermodulation Distortion
–20
0
R
= 200Ω
L, dm
R
= 200Ω
–30
–40
–50
–60
–70
–80
–90
–100
L, dm
–20
–40
–60
–80
–PSRR
+PSRR
–100
–120
–140
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 33. CMRR vs. Frequency
Figure 36. PSRR vs. Frequency
Rev. A | Page 13 of 28
ADA4932-1/ADA4932-2
–10
80
60
90
R
= 200Ω
L, dm
45
–20
–30
–40
–50
–60
–70
40
0
GAIN
20
–45
–90
–135
–180
–225
–270
0
PHASE
–20
–40
–60
–80
1M
10M
100M
1G
1k
10k
100k
1M
10M
100M
1G
10G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 37. Output Balance vs. Frequency
Figure 40. Open-Loop Gain and Phase vs. Frequency
0
–10
–20
–30
–40
–50
–60
100
INPUT SINGLE-ENDED, 50Ω LOAD TERMINATION
OUTPUT DIFFERENTIAL, 100Ω SOURCE TERMINATION
S11: COMMON-MODE-TO-COMMON-MODE
S22: DIFFERENTIAL-TO-DIFFERENTIAL
10
S22
R
= 200Ω
L
S11
1
0.1
1M
10M
100M
1G
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 38. Return Loss (S11, S22) vs. Frequency
Figure 41. Closed-Loop Output Impedance Magnitude vs. Frequency, G = 1
100
10
1
10
2 × V
IN
8
6
V
OUT, dm
4
2
0
–2
–4
–6
–8
–10
10
100
1k
10k
100k
1M
0
100 200 300 400 500 600 700 800 900 1000
TIME (ns)
FREQUENCY (Hz)
Figure 42.Overdrive Recovery, G = 2
Figure 39. Voltage Noise Spectral Density, Referred to Input
Rev. A | Page 14 of 28
ADA4932-1/ADA4932-2
1.5
1.0
0.06
0.04
0.02
0
0.5
0
–0.5
–1.0
–1.5
–0.02
–0.04
–0.06
0
5
10
15
20
25
30
0
5
10
15
20
25
30
TIME (ns)
TIME (ns)
Figure 43. Small Signal Pulse Response
Figure 46. Large Signal Pulse Response
0.08
0.06
0.04
0.02
0
1.5
1.0
0.5
0
C
C
C
= 0pF
= 0.9pF
= 1.8pF
–0.02
–0.04
–0.06
–0.08
L
L
L
–0.5
C
C
C
= 0pF
= 0.9pF
= 1.8pF
L
L
L
–1.0
–1.5
0
5
10
15
20
25
30
0
5
10
15
20
25
30
TIME (ns)
TIME (ns)
Figure 44. Small Signal Pulse Response for Various Capacitive Loads
Figure 47. Large Signal Pulse Response for Various Capacitive Loads
0.06
0.04
0.02
0
1.5
1.0
0.5
0
–0.02
–0.04
–0.06
–0.5
–1.0
–1.5
0
5
10
15
20
25
30
0
5
10
15
20
25
30
TIME (ns)
TIME (ns)
Figure 48. VOCM Large Signal Pulse Response
Figure 45. VOCM Small Signal Pulse Response
Rev. A | Page 15 of 28
ADA4932-1/ADA4932-2
2.0
0.5
1.2
1.0
0.8
0.6
0.4
0.2
0
6
R
= 200Ω
L, dm
1.6
0.4
PD
5
1.2
0.3
INPUT
4
0.8
0.2
0.4
0.1
3
OUTPUT
0
0
2
–0.4
–0.8
–1.2
–1.6
–2.0
ERROR
–0.1
–0.2
–0.3
–0.4
–0.5
1
V
ON
0
–0.2
–1
0
2
4
6
8
10
12
14
16
18
20
0
1
2
3
4
5
6
TIME (ns)
TIME (µs)
Figure 49. Settling Time
PD
Figure 51.
Response Time
0
V
= 2V p-p
OUT, dm
R
= 200Ω
L, dm
–20
–40
–60
–80
CHANNEL 1 TO CHANNEL 2
CHANNEL 2 TO CHANNEL 1
–100
–120
–140
–160
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 50. Crosstalk vs. Frequency, ADA4932-2
Rev. A | Page 16 of 28
ADA4932-1/ADA4932-2
TEST CIRCUITS
499Ω
+5V
DC-COUPLED
GENERATOR
50Ω
499Ω
53.6Ω
25.5Ω
V
V
IN
OCM
ADA4932-x
1kΩ
499Ω
–5V
499Ω
Figure 52. Equivalent Basic Test Circuit, G = 1
NETWORK
ANALYZER
INPUT
NETWORK
ANALYZER
OUTPUT
499Ω
+5V
49.9Ω
50Ω
AC-COUPLED
50Ω
499Ω
V
OCM
53.6Ω
ADA4932-x
V
IN
499Ω
NETWORK
ANALYZER
INPUT
25.5Ω
–5V
499Ω
49.9Ω
0.1µF
50Ω
Figure 53. Test Circuit for Output Balance, CMRR
499Ω
DC-COUPLED
GENERATOR
+5V
200Ω
50Ω
0.1µF
0.1µF
50Ω
499Ω
442Ω
HP
2:1
DUAL
FILTER
LOW-PASS
FILTER
LP
CT
V
V
IN
OCM
53.6Ω
ADA4932-x
261Ω
442Ω
499Ω
25.5Ω
–5V
499Ω
Figure 54. Test Circuit for Distortion Measurements
Rev. A | Page 17 of 28
ADA4932-1/ADA4932-2
TERMINOLOGY
–FB
Common-Mode Voltage
R
F
Common-mode voltage refers to the average of two node voltages
with respect to the local ground reference. The output common-
mode voltage is defined as
R
G
+IN
–IN
–OUT
+D
IN
V
R
V
OUT, dm
OCM
L, dm
ADA4932-x
–D
IN
V
OUT, cm = (V+OUT + V−OUT)/2
+OUT
R
G
R
F
+FB
Balance
Figure 55. Signal and Circuit Definitions
ꢀutput balance is a measure of how close the output differential
signals are to being equal in amplitude and opposite in phase.
ꢀutput balance is most easily determined by placing a well-
matched resistor divider between the differential voltage nodes
and comparing the magnitude of the signal at the divider midpoint
with the magnitude of the differential signal (see Figure 53). By
this definition, output balance is the magnitude of the output
common-mode voltage divided by the magnitude of the output
differential mode voltage.
Differential Voltage
Differential voltage refers to the difference between two
node voltages. For example, the output differential voltage (or
equivalently, output differential mode voltage) is defined as
V
OUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +ꢀUT and
−ꢀUT terminals with respect to a common ground reference.
Similarly, the differential input voltage is defined as
VOUT, cm
Output Balance Error
VOUT, dm
V
IN, dm = (+DIN − (−DIN))
Rev. A | Page 18 of 28
ADA4932-1/ADA4932-2
THEORY OF OPERATION
The ADA4932-x differs from conventional op amps in that it
has two outputs whose voltages move in opposite directions and
an additional input, VꢀCM. Like an op amp, it relies on high open-
loop gain and negative feedback to force these outputs to the
desired voltages. The ADA4932-x behaves much like a standard
voltage feedback op amp and facilitates single-ended-to-differential
conversions, common-mode level shifting, and amplifications of
differential signals. Like an op amp, the ADA4932-x has high input
impedance and low output impedance. Because it uses voltage
feedback, the ADA4932-x manifests a nominally constant gain
bandwidth product.
with external resistors, controls only the differential output voltage.
The common-mode feedback controls only the common-mode
output voltage. This architecture makes it easy to set the output
common-mode level to any arbitrary value within the specified
limits. The output common-mode voltage is forced, by the internal
common-mode feedback loop, to be equal to the voltage applied
to the VꢀCM input.
The internal common-mode feedback loop produces outputs
that are highly balanced over a wide frequency range without
requiring tightly matched external components. This results in
differential outputs that are very close to the ideal of being
identical in amplitude and are exactly 180° apart in phase.
Two feedback loops are employed to control the differential and
common-mode output voltages. The differential feedback, set
Rev. A | Page 19 of 28
ADA4932-1/ADA4932-2
APPLICATIONS INFORMATION
input, and the noise currents, inIN− and inIN+, appear between
each input and ground. The output voltage due to vnIN is obtained
by multiplying vnIN by the noise gain, GN (defined in the GN
equation that follows). The noise currents are uncorrelated with
the same mean-square value, and each produces an output voltage
that is equal to the noise current multiplied by the associated
feedback resistance. The noise voltage density at the VOCM pin is
ANALYZING AN APPLICATION CIRCUIT
The ADA4932-x uses high open-loop gain and negative feedback
to force its differential and common-mode output voltages in
such a way as to minimize the differential and common-mode
error voltages. The differential error voltage is defined as the
voltage between the differential inputs labeled +IN and −IN
(see Figure 55). For most purposes, this voltage can be assumed
to be zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to VOCM can also
be assumed to be zero. Starting from these principles, any applica-
tion circuit can be analyzed.
vnCM. When the feedback networks have the same feedback factor,
as is true in most cases, the output noise due to vnCM is common
mode. Each of the four resistors contributes (4kTRxx)1/2. The
noise from the feedback resistors appears directly at the output,
and the noise from the gain resistors appears at the output multip-
lied by RF/RG. Table 11 summarizes the input noise sources, the
multiplication factors, and the output-referred noise density terms.
SETTING THE CLOSED-LOOP GAIN
Using the approach described in the Analyzing an Application
Circuit section, the differential gain of the circuit in Figure 55
can be determined by
V
V
nRG1
nRF1
R
R
F1
G1
inIN+
VOUT, dm
+
RF
RG
V
nIN
V
nOD
inIN–
ADA4932-x
VIN, dm
V
This presumes that the input resistors (RG) and feedback resistors
(RF) on each side are equal.
OCM
V
nCM
R
R
F2
G2
V
V
nRF2
nRG2
ESTIMATING THE OUTPUT NOISE VOLTAGE
Figure 56. Noise Model
The differential output noise of the ADA4932-x can be
estimated using the noise model in Figure 56. The input-
referred noise voltage density, vnIN, is modeled as a differential
Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks
Input Noise
Voltage Density
Output
Multiplication Factor
Differential Output Noise
Voltage Density Term
Input Noise Contribution
Differential Input
Inverting Input
Noninverting Input
VOCM Input
Gain Resistor, RG1
Gain Resistor, RG2
Feedback Resistor, RF1
Feedback Resistor, RF2
Input Noise Term
vnIN
inIN−
inIN+
vnCM
vnRG1
vnRG2
vnRF1
vnRF2
vnIN
GN
1
1
0
RF1/RG1
RF2/RG2
1
1
vnO1 = GN(vnIN)
vnO2 = (inIN−)(RF2)
vnO3 = (inIN+)(RF1)
vnO4 = 0 V
vnO5 = (RF1/RG1)(4kTRG1)1/2
vnO6 = (RF2/RG2)(4kTRG2)1/2
vnO7 = (4kTRF1)1/2
vnO8 = (4kTRF2)1/2
inIN− × (RF2)
inIN+ × (RF1)
vnCM
(4kTRG1)1/2
(4kTRG2)1/2
(4kTRF1)1/2
(4kTRF2)1/2
Table 12. Differential Input, DC-Coupled
Nominal Gain (dB)
RF (Ω)
RG (Ω)
499
249
RIN, dm (Ω)
998
498
Differential Output Noise Density (nV/√Hz)
0
6
10
499
499
768
9.25
12.9
18.2
243
486
Table 13. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω
Nominal Gain (dB)
RF (Ω) RG1 (Ω) RT (Ω) (Std 1%) RIN, cm (Ω)
RG2 (Ω)1
525
276
270
Differential Output Noise Density (nV/√Hz)
0
6
10
511
523
806
499
249
243
53.6
57.6
57.6
665
374
392
9.19
12.6
17.7
1 RG2 = RG1 + (RS||RT).
Rev. A | Page 20 of 28
ADA4932-1/ADA4932-2
Similar to the case of a conventional op amp, the output noise
voltage densities can be estimated by multiplying the input-
referred terms at +IN and −IN by the appropriate output factor,
Mismatched feedback networks also result in a degradation of
the ability of the circuit to reject input common-mode signals,
much the same as for a four-resistor difference amplifier made
from a conventional op amp.
where:
2
As a practical summarization of the above issues, resistors of 1%
tolerance produce a worst-case input CMRR of approximately
40 dB, a worst-case differential-mode output offset of 25 mV
due to a 2.5 V VꢀCM input, negligible VꢀCM noise contribution,
and no significant degradation in output balance error.
GN
is the circuit noise gain.
β1 β2
RG1
RG2
β1
and β2
are the feedback factors.
RF1 RG1
RF2 RG2
When the feedback factors are matched, RF1/RG1 = RF2/RG2, β1 =
β2 = β, and the noise gain becomes
CALCULATING THE INPUT IMPEDANCE FOR AN
APPLICATION CIRCUIT
1
β
RF
RG
GN
1
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 57, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is RIN, dm = RG + RG = 2 × RG.
Note that the output noise from VꢀCM goes to zero in this case.
The total differential output noise density, vnꢀD, is the root-sum-
square of the individual output noise terms.
R
F
8
vnOD
v2
nOi
+V
S
i1
R
G
G
+IN
+D
–D
IN
Table 12 and Table 13 list several common gain settings,
associated resistor values, input impedance, and output noise
density for both balanced and unbalanced input configurations.
V
OCM
V
ADA4932-x
OUT, dm
IN
–IN
R
–V
S
IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
R
F
Figure 57. ADA4932-x Configured for Balanced (Differential) Inputs
As previously mentioned, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.
For an unbalanced, single-ended input signal (see Figure 58),
the input impedance is
RG
RF
RG RF
RIN, se
1
The gain from the VꢀCM pin to VꢀUT, dm is equal to
2
2(β1 − β2)/(β1 + β2)
R
F
When β1 = β2, this term goes to zero and there is no differential
output voltage due to the voltage on the VꢀCM input (including
noise). The extreme case occurs when one loop is open and the
other has 100% feedback; in this case, the gain from VꢀCM input
to VꢀUT, dm is either +2 or −2, depending on which loop is closed.
The feedback loops are nominally matched to within 1% in
most applications, and the output noise and offsets due to the
VꢀCM input are negligible. If the loops are intentionally mismatched
by a large amount, it is necessary to include the gain term from
VꢀCM to VꢀUT, dm and account for the extra noise. For example, if
β1 = 0.5 and β2 = 0.25, the gain from VꢀCM to VꢀUT, dm is 0.67. If
the VꢀCM pin is set to 2.5 V, a differential offset voltage is present at
the output of (2.5 V)(0.67) = 1.67 V. The differential output noise
contribution is (9.6 nV/√Hz)(0.67) = 6.4 nV/√Hz. Both of these
results are undesirable in most applications; therefore, it is best
to use nominally matched feedback factors.
+V
R
S
IN, se
R
G
V
OCM
ADA4932-x
R
V
OUT, dm
L
R
G
–V
S
R
F
Figure 58. ADA4932-x with Unbalanced (Single-Ended) Input
The input impedance of the circuit is effectively higher than it is
for a conventional op amp connected as an inverter because a
fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor, RG. The common-mode voltage at the
amplifier input terminals can be easily determined by noting that
the voltage at the inverting input is equal to the noninverting
output voltage divided down by the voltage divider that is formed
by RF and RG in the lower loop. This voltage is present at both
Rev. A | Page 21 of 28
ADA4932-1/ADA4932-2
input terminals due to negative voltage feedback and is in phase
with the input signal, thus reducing the effective voltage across
RG in the upper loop and partially bootstrapping RG.
3. Figure 60 shows that the effective RG in the upper feedback
loop is now greater than the RG in the lower loop due to the
addition of the termination resistors. To compensate for the
imbalance of the gain resistors, add a correction resistor (RTS)
in series with RG in the lower loop. RTS is the Thevenin
equivalent of the source resistance, RS, and the termination
resistance, RT, and is equal to RS||RT.
Terminating a Single-Ended Input
This section describes how to properly terminate a single-ended
input to the ADA4932-x with a gain of 1, RF = 499 ꢁ, and RG =
499 ꢁ. An example using an input source with a terminated output
voltage of 1 V p-p and source resistance of 50 ꢁ illustrates the four
steps that must be followed. Note that because the terminated
output voltage of the source is 1 V p-p, the open-circuit output
voltage of the source is 2 V p-p. The source shown in Figure 59
indicates this open-circuit voltage.
R
R
S
TH
50Ω
R
53.6Ω
25.9Ω
T
V
V
S
TH
1.03V p-p
2V p-p
Figure 61. Calculating the Thevenin Equivalent
1. The input impedance is calculated using the formula
RTS = RTH = RS||RT = 25.9 ꢁ. Note that VTH is greater than
1 V p-p, which was obtained with RT = 50 ꢁ. The modified
circuit with the Thevenin equivalent (closest 1% value used for
RTH) of the terminated source and RTS in the lower feedback
loop is shown in Figure 62.
RG
RF
2(RG RF )
499
499
2( 499 499)
R
IN,se
665Ω
1
1
R
F
499Ω
+V
S
R
F
R
R
499Ω
+V
TH
G
R
665Ω
IN, se
S
25.5Ω
499Ω
V
TH
1.03V p-p
V
OCM
V
OUT, dm
R
ADA4932-x
R
R
L
S
G
R
50Ω
499Ω
G
V
S
V
499Ω
OCM
R
25.5Ω
ADA4932-x
R
V
OUT, dm
2V p-p
TS
L
R
G
–V
S
499Ω
R
F
499Ω
–V
S
Figure 62. Thevenin Equivalent and Matched Gain Resistors
R
F
499Ω
Figure 62 presents a tractable circuit with matched
feedback loops that can be easily evaluated.
Figure 59. Calculating Single-Ended Input Impedance, RIN
2. To match the 50 ꢁ source resistance, calculate the
termination resistor, RT, using RT||665 ꢁ = 50 ꢁ. The
closest standard 1% value for RT is 53.6 ꢁ.
It is useful to point out two effects that occur with a termi-
nated input. The first is that the value of RG is increased in
both loops, lowering the overall closed-loop gain. The
second is that VTH is a little larger than 1 V p-p, as it would
be if RT = 50 ꢁ. These two effects have opposite impacts on
the output voltage, and for large resistor values in the feedback
loops (~1 kꢁ), the effects essentially cancel each other out.
For small RF and RG, or high gains, however, the diminished
closed-loop gain is not canceled completely by the increased
VTH. This can be seen by evaluating Figure 62.
R
F
499Ω
+V
R
IN, se
50Ω
S
R
R
S
G
50Ω
499Ω
R
53.6Ω
T
V
S
V
OCM
ADA4932-x
R
V
OUT, dm
2V p-p
L
R
G
499Ω
The desired differential output in this example is 1 V p-p
because the terminated input signal was 1 V p-p and the
closed-loop gain = 1. The actual differential output voltage,
however, is equal to (1.03 V p-p)(499/524.5) = 0.98 V p-p.
To obtain the desired output voltage of 1 V p-p, a final gain
adjustment can be made by increasing RF without modifying
any of the input circuitry. This is discussed in Step 4.
–V
S
R
F
499Ω
Figure 60. Adding Termination Resistor, RT
Rev. A | Page 22 of 28
ADA4932-1/ADA4932-2
4. The feedback resistor value is modified as a final gain
adjustment to obtain the desired output voltage.
INPUT AND OUTPUT CAPACITIVE AC COUPLING
While the ADA4932-x is best suited to dc-coupled applications,
it is nonetheless possible to use it in ac-coupled circuits. Input
ac coupling capacitors can be inserted between the source and
RG. This ac coupling blocks the flow of the dc common-mode
feedback current and causes the ADA4932-x dc input common-
mode voltage to equal the dc output common-mode voltage.
These ac coupling capacitors must be placed in both loops to keep
the feedback factors matched. ꢀutput ac coupling capacitors can
be placed in series between each output and its respective load.
To make the output voltage VꢀUT = 1 V p-p, calculate RF
using the following formula:
RF
Desired VOUT,dm
RG RTS
509
1V p p 524.5
VTH
1.03 V p p
The closest standard 1% value to 509 ꢁ is 511 ꢁ, which
gives a differential output voltage of 1.00 V p-p.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VꢀCM pin of the ADA4932-x is internally biased with a vol-
tage divider comprised of two 50 kꢁ resistors across the supplies,
with a tap at a voltage approximately equal to the midsupply
point, [(+VS) + (−VS)]/2. Because of this internal divider, the
The final circuit is shown in Figure 63.
R
F
511Ω
+V
1V p-p
S
V
ꢀCM pin sources and sinks current, depending on the externally
R
R
S
G
applied voltage and its associated source resistance. Relying on
the internal bias results in an output common-mode voltage
that is within about 100 mV of the expected value.
50Ω
499Ω
R
53.6Ω
T
V
S
V
OUT, dm
1.00V p-p
V
OCM
ADA4932-x
R
2V p-p
L
R
G
499Ω
R
TS
25.5Ω
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external
source or resistor divider be used with source resistance less
than 100 ꢁ. If an external voltage divider consisting of equal
resistor values is used to set VꢀCM to midsupply with greater
accuracy than produced internally, higher values can be used
because the external resistors are placed in parallel with the
internal resistors. The output common-mode offset listed in the
Specifications section assumes that the VꢀCM input is driven by a
low impedance voltage source.
–V
S
R
F
511Ω
Figure 63. Terminated Single-Ended-to-Differential System with G = 2
INPUT COMMON-MODE VOLTAGE RANGE
The ADA4932-x input common-mode range is shifted down
by approximately one VBE, in contrast to other ADC drivers
with centered input ranges such as the ADA4939-x. The
downward-shifted input common-mode range is especially
suited to dc-coupled, single-ended-to-differential, and single-
supply applications.
It is also possible to connect the VꢀCM input to a common-mode
level (CML) output of an ADC; however, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VꢀCM pin is approximately 10 kꢁ. If multiple
ADA4932-x devices share one ADC reference output, a buffer
may be necessary to drive the parallel inputs.
For 5 V operation, the input common-mode range at the
summing nodes of the amplifier is specified as −4.8 V to +3.2 V,
and is specified as +0.2 V to +3.2 V with a +5 V supply. To
avoid nonlinearities, the voltage swing at the +IN and −IN
terminals must be confined to these ranges.
Rev. A | Page 23 of 28
ADA4932-1/ADA4932-2
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4932-x is sensitive to the
PCB environment in which it operates. Realizing its superior
performance requires attention to the details of high speed
PCB design.
Bypass the power supply pins as close to the device as possible
and directly to a nearby ground plane. High frequency ceramic
chip capacitors should be used. It is recommended that two
parallel bypass capacitors (1000 pF and 0.1 μF) be used for each
supply. Place the 1000 pF capacitor closer to the device. Further
away, provide low frequency bulk bypassing using 10 μF tantalum
capacitors from each supply to ground.
The first requirement is a solid ground plane that covers as much
of the board area around the ADA4932-x as possible. However,
the area near the feedback resistors (RF), gain resistors (RG), and
the input summing nodes (Pin 2 and Pin 3) should be cleared of
all ground and power planes (see Figure 64). Clearing the ground
and power planes minimizes any stray capacitance at these nodes
and thus minimizes peaking of the response of the amplifier at
high frequencies.
Signal routing should be short and direct to avoid parasitic effects.
Wherever complementary signals exist, provide a symmetrical
layout to maximize balanced performance. When routing
differential signals over a long distance, keep PCB traces close
together, and twist any differential wiring to minimize loop
area. Doing this reduces radiated energy and makes the circuit
less susceptible to interference.
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity 4-layer
circuit board, as described in EIA/JESD51-7.
1.30
0.80
1.30 0.80
Figure 64. Ground and Power Plane Voiding in Vicinity of RF and RG
Figure 65. Recommended PCB Thermal Attach Pad Dimensions (Millimeters)
1.30
TOP METAL
GROUND PLANE
0.30
PLATED
VIA HOLE
POWER PLANE
BOTTOM METAL
Figure 66. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters)
Rev. A | Page 24 of 28
ADA4932-1/ADA4932-2
HIGH PERFORMANCE ADC DRIVING
The ADA4932-x is ideally suited for broadband dc-coupled
applications. The circuit in Figure 67 shows a front-end
connection for an ADA4932-1 driving an AD9245, a 14-bit,
20 MSPS/40 MSPS/65 MSPS/80 MSPS ADC, with dc coupling
on the ADA4932-1 input and output. (The AD9245 achieves
its optimum performance when driven differentially.) The
ADA4932-1 eliminates the need for a transformer to drive the
ADC and performs a single-ended-to-differential conversion and
buffering of the driving signal.
In this example, the signal generator has a 1 V p-p symmetric,
ground-referenced bipolar output when terminated in 50 ꢁ.
The VꢀCM input is bypassed for noise reduction, and set externally
with 1% resistors to maximize output dynamic range on the
tight 3.3 V supply.
Because the inputs are dc-coupled, dc common-mode current
flows in the feedback loops, and a nominal dc level of 0.84 V is
present at the amplifier input terminals. A fraction of the output
signal is also present at the input terminals as a common-mode
signal; its level is equal to the ac output swing at the noninverting
output, divided down by the feedback factor of the lower loop.
In this example, this ripple is 0.5 V p-p × [524.5/(524.5 + 511)] =
0.25 V p-p. This ac signal is riding on the 0.84 V dc level, produc-
ing a voltage swing between 0.72 V and 0.97 V at the input
terminals. This is well within the specified limits of 0.2 V to 1.5 V.
The ADA4932-1 is configured with a single 3.3 V supply and a
gain of 1 for a single-ended input to differential output. The
53.6 ꢁ termination resistor, in parallel with the single-ended
input impedance of approximately 665 ꢁ, provides a 50 ꢁ
termination for the source. The additional 25.5 ꢁ (524.5 ꢁ
total) at the inverting input balances the parallel impedance
of the 50 ꢁ source and the termination resistor driving the
noninverting input.
With an output common-mode voltage of 1.65 V, each ADA4932-1
output swings between 1.4 V and 1.9 V, opposite in phase, provid-
ing a gain of 1 and a 1 V p-p differential signal to the ADC input.
The differential RC section between the ADA4932-1 output and
the ADC provides single-pole low-pass filtering and extra buffering
for the current spikes that are output from the ADC input when its
SHA capacitors are discharged.
The AD9245 is configured for a 1 V p-p full-scale input by
connecting its SENSE pin to VREF, as shown in Figure 67.
511Ω
3.3V
V
V
= 1V p-p
= 1.65V
OUT, dm
OUT, cm
1V p-p CENTERED
AT GROUND
0.1µF
0.1µF
10kΩ
1%
499Ω
50Ω
33Ω
VIN–
AVDD
V
53.6Ω
OCM
20pF
2V p-p
AD9245
ADA4932-1
10kΩ
1%
SIGNAL
GENERATOR
0.1µF
499Ω
VIN+ VREF SENSE AGND
33Ω
25.5Ω
+
0.1µF
10µF
511Ω
Figure 67. ADA4932-1 Driving an AD9245 ADC with DC-Coupled Input and Output
Rev. A | Page 25 of 28
ADA4932-1/ADA4932-2
OUTLINE DIMENSIONS
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.45
1.30 SQ
1.15
13
16
1
0.45
(BOTTOM VIEW)
12
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PAD
4
9
0.50
BSC
8
5
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 68. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad (CP-16-2)
Dimensions shown in millimeters
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
24
19
18
PIN 1
INDICATOR
0.50
BSC
2.25
TOP
VIEW
3.75
BSC SQ
EXPOSED
2.10 SQ
1.95
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
6
13
12
7
0.25 MIN
0.80 MAX
0.65TYP
2.50 REF
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.30
0.23
0.18
0.20 REF
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 69. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad (CP-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Package Option
CP-16-2
CP-16-2
Ordering Quantity
Branding
H1K
H1K
ADA4932-1YCPZ-R21
ADA4932-1YCPZ-RL1
ADA4932-1YCPZ-R71
ADA4932-2YCPZ-R21
ADA4932-2YCPZ-RL1
ADA4932-2YCPZ-R71
250
5,000
1,500
250
5,000
1,500
CP-16-2
H1K
CP-24-1
CP-24-1
CP-24-1
1 Z = RoHS Compliant Part.
Rev. A | Page 26 of 28
ADA4932-1/ADA4932-2
NOTES
Rev. A | Page 27 of 28
ADA4932-1/ADA4932-2
NOTES
©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07752-0-8/09(A)
Rev. A | Page 28 of 28
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