ADA4930-1YCPZ-R7 [ADI]
Ultralow Noise Drivers for Low Voltage ADCs; 对于低电压ADC的超低噪声驱动器
| 型号： | ADA4930-1YCPZ-R7 |
| 厂家： | 
ADI |
| 描述： | Ultralow Noise Drivers for Low Voltage ADCs |
| 文件： | 总28页 (文件大小：563K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Noise
Drivers for Low Voltage ADCs
ADA4930-1/ADA4930-2
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Low input voltage noise: 1.2 nV/√Hz
Low common-mode output: 0.9 V on single supply
Extremely low harmonic distortion
−104 dBc HD2 at 10 MHz
−79 dBc HD2 at 70 MHz
−73 dBc HD2 at 100 MHz
ADA4930-1
12 PD
–FB
+IN
–IN
1
2
3
4
11 –OUT
10 +OUT
+FB
9 V
OCM
−101 dBc HD3 at 10 MHz
−82 dBc HD3 at 70 MHz
−75 dBc HD3 at 100 MHz
High speed
Figure 1.
ADA4930-2
Figure 2.
−3 dB bandwidth of 1.35 GHz, G = 1
Slew rate: 3400 V/μs, 25% to 75%
0.1 dB gain flatness to 380 MHz
Fast overdrive recovery of 1.5 ns
0.5 mV typical offset voltage
Externally adjustable gain
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Single-supply operation: 3.3 V or 5 V
–IN1
+FB1
1
18 +OUT1
17 V
2
3
4
5
6
OCM1
16 –V
+V
S2
S2
S1
–V
15
14
+V
S1
–FB2
+IN2
PD2
13 –OUT2
100
APPLICATIONS
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
10
Line drivers
1
GENERAL DESCRIPTION
The ADA4930-1/ADA4930-2 are very low noise, low distortion,
high speed differential amplifiers. They are an ideal choice for
driving 1.8 V high performance ADCs with resolutions up to
14 bits from dc to 70 MHz. The adjustable output common
mode allows the ADA4930-1/ADA4930-2 to match the input of
the ADC. The internal common-mode feedback loop provides
exceptional output balance, suppression of even-order harmonic
distortion products, and dc level translation.
0
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 3. Voltage Noise Spectral Density
The low dc offset and excellent dynamic performance of the
ADA4930-1/ADA4930-2 make them well suited for a wide
variety of data acquisition and signal processing applications.
With the ADA4930-1/ADA4930-2, differential gain configurations
are easily realized with a simple external feedback network of
four resistors determining the closed-loop gain of the amplifier.
The ADA4930-1 is available in a Pb-free, 3 mm × 3 mm 16-lead
LFCSP, and the ADA4930-2 is available in a Pb-free, 4 mm × 4 mm
24-lead LFCSP. The pinout has been optimized to facilitate printed
circuit board (PCB) layout and minimize distortion. The ADA4930-1
is specified to operate over the −40°C to +105°C temperature range,
and the ADA4930-2 is specified to operate over the −40°C to +105°C
temperature range for 3.3 V or 5 V supply voltages.
The ADA4930-1/ADA4930-2 are fabricated using Analog Devices,
Inc., proprietary silicon-germanium (SiGe), complementary
bipolar process, enabling them to achieve very low levels of
distortion with an input voltage noise of only 1.2 nV/√Hz.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADA4930-1/ADA4930-2
TABLE OF CONTENTS
Test Circuits..................................................................................... 15
Operational Description................................................................ 16
Definition of Terms.................................................................... 16
Theory of Operation ...................................................................... 17
Analyzing an Application Circuit ............................................ 17
Setting the Closed-Loop Gain .................................................. 17
Estimating the Output Noise Voltage...................................... 17
Impact of Mismatches in the Feedback Networks................. 18
Input Common-Mode Voltage Range..................................... 18
Minimum RG Value.................................................................... 19
Setting the Output Common-Mode Voltage.......................... 19
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
3.3 V Operation ............................................................................ 3
3.3 V VOCM to VO, cm Performance............................................... 4
3.3 V General Performance......................................................... 4
5 V Operation ............................................................................... 5
5 V VOCM to VO, cm Performance .................................................. 6
5 V General Performance............................................................ 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
Maximum Power Dissipation ..................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Calculating the Input Impedance for an Application Circuit
....................................................................................................... 19
Layout, Grounding, and Bypassing.............................................. 23
High Performance ADC Driving ................................................. 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
10/10—Rev. 0 to Rev. A
Changes to General Description .................................................... 1
10/10—Revision 0: Initial Version
Rev. A | Page 2 of 28
ADA4930-1/ADA4930-2
SPECIFICATIONS
3.3 V OPERATION
VS = 3.3 V, VICM = 0.9 V, VOCM = 0.9 V, RF = 301 Ω, RG = 301 Ω, RL, dm = 1 kΩ, single-ended input, differential output, TA = 25°C, TMIN to
MAX = −40°C to +105°C, unless otherwise noted.
T
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
ADA4930-1
ADA4930-2
Slew Rate
Settling Time to 0.1%
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
HD2/HD3
VO, dm = 0.1 V p-p
VO, dm = 2 V p-p
VO, dm = 0.1 V p-p
1430
887
MHz
MHz
380
89
2877
6.3
MHz
MHz
V/μs
ns
VO, dm = 2 V step, 25% to 75%
VO, dm = 2 V step, RL = 200 Ω
G = 3, VIN, dm = 0.7 V p-p pulse
1.5
ns
VO, dm = 2 V p-p, fC = 10 MHz
VO, dm = 2 V p-p, fC = 30 MHz
VO, dm = 2 V p-p, fC = 70 MHz
VO, dm = 2 V p-p, fC = 100 MHz
VO, dm = 1 V p-p/tone, fC = 70.05 MHz 0.05 MHz
VO, dm = 1 V p-p/tone, fC = 140.05 MHz 0.05 MHz
f = 100 kHz
−98/−97
−91/−88
−79/−79
−73/−73
91
86
1.15
3
−90
dB
dB
dB
dB
dBc
dBc
nV/√Hz
pA/√Hz
dB
Third-Order IMD
Input Voltage Noise
Input Current Noise
Crosstalk
f = 100 kHz
f = 100 MHz, ADA4930-2, RL = 200 Ω
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Open-Loop Gain
VIP = VIN = VOCM = 0 V, RL = open circuit
TMIN to TMAX
−3.1 −0.5
2.75
+3.1
−16
+1.8
mV
μV/°C
μA
−36
−24
TMIN to TMAX
−0.05
μA/°C
μA
dB
−1.8 +0.1
64
RF = RG = 10 kΩ, ΔVO = 0.5 V, RL = open circuit
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
0.3
150
3
1.2
V
Differential
Common mode
Common mode
ΔVICM = 0.5 V dc; RF = RG = 10 kΩ, RL = open circuit
kΩ
MΩ
pF
dB
Input Capacitance
CMRR
1
−82
−77
1.74
OUTPUT CHARACTERISTICS
Output Voltage
Linear Output Current
Output Balance Error
Each single-ended output; RF = RG = 10 kΩ
Each single-ended output; f = 1 MHz, TDH ≤ 60 dBc
f = 1 MHz
0.11
30
V
mA
dB
55
Rev. A | Page 3 of 28
ADA4930-1/ADA4930-2
3.3 V VOCM TO VO, CM PERFORMANCE
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
VO, cm = 0.1 V p-p
VO, cm = 2 V p-p, 25% to 75%
745
828
MHz
V/μs
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Voltage Noise
Gain
0.8
7.0
−25
1.1
10.3
+31
V
kΩ
mV
nV/√Hz
V/V
dB
8.3
VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 0 V
f = 100 kHz
+15.4
23.5
1
0.99
1.02
−77
CMRR
ΔVOCM = 0.5 V dc; RF = RG = 10 kΩ, RL = open circuit
−83
3.3 V GENERAL PERFORMANCE
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
3.3
35
81
V
Enabled
Enabled, TMIN to TMAX variation
Disabled
ΔVICM = 0.5 V; RF = RG = 10 kΩ, RL = open circuit
ΔVICM = 0.5 V; RF = RG = 10 kΩ, RL = open circuit
32
40
mA
μA/°C
mA
dB
0.44
1.8
−74
−87
2.35
−70
−76
+PSRR
−PSRR
dB
POWER-DOWN (PD)
PD Input Voltage
Disabled
Enabled
<0.8
>1.3
1
V
V
μs
ns
Turn-Off Time
Turn-On Time
PD Pin Bias Current
Enabled
12
PD = 3.3 V
PD = 0 V
0.09
97
μA
μA
°C
Disabled
OPERATING TEMPERATURE RANGE
−40
+105
Rev. A | Page 4 of 28
ADA4930-1/ADA4930-2
5 V OPERATION
VS = 5 V, VICM = 0.9 V, VOCM = 0.9 V, RF = 301 Ω, RG = 301 Ω, RL, dm = 1 kΩ, single-ended input, differential output, TA= 25°C,
MIN to TMAX = −40°C to +105°C, unless otherwise noted.
T
Table 4.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
ADA4930-1
ADA4930-2
Slew Rate
Settling Time to 0.1%
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
HD2/HD3
VO, dm = 0.1 V p-p
VO, dm = 2 V p-p
VO, dm = 0.1 V p-p
1350
937
MHz
MHz
369
90
3400
6
MHz
MHz
V/μs
ns
VO, dm = 2 V step, 25% to 75%
VO, dm = 2 V step, RL = 200 Ω
G = 3, VIN, dm = 0.7 V p-p pulse
1.5
ns
VO, dm = 2 V p-p, fC = 10 MHz
VO, dm = 2 V p-p, fC = 30 MHz
VO, dm = 2 V p-p, fC = 70 MHz
VO, dm = 2 V p-p, fC = 100 MHz
VO, dm = 1 V p-p/tone, fC = 70.05 MHz 0.05 MHz
VO, dm = 1 V p-p/tone, fC = 140.05 MHz 0.05 MHz
f = 100 kHz
−104/−101
−91/−93
−79/−82
−73/−75
94
90
1.2
2.8
−90
dB
dB
dB
dB
dBc
dBc
nV/√Hz
pA/√Hz
dB
Third-Order IMD
Input Voltage Noise
Input Current Noise
Crosstalk
f = 100 kHz
f = 100 MHz, ADA4930-2, RL = 200 Ω
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
VIP = VIN = VOCM = 0 V, RL = open circuit
TMIN to TMAX
−3.1
−34
−0.15
1.8
−23
+3.1
−15
mV
μV/°C
μA
Input Bias Current Drift
Input Offset Current
Open-Loop Gain
TMIN to TMAX
−0.05
μA/°C
+0.82 μA
−0.82 +0.1
64
RF = RG = 10 kΩ, ΔVO = 1 V, RL = open circuit
dB
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
0.3
150
3
2.8
V
Differential
Common mode
Common mode
ΔVICM = 1 V dc; RF = RG = 10 kΩ, RL = open circuit
kΩ
MΩ
pF
dB
Input Capacitance
CMRR
1
−82
−77
3.38
OUTPUT CHARACTERISTICS
Output Voltage
Linear Output Current
Output Balance Error
Each single-ended output; RF = RG = 10 kΩ
Each single-ended output; f = 1 MHz, TDH ≤ 60 dBc
f = 1 MHz
0.18
30
V
mA
dB
55
Rev. A | Page 5 of 28
ADA4930-1/ADA4930-2
5 V VOCM TO VO, CM PERFORMANCE
Table 5.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
VO, cm = 0.1 V p-p
VO, cm = 2 V p-p, 25% to 75%
740
1224
MHz
V/μs
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Voltage Noise
Gain
0.5
7.0
−25
2.3
10.2
+15
V
kΩ
mV
nV/√Hz
V/V
dB
8.3
VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 0 V
f = 100 kHz
+0.35
23.5
1
0.99
1.02
−77
CMRR
ΔVOCM = 1.5 V; RF = RG = 10 kΩ, RL = open circuit
−80
5 V GENERAL PERFORMANCE
Table 6.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
5
34
74.5
1.8
−74
−91
V
Enabled
Enabled, TMIN to TMAX variation
Disabled
ΔVICM = 1 V; RF = RG = 10 kΩ, RL = open circuit
ΔVICM = 1 V; RF = RG = 10 kΩ, RL = open circuit
31.1
0.45
38.4
mA
μA/°C
mA
dB
2.6
−71
−75
+PSRR
−PSRR
dB
POWER-DOWN (PD)
PD Input Voltage
Disabled
Enabled
<2.5
>3
1
V
V
μs
ns
Turn-Off Time
Turn-On Time
PD Pin Bias Current
Enabled
12
PD = 5 V
PD = 0 V
0.09
97
μA
μA
°C
Disabled
OPERATING TEMPERATURE RANGE
−40
+105
Rev. A | Page 6 of 28
ADA4930-1/ADA4930-2
ABSOLUTE MAXIMUM RATINGS
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Table 7.
Parameter
Rating
Supply Voltage
5.5 V
Power Dissipation
See Figure 4
−65°C to +125°C
−40°C to +105°C
300°C
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads/
exposed pad from metal traces, through holes, ground, and
power planes reduces θJA.
Figure 4 shows the maximum safe power dissipation vs. the
ambient temperature for the ADA4930-1 single 16-lead LFCSP
(98°C/W) and the ADA4930-2 dual 24-lead LFCSP (67°C/W)
on a JEDEC standard 4-layer board.
THERMAL RESISTANCE
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p circuit board, as described
in EIA/JESD51-7.
3.5
3.0
2.5
Table 8. Thermal Resistance
Package Type
θJA
98
67
Unit
°C/W
°C/W
ADA4930-2
16-Lead LFCSP (Exposed Pad)
24-Lead LFCSP (Exposed Pad)
2.0
1.5
ADA4930-1
1.0
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4930-1/ADA4930-2
packages is limited by the associated rise in junction temperature (TJ)
on the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the ADA4930-1/ADA4930-2. Exceeding a
0.5
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100 110
TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Ambient Temperature,
4-Layer Board
junction temperature of 150°C for an extended period can result
in changes in the silicon devices, potentially causing failure.
ESD CAUTION
Rev. A | Page 7 of 28
ADA4930-1/ADA4930-2
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
PIN 1
–IN1
+FB1
1
2
3
4
5
6
18
17 V
16 –V
15
14
+OUT1
INDICATOR
12 PD
–FB
+IN
1
2
3
4
OCM1
11 –OUT
10 +OUT
ADA4930-1
TOP VIEW
(Not to Scale)
+V
ADA4930-2
TOP VIEW
(Not to Scale)
S2
S2
S1
–V
+V
S1
–FB2
+IN2
–IN
PD2
+FB
9 V
OCM
13 –OUT2
NOTES
1. EXPOSED PADDLE. THE EXPOSED PAD IS NOT
ELECTRICALLY CONNECTED TO THE DEVICE. IT IS
TYPICALLY SOLDERED TO GROUND OR A POWER
PLANE ON THE PCB THAT IS THERMALLY CONDUCTIVE.
NOTES
1. EXPOSED PADDLE. THE EXPOSED PAD IS NOT
ELECTRICALLY CONNECTED TO THE DEVICE. IT IS
TYPICALLY SOLDERED TO GROUND OR A POWER
PLANE ON THE PCB THAT IS THERMALLY CONDUCTIVE.
Figure 5. ADA4930-1 Pin Configuration
Figure 6. ADA4930-2 Pin Configuration
Table 9. ADA4930-1 Pin Function Descriptions
Table 10. ADA4930-2 Pin Function Descriptions
Pin No. Mnemonic Description
Pin No.
Mnemonic
Description
1
−FB
Negative Output for Feedback
Component Connection.
Positive Input Summing Node.
Negative Input Summing Node.
Positive Output for Feedback
Component Connection.
Positive Supply Voltage.
Output Common-Mode Voltage.
Positive Output for Load Connection.
Negative Output for Load Connection.
Power-Down Pin.
1
2
3, 4
5
6
7
8
9, 10
11
12
−IN1
+FB1
+VS1
−FB2
+IN2
−IN2
+FB2
+VS2
VOCM2
+OUT2
−OUT2
PD2
Negative Input Summing Node 1.
Positive Output Feedback Pin 1.
Positive Supply Voltage 1.
Negative Output Feedback Pin 2.
Positive Input Summing Node 2.
Negative Input Summing Node 2.
Positive Output Feedback Pin 2.
Positive Supply Voltage 2.
Output Common-Mode Voltage 2.
Positive Output 2.
2
3
4
+IN
−IN
+FB
5 to 8
9
10
11
12
+VS
VOCM
+OUT
−OUT
PD
13
14
Negative Output 2.
Power-Down Pin 2.
13 to 16 −VS
EPAD
Negative Supply Voltage.
Exposed Paddle. The exposed pad is not
electrically connected to the device. It is
typically soldered to ground or a power
plane on the PCB that is thermally
conductive.
15, 16
17
18
19
20
−VS2
Negative Supply Voltage 2.
Output Common-Mode Voltage 1.
Positive Output 1.
Negative Output 1.
Power-Down Pin 1.
VOCM1
+OUT1
−OUT1
PD1
21, 22
23
24
−VS1
−FB1
+IN1
Negative Supply Voltage 1.
Negative Output Feedback Pin 1.
Positive Input Summing Node 1.
EPAD
Exposed Paddle. The exposed pad is
not electrically connected to the
device. It is typically soldered to
ground or a power plane on the PCB
that is thermally conductive.
Rev. A | Page 8 of 28
ADA4930-1/ADA4930-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 5 V, VICM = 0.9 V, VOCM = 0.9 V, RL, dm = 1 kΩ, unless otherwise noted.
3
0
3
V
= 100mV
V
= 2V p-p
IN
IN
IN
IN
IN
IN
0
–3
–3
G = 1, R = 300Ω
G = 1, R = 300Ω
G
G
G = 2, R = 150Ω
G = 2, R = 150Ω
–6
–6
G
G
G = 5, R = 60Ω
G = 5, R = 60Ω
G
G
–9
–9
–12
–15
–18
–21
–24
–27
–12
–15
–18
–21
–24
–27
1M
10M
100M
1G
10G
10G
10G
1M
10M
100M
1G
10G
10G
10G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. Small Signal Frequency Response
at Gain = 1, Gain = 2, and Gain = 5
Figure 10. Large Signal Frequency Response
at Gain = 1, Gain = 2, and Gain = 5
3
0
6
3
V
= 100mV
V
= 2V p-p
0
–3
V
V
= 3.3V
= 5.0V
V
V
= 3.3V
= 5.0V
–3
S
S
S
S
–6
–6
–9
–9
–12
–15
–18
–21
–24
–27
–12
–15
–18
–21
–24
–27
1M
10M
100M
FREQUENCY (Hz)
1G
1M
10M
100M
FREQUENCY (Hz)
1G
Figure 8. Small Signal Frequency Response
at VS = 3.3 V and VS = 5 V
Figure 11. Large Signal Frequency Response
at VS = 3.3 V and VS = 5 V
3
0
6
3
V
= 100mV
V
= 2V p-p
0
–3
T
T
T
= –40°C
= +25°C
= +105°C
A
A
A
–3
–6
–6
T
T
T
= –40°C
= +25°C
= +105°C
–9
A
A
A
–9
–12
–15
–18
–21
–24
–27
–12
–15
–18
–21
–24
–27
1M
10M
100M
FREQUENCY (Hz)
1G
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 9. Small Signal Frequency Response
at TA = −40°C, TA = 25°C, and TA = 105°C
Figure 12. Large Signal Frequency Response
at TA = −40°C, TA = 25°C, and TA = 105°C
Rev. A | Page 9 of 28
ADA4930-1/ADA4930-2
3
6
3
V
= 100mV p-p
V
= 2V p-p
IN
IN
0
–3
0
–3
R
R
= 1kΩ
= 200Ω
L
L
R
R
= 1kΩ
= 200Ω
–6
L
L
–6
–9
–9
–12
–15
–18
–21
–24
–27
–12
–15
–18
–21
–24
–27
1M
10M
100M
FREQUENCY (Hz)
1G
10G
1M
10M
100M
FREQUENCY (Hz)
1G
10G
Figure 13. Small Signal Frequency Response for RL = 200 Ω and RL = 1 kΩ
Figure 16. Large Signal Frequency Response
for RL = 200 Ω and RL = 1 kΩ
3
0.4
0.3
V
= 100mV
IN
2
1
ADA4930-2, 200ꢀ, OUT 1
ADA4930-2, 200ꢀ, OUT 2
ADA4930-1, 200ꢀ
0.2
ADA4930-1, 1kꢀ
ADA4930-2, 1kꢀ, OUT 1
ADA4930-2, 1kꢀ, OUT 2
0
0.1
–1
–2
–3
–4
–5
–6
0
–0.1
–0.2
–0.3
–0.4
1M
10M
100M
1M
10M
100M
1G
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14. VOCM Small Signal Frequency Response
Figure 17. Small Signal 0.1 dB Flatness vs. Frequency for
RL = 200 Ω and RL = 1 kΩ
–40
–50
–50
–60
–70
HD2, GAIN = 1
HD3, GAIN = 1
HD2, GAIN = 2
HD3, GAIN = 2
HD2, GAIN = 5
HD3, GAIN = 5
–60
–70
HD2, R = 200ꢀ
L
HD3, R = 200ꢀ
L
–80
–80
HD2, R = 1kꢀ
L
HD3, R = 1kꢀ
L
–90
–90
–100
–110
–120
–100
–110
1M
10M
100M 200M
1M
10M
100M
200M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15. Harmonic Distortion vs. Frequency
for Gain = 1, Gain = 2, and Gain = 5
Figure 18. Harmonic Distortion vs. Frequency
for RL = 200 Ω and RL = 1 kΩ
Rev. A | Page 10 of 28
ADA4930-1/ADA4930-2
–20
–40
–60
–65
–70
–75
–60
–80
HD2, V = 3.3V
S
HD2, 3.3V
HD3, 3.3V
HD2, 5.0V
HD3, 5.0V
HD3, V = 3.3V
S
–85
–80
HD2, V = 5.0V
S
HD3, V = 5.0V
S
–90
–100
–120
–140
–95
–100
–105
–110
1M
10M
100M 200M
1.0
1.5
2.0
V
2.5
(V p-p)
3.0
3.5
FREQUENCY (Hz)
OUT
Figure 19. ADA4930-1 Harmonic Distortion vs. Frequency
at VS = 3.3 V and VS = 5 V
Figure 22. Harmonic Distortion vs. Output @ 10 MHz
–40
–40
–50
10MHz, HD2
10MHz, HD3
70MHz, HD2
70MHz, HD3
–50
–60
10MHz, HD2
10MHz, HD3
70MHz, HD2
70MHz, HD3
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.5
1.0
1.5
2.0
2.5
3.0
V
ABOVE – V (V)
V
ABOVE – V (V)
S
OCM
S
OCM
Figure 20. Harmonic Distortion vs. VOCM at VS = 3.3 V
at 10 MHz and 70 MHz
Figure 23. Harmonic Distortion vs. VOCM
at 10 MHz and 70 MHz
0
–20
20
0
HD2, V
HD3, V
HD2, V
HD3, V
= 1V p-p
= 1V p-p
= 2V p-p
= 2V p-p
OUT
OUT
OUT
OUT
–20
–40
–60
–80
–100
–120
–140
–40
–60
–80
–100
–120
–140
1M
10M
100M 200M
69.8
69.9
70.0
70.1
70.2
70.3
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 24. 70 MHz Intermodulation Distortion
Figure 21. Distortion vs. VOUT at VS = 3.3 V
Rev. A | Page 11 of 28
ADA4930-1/ADA4930-2
–40
–45
–50
–55
–60
–65
–70
–75
–20
–30
–40
–50
–60
–70
–80
–90
–100
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 25. CMRR vs. Frequency, RL = 200 Ω
Figure 28. PSRR vs. Frequency, RL = 200 Ω
–60
–20
–25
–30
–35
–40
–45
–50
–55
–60
V
= 1V p-p
IN
GAIN = 2
CHANNEL 1 TO CHANNEL 2
CHANNEL 2 TO CHANNEL 1
–70
–80
–90
–100
–110
–120
–130
–140
1G
1M
10M
100M
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 29. Output Balance vs. Frequency, RL = 200 Ω
Figure 26. Crosstalk vs. Frequency, RL = 200 Ω
–50
0
–10
–20
–30
–40
–50
–60
–70
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
S11
S22
R
R
= 200ꢀ
= 1kꢀ
L
L
1M
10M
100M 200M
1M
10M
100M
1G
10G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 30. SFDR
Figure 27. S11, S22, RL = 200 Ω
Rev. A | Page 12 of 28
ADA4930-1/ADA4930-2
60
80
70
100
30
0
60
30
50
GAIN
–60
–90
–120
–150
–180
–210
–240
–270
–300
40
10
30
PHASE
20
10
0
1
–10
–20
–30
–40
0
10
100
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
1G
10G
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 31. Open Loop Gain and Phase
Figure 34. Voltage Noise Spectral Density
0.10
1.00
0.98
0.96
0.94
0.92
0.90
0.88
0.86
0.84
0.82
0.80
0.05
0
–0.05
–0.10
0
2
4
6
8
10
0
2
4
6
8
10
12
14
16
18
20
TIME (ns)
TIME (ns)
Figure 32. Small Signal Pulse Response
Figure 35. Small Signal VOCM Pulse Response
2.0
1.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
= 2V p-p
= 1V p-p
O
O
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
2
4
6
8
10
0
2
4
6
8
10
12
14
16
18
20
TIME (ns)
TIME (ns)
Figure 33. Large Signal Pulse Response
Figure 36. Large Signal VOCM Pulse Response
Rev. A | Page 13 of 28
ADA4930-1/ADA4930-2
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
2.5
2.0
1.5
V
V
× 3
IN
O, dm
1.0
0.5
PD
+OUT
–OUT
0
–0.5
–1.0
–1.5
–2.0
–2.5
–0.25
0
100 200 300 400 500 600 700 800 900 1000
TIME (ns)
0
5
10
15
20
25
TIME (ns)
30
35
40
45
50
PD
Figure 37.
Response vs. Time
Figure 38. Vo, dm Overdrive Recovery
Rev. A | Page 14 of 28
ADA4930-1/ADA4930-2
TEST CIRCUITS
301ꢀ
+V
S
50ꢀ
301ꢀ
V
57.6ꢀ
0.9V
V
IN
OCM
ADA4930
1kꢀ
301ꢀ
0.9V
26.7ꢀ
301ꢀ
0.9V
Figure 39. Equivalent Basic Test Circuit
301ꢀ
+V
S
50ꢀ
301ꢀ
50ꢀ
57.6ꢀ
0.9V
V
V
IN
OCM
ADA4930
50ꢀ
301ꢀ
26.7ꢀ
0.9V
0.9V
301ꢀ
Figure 40. Test Circuit for Output Balance
301ꢀ
+V
S
0.1µF
0.1µF
50ꢀ
301ꢀ
412ꢀ
FILTER
FILTER
57.6ꢀ
V
V
IN
261ꢀ
412ꢀ
OCM
ADA4930
0.9V
301ꢀ
0.9V
0.9V
26.7ꢀ
301ꢀ
0.9V
Figure 41. Test Circuit for Distortion Measurements
Rev. A | Page 15 of 28
ADA4930-1/ADA4930-2
OPERATIONAL DESCRIPTION
Common-Mode Voltage
DEFINITION OF TERMS
–FB
Common-mode voltage refers to the average of two node voltages.
The output common-mode voltage is defined as
R
F
R
G
G
+IN
–IN
–OUT
+D
IN
V
OUT, cm = (V+OUT + V−OUT)/2
V
R
V
OUT, dm
OCM
L, dm
ADA4930
–D
IN
Balance
+OUT
R
R
F
Output balance is a measure of how close the differential signals are
to being equal in amplitude and opposite in phase. Output balance
is most easily determined by placing a well-matched resistor divider
between the differential voltage nodes and comparing the magnitude
of the signal at the divider midpoint with the magnitude of the
differential signal (see Figure 39). By this definition, output balance
is the magnitude of the output common-mode voltage divided by
the magnitude of the output differential mode voltage.
+FB
Figure 42. Circuit Definitions
Differential Voltage
Differential voltage refers to the difference between two
node voltages. For example, the output differential voltage (or,
equivalently, output differential-mode voltage) is defined as
V
OUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
VOUT, cm
Output Balance Error =
VOUT, dm
Rev. A | Page 16 of 28
ADA4930-1/ADA4930-2
THEORY OF OPERATION
The ADA4930-1/ADA4930-2 differ from conventional op amps
in that they have two outputs whose voltages move in opposite
directions and an additional input, VOCM. Like an op amp, they rely
on high open-loop gain and negative feedback to force these
outputs to the desired voltages. The ADA4930-1/ADA4930-2
behave much like standard voltage feedback op amps and facilitate
single-ended-to-differential conversions, common-mode level
shifting, and amplifications of differential signals. Like op amps,
the ADA4930-1/ADA4930-2 have high input impedance and low
output impedance.
ESTIMATING THE OUTPUT NOISE VOLTAGE
The differential output noise of the ADA4930-1/ADA4930-2 can
be estimated using the noise model in Figure 43. The input-referred
noise voltage density, vnIN, is modeled as differential. The noise
currents, inIN− and inIN+, appear between each input and ground.
V
V
nRG1
nRF1
R
R
F1
G1
inIN+
+
V
nIN
V
nOD
inIN–
ADA4930
Two feedback loops control the differential and common-mode
output voltages. The differential feedback, set with external
resistors, controls the differential output voltage. The common-
mode feedback controls the common-mode output voltage. This
architecture makes it easy to set the output common-mode level
to any arbitrary value within the specified limits. The output
common-mode voltage is forced to be equal to the voltage applied
to the VOCM input by the internal common-mode feedback loop.
V
OCM
V
nCM
R
R
F2
G2
V
V
nRG2
nRF2
Figure 43. Noise Model
Similar to the case of conventional op amps, the output noise
voltage densities can be estimated by multiplying the input-
referred terms at +IN and −IN by an appropriate output factor.
The internal common-mode feedback loop produces outputs
that are highly balanced over a wide frequency range without
requiring tightly matched external components. This results
in differential outputs that are very close to the ideal of being
identical in amplitude and are exactly 180°◀apart in phase.
The output voltage due to vnIN is obtained by multiplying vnIN by
the noise gain, GN.
The circuit noise gain is
2
GN
=
(
β1 + β2
)
ANALYZING AN APPLICATION CIRCUIT
RG1
RF1 + RG1
RG2
RF2 + RG2
The ADA4930-1/ADA4930-2 use high open-loop gain and
negative feedback to force their differential and common-mode
output voltages to minimize the differential and common-mode
error voltages. The differential error voltage is defined as the
voltage between the differential inputs labeled +IN and −IN
(see Figure 42). For most purposes, this voltage can be assumed
to be zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to VOCM can also
be assumed to be zero. Starting from these two assumptions,
any application circuit can be analyzed.
where the feedback factors are β1 =
and β2 =
.
When the feedback factors are matched, RF1/RG1 = RF2/RG2,
1
β
RF
RG
β1 = β2 = β, and the noise gain becomes GN = =1+
.
The noise currents are uncorrelated with the same mean-square
value, and each produces an output voltage that is equal to the
noise current multiplied by the associated feedback resistance.
The noise voltage density at the VOCM pin is vnCM. When the
feedback networks have the same feedback factor, as in most
cases, the output noise due to vnCM is common-mode and the
output noise from VOCM is zero.
Each of the four resistors contributes (4kTRxx)1/2. The noise
from the feedback resistors appears directly at the output, and
the noise from the gain resistors appears at the output multiplied
by RF/RG.
SETTING THE CLOSED-LOOP GAIN
The differential-mode gain of the circuit in Figure 42 is
determined by
VOUT, dm
RF
RG
=
VIN, dm
where the gain and feedback resistors, RG and RF, on each side
are equal.
The total differential output noise density, vnOD, is the root-sum-
square of the individual output noise terms.
8
2
vnOD
=
(v
)
nODi
∑
i=1
Rev. A | Page 17 of 28
ADA4930-1/ADA4930-2
Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks
Input Noise
Voltage Density
Output
Multiplication Factor
Differential Output Noise
Voltage Density Terms
Input Noise Contribution
Differential Input
Inverting Input
Noninverting Input
VOCM Input
Gain Resistor RG1
Gain Resistor RG2
Feedback Resistor RF1
Feedback Resistor RF2
Input Noise Term
vnIN
inIN+
inIN−
vnCM
vnRG1
vnRG2
vnRF1
vnRF2
vnIN
GN
1
1
0
RF1/RG1
RF2/RG2
1
1
vnOD1 = GN(vnIN)
inIN+ × (RF2)
inIN− × (RF1)
vnCM
(4kTRG1)1/2
(4kTRG2)1/2
(4kTRF1)1/2
(4kTRF2)1/2
vnOD2 = (inIN+)(RF2)
vnOD3 = (inIN−)(RF1)
vnOD4 = 0
vnOD5 = (RF1/RG1)(4kTRG1)1/2
vnOD6 = (RF2/RG2)(4kTRG2)1/2
vnOD7 = (4kTRF1)1/2
vnOD8 = (4kTRF2)1/2
Table 12. Differential Input, DC-Coupled, VS = 5 V
Nominal Gain (dB)
RF1, RF2 (Ω)
RG1, RG2 (Ω)
RIN, dm (Ω)
602
Differential Output Noise Density (nV/√Hz)
0
301
301
4.9
6
301
150
300
6.2
10
14
301
301
95.3
60.4
190.6
120.4
7.8
10.1
Table 13. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω, VS = 5 V
Nominal Gain (dB)
RF1, RF2 (Ω)
RG1 (Ω) RT (Ω) RIN, cm (Ω)
RG2 (Ω)1 Differential Output Noise Density (nV/√Hz)
0
6
10
14
301
301
301
301
142
64.2
84.5
1 k
190.67
95.06
53.54
170
95
69.3
57.7
5.9
7.8
9.3
10.4
63.4
33.2
10.2
1.15 k 17.5
1 RG2 = RG1 + (RS||RT).
large amount, it is necessary to include the gain term from VOCM
to VO, dm and account for the extra noise. For example, if β1 = 0.5
and β2 = 0.25, the gain from VOCM to VO, dm is 0.67. If the VOCM pin
is set to 0.9 V, a differential offset voltage is present at the output of
(0.9 V)(0.67) = 0.6 V. The differential output noise contribution is
(5 nV/√Hz)(0.67) = 3.35 nV/√Hz. Both of these results are
undesirable in most applications; therefore, it is best to use
nominally matched feedback factors.
Table 11 summarizes the input noise sources, the multiplication
factors, and the output-referred noise density terms.
Table 12 and Table 13 list several common gain settings, associated
resistor values, input impedance, and output noise density for
both balanced and unbalanced input configurations.
IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
Mismatched feedback networks also result in a degradation of
the ability of the circuit to reject input common-mode signals,
much the same as for a four-resistor difference amplifier made
from a conventional op amp.
As previously mentioned, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.
As a practical summarization of the previous issues, resistors of
1% tolerance produce a worst-case input CMRR of approximately
40 dB, a worst-case differential-mode output offset of 9 mV due
to a 0.9 V VOCM input, negligible VOCM noise contribution, and
no significant degradation in output balance error.
The gain from the VOCM pin to VO, dm is equal to
2(β1 − β2)/(β1 + β2)
INPUT COMMON-MODE VOLTAGE RANGE
When β1 = β2, this term goes to zero and there is no differential
output voltage due to the voltage on the VOCM input (including
noise). The extreme case occurs when one loop is open and the
other has 100% feedback; in this case, the gain from VOCM input
to VO, dm is either +2 or −2, depending on which loop is closed. The
feedback loops are nominally matched to within 1% in most
applications, and the output noise and offsets due to the VOCM
input are negligible. If the loops are intentionally mismatched by a
The input common-mode range at the summing nodes of the
ADA4930-1/ADA4930-2 is specified as 0.3 V to 1.5 V at VS = 3.3 V.
To avoid nonlinearities, the voltage swing at the +IN and −IN
terminals must be confined to these ranges.
Rev. A | Page 18 of 28
ADA4930-1/ADA4930-2
For an unbalanced single-ended input signal, as shown in
Figure 45, the input impedance is
MINIMUM RG VALUE
Due to the wide bandwidth of the ADA4930-1/ADA4930-2, the
value of RG must be greater than or equal to 301 Ω at unity gain
to provide sufficient damping in the amplifier front end. In the
terminated case, RG includes the Thevenin resistance of the
source and load terminations.
β1+ β2
β1(β2 +1)
RIN,SE = RG1
where:
RG1
β1 =
SETTING THE OUTPUT COMMON-MODE VOLTAGE
RG1 + RF1
The VOCM pin of the ADA4930-1/ADA4930-2 is biased at 3/10 of
the total supply voltage above −VS with an internal voltage divider.
The input impedance of the VOCM pin is 8.4 kΩ. When relying
on the internal bias, the output common-mode voltage is within
about 100 mV of the expected value.
RG2
RG2 + RF2
β2 =
R
F1
+V
R
S
IN, SE
In cases where accurate control of the output common-mode
level is required, it is recommended that an external source or
resistor divider be used with source resistance less than 100 Ω.
The output common-mode offset listed in the Specifications
section assumes that the VOCM input is driven by a low impedance
voltage source.
R
G1
V
OCM
ADA4930
R
V
OUT, dm
L
R
G2
–V
S
It is also possible to connect the VOCM input to a common-mode
voltage (VCM) output of an ADC. However, care must be taken
to ensure that the output has sufficient drive capability. The
input impedance of the VOCM pin is approximately 10 kΩ. If
multiple ADA4930-1/ADA4930-2 devices share one reference
output, it is recommended that a buffer be used.
R
F2
Figure 45. ADA4930-1/ADA4930-2 with Unbalanced (Single-Ended) Input
For a balanced system where RG1 = RG2 = RG and RF1 = RF2 = RF,
the equations simplify to
⎛
⎜
⎞
⎟
CALCULATING THE INPUT IMPEDANCE FOR AN
APPLICATION CIRCUIT
RG
RG + RF
RG
RF
2(RG + RF )
⎜
⎜
⎜
⎝
⎟
⎟
⎟
⎠
β1 = β2 =
and RIN,SE =
1−
The effective input impedance depends on whether the signal
source is single-ended or differential. For a balanced differential
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the input resistor RG1. The common-mode
voltage at the amplifier input terminals can be easily determined
by noting that the voltage at the inverting input is equal to the
noninverting output voltage divided down by the voltage divider
formed by RF2 and RG2. This voltage is present at both input
terminals due to negative voltage feedback and is in phase
with the input signal, thus reducing the effective voltage across
RG1, partially bootstrapping it.
input signal, as shown in Figure 44, the input impedance (RIN, dm
between the inputs (+DIN and −DIN) is RIN, dm = 2 × RG.
)
R
F
ADA4930
+V
S
R
R
G
+IN
+D
–D
IN
V
OCM
V
OUT, dm
IN
–IN
G
R
F
Figure 44. ADA4930-1/ADA4930-2 Configured for Balanced (Differential) Inputs
Rev. A | Page 19 of 28
ADA4930-1/ADA4930-2
Terminating a Single-Ended Input
4. Set RF1 = RF2 = RF to maintain a balanced system.
Compensate the imbalance caused by RTH. There are two
methods available to compensate, which follow:
This section describes the five steps that properly terminate a
single-ended input to the ADA4930-1/ADA4930-2. Assume a
system gain of 1, RF1 = RF2 = 301 Ω, an input source with an open-
circuit output voltage of 2 V p-p, and a source resistance of 50 Ω.
Figure 46 shows this circuit.
•
Add RTH to RG2 to maintain balanced gain resistances
VS
and increase RF1 and RF2 to RF =
Gain(RG + RTH) to
VTH
1. Calculate the input impedance.
maintain the system gain.
RF ×VTH
VS ×Gain
β1 = β2 = 301/602 = 0.5 and RIN = 401.333 Ω
•
Decrease RG2 to RG2
=
to maintain system
R
F1
301ꢀ
+V
R
IN
401.333ꢀ
gain and decrease RG1 to (RG2 − RTH) to maintain
balanced gain resistances.
S
R
R
S
G1
The first compensation method is used in the Diff Amp
Calculator™ tool. Using the second compensation method,
50ꢀ
301ꢀ
V
S
V
OCM
ADA4930
R
V
OUT, dm
2V p-p
L
RG2 = 160.498 Ω and RG1 = 160.498 − 26.66 = 133.837 ꢀ.
R
G2
The modified circuit is shown in Figure 49.
301ꢀ
R
F1
301ꢀ
+V
–V
S
R
F2
301ꢀ
S
R
R
TH
G1
Figure 46. Single-Ended Input Impedance RIN
26.661ꢀ
133.837ꢀ
V
TH
1.066V p-p
2. Add a termination resistor, RT. To match the 50 Ω source
resistance, RT is added. Because RT||401.33 Ω = 50 Ω,
RT = 57.116 ꢀ.
V
OCM
V
OUT, dm
ADA4930
R
L
R
G2
160.498ꢀ
R
F1
301ꢀ
+V
–V
S
R
R
F2
301ꢀ
IN
50ꢀ
S
R
R
S
G1
Figure 49. Thevenin Equivalent with Matched Gain Resistors
50ꢀ
301ꢀ
R
T
V
S
Figure 49 presents an easily manageable circuit with matched
feedback loops that can be easily evaluated.
57.116ꢀ
V
OCM
ADA4930
R
V
2V p-p
L OUT, dm
R
G2
5. The modified gain resistor, RG1, changes the input impedance.
Repeat Step 1 through Step 4 several times using the modified
value of RG1 from the previous iteration until the value of
RT does not change from the previous iteration. After three
additional iterations, the change in RG1 is less than 0.1%.
The final circuit is shown in Figure 50 with the closest
0.5% resistor values.
301ꢀ
–V
S
R
F2
301ꢀ
Figure 47. Adding Termination Resistor RT
3. Replace the source-termination resistor combination with
its Thevenin equivalent. The Thevenin equivalent of the
source resistance RS and the termination resistance RT is
R
F1
301ꢀ
+V
R
TH = RS||RT = 26.66 ꢀ. TheThevenin equivalent of the
S
0.998V p-p
source voltage is
R
R
V
V
S
G
P
50ꢀ
142ꢀ
R
64.2ꢀ
T
RT
RS + RT
V
S
V
V
TH = VS
= 1.066 V p-p
OUT, dm
1.990V p-p
V
OCM
ADA4930
R
2V p-p
L
R
G2
N
R
S
R
TH
169ꢀ
50ꢀ
R
T
57.116ꢀ
26.661ꢀ
V
V
S
TH
1.066V p-p
–V
S
2V p-p
R
F2
301ꢀ
Figure 48. Thevenin Equivalent Circuit
Figure 50. Terminated Single-Ended-to-Differential System with G = 1
Rev. A | Page 20 of 28
ADA4930-1/ADA4930-2
Terminating a Single-Ended Input in a Single-Supply
Applications
3. To comply with the minimum specified input common-mode
voltage of 0.3 V at VS = 3.3 V, set the minimum value of VP
and VN to 0.3 V.
When the application circuit of Figure 50 is powered by a single
supply, the common-mode voltage at the amplifier inputs, VP
and VN, may have to be raised to comply with the specified input
common-mode range. Two methods are available: a dc bias on
the source, as shown in Figure 51, or by connecting resistors RCM
between each input and the supply, as shown on Figure 54.
4. Recognize that VP and VN are at their minimum values when
VOP and VS are at their minimum (and therefore VON is at its
maximum).
Let
VP min = VN min = 0.3 V, VOCM = VCM = 1 V, VTH min = −VTH/2
VON max = VOCM + VOUT, dm/4 and VOP min = VOCM − VOUT, dm/4
Input Common-Mode Adjustment with DC Biased Source
To drive a 1.8 V ADC with VCM = 1 V, a 3.3 V single supply
minimizes the power dissipation of the ADA4930-1/ADA4930-2.
The application circuit of Figure 50 on a 3.3 V single supply with a
dc bias added to the source is shown in Figure 51.
Substitute conditions into the nodal equation for VP and solve
for VDC-TH
0.3 = −1.124/2 + VDC-TH + 0.361 × (1 + 1.99/4 = 1.124/2 – VDC-TH
0.3 + 0.562 − 0.361 − 0.18 − 0.203 = 0.639 VDC-TH
DC-TH = 0.186 V
.
)
R
F1
301ꢀ
3.3V
V
R
R
V
S
G1
P
N
Or
50ꢀ
142ꢀ
R
64.2ꢀ
Substitute conditions into the nodal equation for VN and
solve for VDC-TH
T
V
S
V
OCM
ADA4930
R
V
2V p-p
L
OUT, dm
1.990V p-p
.
R
V
G2
0.3 = VDC-TH + 0.361 × (1 − 1.99/4 − VDC-TH
)
142ꢀ
64.2ꢀ
50ꢀ
0.3 – 0.361 + 0.18 = 0.639 × VDC-TH
R
F2
V
DC-TH = 0.186 V
V
DC
301ꢀ
5. Converting VDC-TH from its Thevenin equivalent results in
Figure 51. Single-Supply, Terminated Single-Ended-to-Differential System with G = 1
RS + RTH
VDC
=
×0.186 = 0.33 V
To determine the minimum required dc bias, the following steps
must be taken:
RTH
The final application circuit is shown in Figure 53. The
additional dc bias of 0.33 V at the inputs ensures that the
minimum input common-mode requirements are met when
the source signal is bipolar with a 2 V p-p amplitude and
VOCM is at 1 V.
1. Convert the terminated inputs to their Thevenin equivalents,
as shown in the Figure 52 circuit.
R
F1
301ꢀ
3.3V
R
F1
301ꢀ
3.3V
R
R
V
V
VON
VOP
TH
G1
P
28.11ꢀ
142ꢀ
V
OCM
ADA4930
R
V
L
OUT, dm
1.99V p-p
V
TH
1.124V p-p
R
R
V
V
S
G1
P
R
R
TH
G2
N
50ꢀ
142ꢀ
R
64.2ꢀ
T
28.11ꢀ
142ꢀ
V
S
V
OCM
ADA4930
R
V
2V p-p
L
OUT, dm
1.990V p-p
R
V
DC-TH
G2
N
R
F2
142ꢀ
64.2ꢀ
50ꢀ
301ꢀ
Figure 52. Thevenin Equivalent of Single-Supply Application Circuit
V
R
DC
0.33V
F2
2. Write a nodal equation for VP or VN.
301ꢀ
301
VP = VTH +VDC−TH
+
(
VON −VTH −VDC−TH
)
Figure 53. Single-Supply Application Circuit with DC Source Bias
301+142 + 28.11
301
VN = VDC−TH
+
VOP
301+142 + 28.11
Recognize that while the ADA4930-1/ADA4930-2 is in its
linear operating region, VP and VN are equal. Therefore,
both equations in Step 2 give equal results.
Rev. A | Page 21 of 28
ADA4930-1/ADA4930-2
Calculate the following:
Input Common-Mode Adjustment with Resistors
The circuit shown in Figure 54 shows an alternate method to
bias the amplifier inputs, eliminating the dc source.
1. β1 and β2. For the circuit shown in Figure 54, β1 = 0.5 and
β2 = 0.5.
3.3V
2. RCM for VP min = 0.3 V and VIN min = −0.5 V. RCM = 9933 Ω.
3. The new values for β1 and β2. β1 = 0.4925 and β2 = 0.4925.
4. The input impedance using the following:
R
R
V
S
CM
F1
301ꢀ
+V
S
⎛
⎜
⎞
⎟
⎛
⎜
⎞
⎟
V
R
R
IN
S
G1
1
β1+ β2
50ꢀ
301ꢀ
⎜
⎜
⎟
⎟
⎜
⎜
⎟
⎟
RIN −SE = RG1
= RG1
R
V
T
SOURCE
2V p-p
VP
RF1
V
OCM
ADA4930
R
V
OUT, dm
L
1−
β1+ β2 −
β1β2
⎜
⎝
⎟
⎠
⎜
⎟
VINP
RG1
R
⎝
⎠
G2
301ꢀ
RIN-SE = 399.35 ꢀ.
–V
S
5. RT, RTH, and VTH. RT = 57.16 ꢀ, RTH = 26.67 ꢀ, and
VTH = 1.067 V.
6. The new values for RG1 and RG2. RG2 = 160.55 ꢀ and
RG1 = 133.88 ꢀ.
R
R
CM
F2
V
301ꢀ
S
3.3V
Figure 54. Single-Supply Biasing Scheme with Resistors
7. The new values for β1 and β2. β1 = 0.284 and β2 = 0.317.
8. The new value of RCM. RCM = 4759.63 ꢀ.
9. Repeat Step 3 through Step 8 until the values of RG1 and RG2
remain constant between iterations. After four iterations,
the final circuit is shown in Figure 55.
Define β1 = RP/RF1 and β2 = RN/RF2, where RP = RG1||RCM||RF1
and RN = RG2||RCM||RF2.
Set RF1 = RF2 = RF to maintain a balanced system, as shown.
Write a nodal equation at VP and solve for VP.
+V
S
R
R
CM
F1
301ꢀ
+V
⎛
⎞
⎟
⎟
⎠
β1β2 RF
2RF
RCM
⎜
VP =
VIN + 2VOCM +VS
1.87kꢀ
⎜
β1+ β2 RG1
⎝
S
R
R
S
G1
Determine VP min. This is the minimum input common-mode
voltage from the Specifications section. For a 3.3 V supply,
VP min = 0.3 V.
50ꢀ
142ꢀ
R
T
65.1ꢀ
V
S
V
OCM
ADA4930
R
V
OUT, dm
2V p-p
L
R
G2
Determine the minimum input voltage, VIN min at the output of
the source. Recognize that once properly terminated, the source
voltage is ½ of its open circuit value. Therefore, VIN min = −0.5 V.
170ꢀ
–V
S
R
R
CM
F2
Rearrange the VP equation for RCM
1.87kꢀ
301ꢀ
+V
S
⎛
⎜
⎜
⎞
⎟
⎟
⎠
1
1
β1+ β2
RF
RG1
=
VP min
−
VIN min − 2VOCM
Figure 55. Single-Supply, Single-Ended Input System with Bias Resistors
RCM 2VSRF β1β2
⎝
Rev. A | Page 22 of 28
ADA4930-1/ADA4930-2
LAYOUT, GROUNDING, AND BYPASSING
The ADA4930-1/ADA4930-2 are high speed devices. Realizing
their superior performance requires attention to the details of
high speed PCB design.
Use radio frequency transmission lines to connect the driver
and receiver to the amplifier.
Minimize stray capacitance at the input/output pins by clearing
the underlying ground and low impedance planes near these pins
(see Figure 56).
The first requirement is to use a multilayer PCB with solid ground
and power planes that cover as much of the board area as possible.
Bypass each power supply pin directly to a nearby ground plane, as
close to the device as possible. Use 0.1 μF high frequency ceramic
chip capacitors.
If the driver/receiver is more than one-eighth of the wavelength
from the amplifier, the signal trace widths should be minimal.
This nontransmission line configuration requires the underlying
and adjacent ground and low impedance planes to be cleared
near the signal lines.
Provide low frequency bulk bypassing, using 10 μF tantalum
capacitors from each supply to ground.
The exposed thermal paddle is internally connected to the ground
pin of the amplifier. Solder the paddle to the low impedance
ground plane on the PCB to ensure the specified electrical
performance and to provide thermal relief. To reduce thermal
impedance further, it is recommended that the ground planes
on all layers under the paddle be connected together with vias.
Stray transmission line capacitance in combination with package
parasitics can potentially form a resonant circuit at high frequencies,
resulting in excessive gain peaking or possible oscillation.
Signal routing should be short and direct to avoid such parasitic
effects. Provide symmetrical layout for complementary signals
to maximize balanced performance.
1.30
0.80
1.30 0.80
Figure 56. ADA4930-1 Ground and Power Plane Voiding
in the Vicinity of RF and RG
Figure 57. Recommended PCB Thermal Attach Pad Dimensions (Millimeters)
1.3 mm
0.8 mm
TOP METAL
GROUND PLANE
POWER PLANE
BOTTOM METAL
Figure 58. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters)
Rev. A | Page 23 of 28
ADA4930-1/ADA4930-2
HIGH PERFORMANCE ADC DRIVING
The ADA4930-1/ADA4930-2 provide excellent performance in
3.3 V single-supply applications.
A third-order, 40 MHz, low-pass filter between the ADA4930-1
and the AD9255 reduces the noise bandwidth of the amplifier
and isolates the driver outputs from the ADC inputs.
The circuit shown in Figure 59 is an example of the ADA4930-1
driving an AD9255, 14-bit, 80 MSPS ADC that is specified to
operate with a single 1.8 V supply. The performance of the ADC
is optimized when it is driven differentially, making the best use of
the signal swing available within the 1.8 V supply. The ADA4930-1
performs the single-ended-to-differential conversion, common-
mode level shifting, and buffering of the driving signal.
The circuit shown in Figure 60 is an example of ½ of an
ADA4930-2 driving ½ of an AD9640, a 14-bit, 80 MSPS
ADC that is specified to operate with a single 1.8 V supply.
The performance of the ADC is optimized when it is driven
differentially, making the best use of the signal swing available
within the 1.8 V supply. The ADA4930-2 performs the single-
ended-to-differential conversion, common-mode level shifting,
and buffering of the driving signal.
The ADA4930-1 is configured for a single-ended input to differential
output with a gain of 2 V/V. The 84.5 Ω termination resistor, in
parallel with the single-ended input impedance of 95.1 Ω, provides
a 50 Ω termination for the source. The additional 31.6 Ω (95 Ω
total) at the inverting input balances the parallel impedance of
the 50 Ω source and the termination resistor that drives the
noninverting input.
The ADA4930-2 is configured for a single-ended input to differential
output with a gain of 2 V/V. The 88.5 Ω termination resistor, in
parallel with the single-ended input impedance of 114.75 Ω,
provides a 50 Ω termination for the source. The increased gain
resistance at the inverting input balances the 50 Ω source resistance
and the termination resistor that drives the noninverting input.
The VOCM pin is connected to the VCM output of the AD9255
and sets the output common mode of the ADA4930-1 at 1 V.
The VOCM pin is connected to the CML output of the AD9640 and
sets the output common mode of the ADA4930-2 at 1 V.
Note that a dc bias must be added to the signal source and its
Thevenin equivalent to the gain resistor on the inverting side
to ensure that the inputs of the ADA4930-1 are kept at or above
the specified minimum input common-mode voltage at all times.
The 739 Ω resistors between each input and the 3.3 V supply
provide the necessary dc bias to guarantee compliance with the
input common-mode range of the ADA4930-2.
The 0.5 V dc bias at the signal source and the 0.314 V dc bias on the
gain resistor at the inverting input set the inputs of the ADA4930-1
to ~0.48 V dc. With 1 V p-p maximum signal swing at the input,
the ADA4930-1 inputs swing between 0.36 V and 0.6 V.
For a common-mode voltage of 1 V, each ADA4930-2 output
swings between 0.501 V and 1.498 V, providing a 1.994 V p-p
differential output.
A third-order, 40 MHz, low-pass filter between the ADA4930-2
and the AD9640 reduces the noise bandwidth of the amplifier
and isolates the driver outputs from the ADC inputs.
For a common-mode voltage of 1 V, each ADA4930-1 output
swings between 0.501 V and 1.498 V, providing a 1.994 V p-p
differential output.
301ꢀ
1.8V
3.3V
168nH
63.4ꢀ
50ꢀ
33ꢀ
AVDD DRVDD
+
VIN–
V
D11 TO
D0
84.5ꢀ
OCM
V
AD9255
30pF
90pF
ADA4930-1
IN
1V p-p
VIN+
0.5V
AGND
VCM
168nH
33ꢀ
95ꢀ
0.314V
301ꢀ
Figure 59. Driving an AD9255, 14-Bit, 80 MSPS ADC
301ꢀ
1.8V
3.3V
3.3V
739ꢀ
168nH
50ꢀ
AVDD DRVDD
VIN–
+
64.2ꢀ
96.2ꢀ
D11 TO
D0
88.5ꢀ
V
AD9640
V
30pF
90pF
ADA4930-2
IN
1V p-p
OCM
VIN+
AGND
CML
168nH
739ꢀ
3.3V
301ꢀ
V
OCM
Figure 60. Driving an AD9640, 14-Bit, 80 MSPS ADC
Rev. A | Page 24 of 28
ADA4930-1/ADA4930-2
OUTLINE DIMENSIONS
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.45
1.30 SQ
1.15
13
16
1
0.45
(BOTTOM VIEW)
12
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PAD
4
9
0.50
BSC
8
5
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 61. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-2)
Dimensions shown in millimeters
4.10
4.00 SQ
0.60 MAX
3.90
0.60 MAX
PIN 1
INDICATOR
18
1
24
19
0.50
BSC
PIN 1
INDICATOR
2.44
2.34 SQ
2.24
3.75 BSC
SQ
EXPOSED
PAD
(BOTTOM VIEW)
13
12
6
7
0.50
0.40
0.30
0.20 MIN
TOP VIEW
2.50 BCS
0.70 MAX
0.65 TYP
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.90
0.85
0.80
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.05
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8
Figure 62. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
Evaluation Board
Package Option
CP-16-2
CP-16-2
Ordering Quantity
Branding
H1G
H1G
ADA4930-1YCPZ-R2
ADA4930-1YCPZ-RL
ADA4930-1YCPZ-R7
ADA4930-1YCP-EBZ
ADA4930-2YCPZ-R2
ADA4930-2YCPZ-RL
ADA4930-2YCPZ-R7
ADA4930-2YCP-EBZ
250
5,000
1,500
CP-16-2
H1G
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Evaluation Board
CP-24-13
CP-24-13
CP-24-13
250
5,000
1,500
1 Z = RoHS Compliant Part.
Rev. A | Page 25 of 28
ADA4930-1/ADA4930-2
NOTES
Rev. A | Page 26 of 28
ADA4930-1/ADA4930-2
NOTES
Rev. A | Page 27 of 28
ADA4930-1/ADA4930-2
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09209-0-10/10(A)
Rev. A | Page 28 of 28
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