AD9979BCPZ [ADI]
14-Bit, CCD Signal Processor with Precision Timing Core; 14位CCD信号处理器， Precision Timing内核
| 型号： | AD9979BCPZ |
| 厂家： | 
ADI |
| 描述： | 14-Bit, CCD Signal Processor with Precision Timing Core |
| 文件： | 总56页 (文件大小：589K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
14-Bit, CCD Signal Processor with
Precision Timing Core
AD9979
FEATURES
GENERAL DESCRIPTION
1.8 V analog and digital core supply voltage
Correlated double sampler (CDS) with –3 dB, 0 dB, +3 dB, and
+6 dB gain
The AD9979 is a highly integrated CCD signal processor for
high speed digital video camera applications. Specified at pixel
rates of up to 65 MHz, the AD9979 consists of a complete
analog front end with analog-to-digital conversion, combined
with a programmable timing driver. The Precision Timing core
allows adjustment of high speed clocks with approximately
240 ps resolution at 65 MHz operation.
6 dB to 42 dB 10-bit variable gain amplifier (VGA)
14-bit 65 MHz analog-to-digital converter
Black-level clamp with variable level control
Complete on-chip timing generator
Precision Timing™ core with 240 ps resolution @ 65 MHz
On-chip 3 V horizontal and RG drivers
General-purpose outputs (GPOs) for shutter and system
support
The analog front end includes black-level clamping, CDS, VGA,
and a 65 MSPS, 14-bit analog-to-digital converter (ADC). The
timing driver provides the high speed CCD clock drivers for RG,
HL, and H1 to H4. Operation is programmed using a 3-wire
serial interface.
7 mm × 7 mm, 48-lead LFCSP
Internal LDO regulator circuitry
Available in a space-saving, 7 mm × 7 mm, 48-lead LFCSP,
the AD9979 is specified over an operating temperature range of
−25°C to +85°C.
APPLICATIONS
Professional HDTV camcorders
Professional/high end digital cameras
Broadcast cameras
Industrial high speed cameras
FUNCTIONAL BLOCK DIAGRAM
REFT
REFB
AD9979
VREF
14
CCDINP
CCDINM
DOUT
D0 TO D13
ADC
CDS
VGA
6dB TO 42dB
–3dB, 0dB, +3dB, +6dB
CLAMP
LDOOUT
LDO
INTERNAL CLOCKS
RG
HL
PRECISION
TIMING
CORE
CLI
HORIZONTAL
DRIVERS
4
H1 TO H4
SYNC
GENERATOR
INTERNAL
REGISTERS
GPO1 GPO2
HD
VD
SL
SCK
SDI
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
AD9979
TABLE OF CONTENTS
Features .............................................................................................. 1
Complete Field—Combining H-Patterns ............................... 23
Mode Registers ........................................................................... 24
Horizontal Timing Sequence Example.................................... 26
General-Purpose Outputs (GPO)............................................ 27
GP Look-Up Tables (LUT)........................................................ 30
Analog Front-End Description and Operation...................... 31
Applications Information.............................................................. 35
Recommended Power-Up Sequence ....................................... 35
Standby Mode Operation.......................................................... 37
CLI Frequency Change.............................................................. 37
Circuit Configuration................................................................ 38
Grounding and Decoupling Recommendations.................... 38
3-Wire Serial Interface Timing..................................................... 40
Layout of Internal Registers...................................................... 41
Updating of New Register Values............................................. 42
Complete Register Listing......................................................... 43
Outline Dimensions....................................................................... 54
Ordering Guide .......................................................................... 54
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Digital Specifications ................................................................... 5
Analog Specifications................................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Equivalent Input/Output Circuits ................................................ 11
Theory of Operation ...................................................................... 12
Programmable Timing Generation.............................................. 13
Precision Timing High Speed Timing Core............................. 13
Horizontal Clamping and Blanking......................................... 16
REVISION HISTORY
10/09—Rev. B to Rev. C
Changes to Clock Rate (CLI) Parameter, Table 1......................... 3
Changes to Figure 3 and Table 7......................................................8
Changes to Figure 22...................................................................... 16
Added GP_LINE_MODE Name, Table 16 ................................. 28
Changes to Figure 42...................................................................... 31
Added Example Register Settings for Power-Up Section.......... 36
Changes to Additional Restriction Section................................. 37
Changes to Table 22, 3 V System Compatibility Section, and
Grounding and Decoupling Recommendations Section.......... 38
Changes to Table 33 ....................................................................... 51
Changes to Table 34 ....................................................................... 52
Added Exposed Paddle Notation to Outline Dimensions........ 54
9/09—Rev. A to Rev. B
Changed SCK Falling Edge to SDATA Valid Hold Parameter to
SCK Rising Edge to SDATA Hold .................................................. 4
Changes to Individual HBLK Patterns Section .......................... 18
6/09—Rev. Sp0 to Rev. A
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Changes to Figure 2.......................................................................... 6
Changes to Table 5 and Thermal Resistance Section................... 7
2/07—Revision Sp0: Initial Version
Rev. C | Page 2 of 56
AD9979
SPECIFICATIONS
Table 1.
Parameter
Min Typ Max
Unit
TEMPERATURE RANGE
Operating
Storage
−25
−65
+85
+150 °C
°C
POWER SUPPLY VOLTAGE
AVDD (AFE, Timing Core)
RGVDD (RG, HL Drivers)
HVDD (H1 to H4 Drivers)
DVDD (Internal Digital Supply)
DRVDD (Parallel Data Output Drivers )
IOVDD (I/O Supply Without the Use of LDO)
POWER SUPPLY CURRENTS—65 MHz OPERATION
AVDD (1.8 V)
RGVDD (3.3 V, 20 pF RG Load, 20 pF HL Load)
HVDD1 (3.3 V, 200 pF Total Load on H1 to H4)
DVDD (1.8 V)
DRVDD (3.0 V)
IOVDD (1.8 V)
1.6
2.7
2.7
1.6
1.6
1.6
1.8
3.3
3.3
1.8
3.0
1.8
2.0
3.6
3.6
2.0
3.6
3.6
V
V
V
V
V
V
48
8
40
13
4
mA
mA
mA
mA
mA
mA
2
POWER SUPPLY CURRENTS—STANDBY MODE OPERATION
Reference Standby
Total Shutdown
10
0.5
mA
mA
LDO2
IOVDD (I/O Supply When Using LDO)
Output Voltage
Output Current
2.5
1.8
60
8
3.0
1.85 1.9
3.6
V
V
mA
MHz
CLOCK RATE (CLI)
65
1 The total power dissipated by the HVDD (or RGVDD) supply can be approximated using the equation
Total HVDD Power = [CLOAD × HVDD × Pixel Frequency] × HVDD
where CLOAD is the total capacitance seen by all H outputs.
Reducing the capacitive load and/or reducing the HVDD supply reduces the power dissipation.
2 LDO can be used to supply AVDD and DVDD only.
Rev. C | Page 3 of 56
AD9979
TIMING SPECIFICATIONS
CL = 20 pF, AVDD = DVDD = 1.8 V, fCLI = 65 MHz, unless otherwise noted.
Table 2.
Parameter
Symbol
Min
Typ Max
Unit
Comments
MASTER CLOCK (CLI)
CLI Clock Period
CLI High/Low Pulse Width
Delay from CLI Rising Edge to Internal
Pixel Position 0
See Figure 15
tCONV
tADC
tCLIDLY
15.38
6.9
ns
ns
ns
7.7
5
8.9
8.5
AFE
SHP Rising Edge to SHD Rising Edge
AFE Pipeline Delay
CLPOB Pulse Width (Programmable)1
tS1
6.9
7.7
16
20
ns
See Figure 19
See Figure 20
Cycles
Pixels
ns
tCOB
2
tCONV
HD Pulse Width
VD Pulse Width
1 HD period
ns
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
See Figure 56
See Figure 53
fSCLK
tLS
tLH
tDS
tDH
40
10
10
10
10
MHz
ns
ns
ns
ns
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Rising Edge to SDATA Hold
H-COUNTER RESET SPECIFICATIONS
HD Pulse Width
VD Pulse Width
VD Falling Edge to HD Falling Edge
HD Falling Edge to CLI Rising Edge
tCONV
1 HD period
0
3
3
ns
ns
ns
ns
ns
tVDHD
tHDCLI
tCLISHP
VD period − tCONV
tCONV − 2
tCONV − 2
CLI Rising Edge to SHPLOC (Internal
Sample Edge)
TIMING CORE SETTING RESTRICTIONS
Inhibited Region for SHP Edge Location2
(See Figure 19)
tSHPINH
50
64/0
Edge location
Inhibited Region for SHP or SHD with
Respect to H-Clocks(See Figure 19)3, 4, 5, 6
RETIME = 0, MASK = 0
RETIME = 0, MASK = 1
RETIME = 1, MASK = 0
RETIME = 1, MASK = 1
Inhibited Region for DOUTPHASE Edge
Location (See Figure 19)
tSHDINH
tSHDINH
tSHPINH
tSHPINH
tDOUTINH
H × NEGLOC − 15
H × POSLOC − 15
H × NEGLOC − 15
H × POSLOC − 15
SHDLOC + 0
H × NEGLOC − 0
H × POSLOC − 0
H × NEGLOC − 0
H × POSLOC − 0
SHDLOC + 15
Edge location
Edge location
Edge location
Edge location
Edge location
1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
2 Only applies to slave mode operation. The inhibited area for SHP is needed to meet the timing requirements for tCLISHP for proper H-counter reset operation.
3 When 0x34[2:0] HxBLKRETIME bits are enabled, the inhibit region for SHD location changes to inhibit region for SHP location.
4 When sequence register 0x09[23:21] HBLK masking registers are set to 0, the H-edge reference becomes H × NEGLOC.
5 The H-clock signals that have SHP/SHD inhibit regions depends on the HCLK mode: Mode 1 = H1, Mode 2 = H1, H2, and Mode 3 = H1, H3.
6 These specifications apply when H1POL, H2POL, RGPOL, and HLPOL are all set to 1 (default setting).
Rev. C | Page 4 of 56
AD9979
DIGITAL SPECIFICATIONS
IOVDD = 1.6 V to 3.6 V, RGVDD = HVDD = 2.7 V to 3.6 V, CL = 20 pF, tMIN to tMAX, unless otherwise noted.
Table 3.
Test Conditions/
Unit Comments
Parameter
Symbol
Min
Typ Max
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
IOVDD − 0.6
V
V
μA
μA
pF
0.6
10
10
10
LOGIC OUTPUTS
High Level Output Voltage
Low Level Output Voltage
CLI INPUT (CLI_BIAS = 0)
High Level Input Voltage
Low Level Input Voltage
H-DRIVER OUTPUTS
High Level Output Voltage at Maximum Current
Low Level Output Voltage at Maximum Current
Maximum Output Current (Programmable)
Maximum Load Capacitance
VOH
VOL
IOVDD − 0.5
IOVDD/2 + 0.5
HVDD − 0.5
100
V
V
IOH = 2 mA
IOL = 2 mA
0.5
VIHCLI
VILCLI
V
V
IOVDD/2 − 0.5
VOH
VOL
V
V
mA
pF
0.5
30
Rev. C | Page 5 of 56
AD9979
ANALOG SPECIFICATIONS
AVDD = 1.8 V, fCLI = 65 MHz, typical timing specifications, tMIN to tMAX, unless otherwise noted.
Table 4.
Parameter
CDS1
Min
Typ
Max
Unit
Test Conditions/Comments
Allowable CCD Reset Transient
CDS Gain Accuracy
0.5
0.8
V
−3.0 dB CDS Gain
0 dB CDS Gain (Default)
+3 dB CDS Gain
–3.7
–0.9
+1.9
+4.3
–3.2
–0.4
+2.4
+4.8
–2.7
+0.1
+2.9
+5.3
dB
dB
dB
dB
+6 dB CDS Gain
Maximum Input Voltage
−3 dB CDS Gain
0 dB CDS Gain (Default)
+3 dB CDS Gain
VGA gain = 6.3 dB, Code 15 (default value)
1.4
1.0
0.7
0.5
V p-p
V p-p
V p-p
V p-p
+6 dB CDS Gain
Allowable Optical Black Pixel Amplitude
0 dB CDS Gain (Default)
+6 dB CDS Gain
–100
–50
+200
+100
mV
mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
1024
Guaranteed
Steps
Low Gain Setting
Maximum Gain Setting
BLACK LEVEL CLAMP
6
42
dB
dB
VGA Code 15 (default)
VGA Code 1023
Clamp Level Resolution
Minimum Clamp Level (Code 0)
Maximum Clamp Level (Code 1023)
ANALOG-TO-DIGITAL CONVERTER (ADC)
Resolution
1024
0
1023
Steps
LSB
LSB
Measured at ADC output
Measured at ADC output
14
–1.0
Bits
LSB
Differential Nonlinearity (DNL)
No Missing Codes
0.5
Guaranteed
5
2.0
+1.2
16
Integral Nonlinearity (INL)
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
SYSTEM PERFORMANCE
VGA Gain Accuracy
LSB
V
1.4
0.4
V
V
Specifications include entire signal chain
0 dB CDS gain (default)
Low Gain (Code 15)
5.1
41.3
5.6
41.8
0.1
2
6.1
42.3
0.4
dB
dB
%
LSB rms
dB
Gain = (0.0359 × code) + 5.1 dB
Maximum Gain (Code 1023)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
12 dB total gain applied
AC grounded input, 6 dB gain applied
Measured with step change on supply
Power Supply Rejection (PSR)
45
1 Input signal characteristics are defined as shown in Figure 2.
MAXIMUM INPUT LIMIT =
LESSER OF 2.2V
OR (AVDD + 0.3V)
+1.8V TYP (AVDD)
800mV
MAXIMUM
+1.3V TYP (AVDD – 0.5V)
DC RESTORE VOLTAGE
500mV TYP
RESET TRANSIENT
1V MAXIMUM INPUT
SIGNAL RANGE
(0dB CDS GAIN)
200mV MAX
OPTICAL BLACK PIXEL
0V (AVSS)
MINIMUM INPUT LIMIT
(AVSS – 0.3V)
Figure 2. Input Signal Characteristics
Rev. C | Page 6 of 56
AD9979
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
θJA is measured using a 4-layer printed circuit board (PCB) with
the exposed paddle soldered to the board.
With
Parameter
AVDD
DVDD
Respect To Rating
AVSS
DVSS
−0.3 V to +2.2 V
−0.3 V to +2.2 V
Table 6.
Package Type
θJA
Unit
DRVDD
IOVDD
DRVSS
DVSS
−0.3 V to +3.9 V
−0.3 V to +3.9 V
48-Lead, 7 mm × 7 mm LFCSP
25.8
°C/W
HVDD
HVSS
−0.3 V to +3.9 V
RGVDD
Any VSS
RGVSS
Any VSS
RGVSS
HVSS
DVSS
AVSS
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to RGVDD + 0.3 V
−0.3 V to HVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.2 V to AVDD + 0.2 V
ESD CAUTION
RG Output
H1 to H4, HL Output
SCK, SL, SDI
REFT, REFB, CCDINM,
CCDINP
Junction Temperature
Lead Temperature (10 sec)
150°C
350°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. C | Page 7 of 56
AD9979
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
36 REFB
D2
D3
D4
D5
D6
PIN 1
INDICATOR
REFT
AVDD
2
3
4
5
6
7
35
34
33 AVSS
32
CCDINM
31 CCDINP
AD9979
TOP VIEW
DRVSS
DRVDD
D7
AVDD
AVSS
30
29
(Not to Scale)
8
9
28 CLI
D8
10
11
12
27 LDOOUT
26 IOVDD
25 RG
D9
D10
D11
NC = NO CONNECT
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
2
3
4
5
6
7
8
D2
D3
D4
D5
DO
DO
DO
DO
DO
P
Data Output
Data Output
Data Output
Data Output
D6
Data Output
DRVSS
DRVDD
D7
D8
D9
D10
D11
D12
D13 (MSB)
NC
H1
H2
HVSS
HVDD
H3
H4
RGVSS
HL
RGVDD
RG
IOVDD
LDOOUT
Digital Driver Ground
Digital Driver Supply (1.8 V or 3 V)
Data Output
Data Output
Data Output
Data Output
Data Output
Data Output
Data Output
P
DO
DO
DO
DO
DO
DO
DO
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Not Connected
DO
DO
P
CCD Horizontal Clock 1
CCD Horizontal Clock 2
H1 to H4 Driver Ground
H1 to H4 Driver Supply (3 V)
CCD Horizontal Clock 3
CCD Horizontal Clock 4
RG Driver Ground
CCD Last Horizontal Clock
RG Driver Supply (3 V)
CCD Reset Gate Clock
P
DO
DO
P
DO
P
DO
P
P
Digital I/O Supply (1.8 V or 3 V)/LDO Input Voltage (3 V)
LDO Output Voltage (1.8 V)
Rev. C | Page 8 of 56
AD9979
Pin No.
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Mnemonic
CLI
Type1
DI
P
P
AI
AI
P
P
AO
AO
DI
DI
DI
Description
Master Clock Input
Analog Ground for AFE
Analog Supply for AFE (1.8 V)
CCD Signal Positive Input
CCD Signal Negative Input; Normally Tied to AVSS
Analog Ground for AFE
Analog Supply for AFE (1.8 V)
Reference Top Decoupling (Decouple with 1.0 μF to AVSS)
Reference Bottom Decoupling (Decouple with 1.0 μF to AVSS)
LDO Output Enable; 3 V = LDO Enabled, GND = LDO Disabled
3-Wire Serial Load
3-Wire Serial Data Input
3-Wire Serial Clock
General-Purpose Input/Output 1
General-Purpose Input/Output 2
Vertical Sync Pulse
Horizontal Sync Pulse
Digital Ground
Digital Supply (1.8 V)
Data Output
AVSS
AVDD
CCDINP
CCDINM
AVSS
AVDD
REFT
REFB
LDOEN
SL
SDI
SCK
GPO1
GPO2
VD
DI
DIO
DIO
DI
DI
P
P
DO
DO
HD
DVSS
DVDD
D0 (LSB)
D1
Data Output
EPAD
The exposed pad must be connected to GND.
1 AI = analog input, AO = analog output, DI = digital input, DO = digital output, DIO = digital input/output, P = power.
Rev. C | Page 9 of 56
AD9979
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
250
200
0.6
TOTAL POWER
0.4
150
0.2
3.3V SUPPLIES
0
100
–0.2
–0.4
–0.6
–0.8
–1.0
50
1.8V SUPPLIES
0
40
45
50
55
60
65
0
2k
4k
6k
8k
10k
12k
14k
16k
ADC OUTPUT CODE
SAMPLE RATE (MHz)
Figure 6. Differential Nonlinearity (DNL)
Figure 4. Power vs. Sample Rate
10
8
180
160
140
120
100
80
6
4
2
0
–2
–4
–6
–8
60
40
20
0
0
5
10
15
20
25
30
35
40
45
0
2k
4k
6k
8k
10k
12k
14k
16k
ADC OUTPUT CODE
VGA GAIN (dB)
Figure 5. RMS Output Noise vs. VGA Gain
Figure 7. System Integral Nonlinearity (INL)
Rev. C | Page 10 of 56
AD9979
EQUIVALENT INPUT/OUTPUT CIRCUITS
IOVDD
AVDD
330Ω
R
AVSS
AVSS
DVSS
Figure 8. CCD Input
Figure 10. Digital Inputs
HVDD OR RGVDD
DATA
OUTPUT
ENABLE
IOVDD
330Ω
100kΩ
CLI
+
AVSS
HVSS OR RGVSS
Figure 9. CLI Input, Register 0x15[0] =1 Enables the Bias Circuit
Figure 11. H1 to H4, HL, and RG Outputs
Rev. C | Page 11 of 56
AD9979
THEORY OF OPERATION
All AD9979 clocks are synchronized with VD and HD inputs.
All of the horizontal pulses (CLPOB, PBLK, and HBLK) of the
AD9979 are programmed and generated internally.
V DRIVER
V1 > Vx, VSG1 > VSGx, SUBCK
H1 TO H4, HL, RG
The H drivers for H1 to H4 and RG are included in the AD9979,
allowing these clocks to be directly connected to the CCD.
The H-drive voltage of 3 V is supported in the AD9979.
D0 TO D13
CCDINM/
CCDINP
AD9979
CCD
DIGITAL IMAGE
PROCESSING
ASIC
Figure 13 and Figure 14 show the maximum horizontal and
vertical counter dimensions for the AD9979.These counters
control all internal horizontal and vertical clocking, to specify
line and pixel locations. The maximum HD length is 8191 pixels
per line, and the maximum VD length is 8192 lines per field.
INTEGRATED
AFE + TD
HD, VD
CLI
GPO1, GPO2
SERIAL
INTERFACE
Figure 12. Typical Application
Figure 12 shows the typical application for the AD9979. The
CCD output is processed by the AFE circuitry of the AD9979,
which consists of a CDS, a VGA, a black-level clamp, and an
ADC. The digitized pixel information is sent to the digital
image processor chip, which performs the post-processing and
compression. To operate the CCD, all CCD timing parameters
are programmed into the AD9979 from the system ASIC, through
the 3-wire serial interface. From the system master clock, CLI,
provided by the image processor or an external crystal, the
AD9979 generates the horizontal clocks of the CCD and all
internal AFE clocks.
13-BIT HORIZONTAL = 8192 PIXELS MAX
13-BIT VERTICAL = 8192 LINES MAX
Figure 13. Maximum Dimensions for Vertical and Horizontal Counters
MAX VD LENGTH IS 8192 LINES
VD
MAX HD LENGTH IS 8192 PIXELS
HD
CLI
Figure 14. Maximum VD and HD Dimensions
Rev. C | Page 12 of 56
AD9979
PROGRAMMABLE TIMING GENERATION
Using a 65 MHz CLI frequency, the edge resolution of the
PRECISION TIMING HIGH SPEED TIMING CORE
Precision Timing core is approximately 240 ps. If a 1× system
clock is not available, it is also possible to use a 2× reference
clock, by programming the CLIDIVIDE register (Address 0x0D).
The AD9979 then internally divides the CLI frequency by 2.
The AD9979 generates flexible high speed timing signals using
the Precision Timing core. This core is the foundation for
generating the timing for both the CCD and the AFE; the reset
gate (RG), the HL, Horizontal Driver H1 to Horizontal Driver
H4, and the SHP and SHD sample clocks. A unique architecture
makes it routine for the system designers to optimize image
quality by providing precise control over the horizontal CCD
readout and the AFE-correlated double sampling.
High Speed Clock Programmability
Figure 16 shows how the high speed clocks, RG, HL, H1 to H4,
SHP, and SHD, are generated. The RG pulse has programmable
rising and falling edges and can be inverted using the polarity
control. The HL, H1, and H2 horizontal clocks have separate
programmable rising and falling edges and polarity control. The
AD9979 provides additional HCLK mode programmability, see
Table 8.
Timing Resolution
The Precision Timing core uses a master clock input (CLI) as a
reference. This clock is recommended to be the same as the
CCD pixel clock frequency. Figure 15 illustrates how the internal
timing core divides the master clock period into 64 steps, or
edge positions. Therefore, the edge resolution of the Precision
Timing core is tCLI/64. (For more information on using the
CLI input, refer to the Applications Information section.)
The edge location registers are each six bits wide, allowing the
selection of all 64 edge locations. Figure 19 shows the default
timing locations for all of the high speed clock signals.
POSITION
CLI
P[0]
P[16]
P[32]
P[48]
P[64] = P[0]
tCLIDLY
1 PIXEL
PERIOD
tCONV
NOTES
1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 64 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (tCLIDLY).
Figure 15. High Speed Clock Resolution From CLI Master Clock Input
1
CCD
2
SIGNAL
3
5
4
RG
6
8
H1, H3
H2, H4
7
HL
PROGRAMMABLE CLOCK POSITIONS:
1
SHP SAMPLE LOCATION.
SHD SAMPLE LOCATION.
RG RISING EDGE.
RG FALLING EDGE.
H1 RISING EDGE.
H1 FALLING EDGE.
HL RISING EDGE.
HL FALLING EDGE.
2
3
4
5
6
7
8
Figure 16. High Speed Clock Programmable Locations (HCLKMODE = 1)
Rev. C | Page 13 of 56
AD9979
1
2
H1, H3
H2, H4
4
3
H1 TO H4 PROGRAMMABLE LOCATIONS:
1
H1 RISING EDGE.
2
H1 FALLING EDGE.
3
H2 RISING EDGE.
4
H2 FALLING EDGE.
Figure 17. HCLK Mode 2 Operation
1
2
H1
H2
H3
H4
3
4
H1 TO H4 PROGRAMMABLE LOCATIONS:
1
H1 RISING EDGE.
2
H1 FALLING EDGE.
3
H3 RISING EDGE.
4
H3 FALLING EDGE.
Figure 18. HCLK Mode 3 Operation
POSITION
CLI
P[0]
P[16]
P[32]
P[48]
P[64] = P[0]
RGr[0]
H1r[0]
RGf[16]
RG
H1
H2
H1f[32]
tS1
CCD
SIGNAL
SHPLOC[32]
SHP
SHD
tSHPINH
SHDLOC[0]
tSHDINH
DATAPHASEP[32]
tDOUTINH
DOUTPHASEP
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN 1 PIXEL PERIOD.
TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN.
2. CERTAIN POSITIONS MUST BE AVOIDED FOR EACH SIGNAL, SHOWN ABOVE AS INHIBIT REGIONS.
3. IF A SETTING IN THE INHIBIT REGION IS USED, AN UNSTABLE PIXEL SHIFT CAN OCCUR IN THE HBLK LOCATION OR AFE PIPELINE.
Figure 19. High Speed Timing Default Locations
Rev. C | Page 14 of 56
AD9979
Table 8. HCLK Modes (Selected by Register Address 0x23, Bits[7:5])
HCLK Mode
Register Value
Description
Mode 1
001
010
H1 edges are programmable; H3 = H1, H2 = H4 = inverse of H1.
Mode 2
H1 edges are programmable; H3 = H1.
H2 edges are programmable; H4 = H2.
Mode 3
100
H1 edges are programmable; H2 = inverse of H1.
H3 edges are programmable; H4 = inverse of H3.
Invalid Selection
000, 011, 101, 110, 111
Invalid register settings.
Table 9. Horizontal Clock, RG, Drive, and Sample Control Registers Parameters
Name
Length
Range
Description
Polarity
1 bit
High/low
Polarity control for H1/H3 and RG; 0 = no inversion, 1 = inversion
Positive edge location for H1/H3 and RG
Negative edge location for H1/H3 and RG
Sampling location for SHP and SHD
Drive current for H1 to H4 and RG outputs (4.3 mA steps)
Positive Edge
Negative Edge
Sample Location
Drive Control
6 bits
6 bits
6 bits
3 bits
0 to 63 edge location
0 to 63 edge location
0 to 63 sample location
0 to 7 current steps
CLI
tCLIDLY
N+15 N+16 N+17
N
N+1
N+2
N+5
N+6
N+7
N+8
N+9 N+10 N+11 N+12 N+13 N+14
N+3
N+4
CCDIN
SAMPLE PIXEL N
SHD
(INTERNAL)
ADC OUT
(INTERNAL)
N–17 N–16 N–15 N–14 N–13 N–12 N–11 N–10
tDOUTINH
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
DOUTPHASE
CLK
PIPELINE LATENCY = 16 CYCLES
N–17 N–16 N–15 N–14 N–13 N–12 N–11 N–10 N–9 N–8 N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
DOUT
NOTES
1. EXAMPLE SHOWN FOR SHDLOC = 0.
2. HIGHER VALUES OF SHD AND/OR DOUTPHASE SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
Figure 20. Pipeline Delay of AFE Data Outputs
H-Driver and RG Outputs
Digital Data Outputs
In addition to the programmable timing positions, the AD9979
features on-chip output drivers for the HL, RG, and H1 to H4
outputs. These drivers are powerful enough to directly drive
the CCD inputs. The H-driver and RG-driver currents can be
adjusted for optimum rise/fall times into a particular load by
using the drive strength control register (Address 0x35). Use
the register to adjust the drive strength in 4.3 mA increments.
The minimum setting of 0 is equal to off or three-state, and the
maximum setting of 7 is equal to 30.1 mA.
For maximum system flexibility, the AD9979 uses DOUTPHASEN
and DOUTPHASEP (Address 0x37, Bits[11:0]) to select the
location for the start of each new pixel data value. Any edge
location from 0 to 63 can be programmed. Register 0x37
determines the start location of the data output and the
DOUTPHASEx clock rising edge with respect to the master
clock input CLI.
The pipeline delay through the AD9979 is shown in Figure 20.
After the CCD input is sampled by SHD, there is a 16-cycle
delay before the data is available.
Rev. C | Page 15 of 56
AD9979
Figure 32 shows how the sequence change positions divide the
readout field into different regions. By assigning a different
H-pattern to each region, the CLPOB and PBLK signals can
change with each change in the vertical timing.
HORIZONTAL CLAMPING AND BLANKING
The horizontal clamping and blanking pulses of the AD9979 are
fully programmable to suit a variety of applications. Individual
control is provided for CLPOB, PBLK, and HBLK during the
different regions of each field. This allows the dark-pixel clamping
and blanking patterns to be changed at each stage of the readout
to accommodate the different image transfer timing and high
speed line shifts.
CLPOB and PBLK Masking Area
Additionally, the AD9979 allows the CLPOB and PBLK signals
to be disabled during certain lines in the field, without changing
any of the existing pattern settings. There are three sets of start
and end registers for both CLPOB and PBLK that allows the
creation of up to three masking areas for each signal.
Individual CLPOB and PBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK,
as shown in Figure 21. These two signals are independently
programmed using the registers in Table 10. The start polarity
for the CLPOB (PBLK) signal is CLPOB_POL (PBLK_POL),
and the first and second toggle positions of the pulse are
CLPOBx_TOG1 (PBLKx_TOG1) and CLPOBx_TOG2
(PBLKx_TOG2), respectively. Both signals are active low
and need to be programmed accordingly.
For example, to use the CLPOB masking, program the
CLPOBMASKSTARTx and CLPOBMASKENDx registers to
specify the starting and ending lines in the field where the
CLPOB patterns are to be ignored. Figure 22 illustrates this
feature.
The masking registers are not specific to a certain H-pattern;
they are always active for any existing field of timing. To disable
the CLPOB and PBLK masking feature, set these registers to the
maximum value of 0x1FFF.
Two separate patterns for CLPOB and PBLK can be programmed
for each H-pattern, CLPOB0, CLPOB1, PBLK0, and PBLK1.
The CLPOB_PAT and PBLK_PAT field registers select which
of the two patterns are used in each field.
Note that to disable CLPOB and PBLK masking during
power-up, it is recommended to set CLPOBMASKSTARTx
(PBLKMASKSTARTx) to 8191 and CLPOBMASKENDx
(PBLKMASKENDx) to 0. This prevents any accidental masking
caused by different register update events.
HD
2
3
CLPOB
PBLK
1
ACTIVE
ACTIVE
PROGRAMMABLE SETTINGS:
1
2
START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW).
FIRST TOGGLE POSITION.
3
SECOND TOGGLE POSITION.
Figure 21. Clamp and Preblank Pulse Placement
NO CLPOB SIGNAL
FOR LINES 6 TO 8
NO CLPOB SIGNAL
FOR LINE 600
VD
0
1
2
597 598
HD
CLPOB
CLPOBMASKSTART1 = 6 CLPOBMASKEND1 = 8 CLPOBMASKSTART2 = CLPOBMASKEND2 = 600
Figure 22. CLPOB Masking Example
Rev. C | Page 16 of 56
AD9979
Table 10. CLPOB and PBLK Registers
Name
Length
13 bits
13 bits
13 bits
13 bits
9 bits
Range
Description
CLPOB0_TOG1
CLPOB0_TOG2
CLPOB1_TOG1
CLPOB1_TOG2
CLPOB_POL
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
High/low
First CLPOB0 toggle position within the line for each V-sequence.
Second CLPOB0 toggle position within the line for each V-sequence.
First CLPOB1 toggle position within the line for each V-sequence.
Second CLPOB1 toggle position within the line for each V-sequence.
Starting polarity of CLPOB for each V-sequence[8:0] (in field registers).
CLPOB pattern selection for each V-sequence[8:0] (in field registers).
CLPOB mask start position. Three values available (in field registers).
CLPOB mask end position. Three values available (in field registers).
First PBLK0 toggle position within the line for each V-sequence.
Second PBLK0 toggle position within the line for each V-sequence.
First PBLK1 toggle position within the line for each V-sequence.
Second PBLK1 toggle position within the line for each V-sequence.
Starting polarity of PBLK for each V-sequence[8:0] (in field registers).
PBLK pattern selection for each V-sequence[8:0] (in field registers).
PBLK mask start position. Three values available (in field registers).
PBLK mask end position. Three values available (in field registers).
CLPOB_PAT
9 bits
0 to 9 settings
CLPOBMASKSTARTx
CLPOBMASKENDx
PBLK0_TOG1
PBLK0_TOG2
PBLK1_TOG1
PBLK1_TOG2
PBLK_POL
PBLK_PAT
PBLKMASKSTARTx
PBLKMASKENDx
13 bits
13 bits
13 bits
13 bits
13 bits
13 bits
9 bits
9 bits
13 bits
13 bits
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
High/low
0 to 9 settings
0 to 8191 pixel location
0 to 8191 pixel location
HD
HBLKTOGE1
HBLKTOGE2
BLANK
BLANK
HBLK
BASIC HBLK PULSE IS GENERATED USING HBLKTOGE1 AND HBLKTOGE2 (HBLKALT_PATx = 0).
Figure 23. Typical Horizontal Blanking Pulse Placement (HBLKMODE = 0)
HD
HBLK
H1/H3
THE POLARITY OF H1/H3 DURING BLANKING IS PROGRAMMABLE
(H2/H4 AND HL POLARITIES ARE SEPARATELY PROGRAMMABLE).
H1/H3
H2/H4
Figure 24. HBLK Masking Control
Rev. C | Page 17 of 56
AD9979
Individual HBLK Patterns
HBLK Mode 0 Operation
The HBLK programmable timing shown in Figure 23 is similar
to CLPOB and PBLK; however, there is no start polarity control.
Only the toggle positions designate the start and the stop positions
of the blanking period. Additionally, as shown in Figure 24,
there is a polarity control, HBLKMASK, for H1/H3 and H2/H4
that designates the polarity of the horizontal clock signals
during the blanking period. Setting HBLKMASK_H1 low sets
H1 = H3 = low and HBLKMASK_H2 high sets H2 = H4 = high
during the blanking. As with the CLPOB and PBLK signals,
HBLK registers are available in each H-pattern group, allowing
unique blanking signals to be used with different vertical timing
sequences.
There are six toggle positions available for HBLK. Normally,
only two of the toggle positions are used to generate the
standard HBLK interval. However, the additional toggle
positions can be used to generate special HBLK patterns, as
shown in Figure 25. The pattern in this example uses all six
toggle positions to generate two extra groups of pulses during
the HBLK interval. By changing the toggle positions, different
patterns are created.
Separate toggle positions are available for even and odd lines. If
alternation is not needed, load the same values into both the
HBLKTOGEx and HBLKTOGOx registers.
The AD9979 supports three different modes for HBLK
operation. HBLK Mode 0 supports basic operation and offers
some support for special HBLK patterns. HBLK Mode 1
supports pixel mixing HBLK operation. HBLK Mode 2 supports
advanced HBLK operation. The following sections describe
each mode. Register names are detailed in Table 11.
HBLKTOGE2
HBLKTOGE4
HBLKTOGE3
HBLKTOGE6
HBLKTOGE5
HBLKTOGE1
HBLK
H1/H3
H2/H4
SPECIAL HBLK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS (HBLKALT_PATx = 0).
Figure 25. Generating Special HBLK Patterns
Table 11. HBLK Pattern Registers
Name
Length Range
Description
HBLKMODE
2 bits
0 to 2
Enables different HBLK toggle position operation.
0 = normal mode. Six toggle positions are available for even and odd lines. If even/
odd alternation is not need, set the toggle positions for the even/odd the same.
1 = pixel mixing mode. Instead of only six toggle positions, use the HBLKSTART,
HBLKEND, HBLKLEN, and HBLKREP registers, along with HBLKTOGOx and
HBLKTOGEx. If even/odd alternation is not need, set the even/odd toggles the same.
2 = advanced HBLK mode. It divides HBLK interval into six different repeat areas.
It uses HBLKSTARTA, HBLKSTARTB, HBLKSTARTC, and RAxHyREPA/RAxHyREPB/
RAxHyREPC registers.
3 = test mode. Do not access.
HBLKSTART
HBLKEND
HBLKLEN
HBLKREP
13 bits
13 bits
13 bits
13 bits
0 to 8191 pixel location Start location for HBLK in HBLK Mode 1 and HBLK Mode 2.
0 to 8191 pixel location End location for HBLK in HBLK Mode 1 and HBLK Mode 2.
0 to 8191 pixels
0 to 8191 repetitions
High/low
HBLK length in HBLK Mode 1 and HBLK Mode 2.
Number of HBLK repetitions in HBLK Mode 1 and HBLK Mode 2.
Masking polarity for H1/H3 during HBLK.
HBLKMASK_H1 1 bit
HBLKMASK_H2 1 bit
HBLKMASK_HL 1 bit
High/low
Masking polarity for H2/H4 during HBLK.
High/low
Masking polarity for HL during HBLK.
Rev. C | Page 18 of 56
AD9979
Name
Length Range
Description
HBLKTOGO1
HBLKTOGO2
HBLKTOGO3
HBLKTOGO4
HBLKTOGO5
HBLKTOGO6
HBLKTOGE1
HBLKTOGE2
HBLKTOGE3
HBLKTOGE4
HBLKTOGE5
HBLKTOGE6
RAxHyREPz1
13 bits
13 bits
13 bits
13 bits
13 bits
13 bits
13 bits
13 bits
13 bits
13 bits
13 bits
13 bits
12 bits
0 to 8191 pixel location First HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
0 to 8191 pixel location Second HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
0 to 8191 pixel location Third HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
0 to 8191 pixel location Fourth HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
0 to 8191 pixel location Fifth HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
0 to 8191 pixel location Sixth HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
0 to 8191 pixel location First HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
0 to 8191 pixel location Second HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
0 to 8191 pixel location Third HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
0 to 8191 pixel location Fourth HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
0 to 8191 pixel location Fifth HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1
0 to 8191 pixel location Sixth HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
0 to 15 HCLK pulses
HBLK Mode 2 even field Repeat Area x. Number of Hy repetitions for HBLKSTARTz
even lines.2
Bits[3:0]: number of Hy pulses following HBLKSTARTA.
Bits[7:4]: number of Hy pulses following HBLKSTARTB.
Bits[11:8]: number of Hy pulses following HBLKSTARTC.
HBLKSTARTA
HBLKSTARTB
HBLKSTARTC
13 bits
13 bits
13 bits
0 to 8191 pixel location HBLK Repeat Area Start Position A for HBLK Mode 2.
0 to 8191 pixel location HBLK Repeat Area Start Position B for HBLK Mode 2.
0 to 8191 pixel location HBLK Repeat Area Start Position C for HBLK Mode 2.
0 to 5 even repeat area HBLK Mode 2 odd field Repeat Area x pattern. Selected from even field repeat areas.4
HBLKALT_PATx3 3 bits
1 The variable x represents the repeat area, from 0 to 5. The variable y represents the horizontal driver, 1 or 2. The variable z represents the HBLK repeat area start
position for HBLK Mode 2, A, B, or C.
2 Odd lines defined using HBLKALT_PATx.
3 The variable x represents the repeat area, from 0 to 5.
4 Even lines defined using RAxHyREPz; also see Note 1.
HBLKTOGE2
HBLKSTART HBLKTOGE1 HBLKTOGE3
HBLKTOGE4
HBLKEND
HBLK
HBLKLEN
HBLKREP = 3
H1/H3
H2/H4
HBLKREP NUMBER 1
HBLKREP NUMBER 2
HBLKREP NUMBER 3
HBLK REPEATING PATTERN IS CREATED USING HBLKLEN AND HBLKREP REGISTERS.
Figure 26. HBLK Repeating Pattern Using HBLK Mode 1 (Register Value = 1)
HBLK Mode 1 Operation
Generating HBLK Line Alternation
Multiple repeats of the HBLK signal can be enabled by setting
HBLKMODE to 1. In this mode, the HBLK pattern is generated
using a different set of registers: HBLKSTART, HBLKEND,
HBLKLEN, and HBLKREP, along with the six toggle positions
(see Figure 26).
HBLK Mode 0 and HBLK Mode 1 provide the ability to alternate
HBLK toggle positions on even and odd lines for which separate
toggle positions are available. If even/odd line alternation is not
required, load the same values into the registers for the even
lines (HBLKTOGEx) as the odd (HBLKTOGOx) lines.
Rev. C | Page 19 of 56
AD9979
Increasing Horizontal Clock Width During HBLK
The reduced frequency occurs only for H1 to H4 pulses that are
located within the HBLK area.
HBLK Mode 0 and HBLK Mode 1 allow the H1 to H4 pulse width
to increase during the HBLK interval. As shown in Figure 27,
the horizontal clock frequency can reduce by a factor of 1/2,
1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30 (see Table 12). To
enable this feature, the HCLK_WIDTH register (Address 0x34,
Bits[7:4]) is set to a value between 1 and 15. When this register
is set to 0, the wide HCLK feature is disabled.
The HCLK_WIDTH feature is generally used in conjunction
with special HBLK patterns to generate vertical and horizontal
mixing in the CCD.
Note that the wide HCLK feature is available only in HBLK
Mode 0 and HBLK Mode 1, and not in HBLK Mode 2.
Table 12. HCLK Width Register
Name
Length
Description
HCLK_WIDTH
4 bits
Controls H1 to H4 width during HBLK as a fraction of pixel rate.
0 = same frequency as pixel rate
1 = 1/2 pixel frequency, that is, doubles the HCLK pulse width
2 = 1/4 pixel frequency
3 = 1/6 pixel frequency
4 = 1/8 pixel frequency
5 = 1/10 pixel frequency
6 = 1/12 pixel frequency
7 = 1/14 pixel frequency
8 = 1/16 pixel frequency
9 = 1/18 pixel frequency
10 = 1/20 pixel frequency
11 = 1/22 pixel frequency
12 = 1/24 pixel frequency
13 = 1/26 pixel frequency
14 = 1/28 pixel frequency
15 = 1/30 pixel frequency
HBLK
H1/H3
H2/H4
1/fPIX
2 × (1/fPIX
)
HORIZONTAL CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS SHOWN),
1/4, 1/6, 1/8, 1/10, 1/12, AND SO ON, UP TO 1/30 USING HBLK_WIDTH REGISTER.
Figure 27. Generating Wide Horizontal Clock Pulses During HBLK Interval
Rev. C | Page 20 of 56
AD9979
Figure 28 shows the example
HBLK Mode 2 Operation
RA0H1REPA/RA0H1REPB/RA0H1REPC =
RA0H2REPA/RA0H2REPB/RA0H2REPC =
RA1H1REPA/RA1H1REPB/RA1H1REPC =
RA1H2REPA/RA1H2REPB/RA1H2REPC = 2.
HBLK Mode 2 allows more advanced HBLK pattern operation.
If unevenly spaced, multiple areas of HCLK pulses are needed;
therefore, use HBLK Mode 2. Using a separate set of registers,
HBLK Mode 2 can divide the HBLK region into up to six
different repeat areas (see Table 11). As shown in Figure 28,
each repeat area shares a common group of toggle positions,
HBLKSTARTA, HBLKSTARTB, and HBLKSTARTC. However, the
number of toggles following each HBLKSTARTA, HBLKSTARTB,
and HBLKSTARTC position can be unique in each repeat area
by using RAxHyREPz, where x represents the repeat area, from 0
to 5, y represents the horizontal driver, 1 or 2, and z represents the
HBLK repeat area start position for HBLK Mode 2, A, B, or C.
As shown in Figure 29, setting the RAxH1REPA/RAxH1REPB/
RAxH1REPC or RAxH2REPA/RAxH2REPB/RAxH2REPC
registers to 0 masks the HCLK groups from appearing in a
particular repeat area. Figure 28 shows only two repeat areas
being used, although up to six are available. It is possible to
program a separate number of repeat area repetitions for H1
and H2, but generally, the same value is used for both H1 and H2.
Furthermore, HBLK Mode 2 allows a different HBLK pattern
on even and odd lines. HBLKSTARTA, HBLKSTARTB, and
HBLKSTARTC, as well as RAxH1REPA/RAxH1REPB/
RAxH1REPC and RAxH2REPA/RAxH2REPB/RAxH2REPC,
define operation for the even lines. For separate control of the
odd lines, the HBLKALT_PATx registers specify up to six repeat
areas on the odd lines by reordering the repeat areas used for the
even lines. New patterns are not available, but the order of the
previously defined repeat areas on the even lines can be changed
for the odd lines to accommodate advanced CCD operation.
HD
HBLKLEN
HBLK
HBLKSTARTA
ALL RAxHyREPz REGISTERS = 2, TO CREATE 2 HCLK PULSES
HBLKSTARTB
HBLKSTARTC
H1
RA0H1REPB
RA0H1REPC
RA0H2REPC
RA1H1REPA
RA1H1REPB
RA0H1REPA
RA0H2REPA
RA1H1REPC
RA1H2REPC
H2
HBLKSTART
RA1H2REPA RA1H2REPB
RA0H2REPB
HBLKEND
REPEAT AREA 0
REPEAT AREA 1
HBLKREP = 2
TO CREATE 2 REPEAT AREAS
Figure 28. HBLK Mode 2 Registers
CREATE UP TO 3 GROUPS OF TOGGLES
A, B, C COMMON IN ALL REPEAT AREAS
HD
CHANGE NUMBER OF A, B, C PULSES IN ANY
REPEAT AREA USING RAxHyREPz REGISTERS
MASK A, B, C PULSES IN ANY REPEAT
AREA BY SETTING RAxHyREPz = 0
A
B
C
H1
H2
REPEAT AREA 0 REPEAT AREA 1 REPEAT AREA 2 REPEAT AREA 3 REPEAT AREA 4 REPEAT AREA 5
HBLKSTART
HBLKEND
Figure 29. HBLK Mode 2 Operation
Rev. C | Page 21 of 56
AD9979
Note that toggle positions cannot be programmed during the
12-cycle delay from the HD falling edge until the horizontal
counter has reset. See Figure 31 for an example of this restriction.
HBLK, PBLK, and CLPOB Toggle Positions
The AD9979 uses an internal horizontal pixel counter to position
the HBLK, PBLK, and CLPOB toggle positions. The horizontal
counter does not reset to 0 until 12 CLI periods after the falling
edge of HD. This 12-cycle pipeline delay must be considered
when determining the register toggle positions. For example, if
CLPOBx_TOGy is 100 and the pipeline delay is not considered,
the final toggle position is applied at 112. To obtain the correct
toggle positions, the toggle position registers must be set to the
desired toggle position minus 12. For example, if the desired
toggle position is 100, CLPOBx_TOGy needs to be set to 88,
that is, 100 minus 12. Figure 53 shows the 12-cycle pipeline delay
referenced to the falling edge of HD.
0
60
100 103
112
PIXEL NO.
HD
1
2
H1
3
4
CLPOB
DESIRED
TOGGLE
ACTUAL
REGISTER
POSITION VALUE
1
2
3
4
HBLKTOGE1/HBLKTOGO1
HBLKTOGE2/HBLKTOGO2
CLPOBx_TOG1
60
(60 – 12) = 48
100
103
112
(100 – 12) = 88
(103 – 12) = 91
(112 – 12) = 100
CLPOBx_TOG2
Figure 30. Example of Register Setting to Obtain Desired Toggle Positions
VD
HD
H-COUNTER
RESET
NO TOGGLE POSITIONSALLOWED IN THIS AREA
H-COUNTER
(PIXEL COUNTER)
X
X
X
X
N-12 N-11 N-10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1
N
0
1
2
NOTES
1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 12 PIXELS OF PIXEL 0 LOCATION.
Figure 31. Restriction for Toggle Position Placement
Rev. C | Page 22 of 56
AD9979
H-Pattern Selection
COMPLETE FIELD—COMBINING H-PATTERNS
The H-patterns are stored in the HPAT memory, as described in
Table 33. The user decides how many H-pattern groups are
required, up to a maximum of 32, and then uses the HPAT_SELx
registers to select which H-pattern group is output in each
region of the field. Figure 32 shows how to use the HPAT_SELx
and SCPx registers. The SCPx registers create the line
boundaries for each region.
After creating the H-patterns, they combine to create different
readout fields. A field consists of up to nine different regions
determined by the SCP registers, and within each region, a
different H-pattern group can be selected, up to a maximum of
32 groups. Registers to control the H-patterns are located in the
field registers. Table 13 describes the field registers.
SCP 0
SCP 1
SCP 2
SCP 3
SCP 4
SCP 5
SCP 8
VD
HD
REGION 0
REGION 1
REGION 2
REGION 3
REGION 4
REGION 8
H-PATTERNS
HPAT_SEL0
HPAT_SEL1
HPAT_SEL8
HPAT_SEL2
HPAT_SEL3
HPAT_SEL4
FIELD SETTINGS:
1. SEQUENCE CHANGE POSITIONS (SCP0 TO SCP8) DEFINE EACH OF THE NINE AVAILABLE REGIONS IN THE FIELD.
2. HPAT_SEL SELECTS THE DESIRED H-PATTERN FOR EACH REGION.
Figure 32. Complete Field Divided into Regions
Table 13. Field Registers
Name
Length Range
Description
SCPx
13 bits
5 bits
9 bits
9 bits
0 to 8191 line number
0 to 31 H-patterns
High/low
Sequence change position for each region; selects an individual line
Selected H-pattern for each region of the field
CLPOB start polarity settings for each region of the field
CLPOB pattern selector for each region of the field
HPAT_SELx
CLPOB_POL
CLPOB_PAT
0 to 9 patterns
CLPOBMASKSTARTx,
CLPOBMASKENDx
13 bits
Number of lines
CLPOB mask positions for up to three masking configurations
PBLK_POL
PBLK_PAT
9 bits
9 bits
High/low
0 to 9 patterns
PBLK start polarity settings for each region of the field
PBLK pattern selector for each region of the field
PBLKMASKSTARTx,
PBLKMASKENDx,
13 bits
Number of lines
PBLK mask positions for up to three masking configurations
Rev. C | Page 23 of 56
AD9979
A basic still camera application can require five different fields
of horizontal timing: one for draft mode operation, one for auto
focusing, and three for still-image readout. With the AD9979,
all register timing information for the five fields is loaded at
startup. Then, during camera operation, the mode registers
selects which field timing to activate depending on how the
camera is being used.
MODE REGISTERS
To select the final field timing of the AD9979, use the mode
registers. Typically, all of the field and H-pattern group
information is programmed into the AD9979 at startup.
During operation, the mode registers allows the user to
select any combination of field timing to meet the current
requirements of the system. The advantage of using the mode
registers in conjunction with preprogrammed timing is that it
greatly reduces the system programming requirements during
camera operation. Only a few register writes are required when
the camera operating mode is changed, rather than having to
write in all of the vertical timing information with each camera
mode change.
The AD9979 supports up to seven field sequences, selected
from up to 31 preprogrammed field groups, using the FIELD_SELx
registers. When FIELDNUM is greater than 1, the AD9979
starts with Field 1 and increments to each Field N at the start of
each VD.
Figure 33 provides examples of the mode configuration settings.
This example assumes having four field groups, Field Group 0
to Field Group 3, stored in memory.
Table 14. Mode Registers
Name
Length
5 bits
3 bits
5 bits
5 bits
5 bits
5 bits
5 bits
5 bits
5 bits
Range
Description
HPATNUM
FIELDNUM
FIELD_SEL1
FIELD_SEL2
FIELD_SEL3
FIELD_SEL4
FIELD_SEL5
FIELD_SEL6
FIELD_SEL7
0 to 31 H-pattern groups
0 to 7 fields
Total number of H-pattern groups starting at Address 0x800
Total number of applied fields (1 = single-field operation)
Selected first field
Selected second field
Selected third field
Selected fourth field
Selected fifth field
Selected sixth field
Selected seventh field
0 to 31 field groups
0 to 31 field groups
0 to 31 field groups
0 to 31 field groups
0 to 31 field groups
0 to 31 field groups
0 to 31 field groups
Rev. C | Page 24 of 56
AD9979
H-PATTERN MEMORY
FIELD 0
FIELD 1
FIELD 2
FIELD 3
EXAMPLE 1:
TOTAL FIELDS = 3, FIRST FIELD = FIELD 0, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 2
FIELD_SEL1 = 0
FIELD 0
FIELD_SEL2 = 1
FIELD 1
FIELD_SEL3 = 2
FIELD 2
EXAMPLE 2:
TOTAL FIELDS = 1, FIRST FIELD = FIELD 3
FIELD_SEL1 = 3
FIELD 3
EXAMPLE 3:
TOTAL FIELDS = 4, FIRST FIELD = FIELD 5, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 4, FOURTH FIELD = FIELD 2
FIELD_SEL1 = 5
FIELD 5
FIELD_SEL2 = 1
FIELD 1
FIELD_SEL3 = 4 FIELD_SEL4 = 2
FIELD 2
FIELD 4
Figure 33. Example of Mode Configurations
Rev. C | Page 25 of 56
AD9979
clamping sequences. It is important to use CLPOB only during
valid OB pixels. During other portions on the frame timing, such
as during vertical blanking or SG line timing, the CCD does not
output valid OB pixels. Any CLPOB pulses that occur during this
time cause errors in clamping operation, and therefore, cause
changes in the black level of the image.
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 34 shows an example of a CCD layout. The horizontal
register contains 28 dummy pixels, which occur on each line
clocked from the CCD. In the vertical direction, there are 10 optical
black (OB) lines at the front of the readout and 2 OB lines at the
back of the readout. The horizontal direction has 4 OB pixels in
the front and 48 in the back.
Figure 35 shows the basic sequence layout to use during the
effective pixel readout. The 48 OB pixels at the end of each line
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the HBLK time. HBLK
is used during the vertical shift interval.
2 VERTICAL
OB LINES
V
EFFECTIVE IMAGE AREA
10 VERTICAL
OB LINES
Because PBLK is used to isolate the CDS input (see the Analog
Front-End Description and Operation section), the PBLK signal
cannot be used during CLPOB operation. The change in the
offset behavior that occurs during PBLK impacts the accuracy
of the CLPOB circuitry.
H
The HBLK, CLPOB, and PBLK parameters are programmed in
the V-sequence registers. More elaborate clamping schemes can
be used, such as adding in a separate sequence to clamp in the
entire shield OB lines. This requires configuring a separate
V-sequence for clocking out the OB lines.
48 OB PIXELS
4 OB PIXELS
HORIZONTAL CCD REGISTER
28 DUMMY PIXELS
Figure 34. Example CCD Configuration
The CLPOB mask registers are also useful for disabling the
CLPOB on a few lines without affecting the setup of the
OB
OB
HD
CCD OUTPUT
VERTICAL SHIFT
DUMMY
EFFECTIVE PIXELS
OB
VERT. SHIFT
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
CLPOB
NOTES
1. IT IS RECOMMENDED THAT PBLK ACTIVE (LOW) NOT BE USED DURING CLPOB ACTIVE (LOW).
Figure 35. Horizontal Sequence Example
Rev. C | Page 26 of 56
AD9979
GP Toggles
GENERAL-PURPOSE OUTPUTS (GPO)
When configured as an output, each GPO can deliver a signal
that is the result of programmable toggle positions. The GP
signals are independent and can be linked to a specific VD
period or over a range of VD periods, via the primary field
counter, through the GP protocol register (Address 0x52). As
a result of their associations with the field counters, the GP
toggles inherit the characteristics of the field counter, such as
RapidShot and ShotDelay. To use the GP toggles
The AD9979 provides programmable outputs to control a
mechanical shutter, strobe/flash, the CCD bias select signal,
or any other external component with general-purpose (GP)
signals. Two GP signals are available, with up to two toggles
each, that can be programmed and assigned to GPO1 and
GPO2. These pins are bidirectional and also allow visibility of
CLPOB, PBLK, and internal high speed signals (as an output)
and external control of HBLK (as an input). The registers
introduced in this section are described in Table 16.
1. Program the toggle positions (Address 0x54 to
Address 0x59)
Primary Field Counter
2. Program the protocol (Address 0x52)
3. Program the counter parameters (Address 0x51)
4. Activate the counter (Address 0x50)
The AD9979 contains a primary field counter that is used to
count multiple fields when using the GPO output signals. This
counter is incremented on each VD cycle. The primary counter
has several modes of operation controlled by Address 0x50,
including the following:
For Protocol 1 (no counter association), skip Step 3 and Step 4.
With these four steps, the GP signals can be programmed to
accomplish many common tasks. Careful protocol selection and
application of the primary counter yields efficient results to
allow the GP signals smooth integration with system operation.
•
•
•
•
Activate counter (single count)
RapidShot (repeating count)
ShotTimer (delayed count)
Force to idle
Several simple examples of GPO application using only one GPO
and one field counter follow. These examples can be used as
building blocks for more complex GPO activity. In addition,
specific GPO signals can be passed through a four-input LUT to
realize combinational logic between them. For example, GPO1
and GPO2 can be sent through an XOR look-up table, and the
result can be delivered on GPO1, GPO2, or both. In addition,
either GPO1 or GPO2 can deliver its original toggles.
The primary counter regulates the placement of the GP toggle
positions. In addition, if the RapidShot feature is used with the
primary counter, the counter automatically repeats as necessary
for multiple expose/read cycles.
Table 15. Primary Field Counter Registers (Address 0x50 and Address 0x51)
Name Length Description
PRIMARY_ACTION 3 bits
0x0 = idle (no counter action). GPO signals still can be controlled using polarity or GPx_PROTOCOL = 1.
0x1 = activate counter. Single cycle of counter from 1 to counter maximum value; then returns to idle state.
0x2 = RapidShot. After reaching maximum counter value, counter wraps and repeats until reset.
0x3 = ShotTimer. Active single cycle of counter after added delay of N fields (use PRIMARY_DELAY register).
0x4 = test mode only.
0x5 = test mode only.
0x6 = test mode only.
0x7 = force to idle.
PRIMARY_MAX
PRIMARY_DELAY
4 bits
4 bits
Primary counter maximum value.
ShotTimer. Number of fields to delay before the next primary count starts.
Rev. C | Page 27 of 56
AD9979
Table 16. GPO Registers (Address 0x52 to Address 0x59)
Name
Length Range
Description
GP1_PROTOCOL
GP2_PROTOCOL
2 bits
2 bits
0 to 3
0 to 3
0x0 = idle.
0x1 = manual, no counter association.
0x2 = link to primary counter.
0x3 = primary repeat. Allows GP signals to repeat with RapidShot.
Enables general-purpose output signals on every line.
0 = disable.
GP_LINE_MODE
2 bits
Off/on
1 = enable.
GPx_POL1
2 bits
2 bits
Low/high
Off/on
Starting polarity for general-purpose signals. Only updated during PROTOCOL = 1.
0 = disable GPOx. Output pins are in high-Z state (default).
1 = enable GPO1 to GPO2 outputs (1 bit per output).
Select signal for GPO output.
0 = use GP toggles.
1 = use CLPOB.
GPO_OUTPUT_EN
SEL_GPOx1
2 bits
0 to 3
0 to 3
Off/on
2 = use PBLK.
3 = use high speed timing signal.
Select GPO output high speed timing signal used.
0 = use delayed CLI.
1 = use delayed ADC output latch clock.
2 = use delayed SHD sample clock.
3 = use delayed SHP sample clock.
1 = enable external HBLK signal to be input to GPO2 pin.
0 = disabled.
SEL_HS_GPOx1
2 bits
HBLK_EXT
GP_LUT_EN
GP12_LUT
1 bit
2 bits
4 bits
Logic setting Desired logic to be realized on GPO1 combined with GPO2. Example logic settings
for GP12_LUT:
0x6 = GPO1 XOR GPO2 (See Figure 41).
0x7 = GPO1 NAND GPO2.
0x8 = GPO1 AND GPO2.
0xE = GPO1 OR GPO2.
GPTx_TOGy_FIELD1, 2
GPTx_TOGy_LINE1, 2
GPTx_TOGy_PIXEL1, 2
4 bits
0 to 15
Field of activity, relative to primary counter for toggle.
Line of activity for toggle.
13 bits
13 bits
0 to 8191
0 to 8191
Pixel of activity for toggle.
1 The variable x represents the general-purpose output, 1 or 2.
2 The variable y represents the toggle, 1 or 2.
Rev. C | Page 28 of 56
AD9979
Single-Field Toggles
VD
REG WRITE
1
2
Single-field toggles begin in the field following the register write.
There can be up to two toggles in the field. The mode is set with
GPx_PROTOCOL equal to 1. In this mode, the field toggle
settings must be set to 1. Toggles repeat for each field until
GPx_PROTOCOL is set to 0. GPx_PROTOCOL must be reset
to 0 for one field before it can be active again.
A
2
0
0
GP1_PROTOCOL
PRIMARY
COUNT
1
2
0
(IDLE)
Preparation
GPO1
The GP toggle positions can be programmed any time prior to
use. For example,
THE PRIMARY COUNTER REGULATES THE SUBCK
AND VSG ACTIVITY. LINK A GPO TO THE PRIMARY COUNTER
ONLY IF IT IS TO HAPPEN DURING EXPOSURE/READ.
0x054
0x055
0x056
←
←
←
0x000A001
0x0002000
0x000000F
Figure 37. Scheduled Toggles Using GP1_PROTOCOL = 2
RapidShot Sequences
Details
RapidShot technology provides continuous repetition of scheduled
toggles. As in the case of scheduled toggles, a pulse can traverse
multiple fields. The mode is set with GPx_PROTOCOL = 3,
which tells the GPO to obey the repeating primary field counter.
GPx_PROTOCOL must be reset to 0 for one field before it can
be active again.
A) Field 0: 0x052 ← 0x0000001
B) Field 1: 0x052 ← 0x0000000
VD
REG WRITE
1
2
A
B
Preparation
The GPO toggle positions can be programmed any time prior
to use. For example,
GP1_PROTOCOL
GPO1
0
1
0
0x051 ← 0x0000002
0x054 ← 0x000A001
0x055 ← 0x0004000
0x056 ← 0x000000F
0x052 ← 0x0000003
NOTES
1. THE FIELD TOGGLE POSITION IS IGNORED WHEN THE GPO
PROTOCOL IS 1.
TOGGLE POSITIONS REPEAT FOR EACH FIELD UNTIL
GPO PROTOCOL IS RESET.
Details
Figure 36. Single-Field Toggles Using GP1_PROTOCOL = 1
A) Field 0: 0x050 ← 0x0000002
B) Field 2: 0x050 ← 0x0000007
Scheduled Toggles
Scheduled toggles are programmed to occur during any upcoming
field. For example, there can be one toggle in Field 1 and the next
toggle in Field 3. The mode is set with GPx_PROTOCOL = 2,
which tells the GPO to obey the primary field counter.
1
2
3
4
5
VD
REG WRITE
A
B
Preparation
0
3
1
GP1_PROTOCOL
The GP toggle positions can be programmed any time prior to
use. For example,
PRIMARY
COUNT
0 (IDLE)
2
1
2
1
0
0x054 ← 0x00C4002
0x055 ← 0x0004000
0x056 ← 0x00000B3
GPO1
TERMINATED
AT VD EDGE
Details
NOTES
A) Field 0: 0x050 ← 0x0000001
0x052 ← 0x0000002
1. THE GPO PROTOCOLS ARE THE SAME AS THE SCHEDULED
TOGGLES, EXCEPT THE TOGGLES CAN BE EXCLUDED FROM
REPETITION BY CHOOSING GPO PROTOCOL 2.
CAUTION! THE FIELD COUNTER MUST BE FORCED INTO IDLE
STATE TO TERMINATE REPETITIONS.
Figure 38. RapidShot Toggle Operation Using GP1_PROTOCOL = 3
Rev. C | Page 29 of 56
AD9979
ShotTimer Sequences
Address 0x52 dictates the behavior of the LUT and identifies
which signals receive the result. Each 4-bit register can realize
any logic combination of GPO1 and GPO2. Table 17 shows
how the register values of GP12_LUT[13:10] are determined.
XOR, NAND, AND, and OR results are shown, but any 4-bit
combination is possible. A simple example of XOR gating is
shown in Figure 41.
ShotTimer technology provides internal delay of scheduled
toggles. The delay is in terms of fields.
Preparation
The GP toggle positions can be programmed any time prior to
use. For example,
0x051 ← 0x0000032
0x054 ← 0x000A001
0x055 ← 0x0004000
0x056 ← 0x000000F
0x052 ← 0x0000002
Table 17. LUT Results Based on GPO1, GPO2 Values
LUT
GPO2
GPO1
XOR
NAND
AND
OR
0
1
1
1
0
0
1
1
0
1
0
1
0
1
1
0
1
1
1
0
0
0
0
1
Details
A) Field 0: 0x050 ← 0x0000003
VD
REG WRITE
1
2
3
4
5
GP12_LUT = 0x6
GP_LUT_EN = 0x2
A
GP1_INT
GP2_INT
GPO2
0
3
1
GP1_PROTOCOL
PRIMARY
COUNT
0 (IDLE)
2
3
1
2
0
GPO1
LOGIC COMBINATION (XOR) OF PROGRAMMED TOGGLES
GPO1 AND GPO2.
GPO1
Figure 41. LUT Example for GPO1 XOR GPO2
Figure 39. ShotDelay Toggle Operation Using GP1_PROTOCOL = 3
Field Counter and GPO Limitations
GP LOOK-UP TABLES (LUT)
1. The following is a summary of the known limitations of the
field counters and GPO signals that dictate usability.
2. The field counter trigger (Address 0x50) is self-reset at the
start of every VD period. Therefore, there must be one VD
period between sequential programming to that address.
3. If the protocol is set to 1, the toggles repeat for each field
until the protocol is set to idle.
The AD9979 includes a LUT for each pair of consecutive GP
signals when configured as outputs. The external GPO outputs
from the GPO1 pair can output the result of the LUT or the
original GPO internal signal.
GP_LUT_EN [8]
0
GPO1
GP1_INT
1
LUT
GP2_INT
1
GPO2
0
GP_LUT_EN [9]
Figure 40. Internal LUT for GPO1 and GPO2 Signals
Rev. C | Page 30 of 56
AD9979
ANALOG FRONT-END DESCRIPTION AND OPERATION
0.1µF 0.1µF
REFB REFT
0.4V 1.4V
AD9979
DC RESTORE
SHP
DOUT PHASE
1.2V
INTERNAL
PBLK (WHEN DCBYP = 1)
V
REF
SHP
SHD
2V FULL SCALE
6dB TO 42dB
1
S1
0.1µF
14
DOUT
CCDINP
14-BIT
ADC
OUTPUT
DATA
LATCH
D0 TO D13
VGA
CDS
–3dB, 0dB,
+3dB, +6dB
OPTICAL BLACK
CLAMP
2
S2
DAC
VGA GAIN
REGISTER
CDS GAIN
REGISTER
CLPOB PBLK
PBLK
1
DIGITAL
FILTER
BLANK TO
ZERO OR
CLAMP LEVEL
S1 IS NORMALLY CLOSED.
S2 IS NORMALLY OPEN.
2
DOUT
PHASE
CLAMP-LEVEL
REGISTER
SHP SHD
CLPOB PBLK
VD
HD
PRECISION
V-H
CLI
TIMING
TIMING
GENERATION
GENERATION
Figure 42. Analog Front End Functional Block Diagram
The AD9979 signal processing chain is shown in Figure 42.
Each processing step is essential in achieving a high quality
image from the raw CCD pixel data.
During the PBLK active time, the ADC outputs can be pro-
grammed to output all zeros or the programmed clamp level.
Note that because the CDS input is shorted during PBLK, the
CLPOB pulse must not be used during the same active time as
the PBLK pulse.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 μF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.2 V, to be compatible with the 1.8 V core
supply voltage of the AD9979. The dc restore switch is active
during the SHP sample pulse time.
Correlated Double Sampler (CDS)
The CDS circuit samples each CCD pixel twice to extract the
video information and to reject low frequency noise. The
timing shown in Figure 19 illustrates how the two internally
generated CDS clocks, SHP and SHD, are used to sample the
reference level and to sample the CCD signal level, respectively.
The placement of the SHP and SHD sampling edges is deter-
mined by the setting of the SHPLOC and SHDLOC registers,
located at Address 0x36. Placement of these two clock signals is
critical in achieving the best performance from the CCD.
The dc restore circuit can be disabled when the optional PBLK
signal is used to isolate large signal swings from the CCD input
(see the Analog Preblanking section). Bit 6 of Address 0x00
controls whether the dc restore is active during the PBLK interval
(see Table 24).
Analog Preblanking
The CDS gain is variable in four steps, set by using CDSGAIN
(Address 0x04): −3 dB, 0 dB (default), +3 dB, and +6 dB (see
Table 24). Improved noise performance results from using the
+3 dB and +6 dB settings, but the input range is reduced with
these settings (see Table 4).
During certain CCD blanking or substrate clocking intervals,
the CCD input signal to the AD9979 can increase in amplitude
beyond the recommended input range. The PBLK signal can
be used to isolate the CDS input from large signal swings. As
shown in Figure 42, when PBLK is active (low), the CDS input
is isolated from the CCDINx pin (S1 open) and is internally
shorted to ground (S2 closed).
Rev. C | Page 31 of 56
AD9979
(N) SIGNAL SAMPLE
Input Configurations
(N) RESET SAMPLE
(N + 1) RESET SAMPLE
The CDS circuit samples each CCD pixel twice to extract the
video information and to reject the low frequency noise (see
Figure 43). There are three possible configurations for the CDS:
inverting CDS mode, noninverting CDS mode, and SHA mode.
CDSMODE (Address 0x00[9:8]) selects which configuration is
used (see Table 24).
V
DD
RESET LEVEL
(V
)
RST
SHP
SIGNAL LEVEL
(V
)
FS
CCDINP
Figure 45. Traditional Inverting CDS Signal
SHA1
Table 18. Inverting Voltage Levels
DIFF
AMP
CDS OUTPUT
Signal Level
Saturation
Reset
Symbol Min
Typ
Max Unit
VFS
1000
1400 mV
CCDINM
SHA2
VRST
VDD − 500 VDD − 300 VDD
mV
Supply Voltage VDD
1600 1800 2000 mV
SHD
Figure 43. CDS Block Diagram (Conceptual)
Noninverting CDS Mode
Inverting CDS Mode
If the noninverting input is desired, the reset level signal (or black
level signal) is established at a voltage above ground potential.
Saturation level (or white level) is approximately 1 V. Samples are
taken at each signal level (see Figure 46 and Table 19).
SIGNAL LEVEL
For this configuration, the signal from the CCD is applied
to the positive input of the CDS system (CCDINP) and the
negative side (CCDINM) is grounded (see Figure 44). The
CDSMODE setting for this configuration is 0x00. Traditional
CCD applications use this configuration with the reset level
established below the AVDD supply level, by the AD9979 dc
restore circuit, at approximately 1.5 V. The maximum saturation
level is 1.0 V below the reset level, as shown in Figure 45 and
Table 18. A maximum saturation voltage of 1.4 V is also
possible when using the minimum CDS gain setting.
(V
)
FS
(N) RESET SAMPLE
(N + 1) RESET SAMPLE
RESET LEVEL
(V
)
RST
GND
AD9979
(N) SIGNAL SAMPLE
CCDINP
Figure 46. Noninverting CDS Signal
IMAGE
SENSOR
SHA/
CDS
Table 19. Noninverting Voltage Levels
CCDINM
Signal Level
Saturation
Reset
Symbol
Min
Typ
1000
250
Max
1400
500
Unit
mV
mV
VFS
VRST
NOTES
0
1. COUPLING CAPACITOR IS NOT REQUIRED FOR CERTAIN
BLACK-LEVEL REFERENCE VOLTAGES.
Figure 44. Single-Input CDS Configuration
Rev. C | Page 32 of 56
AD9979
SHA Mode—Differential Input Configuration
AD9979
CCDINP
CCDINM
In this configuration, which uses a differential input sample-
and- hold amplifier (SHA), a signal is applied to the CCDINP
input, while an inverse signal is applied simultaneously to the
CCDINM input (see Figure 47). Sampling occurs on both
signals at the same time, creating the differential output for
amplification and for the ADC (see Figure 48 and Table 20).
IMAGE
SHA/
CDS
SENSOR
NOTES
1. DC VOLTAGE ABOVE GROUND CAN BE USED TO
MATCH THE SENSOR REFERENCE LEVEL.
AD9979
Figure 49. SHA Mode—DC-Coupled, Single-Ended Input Configuration
CCDINP
(N + 1) SIGNAL SAMPLE
IMAGE
SENSOR
SHA/
CDS
(N) SIGNAL SAMPLE
CCDINM
Figure 47. SHA Mode—Differential Input Configuration
POSITIVE INPUT
NEGATIVE INPUT
PEAK SIGNAL
LEVEL (V
(N + 1) SIGNAL SAMPLE
)
FS
BLACK SIGNAL LEVEL (V
BLK
)
(N) SIGNAL SAMPLE
MINIMUM SIGNAL LEVEL (V
)
MIN
GND
POSITIVE INPUT
Figure 50. SHA Mode—DC-Coupled, Single-Ended Input Signal
PEAK SIGNAL
LEVEL (V
BLACK SIGNAL LEVEL (V
BLK
)
)
FS
Table 21. SHA Mode—Single-Ended, Input Voltage Levels
NEGATIVE INPUT
Signal Level
Symbol Min Typ
Max Unit
Black Signal Level
Saturation Signal Level
Minimum Signal Level
VBLK
VFS
VMIN
0
mV
1000 1400 mV
mV
0
MINIMUM SIGNAL LEVEL (V
)
MIN
GND
CDS Timing Control
Figure 48. SHA Mode—Differential Input Signal
The timing shown in Figure 19 illustrates how the two internally
generated CDS clocks, SHP and SHD, are used to sample the
reference level and the data level of the CCD signal, respectively.
The placement of the SHP and SHD sampling edges is determined
by the setting of SHPLOC and SHDLOC, located at Address 0x36.
Placement of these two clock signals is critical in achieving the
best performance from the CCD.
Table 20. SHA Mode—Differential Voltage Levels
Signal Level
Symbol Min
Typ
Max
Unit
Black Signal Level
VBLK
0
mV
Saturation Signal
Level
VFS
1000 VDD − 300 1400 mV
Minimum Signal
Level
VMIN
0
1800 mV
SHA Timing Control
When SHA mode is selected, only the SHPLOC setting is used
to sample the input signal, but the SHDLOC signal still needs to
be programmed to an edge setting of SHPLOC + 32.
SHA Mode—DC-Coupled, Single-Ended Input
The SHA mode can also be used in a single-ended fashion,
with the signal from the image sensor applied to the CDS/SHA
using a single input, CCDINP. This is similar to the differential
configuration, except in this case, the CCDINM line is held at a
constant dc voltage. This establishes a reference level that matches
the image sensor reference voltage (see Figure 49).
Referring to Figure 50 and Table 21, the CCDINM signal is a
constant dc voltage set at a level above ground potential. The
sensor signal is applied to the other input, and samples are
taken at the signal minimum and at a point of signal maximum.
The resulting differential signal is the difference between the
signal and the reference voltage.
Rev. C | Page 33 of 56
AD9979
Variable Gain Amplifier (VGA)
Optical Black Clamp
The VGA stage provides a gain range of approximately 6 dB to
42 dB, programmable with 10-bit resolution through the serial
digital interface. A gain of 6 dB is needed to match a 1 V input
signal with the ADC full-scale range of 2 V. When compared to
1 V full-scale systems, the equivalent gain range is 0 dB to 36 dB.
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference, selected by the user in the clamp level
register. The value can be programmed between 0 LSB and
255 LSB, in 256 steps. The resulting error signal is filtered to
reduce noise, and the correction value is applied to the ADC
input through a DAC. Normally, the optical black clamp loop is
turned on once per horizontal line, but this loop can be updated
more slowly to suit a particular application. If external digital
clamping is used during the postprocessing, the AD9979 optical
black clamping can be disabled using CLAMPENABLE, Bit 3 in
Address 0x00. When the loop is disabled, the clamp level register
can still be used to provide fixed offset adjustment.
The VGA gain curve follows a linear-in-dB characteristic. The
exact VGA gain is calculated for any gain register value by
Gain (dB) = (0.0358 × Code) + 5.75 dB
where Code is the range of 0 to 1023.
42
36
30
24
18
12
6
Note that if the CLPOB loop is disabled, higher VGA gain settings
reduce the dynamic range because the uncorrected offset in the
signal path is gained up.
It is recommended to align the CLPOB pulse with the CCD
optical black pixels. It is recommended that the CLPOB pulse
duration be at least 20 pixels wide. Shorter pulse widths can be
used, but the ability for the loop to track low frequency variations
in the black level is reduced. See the Horizontal Clamping and
Blanking section for more timing information.
0
127
255
383
511
639
767
895 1023
VGA GAIN REGISTER CODE
Figure 51. VGA Gain Curve
Digital Data Outputs
Analog-to-Digital Converter
The AD9979 digital output data is latched using the DOUTPHASEx
value, as shown in Figure 42. (Output data timing is shown
in Figure 20.) The switching of the data outputs can couple
noise back into the analog signal path. To minimize any switching
noise while using default register settings, it is recommended
that DOUTPHASEPx be set to a value between 15 and 31. Other
settings can produce good results, but experimentation is
necessary.
The AD9979 uses a high performance ADC architecture,
optimized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.5 LSB. The ADC
uses a 2 V input range. (See Figure 5 to Figure 7 for the typical
linearity and noise performance plots of the AD9979.)
The data output coding is normally straight binary, but the coding
can be changed to gray coding by setting Bit 2 of Address 0x01 to 1.
Rev. C | Page 34 of 56
AD9979
APPLICATIONS INFORMATION
4. To place the part into normal power operation, write 0 to
STANDBY (Address 0x00, Bits[1:0])and REFBUF_PWRDN
(Address 0x00, Bit 2).
5. The Precision Timing core must be reset by writing 1 to
TGCORE_RST (Address 0x14, Bit 0). This starts the
internal timing core operation.
RECOMMENDED POWER-UP SEQUENCE
When the AD9979 is powered up, the following sequence is
recommended (refer to Figure 52 for each step).
1. Turn on the power supplies for the AD9979 and apply CLI
clock. There is no required order for bringing up each supply.
2. Although the AD9979 contains an on-chip, power-on reset,
a software reset of the internal registers is recommended.
Write 1 to SW_RST (Address 0x10, Bit [0], which resets all
the internal registers to their default values. This bit is self-
clearing and automatically resets back to 0.
6. Write 1 to OUT_CONTROL (Address 0x11, Bit 0).
The next VD/HD falling edge allows register updates to occur,
including OUT_CONTROL (Address 0x11, Bit [0]), which
enables all clock outputs.
3. Write to the desired registers to configure high speed
timing and horizontal timing. Note that all TESTMODE
registers must be written as described in the register maps.
AD9979 SUPPLIES
0V
POWER
SUPPLIES
1
CLI
(INPUT)
2
3
4
5
6
SERIAL
WRITES
1V
VD
(INPUT)
1ST FIELD
1H
HD
(INPUT)
CLOCKS ACTIVE WHEN OUT_CONTROL
REGISTER IS UPDATED AT VD/HD EDGE
H2, H4
HIGH-Z BY
DEFAULT
HORIZONTAL
CLOCKS
H1, H3, RG
Figure 52. Recommended Power-Up Sequence
Rev. C | Page 35 of 56
AD9979
Example Register Settings for Power-Up
The following settings can be used for basic operation. A single CLPOB pulse is used with only H-pattern and one field. Additional
HPATS and FIELDS can be added, as needed, along with different CLPOB toggle positions.
010
028
800
801
802
803
804
805
806
807
808
809
80a
80b
80c
80d
80e
80f
810
811
812
813
814
815
816
817
818
819
81a
81b
81c
81d
81e
81f
02a
02b
02c
000
014
011
0000001
0000001
0064000
3ffffff
3ffffff
0064000
3ffffff
3ffffff
0000000
0000000
0000000
0000000
0000000
0000000
00dc05a
3ffffff
3ffffff
3ffffff
1000000
1000800
1000800
1000800
0000800
0000000
0000000
0000000
0000001
1000800
1000800
1000800
0000001
1000800
0000000
0000000
0000001
0000000
0000000
0000008
0000001
0000001
//Software Reset
//total number of H-Pattern groups = 1
//HPAT0 HBLKTOGO1, TOGO2 settings
//unused HBLK Odd toggles set to zero or max value
//unused HBLK Odd toggles set to zero or max value
//HPAT0 HBLKTOGE1, TOGE2 settings
//unused HBLK Even toggles set to zero or max value
//unused HBLK Even toggles set to zero or max value
//HBLK StartA, B are not used
//HBLK StartC is not used
//HBLK Alternation Patterns are not used
//HBLKLEN, HBLKREP not used, HBLK masking pol = 0
//HBLKSTART, END not used
//Test, set to zero
//CLPOB pat 0 toggles
//CLPOB pat 1 toggles not used, set to max
//PBLK pat 0 toggles not used, set to max
//PBLK pat 1 toggles not used, set to max
//FIELD0 SCP0, SCP1
//SCP2, SCP3 set same as SCP1
//SCP4, SCP5 set same as SCP1
//SCP6, SCP7 set same as SCP1
//SCP8 set same as SCP1
//Select HPAT0 for all regions
//Select HPAT0 for all regions
//Test, set to zero
//CLPOB start polarity = HIGH
//CLPOB masking set to highest SCP value (no mask)
//CLPOB masking set to highest SCP value (no mask)
//CLPOB masking set to highest SCP value (no mask)
//PBLK start polarity = HIGH
//PBLK masking set to highest SCP value (no mask)
//PBLK masking set to highest SCP value (no mask)
//PBLK masking set to highest SCP value (no mask)
//total number of Fields = 1
//field select = FIELD0
//field select = FIELD0
//AFE settings
//reset TGCORE
//enable outputs
Rev. C | Page 36 of 56
AD9979
VD
HD
CLI
tVDHD
tHDCLI
tCLISHP
tCLIDLY
SHPLOC
INTERNAL
SHDLOC
INTERNAL
HD
INTERNAL
H-COUNTER
RESET
11.5 CYCLES
H-COUNTER
(PIXEL COUNTER)
X
X X X X X
X
X
X
X
X
X
X
X
0
1
2
NOTES
1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, THEN LATCHED AGAIN BY SHPLOC (INTERNAL SAMPLING EDGE).
2. INTERNAL H-COUNTER IS ALWAYS RESET 11.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE, AT SHDLOC (INTERNAL SAMPLING EDGE).
3. DEPENDING ON THE VALUE OF SHDLOC, H-COUNTER RESET CAN OCCUR 13 OR 14 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.
4. SHPLOC = 32, SHDLOC = 0 IS SHOWN IN ABOVE EXAMPLE. IN THIS CASE, THE H-COUNTER RESET OCCURS 13 CLI RISING EDGES AFTER HD FALLING EDGE.
5. HD FALLING EDGE MUST OCCUR COINCIDENT WITH VD FALLING EDGE (WITHIN SAME CLI CYCLE) OR AFTER VD FALLING EDGE. HD FALLING
EDGE MUST NOT OCCUR WITHIN 1 CLI CYCLES IMMEDIATELY BEFORE VD FALLING EDGE.
Figure 53. Horizontal Counter Pipeline Delay
Additional Restrictions
When operating, note the following restrictions:
Table 22 summarizes the operation of each power-down mode.
OUT_CONTROL (Address 0x11, Bit [0]) takes priority over the
reference standby mode in determining the digital output states,
but total shutdown mode takes priority over OUT_CONTROL.
Total shutdown mode has the lowest power consumption. When
returning from total shutdown mode to normal operation, the
timing core must be reset at least 100 μs after STANDBY
(Address 0x00, Bits[1:0]) is written to.
•
The HD falling edge should be located in the same CLI
clock cycle as the VD falling edge or later than the VD
falling edge. The HD falling edge should not be located
within 1 cycle prior to the VD falling edge.
•
If possible, perform all start-up serial writes with VD and
HD disabled. This prevents unknown behavior caused by
partial updating of registers before all information is loaded.
There is an additional register to independently disable the
internal voltage reference buffer, REFBUF_PWRDN (Bit 2,
(Address 0x00). By default, the buffer is disabled. It must be
enabled for normal operation.
The internal horizontal counter is reset 12 CLI cycles after the
falling edge of HD. See Figure 53 for details on how the internal
counter is reset.
CLI FREQUENCY CHANGE
STANDBY MODE OPERATION
If the input clock (CLI) is interrupted or changes to a different
frequency, the timing core must be reset for proper operation. After
the CLI clock has settled to the new frequency, or the previous
frequency is resumed, write 0 and then 1 to TGCORE_RST
(Address 0x14). This guarantees proper timing core operation.
The AD9979 contains two different standby modes to optimize
the overall power dissipation in a particular application. Bits[1:0]
of Address 0x00 control the power-down state of the device.
•
•
•
STANDBY[1:0] = 00 = normal operation (full power)
STANDBY[1:0] = 01 = reference standby mode
STANDBY[1:0] = 10 or 11 = total shut-down mode
(lowest power)
Rev. C | Page 37 of 56
AD9979
Table 22. Standby Mode Operation
I/O Block
Total Shutdown (Default)1, 2
OUT_CONTROL = Low2
Reference Standby
Only REFT, REFB on
On
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low
AFE
Timing Core
H1
H2
H3
H4
HL
RG
Off
Off
No change
No change
Low
High
Low
High
Low
Low
Low
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Low3
DOUT
1 To exit total shutdown, write 00 to STANDBY (Address 0x00, Bits[1:0]), then reset the timing core after 100 μs to guarantee proper settling.
2 Total shutdown mode takes priority over OUT_CONTROL for determining the output polarities.
3 The status of the DOUT pins is unknown at power-up. Low status is guaranteed in total shutdown mode after the power-up sequence is completed.
CIRCUIT CONFIGURATION
GROUNDING AND DECOUPLING
RECOMMENDATIONS
The AD9979 recommended circuit configurations are shown in
Figure 54 and Figure 55. Achieving good image quality from the
AD9979 requires careful attention to PCB layout. Route all signals
to maintain low noise performance. Directly route the CCD
output signal through a 0.1 μF capacitor to Pin 31. To minimize
interference with the CCDINM, CCDINP, REFT, and REFB
signals, carefully route the master clock (CLI) to Pin 28.
As shown in Figure 54 and Figure 55, a single ground plane is
recommended for the AD9979. This ground plane needs to be as
continuous as possible, particularly around the P-type, AI-type,
and A-type pins to ensure that all analog decoupling capacitors
provide the lowest possible impedance path between the power
and bypass pins and their respective ground pins. All high
frequency decoupling capacitors need to be located as close as
possible to the package pins.
The H1 to H4, HL, and RG traces need low inductance to avoid
excessive distortion of the signals. Heavier traces are recommended
because of the large transient current demands on H1 to H4 and
HL from the capacitive load of the CCD. If possible, physically
locating the AD9979 closer to the CCD reduces the inductance
on these lines. Make the routing path as direct as possible from
the AD9979 to the CCD.
All the supply pins must be decoupled to ground with good
quality, high frequency chip capacitors. There also needs to be
a 4.7 μF or larger bypass capacitor for each main supply, that is,
AVDD, RGVDD, HVDD, and DRVDD, although this is not
necessary for each individual pin. In most applications, it is
easier to share the supply for RGVDD and HVDD, which can
be done as long as the individual supply pins are separately
bypassed. A separate 3 V supply can be used for DRVDD, but
this supply pin still needs to be decoupled to the same ground
plane as the rest of the chip. A separate ground for DRVSS is not
recommended.
3 V System Compatibility
The AD9979 typical circuit connections for a 3 V system are
shown in Figure 54. This application uses an external 3.3 V
supply connected to the IOVDD input of the AD9979, which
also serves as the LDO input. The LDO generates a 1.8 V output
for the AD9979 core supply voltages, AVDD and DVDD. The
LDOOUT pin can then be connected directly to the AVDD and
DVDD pins. In this configuration, the LDOEN pin is tied high
to enable the LDO.
The reference bypass pins (REFT, REFB) must be decoupled to
ground as close as possible to their respective pins. The bridge
capacitor between REFT and REFB is recommended for pixel
rates greater than 40 MHz. The analog input capacitor (CCDINM,
CCDINP) also needs to be located close to the pin.
Alternatively, a separate 1.8 V regulated supply voltage may be
used to power the AVDD and DVDD pins. In this case, the
LDOOUT pin needs to be left floating, and the LDOEN pin
needs to be grounded. A typical circuit configuration for a 1.8 V
system is shown in Figure 55.
The GND connections should be tied to the lowest impedance
ground plane on the PCB. Performance does not degrade if
several of these GND connections are left unconnected for
routing purposes.
Rev. C | Page 38 of 56
AD9979
1.8V LDOOUT
2
0.1µF
VD/HD/HBLK INPUTS
2
3
GENERAL-PURPOSE
OUTPUTS
SERIAL
INTERFACE
+3V
0.1µF
PIN 1
INDICATOR
36 REFB
0.1µF
0.1µF
(LSB) D0
1
2
35 REFT
34 AVDD
33 AVSS
32 CCDINM
31 CCDINP
30 AVDD
29 AVSS
28 CLI
D1
D2
0.1µF
3
D3
4
D4
5
DRVSS
DRVDD
D5
6
0.1µF
AD9979
CCD SIGNAL PLUS
1.8V LDOOUT
4.7µF
3V
DRIVER
SUPPLY
7
+
+
8
0.1µF
4.7µF
0.1µF
D6
9
D7
10
27 LDOOUT
26 IOVDD
25 RG
D8 11
D9 12
MASTER CLOCK INPUT
1.8V LDO OUTPUT TO AVDD, DVDD
3.0V I/O, LDO SUPPLY
0.1µF
0.1µF
12
DATA
OUTPUTS
RG TO CCD
0.1µF
NC = NO CONNECT
3V H-DRIVER SUPPLY
+
4.7µF
0.1µF
5
H1, H2, H3, H4, HL TO CCD
Figure 54. Typical 3 V Circuit Configuration
1.8V ANALOG SUPPLY
2
0.1µF
VD/HD/HBLK INPUTS
2
GENERAL-PURPOSE
OUTPUTS
3
SERIAL
INTERFACE
0.1µF
PIN 1
INDICATOR
0.1µF
0.1µF
36 REFB
35 REFT
34 AVDD
33 AVSS
32 CCDINM
31 CCDINP
30 AVDD
29 AVSS
28 CLI
(LSB) D0
D1
1
2
D2
3
0.1µF
D3
4
D4
5
DRVSS
DRVDD
D5
6
0.1µF
AD9979
CCD SIGNAL PLUS
3V
DRIVER
SUPPLY
7
1.8V ANALOG SUPPLY
4.7µF
+
+
8
0.1µF
4.7µF
0.1µF
D6
9
D7
10
27 LDOOUT
26 IOVDD
25 RG
D811
D912
MASTER CLOCK INPUT
1.8V I/O SUPPLY
0.1µF
12
DATA
OUTPUTS
RG TO CCD
0.1µF
3V H-DRIVER SUPPLY
NC = NO CONNECT
+
4.7µF
0.1µF
5
H1, H2, H3, H4, HL TO CCD
Figure 55. Typical 1.8 V Circuit Configuration
Rev. C | Page 39 of 56
AD9979
3-WIRE SERIAL INTERFACE TIMING
All of the internal registers of the AD9979 are accessed through a
3-wire serial interface. Each register consists of a 12-bit address
and a 28-bit data-word. Both the 12-bit address and the 28-bit
data-words are written starting with the LSB. To write to each
register, a 40-bit operation is required, as shown in Figure 56.
Although many registers are fewer than 28-bits wide, all 28 bits
must be written for each register. For example, if the register is only
20-bits wide, the upper 8 bits are don’t care bits and must be filled
with zeros during the serial write operation. If fewer than 28 data
bits are written, the register does not update with new data.
Figure 57 shows a more efficient way to write to the registers,
using the AD9979 address auto-increment capability. Using this
method, the lowest desired address is written first, followed
by multiple 28-bit data-words. Each new 28-bit data-word is
automatically written to the next highest register address. By
eliminating the need to write to each 12-bit address, faster register
loading is achieved. Continuous write operations can be used
starting with any register location.
12-BIT ADDRESS
28-BIT DATA
SDATA
SCK
A0
A1
A2
A3
A4
A5
tDS
A6
A8
A9 A10 A11 D0
D1
D2
D3
D25 D26 D27
A7
tDH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
38
39
tLH
40
tLS
SL
NOTES:
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK MAY IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 40 BITS MUST BE WRITTEN: 12 BITS FOR ADDRESS AND 28 BITS FOR DATA.
3. IF THE REGISTER LENGTH IS <28 BITS, THEN ZEROS MUST BE USED TO COMPLETE THE 28-BIT DATA LENGTH.
4. NEW DATA VALUES ARE UPDATED IN THE SPECIFIED REGISTER LOCATION AT DIFFERENT TIMES, DEPENDING ON THE
PARTICULAR REGISTER WRITTEN TO. SEE THE UPDATING OF NEW REGISTER VALUES SECTION FOR MORE INFORMATION.
Figure 56. Serial Write Operation
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
SDATA
A0
A1
A2
A10 A11 D0
D1
D26 D27 D0
D1
D26 D27 D0
A3
D1
D2
SCK
SL
70
71
1
2
3
4
11
12
13
14
39
40
41
42
67
68
69
NOTES:
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 28-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 28-BIT DATA-WORD (ALL 28 BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
Figure 57. Continuous Serial Write Operation
Rev. C | Page 40 of 56
AD9979
It is important to note that the H-pattern group and field
registers must always occupy a continuous block of addresses.
LAYOUT OF INTERNAL REGISTERS
The AD9979 address space is divided into two different register
areas, as illustrated in Figure 58. In the first area, Address 0x000 to
Address 0x7FF contain the registers for the AFE, miscellaneous
functions, VD/HD parameters, input/output control, mode
control, timing core, test, and update control functions. The
second area of the address space, beginning at Address 0x800,
consists of the registers for the H-pattern groups and fields.
This is a configurable set of register space; the user can decide
how many Hpattern groups and fields are used in a particular
design. The AD9979 supports up to 32 H-patterns.
Figure 59 shows an example using three H-pattern groups and
two fields. The starting address for the H-pattern groups is
always 0x800. Because HPATNUM is set to 3, the H-pattern
groups occupy 48 address locations, that is, 16 registers times
3 H-pattern groups. The starting address of the field registers
for this example is 0x830, or 0x800 plus 48 (decimal). Note the
decimal value must be converted to a hexadecimal number
before adding it to 0x800.
The AD9979 address space contains many unused addresses.
Undefined addresses between Address 0x00 and Address 0xFF
must not be written to; otherwise, the AD9979 can operate
incorrectly. Continuous register writes needs to be performed
carefully to avoid writing to undefined registers.
Register 0x28 specifies the total number of H-pattern groups.
The starting address for the H-pattern group registers is always
0x800, and the starting address for the field registers is determined
by the number of H-pattern groups, and it is equal to 0x800
plus the number of H-pattern groups times 16. Each H-pattern
group and field occupies 16 register addresses.
FIXED REGISTER AREA
CONFIGURABLE REGISTER AREA
ADDR 0x000
HPAT START 0x800
AFE REGISTERS
MISCELLANEOUS FUNCTION REGISTERS
VD/HD REGISTERS
H-PATTERN GROUPS
I/O REGISTERS
MODE CONTROL REGISTERS
TIMING CORE REGISTERS
FIELD START
TEST REGISTERS
FIELDS
UPDATE CONTROL REGISTERS
INVALID—DO NOT ACCESS
ADDR 0x7FF
MAX 0xFFF
NOTES
1. THE H-PATTERN GROUP AND FIELD REGISTERS MUST OCCUPY A CONTINUOUS BLOCK OF ADDRESSES.
Figure 58. Layout of AD9979 Registers
ADDR 0x800
3 H-PATTERN GROUPS
(16 × 3 = 48 REGISTERS)
ADDR 0x830
2 FIELDS
(16 × 2 = 32 REGISTERS)
ADDR 0x850
UNUSED MEMORY
MAX 0xFFF
Figure 59. Example Register Configuration
Rev. C | Page 41 of 56
AD9979
VD Updated (VD)
UPDATING OF NEW REGISTER VALUES
The internal registers of the AD9979 are updated at different
times, depending on the register. Table 23 summarizes the three
different types of register updates. The register listing tables also
contain a column with update type to identify when each register is
updated (see Table 24 to Table 34).
Many of the registers are updated at the next VD falling edge.
By updating these values at the next VD edge, the current field
is not corrupted and the new register values are applied to the
next field. The VD update can be further delayed past the VD
falling edge, using UPDATE (Address 0x17, Bits[12:0]), which
delays the VD-updated register updates to any HD line in the
field. Note that the field registers are not affected by UPDATE.
SCK Updated (SCK)
Some of the registers are updated immediately, as soon as the
28th data bit (D27) is written. These registers are used for
functions that do not require gating with the next VD boundary,
such as power-up and reset functions.
SCP Updated (SCP)
All of the H-pattern group registers are updated at the next SCP
in which the registers are used.
Table 23. Register Update Locations
Update Type
Description
SCK
VD
Register is immediately updated when the 28th data bit (D27) is clocked in.
Register is updated at the VD falling edge. VD-updated registers can be delayed further, using UPDATE (Address 0x17,
Bits[12:0]). Field registers are not affected by UPDATE.
SCP
Register is updated at the next SCP in which the register is used.
Rev. C | Page 42 of 56
AD9979
COMPLETE REGISTER LISTING
All addresses and default values are expressed in hexadecimal. When an address contains less than 28 data bits, all remaining bits must be
written as 0s.
Table 24. AFE Registers
Data Bit
Content
Default
Value
Update
Type
Address
Name
Description
00
[1:0]
3
SCK
STANDBY
Standby modes.
0 = normal operation (full power).
1 = reference standby mode.
2 = total shutdown mode (lowest power).
3 = total shutdown mode (lowest power).
Reference buffer for REFT and REFB power control.
0 = REFT/REFB internally driven.
1 = REFT/REFB not driven.
Clamp enable control.
[2]
[3]
1
1
REFBUF_PWRDN
CLAMPENABLE
0 = disable black clamp.
1 = enable black clamp.
[5:4]
[6]
0
0
TESTMODE
PBLK_LVL
Test operation only. Set to 0.
PBLK level control.
0 = blank to 0.
1 = blank to clamp level.
DC restore circuit control.
0 = enable dc restore circuit during PBLK.
1 = bypass dc restore circuit during PBLK.
CDS operation.
[7]
0
0
DCBYP
[9:8]
CDSMODE
0 = normal (inverting) CDS mode.
1 = sample/hold amplifier (SHA) mode.
2 = positive (noninverting) CDS mode.
3 = invalid. Do not use.
[16:10]
[27:17]
[1:0]
0
TESTMODE
Unused
Test operation only. Set to 0.
Set unused bits to 0.
01
0
0
SCK
TESTMODE
GRAYENCODE
Test operation only. Set to 0.
Gray coding ADC outputs.
0 = disable.
[2]
1 = enable.
[3]
[4]
0
1
TESTMODE
TESTMODE
Unused
Test operation only. Set to 0.
Test operation only. Set to 0.
Set unused bits to 0.
[27:5]
[0]
[27:1]
[23:0]
[27:24]
[1:0]
02
03
04
0
TESTMODE
Unused
Test operation only. Set to 0.
Set unused bits to 0.
FFFFFF
1
TESTMODE
Unused
Test operation only. Set to FFFFFF.
Set unused bits to 0.
VD
CDSGAIN
CDS gain setting.
0 = −3 dB.
1 = 0 dB (default).
2 = +3 dB.
3 = +6 dB.
[27:2]
[9:0]
[27:10]
[9:0]
Unused
Set unused bits to 0.
05
06
F
VD
VD
VGAGAIN
Unused
VGA gain. 6 dB to 42 dB in 0.035 dB per step.
Set unused bits to 0.
1EC
CLAMPLEVEL
Unused
Optical black clamp level; 0 LSB to 1023 LSB (1 LSB per step).
Set unused bits to 0.
[27:10]
Rev. C | Page 43 of 56
AD9979
Data Bit
Content
Default
Value
Update
Type
Address
07
Name
Description
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[0]
0
0
0
0
0
0
0
TESTMODE
TESTMODE
TESTMODE
TESTMODE
TESTMODE
TESTMODE
CLIDIVIDE
Test operation only. Set to 0.
Test operation only. Set to 0.
Test operation only. Set to 0.
Test operation only. Set to 0.
Test operation only. Set to 0.
Test operation only. Set to 0.
CLI divide.
08
09
0A
0B
0C
0D
VD
1 = divide CLI input frequency by 2.
Test operation only. Set to 0.
Set unused bits to 0.
[3:1]
0
TESTMODE
Unused
[27:4]
[27:0]
[27:0]
0E
0F
Unused
Set unused register to 0, if accessed.
Set unused register to 0, if accessed.
Unused
Table 25. Miscellaneous Registers
Data Bit
Address Content
Default
Value
Update
Type
Name
Description
10
[0]
0
SCK
SW_RST
Software reset. Bit self-clears to 0 when a reset occurs.
1 = reset Address 0x00 to Address 0xFF to default values.
Set unused bits to 0.
[27:1]
[0]
Unused
11
0
VD
OUT_CONTROL
Output control.
0 = make all outputs dc inactive.
1 = enable outputs at next VD edge.
Set unused bits to 0.
[27:1]
[1:0]
[27:2]
[0]
[27:1]
[0]
Unused
12
13
14
0
0
0
TESTMODE
Unused
Test operation only. Set to 0.
Set unused bits to 0.
TESTMODE
Unused
Test operation only. Set to 0.
Set unused bits to 0.
SCK
SCK
TGCORE_RST
Timing core reset bar.
0 = hold in reset.
1 = resume operation.
Set unused bits to 0.
[27:1]
[0]
Unused
15
0
0
CLI_BIAS
Enable bias for CLI input (see Figure 9).
0 = disable bias (CLI input is dc-coupled).
1 = enable bias (CLI input is ac-coupled).
Set unused bits to 0.
[27:1]
[0]
[27:1]
[12:0]
Unused
16
17
TESTMODE
Unused
Test operation only. Set to 0.
Set unused bits to 0.
0
0
SCK
UPDATE
Serial interface update line. Sets the line (HD) within the field to
update the VD-updated registers. Disabled when PREVENTUP = 1.
Prevents normal update of VD-updated registers.
0 = normal update at VD.
[13]
PREVENTUP
1 = prevent update of VD-updated registers.
Set unused bits to 0.
[27:14]
[27:0]
[27:0]
[27:0]
Unused
18
0
0
TESTMODE
TESTMODE
Unused
Test operation only. Set to 0.
19
Test operation only. Set to 0.
1A to 1F
Set unused registers to 0.
Rev. C | Page 44 of 56
AD9979
Table 26. VD/HD Registers
Data Bit
Content
Default
Value
Update
Type
Address
Name
Description
20
[0]
[27:1]
[0]
0
TESTMODE
Unused
Test operation only. Set to 0.
Set unused bits to 0.
VD/HD active polarity.
0 = active low.
21
22
0
SCK
VDHDPOL
1 = active high.
[2:1]
[27:3]
[27:0]
0
0
TESTMODE
Unused
Test operation only. Set to 0.
Set unused bits to 0.
Test operation only. Set to 0.
TESTMODE
Table 27. I/O Control Registers
Data Bit
Content
Default
Value
Update
Type
Address
Name
Description
23
[0]
[1]
[2]
0
0
0
SCK
TESTMODE
TESTMODE
IO_NVR
Test operation only. Set to 0.
Test operation only. Set to 0.
IOVDD voltage range for VD, HD, SCK, SDATA, and SL.1
0 = 1.8 V.
1 = 3.3 V.
[3]
[4]
0
0
1
DATA_NVR
TESTMODE
HCLKMODE
Unused
DRVDD voltage range.
Test operation only. Set to 0.
Selects HCLK output configuration (see Table 8).
Set unused bits to 0.
[7:5]
[27:8]
[27:0]
[27:0]
[27:0]
[27:0]
24
25
26
27
0
0
0
0
TESTMODE
TESTMODE
TESTMODE
TESTMODE
Test operation only. Set to 0.
Test operation only. Set to 0.
Test operation only. Set to 0.
Test operation only. Set to 0.
1 The inputs/outputs are 3 V tolerant, so there is no problem having higher than 1.8 V inputs at startup; however, this register needs to be set to 1 at initialization if
using higher than 1.8 V supplies.
Table 28. Mode Control Registers
Data Bit
Content
Default
Value
Update
Type
Address
Name
Description
28
[4:0]
0
VD
HPATNUM
Unused
Total number of H-pattern groups.
Set unused bits to 0.
[27:5]
[27:0]
[2:0]
[27:3]
[4:0]
29
2A
Unused
Set unused register to 0, if accessed.
Total number of fields (set to 1 for single-field operation).
Set unused bits to 0.
0
VD
VD
FIELDNUM
Unused
2B
0
0
0
0
0
FIELD_SEL1
FIELD_SEL2
FIELD_SEL3
FIELD_SEL4
FIELD_SEL5
Unused
Selected first field.
Selected second field.
Selected third field.
Selected fourth field.
Selected fifth field.
Set unused bits to 0.
[9:5]
[14:10]
[19:15]
[24:20]
[27:25]
[4:0]
2C
0
0
VD
FIELD_SEL6
FIELD_SEL7
Unused
Selected sixth field.
Selected seventh field.
Set unused bits to 0.
[9:5]
[27:10]
[27:0]
[27:0]
[27:0]
2D
2E
2F
Unused
Set unused register to 0, if accessed.
Set unused register to 0, if accessed.
Set unused register to 0, if accessed.
Unused
Unused
Rev. C | Page 45 of 56
AD9979
Table 29. Timing Core Registers
Data Bit Default Update
Address Content Value
Type
Name
Description
30
31
32
33
34
[5:0]
[7:6]
[13:8]
[15:14]
[16]
0
SCK
H1POSLOC
Unused
H1NEGLOC
TESTMODE
H1POL
H1 rising edge location.
Set unused bits to 0.
H1 falling edge location.
Test operation only. Set to 0.
H1 polarity control.
20
0
1
0 = inverse of Figure 19.
1 = no inversion.
[27:17]
[5:0]
[7:6]
[13:8]
[15:14]
[16]
Unused
Set unused bits to 0.
H2 rising edge location.
Set unused bits to 0.
H2 falling edge location.
Test operation only. Set to 0.
H2 polarity control.
0
SCK
SCK
SCK
SCK
H2POSLOC
Unused
H2NEGLOC
TESTMODE
H2POL
20
0
1
0 = inverse of Figure 19.
1 = no inversion.
[27:17]
[5:0]
[7:6]
[13:8]
[15:14]
[16]
Unused
Set unused bits to 0.
HL rising edge location.
Set unused bits to 0.
HL falling edge location.
Test operation only. Set to 0.
HL polarity control.
0
HLPOSLOC
Unused
HLNEGLOC
TESTMODE
HLPOL
20
0
1
0 = inverse of Figure 19.
1 = no inversion.
[27:17]
[5:0]
[7:6]
[13:8]
[15:14]
[16]
Unused
Set unused bits to 0.
RG rising edge location.
Set unused bits to 0.
RG falling edge location.
Test operation only. Set to 0.
RG polarity control.
0 = inverse of Figure 19.
1 = no inversion.
Set unused bits to 0.
0
RGPOSLOC
Unused
RGNEGLOC
TESTMODE
RGPOL
10
0
1
[27:17]
[0]
Unused
0
H1BLKRETIME Retime H1 HBLK to internal clock.1
0 = no retime.
1 = enable retime.
[1]
[2]
[3]
0
0
0
H2BLKRETIME Retime H2 HBLK to internal clock.1, 2
HLBLKRETIME Retime HL HBLK to internal clock.1, 2
HL_HBLK_EN
Enables HBLK for HL output.
0 = disable.
1 = enable.
[7:4]
0
HCLK_WIDTH
Unused
Enables wide horizontal clocks during HBLK interval.
0 = disable (see Table 12).
Set unused bits to 0.
[27:8]
Rev. C | Page 46 of 56
AD9979
Data Bit Default Update
Address Content Value
Type
Name
Description
35
[2:0]
1
SCK
H1DRV
H1 drive strength.
0 = off.
1 = 4.3 mA.
2 = 8.6 mA.
3 = 12.9 mA.
4 = 17.2 mA.
5 =21.5 mA.
6 = 25.8 mA.
7 = 30.1 mA.
[3]
[6:4]
[7]
[10:8]
[11]
[14:12]
[15]
[18:16]
[19]
[22:20]
[27:23]
[5:0]
[11:6]
[17:12]
[27:18]
[5:0]
Unused
H2DRV
Unused
H3DRV
Unused
H4DRV
Unused
HLDRV
Unused
RGDRV
Unused
SHDLOC
SHPLOC
SHPWIDTH
Unused
Set unused bits to 0.
H2 drive strength.3
Set unused bits to 0.
H3 drive strength.3
Set unused bits to 0.
H4 drive strength.3
Set unused bits to 0.
HL drive strength.3
Set unused bits to 0.
RG drive strength.3
Set unused bits to 0.
SHD sampling edge location.
SHP sampling edge location.
SHP width. Controls input dc restore switch active time.
Set unused bits to 0.
1
1
1
1
1
36
37
0
20
10
SCK
SCK
0
DOUTPHASEP DOUT positive edge phase control.
[11:6]
20
DOUTPHASEN DOUT negative edge phase control. Set DOUTPHASEN =
DOUTPHASEP + 0x20.
[12]
0
2
DCLKMODE
0 = DCLK tracks DOUT phase.
1 = DCLK is CLI post-Schmitt trigger and postdivider when CLIDIVIDE = 1.
[14:13]
CLKDATA_SEL Data output clock selection.
0 = no delay.
1 = ~4 ns.
2 = ~8 ns.
3 =~12 ns.
[15]
0
INV_DCLK
0 = no inversion.
1 = invert DCLK to output.
[27:16]
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Set unused bits to 0.
38
39
3A
3B
3C
3D
Set unused register to 0 if accessed.
Set unused register to 0 if accessed.
Set unused register to 0 if accessed.
Set unused register to 0 if accessed.
Set unused register to 0 if accessed.
Set unused register to 0 if accessed.
1 Recommended setting is enable retime. Enabling retime adds one cycle delay to programmed HBLK positions.
2 See Address 34, Bit 0 for setting options.
3 See Address 35, Bits[2:0] for setting options.
Rev. C | Page 47 of 56
AD9979
Table 30. Test Registers—Do Not Access
Data Bit
Content
Default
Value
Update
Type
Address
Name
Description
3E
[18:0]
[27:19]
[27:0]
[3:0]
[9:4]
[27:10]
[27:0]
4B020
TESTMODE
Unused
Test operation only. Set to 4B020.
Set unused bits to 0.
3F
40
Unused
Set unused register to 0, if accessed.
Test operation only. Set to F, if accessed.
Test operation only. Set to 0.
Set unused bits to 0.
F
0
TESTMODE
TESTMODE
Unused
41 to 4F
Unused
Set unused registers to 0, if accessed.
Table 31. Shutter and GPIO Registers
Data
Bits
Default Update
Address
Value
Type
Name
Description
50
[2:0]
0
VD
PRIMARY_ACTION Selects action for primary and secondary counters.
0 = idle (do nothing). Auto-reset on VD.
1 = activate counter. Primary: auto-exposure/read.
2 = RapidShot. Wrap/repeat counter.
3 = ShotTimer. Delay start of count.
4 = test operation only.
5 = test operation only.
6 = test operation only.
7 = force to idle.
[27:3]
[3:0]
[7:4]
[8]
[27:9]
[1:0]
Unused
Set unused bits to 0, if accessed.
Primary counter maximum value.
Number of fields to delay before the next count (exposure) starts.
Test operation only. Set to 0.
Set unused bits to 0, if accessed.
Selects protocol for general-purpose signal GPO1.
0 = idle.
51
52
0
0
0
VD
VD
PRIMARY_MAX
PRIMARY_DELAY
TESTMODE
Unused
0
GP1_PROTOCOL
1 = no counter association.
2 = link to primary.
3 = primary repeat.
[3:2]
[5:4]
0
0
GP2_PROTOCOL
GP_LINE_MODE
Selects protocol for general-purpose signal GPO2.1
Enables general-purpose output signals on every line.
0 = disable.
1 = enable.
[6]
[7]
[9:8]
0
0
0
GP1_POL
GP2_POL
GP_LUT_EN
GPO1 low/high start polarity.
GPO2 low/high start polarity.
Use result from LUT or else GPO is unaltered.
Bit [8] = GPO1 enable.
Bit [9] = GPO2 enable.
[13:10]
[27:14]
0
GP12_LUT
Unused
Two-input LUT results. For example, {GP12_LUT} ← [GPO2:GPO1]
{0, 1, 1, 0} = GPO2 XOR GPO1.
{1, 1, 1, 0} = GPO2 OR GPO1.
{0, 1, 1, 1} = GPO2 NAND GPO1.
{1, 0, 0, 0} = GPO2 AND GPO1.
Set unused bits to 0, if accessed.
Rev. C | Page 48 of 56
AD9979
Data
Bits
Default Update
Address
Value
Type
Name
Description
53
[1:0]
0
VD
GPO_OUTPUT_EN
Enable both GPOs.
0 = both disabled.
3 = both enabled.
Select signal for GPO1 output.
0 = GPO.
[3:2]
0
SEL_GPO1
1 = CLPOB.
2 = PBLK.
3 = DLL_SIGNAL_GPO.
Select signal for GPO2 output.2
Select which high speed timing signal is used for GPO1 output.
0 = delayed CLI.
[5:4]
[7:6]
0
0
SEL_GPO2
SEL_HS_GPO1
1 = delayed ADC output latch clock.
2 = delayed SHD sample clock.
3 = delayed SHP sample clock.
[9:8]
[10]
[27:11]
[3:0]
0
0
SEL_HS_GPO2
HBLK_EXT
Unused
Select which high speed timing signal is used for GPO2 output.3
Enable external HBLK signal to be an input to GPO2.
Set unused bits to 0 if accessed.
54
0
0
VD
GPT1_TOG1_FIELD General-Purpose Signal 1, first toggle position, field location.
Unused
GPT1_TOG1_LINE
Unused
[12:4]
[25:13]
[27:26]
[12:0]
[16:13]
[27:19]
[12:0]
[25:13]
[27:25]
[3:0]
[12:4]
[25:13]
[27:26]
[12:0]
[16:13]
[27:19]
[12:0]
[25:13]
[27:25]
[27:0]
Set unused bits to 0 if accessed.
General-Purpose Signal 1, first toggle position, line location.
Set unused bits to 0 if accessed.
55
56
57
0
0
VD
VD
VD
GPT1_TOG1_PIXEL General-Purpose Signal 1, first toggle position, pixel location.
GPT1_TOG2_FIELD General-Purpose Signal 1, second toggle position, field location.
Unused
Set unused bits to 0 if accessed.
0
0
GPT1_TOG2_LINE
General-Purpose Signal 1, second toggle position, line location.
GPT1_TOG2_PIXEL General-Purpose Signal 1, second toggle position, pixel location.
Unused Set unused bits to 0 if accessed.
GPT2_TOG1_FIELD General-Purpose Signal 2, first toggle position, field location.
Unused
GPT2_TOG1_LINE
Unused
0
0
Set unused bits to 0 if accessed.
General-Purpose Signal 2, first toggle position, line location.
Set unused bits to 0 if accessed.
58
0
0
VD
VD
GPT2_TOG1_PIXEL General-Purpose Signal 2, first toggle position, pixel location.
GPT2_TOG2_FIELD General-Purpose Signal 2, second toggle position, field location.
Unused
Set unused bits to 0 if accessed.
59
0
0
GPT2_TOG2_LINE
General-Purpose Signal 2, second toggle position, line location.
GPT2_TOG2_PIXEL General-Purpose Signal 2, second toggle position, pixel location.
Unused
Unused
Set unused bits to 0 if accessed.
5A to 5F
Set unused registers to 0 if accessed.
1 See Address 52, Bits[1:0] for setting options.
2 See Address 53, Bits[3:2] for setting options.
3 See Address 53, Bits[7:6] for setting options.
Rev. C | Page 49 of 56
AD9979
Table 32. Update Control Registers
Data Bit Default Update
Address Content Value
Type
Name
Description
60
61
62
63
64
65
66
[15:0]
1803
E7FC
F8FD
0702
FFF9
0006
FFFF
SCK
AFE_UPDT_SCK
Enable SCK update of AFE registers. Each bit corresponds to
one address location.
AFE_UPDT_SCK[0] = 1; update Address 0x00 on SCK rising edge.
AFE_UPDT_SCK[1] = 1; update Address 0x01 on SCK rising edge.
…
AFE_UPDT_SCK[15] = 1; update Address 0x0F on SCK rising edge.
Set unused bits to 0, if accessed.
[27:16]
[15:0]
Unused
SCK
SCK
SCK
SCK
SCK
SCK
AFE_UPDT_VD
Enable VD update of AFE registers. Each bit corresponds to
one address location.
AFE_UPDT_VD[0] = 1; update Address 0x00 on VD rising edge.
AFE_UPDT_VD[1] = 1; update Address 0x01 on VD rising edge.
…
AFE_UPDT_VD[15] = 1; update Address 0x0F on VD rising edge.
Set unused bits to 0, if accessed.
[27:16]
[15:0]
Unused
MISC_UPDT_SCK
Enable SCK update of miscellaneous registers. Each bit corresponds to
one address location.
MISC_UPDT_SCK[0] = 1; update Address 0x10 on SCK rising edge.
MISC_UPDT_SCK[1] = 1; update Address 0x11 on SCK rising edge.
…
MISC_UPDT_SCK[15] = 1; update Address 0x1F on SCK rising edge.
Set unused bits to 0, if accessed.
[27:16]
[15:0]
Unused
MISC_UPDT_VD
Enable VD update of miscellaneous registers. Each bit corresponds to
one address location.
MISC_UPDT_VD[0] = 1; update Address 0x10 on VD rising edge.
MISC_UPDT_VD[1] = 1; update Address 0x11 on VD rising edge.
…
MISC_UPDT_VD[15] = 1; update Address 0x1F on VD rising edge.
Set unused bits to 0, if accessed.
[27:16]
[15:0]
Unused
VDHD_UPDT_SCK
Enable SCK update of VDHD registers. Each bit corresponds to
one address location.
VDHD_UPDT_SCK[0] = 1; update Address 0x20 on SCK rising edge.
VDHD_UPDT_SCK[1] = 1; update Address 0x21 on SCK rising edge.
…
VDHD_UPDT_SCK[15] = 1; update Address 0x22 on SCK rising edge.
Set unused bits to 0, if accessed.
[27:16]
[15:0]
Unused
VDHD_UPDT_VD
Enable VD update of VDHD registers. Each bit corresponds to
one address location.
VDHD_UPDT_SCK[0] = 1; update Address 0x20 on VD rising edge.
VDHD_UPDT_SCK[1] = 1; update Address 0x21 on VD rising edge.
…
VDHD_UPDT_SCK[15] = 1; update Address 0x22 on VD rising edge.
Set unused bits to 0, if accessed.
[27:16]
[15:0]
Unused
TGCORE_UPDT_SCK Enable SCK update of timing core registers. Each bit corresponds to
one address location.
TGCORE_UPDT_SCK[0] = 1; update Address 0x30 on SCK rising edge.
TGCORE_UPDT_SCK[1] = 1; update Address 0x31 on SCK rising edge.
…
TGCORE_UPDT_SCK[15] = 1; update Address 0x37 on SCK rising edge.
[27:16]
Unused
Set unused bits to 0, if accessed.
Rev. C | Page 50 of 56
AD9979
Data Bit Default Update
Address Content Value
Type
Name
Description
67
[15:0]
0000
SCK
TGCORE_UPDT_VD
Enable VD update of timing core registers. Each bit corresponds to
one address location.
TGCORE_UPDT_VD[0] = 1; update Address 0x30 on VD rising edge.
TGCORE_UPDT_VD[1] = 1; update Address 0x31 on VD rising edge.
…
TGCORE_UPDT_VD[15] = 1; update Address 0x37 on VD rising edge.
Set unused bits to 0, if accessed.
[27:16]
Unused
Unused
68 to 72 [27:0]
Set unused registers to 0, if accessed.
Table 33. HPAT Registers (HPAT Registers Always Start at Address 0x800)
Data Bit Default Update
Address Content Value 1 Type
Name
Description
00
01
02
03
04
05
[12:0]
X
SCP
SCP
SCP
SCP
SCP
SCP
HBLKTOGO1
First HBLK toggle position for odd lines, or RA0H1REPA/RA0H1REPB/
RA0H1REPC.
Second HBLK toggle position for odd lines, or RA1H1REPA/RA1H1REPB/
RA1H1REPC.
[25:13]
X
HBLKTOGO2
[27:26]
[12:0]
Unused
Set unused bits to 0.
X
X
HBLKTOGO3
Third HBLK toggle position for odd lines, or RA2H1REPA/RA2H1REPB/
RA2H1REPC.
Fourth HBLK toggle position for odd lines, or RA3H1REPA/RA3H1REPB/
RA3H1REPC.
[25:13]
HBLKTOGO4
[27:26]
[12:0]
Unused
Set unused bits to 0.
X
X
HBLKTOGO5
Fifth HBLK toggle position for odd lines, or RA4H1REPA/RA4H1REPB/
RA4H1REPC.
Sixth HBLK toggle position for odd lines, or RA5H1REPA/RA5H1REPB/
RA5H1REPC.
[25:13]
HBLKTOGO6
[27:26]
[12:0]
Unused
Set unused bits to 0.
X
X
HBLKTOGE1
First HBLK toggle position for even lines, or RA0H2REPA/RA0H2REPB/
RA0H2REPC.
Second HBLK toggle position for even lines, or RA1H2REPA/RA1H2REPB/
RA1H2REPC.
[25:13]
HBLKTOGE2
[27:26]
[12:0]
Unused
Set unused bits to 0.
X
X
HBLKTOGE3
Third HBLK toggle position for even lines, or RA2H2REPA/RA2H2REPB/
RA2H2REPC.
Fourth HBLK toggle position for even lines, or RA3H2REPA/RA3H2REPB/
RA3H2REPC.
[25:13]
HBLKTOGE4
[27:26]
[12:0]
Unused
Set unused bits to 0.
X
X
HBLKTOGE5
Fifth HBLK toggle position for even lines, or RA4H2REPA/RA4H2REPB/
RA4H2REPC.
Sixth HBLK toggle position for even lines, or RA5H2REPA/RA5H2REPB/
RA5H2REPC.
[25:13]
HBLKTOGE6
[27:26]
[12:0]
[25:13]
[27:26]
[12:0]
Unused
Set unused bits to 0.
06
07
X
X
SCP
SCP
HBLKSTARTA
HBLKSTARTB
Unused
HBLK Repeat Area Start Position A. Used during HBLK Mode 2.
HBLK Repeat Area Start Position B. Used during HBLK Mode 2.
Set unused bits to 0.
X
HBLKSTARTC
Unused
HBLK Repeat Area Start Position C. Used during HBLK Mode 2.
Set unused bits to 0.
[27:13]
Rev. C | Page 51 of 56
AD9979
Data Bit Default Update
Address Content Value 1 Type
Name
Description
08
[2:0]
[5:3]
[8:6]
[11:9]
[14:12]
[17:15]
[19:18]
X
X
X
X
X
X
X
SCP
HBLKALT_PAT1
HBLKALT_PAT2
HBLKALT_PAT3
HBLKALT_PAT4
HBLKALT_PAT5
HBLKALT_PAT6
HBLKMODE
HBLK Pattern 1 order. Used during pixel mixing mode.
HBLK Pattern 2 order. Used during pixel mixing mode.
HBLK Pattern 3 order. Used during pixel mixing mode.
HBLK Pattern 4 order. Used during pixel mixing mode.
HBLK Pattern 5 order. Used during pixel mixing mode.
HBLK Pattern 6 order. Used during pixel mixing mode.
HBLK mode selection.
0 = normal HBLK.
1 = pixel mixing mode.
2 = special pixel mixing mode.
3 = not used.
[20]
X
TESTMODE
Unused
Test operation only. Set to 0.
Set unused bits to 0.
[27:21]
[12:0]
[20:13]
[21]
09
0A
X
X
X
X
SCP
SCP
HBLKLEN
HBLKREP
HBLKMASK_H1
HBLKMASK_H2
Unused
HBLK length in HBLK alteration modes.
Number of HBLK repetitions in HBLK alternation modes.
Masking polarity for H1/H3 during HBLK.
Masking polarity for H2/H4 during HBLK.
Set unused bits to 0.
[22]
[27:23]
[12:0]
[25:13]
[27:26]
[27:0]
[12:0]
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
X
X
HBLKSTART
HBLKEND
Unused
HBLK start position used in pixel mixing modes.
HBLK end position used in pixel mixing modes.
Set unused bits to 0.
0B
0C
X
X
X
TESTMODE
CLPOB0_TOG1
CLPOB0_TOG2
Unused
Test operation only. Set to 0.
SCP
SCP
SCP
SCP
CLPOB0 Toggle Position 1.
CLPOB0 Toggle Position 2.
Set unused bits to 0.
0D
0E
0F
X
X
CLPOB1_TOG1
CLPOB1_TOG2
Unused
CLPOB1 Toggle Position 1.
CLPOB1 Toggle Position 2.
Set unused bits to 0.
X
X
PBLK0_TOG1
PBLK0_TOG2
Unused
PBLK0 Toggle Position 1.
PBLK0 Toggle Position 2.
Set unused bits to 0.
X
X
PBLK1_TOG1
PBLK1_TOG2
Unused
PBLK1 Toggle Position 1.
PBLK1 Toggle Position 2.
Set unused bits to 0.
1 X = Don’t care.
Table 34. Field Registers
Data Bit Default Update
Address Content Value1
Type
Name
SCP0
Description
00
01
02
03
[12:0]
X
X
VD
Sequence Change Position 0.
Sequence Change Position 1.
Set unused bits to 0.
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
SCP1
Unused
SCP2
SCP3
Unused
SCP4
SCP5
Unused
SCP6
SCP7
Unused
X
X
VD
VD
VD
Sequence Change Position 2.
Sequence Change Position 3.
Set unused bits to 0.
X
X
Sequence Change Position 4.
Sequence Change Position 5.
Set unused bits to 0.
X
X
Sequence Change Position 6.
Sequence Change Position 7.
Set unused bits to 0.
Rev. C | Page 52 of 56
AD9979
Data Bit Default Update
Address Content Value1
Type
Name
Description
04
[12:0]
[27:13]
[4:0]
X
VD
SCP8
Unused
Sequence Change Position 8.
Set unused bits to 0.
05
X
X
X
X
X
VD
VD
VD
HPAT_SEL0
HPAT_SEL1
HPAT_SEL2
HPAT_SEL3
HPAT_SEL4
Unused
Selected H-pattern for first region in field.
Selected H-pattern for second region in field.
Selected H-pattern for third region in field.
Selected H-pattern for fourth region in field.
Selected H-pattern for fifth region in field.
Set unused bits to 0.
[9:5]
[14:10]
[19:15]
[24:20]
[27:25]
[4:0]
06
X
X
X
X
HPAT_SEL5
HPAT_SEL6
HPAT_SEL7
HPAT_SEL8
Unused
Selected H-pattern for sixth region in field.
Selected H-pattern for seventh region in field.
Selected H-pattern for eighth region in field.
Selected H-pattern for ninth region in field.
Set unused bits to 0.
[9:5]
[14:10]
[19:15]
[27:20]
[27:0]
[8:0]
07
08
Unused
Set unused register to 0.
X
X
CLPOB_POL
CLPOB_PAT
CLPOB start polarity settings.
CLPOB pattern selector.
[17:9]
0 = CLPOB0_TOGx registers are used.
1 = CLPOB1_TOGx registers are used.
Set unused bits to 0.
[27:18]
[12:0]
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
[8:0]
Unused
09
0A
0B
0C
X
X
VD
VD
VD
VD
CLPOBMASKSTART1 CLPOB Mask Region 1 start position.
CLOBMASKEND1
Unused
CLPOB Mask Region 1 end position.
Set unused bits to 0.
X
X
CLPOBMASKSTART2 CLPOB Mask Region 2 start position.
CLOBMASKEND2
Unused
CLPOB Mask Region 2 end position.
Set unused bits to 0.
X
X
CLPOBMASKSTART3 CLPOB Mask Region 3 start position.
CLOBMASKEND3
Unused
CLPOB Mask Region 3 end position.
Set unused bits to 0.
X
X
PBLK_POL
PBLK_PAT
PBLK start polarity settings for Sequence 0 to Sequence 8.
PBLK pattern selector.
[17:9]
0 = PBLK0_TOGx registers are used.
1 = PBLK1_TOGx registers are used.
Set unused bits to 0
[27:18]
[12:0]
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
[12:0]
[25:13]
[27:26]
Unused
0D
0E
0F
X
X
VD
VD
VD
PBLKMASKSTART1
PBLKMASKEND1
Unused
PBLK Mask Region 1 start position.
PBLK Mask Region 1 end position.
Set unused bits to 0.
X
X
PBLKMASKSTART2
PBLKMASKEND2
Unused
PBLK Mask Region 2 start position.
PBLK Mask Region 2 end position.
Set unused bits to 0.
X
X
PBLKMASKSTART3
PBLKMASKEND3
Unused
PBLK Mask Region 3 start position.
PBLK Mask Region 3 end position.
Set unused bits to 0.
1 X = Don’t care.
Rev. C | Page 53 of 56
AD9979
OUTLINE DIMENSIONS
0.30
0.23
0.18
7.00
0.60 MAX
BSC SQ
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
5.25
5.10 SQ
4.95
TOP
VIEW
6.75
BSC SQ
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
SECTION OF THIS DATA SHEET.
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 60. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9979BCPZ
Temperature Range
−25°C to +85°C
−25°C to +85°C
Package Description
Package Option
CP-48-1
CP-48-1
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
AD9979BCPZRL
1 Z = RoHS Compliant Part.
Rev. C | Page 54 of 56
AD9979
NOTES
Rev. C | Page 55 of 56
AD9979
NOTES
©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05957-0-10/09(C)
Rev. C | Page 56 of 56
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