AD9940BCPZ [ADI]
High Speed, Correlated Double Sampler with Integrated Timing Driver;
| 型号： | AD9940BCPZ |
| 厂家： | 
ADI |
| 描述： | High Speed, Correlated Double Sampler with Integrated Timing Driver 商用集成电路 |
| 文件： | 总20页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, Correlated Double Sampler
with Integrated Timing Driver
AD9940
FEATURES
GENERAL DESCRIPTION
56 MSPS correlated double sampler (CDS) with 6 dB gain
On-chip horizontal and RG timing driver
Single-supply operation (2.7 V min )
Precision Timing™ core with 0.37 ns resolution at 56 MSPS
Low power CMOS: 105 mW at 2.7 V (115 mW at 3.0 V)
48-lead LQFP and 48-lead LFCSP packages
The AD9940 is a high speed, correlated double sampler for
high speed digital imaging applications. Integrated with a
programmable timing driver using the Precision Timing
core, the AD9940 features a 56 MHz CDS amplifier with
6 dB of fixed gain, an internal voltage reference supply,
and timing control for all the high speed clocks necessary
for CCD imaging systems. The Precision Timing core allows
adjustment of high speed clocks with a resolution of 0.37 ns.
Output buffers are also included, providing drive strength for
PCB traces and direct connection to an image signal processor
such as the AD9941.
APPLICATIONS
Professional HDTV camcorders
Professional/high end digital cameras
Broadcast cameras
Industrial high speed cameras
High speed data-acquisition systems
The AD9940 is ideal for applications that need to place the
CDS and VGA/ADC circuits on separate PC boards. The fully
differential outputs of the AD9940 provide good signal integ-
rity when interfaced with the differential input AD9941. The
AD9940 operates from a single 2.7 V power supply, typically
dissipates 105 mW (excluding the H/RG drive current), and is
packaged in 48-lead LQFP and 48-lead LFCSP packages.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
AD9940
V
REF
DIFFN
DIFFP
CCDIN
CDS
BUF
INTERNAL
CLOCKS
RG
HL
PRECISION
TIMING
GENERATOR
HORIZONTAL
DRIVERS
RST
4
H1 TO H4
SYNC
INTERNAL
GENERATOR
REGISTERS
CLI
HD SHP SHD
SL
SCK SDI
.
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2005 Analog Devices, Inc. All rights reserved.
AD9940
TABLE OF CONTENTS
Specifications..................................................................................... 3
System Overview ............................................................................ 13
Analog Front End Operation.................................................... 13
Precision Timing, High Speed Timing Generation................... 14
Timing Resolution...................................................................... 14
High Speed Clock Programmability........................................ 14
H-Driver and RG Outputs ........................................................ 16
HBLK Sequences........................................................................ 17
Application Information................................................................ 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Analog Specifications................................................................... 4
Digital Specifications ................................................................... 5
Timing Specifications (Slave Timing Mode) ............................ 5
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Data Bit Descriptions....................................................................... 9
Serial Interface Timing .................................................................. 12
REVISION HISTORY
7/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD9940
SPECIFICATIONS
Table 1.
Parameter
Min
Typ
Max
Unit
TEMPERATURE RANGE
Operating
Storage
−25
−65
56
+85
+150
°C
°C
MAXIMUM CLOCK RATE
MHz
POWER SUPPLY VOLTAGE
AVDD, TCVDD (AFE, Timing Core)
OVDD (Analog Buffer)
DVDD (Digital)
HVDD (H1 to H4 Drivers)
RGVDD (RG Driver)
2.7
2.7
2.7
2.7
2.7
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
3.6
3.6
V
V
V
V
V
POWER DISSIPATION1
56 MHz, AFE supplies = 2.7 V, HVDD = RGVDD = 3.2 V, 70 pF, H1 to H4 Loading
56 MHz, AFE supplies = 3.0 V, HVDD = RGVDD = 3.2 V, 70 pF, H1 to H4 Loading
56 MHz, AFE supplies = 2.7 V, no H or RG drivers
56 MHz, AFE supplies = 3.0 V, no H or RG drivers
Standby Mode
265
275
105
115
2
mW
mW
mW
mW
mW
1 The total power dissipated by the HVDD supply can be approximated using the following equation:
Total HVDD Power = (CLOAD × HVDD × Pixel Frequency) × HVDD
Reducing the H-loading and/or using a lower HVDD supply reduces the power dissipation.
Rev. 0 | Page 3 of 20
AD9940
ANALOG SPECIFICATIONS
fCLI = 56 MHz, AVDD = OVDD = DVDD = TCVDD = 3.0 V, −25°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Notes
CDS
Gain
5.0
5.5
500
1
50
0.2
36
6.0
dB
mV
V p-p
mV
% FS
dB
Allowable CCD Reset Transient1
Maximum Input Range Before Saturation1
Maximum CCD Black Pixel Amplitude1
Peak Nonlinearity, 500 mV Input Signal
Power Supply Rejection (PSR)
ANALOG OUTPUTS2
Measured with step change on supply
Typical DIFFP Output Signal Range
Typical DIFFN Output Signal Range
Typical Common Mode Level
Maximum Differential Output Voltage Swing
Output Voltage Compliance
Maximum Load Capacitance
Minimum Load Resistance (if required)
1.2
1.2
2.2
2.2
V
V
V
V
V
1.2 V corresponds to black level
2.2 V corresponds to black level
Midscale voltage where DIFFP = DIFFN
Defined as DIFFP − DIFFN
Limitation of output swing into external load
Value for each output (AD9941 CIN is < 24 pF)
Only use resistive loading if required by the
differential receiver. Proper dc biasing should
be used to be compatible with levels in Figure 3
1.7
2
1.0
2.4
24
pF
Ω
5,000
1 Input signal characteristics are defined in Figure 2.
2 Output signal characteristics are defined in Figure 3.
500mV TYP
RESET TRANSIENT
50mV TYP
OPTICAL BLACK PIXEL
850mV TYP
INPUT SIGNAL RANGE
Figure 2. Input Signal Characteristics
1V MAX OUTPUT SIGNAL SWING, DIFFP AND DIFFN
2V p-p MAX DIFFERENTIAL SIGNAL, DIFFP–DIFFN
2.2V
DIFFN
BLACK
LEVEL
WHITE
LEVEL
1.7V
1.2V
DIFFP
GND
Figure 3. Output Signal Characteristics
Rev. 0 | Page 4 of 20
AD9940
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = DVDD = OVDD = TCVDD = HVDD = RGVDD = 2.7 V, −25°C to +85°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
VIH
VIL
IIH
IIL
CIN
2.1
V
V
μA
μA
pF
0.6
10
10
10
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage, IOH = 2 mA
Low Level Output Voltage, IOL = 2 mA
CLI INPUT
VOH
VOL
2.2
V
V
0.5
High Level Input Voltage
Low Level Input Voltage
VIH–CLI
VIL–CLI
1.85
V
V
0.85
0.5
RG-DRIVER AND H-DRIVER OUTPUTS (powered by HVDD, RGVDD)
High Level Output Voltage (at max output current)
Low Level Output Voltage (at max output current)
Maximum Output Current (programmable)
H-Driver (per output)
VOH
VOL
VDD − 0.5
V
V
64
15
mA
mA
RG-Driver, HL-Driver
Maximum Load Capacitance
H-Driver (per output)
RG-Driver, HL-Driver
100
50
pF
pF
TIMING SPECIFICATIONS (SLAVE TIMING MODE)
See Figure 10 for Timing Diagram.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
MASTER CLOCK (CLI)
CLI Clock Period
CLI High Pulse Width
Internal Delay from CLI to First Tap
SAMPLE CLOCKS
TCLI
TADC
TCLIDLY
18
ns
ns
ns
9
6
SHP Rising to SHD Rising
ADCLK Edge Placement for AD9941
SERIAL INTERFACE
TS1
TREC
7.4
9
3
ns
ns
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Rising Edge to SDATA Valid Hold
fSCLK
tLS
tLH
tDS
tDH
10
10
10
10
10
MHz
ns
ns
ns
ns
Rev. 0 | Page 5 of 20
AD9940
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
AVDD and TCVDD to AVSS
HVDD and RGVDD to HVSS and
RGVSS
−0.3 V to +3.9 V
−0.3 V to +3.9 V
DVDD and OVDD to DVSS and OVSS −0.3 V to +3.9 V
Any VSS to Any VSS
−0.3 V to +0.3 V
CLPOB/HBLK to DVSS
SCK, SL, and SDI to DVSS
RG to RGVSS
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to RGVDD + 0.3 V
−0.3 V to HVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
150°C
THERMAL CHARACTERISTICS
θJA is measured using a 4-layer PCB with the exposed paddle
soldered to the board.
H1–H4 to HVSS
REFT, REFB, and CCDIN to AVSS
Junction Temperature
Lead Temperature (10 sec)
Thermal resistance for 48-lead LQFP package:
θJA = 92°C/W
350°C
Thermal resistance for 48-lead LFCSP package:
θJA = 24°C/W1
1 θJA is measured using a 4-layer PCB with the exposed paddle
soldered to the board.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 20
AD9940
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
1
36
35
34
33
32
31
30
29
28
27
26
25
NC
AVSS
CCDIN
AVSS
SHP
SHD
AVSS
H1
PIN 1
2
3
AVSS
AVDD
DIFFN
DIFFP
OVSS
OVDD
TCVDD
CLI
4
5
AD9940
TOP VIEW
(Not to Scale)
6
7
8
H2
9
HVSS
HVDD
H3
10
11
12
TCVSS
DVSS
DVDD
H4
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Menumonic
Type1
NC
P
Description
1
2
3
4
5
6
7
8
NC
No Connect. Connect to GND.
Analog Ground.
Analog Supply.
AVSS
AVDD
DIFFN
DIFFP
OVSS
OVDD
TCVDD
CLI
TCVSS
DVSS
DVDD
DVSS
SL
DVSS
SDI
SCK
RST
HD
NC
RG
HL
P
AO
AO
P
P
P
DI
P
P
P
P
CDS Output, Data (Negative).
CDS Output, Data (Positive).
Analog Output Buffer Ground.
Analog Output Buffer Supply.
Analog Supply for Timing Core.
Reference Clock Input.
Analog Ground for Timing Core.
Digital Ground.
Digital Logic Power Supply.
Digital Ground.
3-Wire Serial Load Pulse.
Digital Ground.
3-Wire Serial Data Input.
3-Wire Serial Clock.
Hardware Reset (Low Active). Low = Reset state, High = Normal operation.
Horizontal Sync Pulse.
Do No Connect. Should be left floating.
CCD Reset Gate Clock.
HL Horizontal Clock.
RG Driver Ground.
RG Driver Power Supply.
CCD Horizontal Clock 4.
CCD Horizontal Clock 3.
Horizontal Clock Driver Supply.
Horizontal Clock Driver Ground.
CCD Horizontal Clock 2.
CCD Horizontal Clock 1.
Analog Ground.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DI
P
DI
DI
DI
DI
NC
DO
DO
P
RGVSS
RGVDD
H4
P
DO
DO
P
H3
HVDD
HVSS
H2
H1
AVSS
SHD
P
DO
DO
P
DI
Test Clock Input for CCD Data Phase Sampling.
Rev. 0 | Page 7 of 20
AD9940
Pin No.
33
34
Menumonic
SHP
AVSS
Type1
DI
P
Description
Test Clock Input for CCD Reset Phase Sampling.
Analog Ground.
35
36
CCDIN
AVSS
AI
P
CCD Signal Input.
Analog Ground (CCD Signal Input Reference).
37
38
AVDD
AVSS
P
P
Analog Supply.
Analog Ground.
39
40
41 to 46
47, 48
REFB
REFT
NC
AVSS
AO
AO
NC
P
Voltage Reference Bottom By-Pass. Decoupled to analog ground with a 0.1 μF capacitor.
Voltage Reference Top By-Pass. Decoupled to analog ground with a 0.1 μF capacitor.
No Connect. Connect to GND.
Analog Ground.
1 Type: AI = analog input; AO = analog output; DI = digital input; DO = digital output; P = power.
Rev. 0 | Page 8 of 20
AD9940
DATA BIT DESCRIPTIONS
Table 7.
Address
Data Bit Content
Default Value
Name
Description
0
[0]
0
PARTSEL
Part Select:
0 = select AD9940
1 = select AD9941
[1]
[2]
0
0
TESTMODE
SW RESET
Always set = 0
Reset registers:
1 = reset all registers to the default values
0 = slave mode
1 = master mode
[3]
[4]
0
0
MODE
STANDBY
0 = normal operation
1 = standby operation
[6:5]
[7]
0
0
TESTMODE
WRITEMODE
Always Set = 0
0 = write to Address 1 to Address 13
1 = write to Address 14 to Address 26
Always set = 0
1
2
[6:0]
[7]
0
0
TESTMODE
HBLKMASKPOL
HBLK mask polarity:
0 = H1/H3 low, H2/H4 high
1 = H1/H3 high, H2/H4 low
[0]
[1]
[2]
[3]
[7:4]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[7:4]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[7:4]
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
HBLKTOG1_0 [8]
HBLKTOG1_0 [9]
HBLKTOG1_0 [10]
HBLKTOG1_0 [11]
TESTMODE
HBLKTOG1 position for Sequence 0 (Bit 8)
HBLKTOG1 position for Sequence 0 (Bit 9)
HBLKTOG1 position for Sequence 0 (Bit 10)
HBLKTOG1 position for Sequence 0 (Bit 11)
Always set = 0
3
HBLKTOG1_0 [0]
HBLKTOG1_0 [1]
HBLKTOG1_0 [2]
HBLKTOG1_0 [3]
HBLKTOG1_0 [4]
HBLKTOG1_0 [5]
HBLKTOG1_0 [6]
HBLKTOG1_0 [7]
HBLKTOG2_0 [8]
HBLKTOG2_0 [9]
HBLKTOG2_0 [10]
HBLKTOG2_0 [11]
TESTMODE
HBLKTOG1 position for Sequence 0 (Bit 0)
HBLKTOG1 position for Sequence 0 (Bit 1)
HBLKTOG1 position for Sequence 0 (Bit 2)
HBLKTOG1 position for Sequence 0 (Bit 3)
HBLKTOG1 position for Sequence 0 (Bit 4)
HBLKTOG1 position for Sequence 0 (Bit 5)
HBLKTOG1 position for Sequence 0 (Bit 6)
HBLKTOG1 position for Sequence 0 (Bit 7)
HBLKTOG2 position for Sequence 0 (Bit 8)
HBLKTOG2 position for Sequence 0 (Bit 9)
HBLKTOG2 position for Sequence 0 (Bit 10)
HBLKTOG2 position for Sequence 0 (Bit 11)
Always set = 0
4
5
HBLKTOG2_0 [0]
HBLKTOG2_0 [1]
HBLKTOG2_0 [2]
HBLKTOG2_0 [3]
HBLKTOG2_0 [4]
HBLKTOG2_0 [5]
HBLKTOG2_0 [6]
HBLKTOG2_0 [7]
HBLKTOG1_1 [8]
HBLKTOG1_1 [9]
HBLKTOG1_1 [10]
HBLKTOG1_1 [11]
TESTMODE
HBLKTOG2 position for Sequence 0 (Bit 0)
HBLKTOG2 position for Sequence 0 (Bit 1)
HBLKTOG2 position for Sequence 0 (Bit 2)
HBLKTOG2 position for Sequence 0 (Bit 3)
HBLKTOG2 position for Sequence 0 (Bit 4)
HBLKTOG2 position for Sequence 0 (Bit 5)
HBLKTOG2 position for Sequence 0 (Bit 6)
HBLKTOG2 position for Sequence 0 (Bit 7)
HBLKTOG1 position for Sequence 1 (Bit 8)
HBLKTOG1 position for Sequence 1 (Bit 9)
HBLKTOG1 position for Sequence 1 (Bit 10)
HBLKTOG1 position for Sequence 1 (Bit 11)
Always set = 0
6
Rev. 0 | Page 9 of 20
AD9940
Address
Data Bit Content
Default Value
Name
Description
7
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[7:4]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[7:4]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[7:4]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
HBLKTOG1_1 [0]
HBLKTOG1_1 [1]
HBLKTOG1_1 [2]
HBLKTOG1_1 [3]
HBLKTOG1_1 [4]
HBLKTOG1_1 [5]
HBLKTOG1_1 [6]
HBLKTOG1_1 [7]
HBLKTOG2_1 [8]
HBLKTOG2_1 [9]
HBLKTOG2_1 [10]
HBLKTOG2_1 [11]
TESTMODE
HBLKTOG1 position for Sequence 1 (Bit 0)
HBLKTOG1 position for Sequence 1 (Bit 1)
HBLKTOG1 position for Sequence 1 (Bit 2)
HBLKTOG1 position for Sequence 1 (Bit 3)
HBLKTOG1 position for Sequence 1 (Bit 4)
HBLKTOG1 position for Sequence 1 (Bit 5)
HBLKTOG1 position for Sequence 1 (Bit 6)
HBLKTOG1 position for Sequence 1 (Bit 7)
HBLKTOG2 position for Sequence 1 (Bit 8)
HBLKTOG2 position for Sequence 1 (Bit 9)
HBLKTOG2 position for Sequence 1 (Bit 10)
HBLKTOG2 position for Sequence 1 (Bit 11)
Always set = 0
8
9
HBLKTOG2_1 [0]
HBLKTOG2_1 [1]
HBLKTOG2_1 [2]
HBLKTOG2_1 [3]
HBLKTOG2_1 [4]
HBLKTOG2_1 [5]
HBLKTOG2_1 [6]
HBLKTOG2_1 [7]
HBLKTOG1_2 [8]
HBLKTOG1_2 [9]
HBLKTOG1_2 [10]
HBLKTOG1_2 [11]
TESTMODE
HBLKTOG2 position for Sequence 1 (Bit 0)
HBLKTOG2 position for Sequence 1 (Bit 1)
HBLKTOG2 position for Sequence 1 (Bit 2)
HBLKTOG2 position for Sequence 1 (Bit 3)
HBLKTOG2 position for Sequence 1 (Bit 4)
HBLKTOG2 position for Sequence 1 (Bit 5)
HBLKTOG2 position for Sequence 1 (Bit 6)
HBLKTOG2 position for Sequence 1 (Bit 7)
HBLKTOG1 position for Sequence 2 (Bit 8)
HBLKTOG1 position for Sequence 2 (Bit 9)
HBLKTOG1 position for Sequence 2 (Bit 10)
HBLKTOG1 position for Sequence 2 (Bit 11)
Always set = 0
10
11
HBLKTOG1_2 [0]
HBLKTOG1_2 [1]
HBLKTOG1_2 [2]
HBLKTOG1_2 [3]
HBLKTOG1_2 [4]
HBLKTOG1_2 [5]
HBLKTOG1_2 [6]
HBLKTOG1_2 [7]
HBLKTOG2_2 [8]
HBLKTOG2_2 [9]
HBLKTOG2_2 [10]
HBLKTOG2_2 [11]
TESTMODE
HBLKTOG1 position for Sequence 2 (Bit 0)
HBLKTOG1 position for Sequence 2 (Bit 1)
HBLKTOG1 position for Sequence 2 (Bit 2)
HBLKTOG1 position for Sequence 2 (Bit 3)
HBLKTOG1 position for Sequence 2 (Bit 4)
HBLKTOG1 position for Sequence 2 (Bit 5)
HBLKTOG1 position for Sequence 2 (Bit 6)
HBLKTOG1 position for Sequence 2 (Bit 7)
HBLKTOG2 position for Sequence 2 (Bit 8)
HBLKTOG2 position for Sequence 2 (Bit 9)
HBLKTOG2 position for Sequence 2 (Bit 10)
HBLKTOG2 position for Sequence 2 (Bit 11)
Always set = 0
12
13
HBLKTOG2_2 [0]
HBLKTOG2_2 [1]
HBLKTOG2_2 [2]
HBLKTOG2_2 [3]
HBLKTOG2_2 [4]
HBLKTOG2_2 [5]
HBLKTOG2_2 [6]
HBLKTOG2_2 [7]
HBLKTOG2 position for Sequence 2 (Bit 0)
HBLKTOG2 position for Sequence 2 (Bit 1)
HBLKTOG2 position for Sequence 2 (Bit 2)
HBLKTOG2 position for Sequence 2 (Bit 3)
HBLKTOG2 position for Sequence 2 (Bit 4)
HBLKTOG2 position for Sequence 2 (Bit 5)
HBLKTOG2 position for Sequence 2 (Bit 6)
HBLKTOG2 position for Sequence 2 (Bit 7)
Rev. 0 | Page 10 of 20
AD9940
Address
Data Bit Content
Default Value
Name
Description
14
[2:0]
3
RGDRV
RG drive strength (resolution = 2.2 mA/Step):
0 = Off
1 = 2.2 mA
2 = 4.4 mA
…
7 = 15.4 mA
[3]
0
3
RGPOL
HLDRV
RG polarity:
0 = normal
1 = inverted
[6:4]
HL drive strength (Resolution = 2.2 mA/Step):
0 = off
1 = 2.2 mA
2 = 4.4 mA
…
7 = 15.4 mA
[7]
0
HLPOL
HL polarity:
0 = normal
1 = inverted
15
16
17
18
19
[5:0]
[7:6]
[5:0]
[7:6]
[5:0]
[7:6]
[5:0]
[7:6]
[3:0]
0
HLPOSLOC
Unused
HL rising edge location
HL negative edge location
RG rising edge location
RG negative edge location
—
24
0
HLNEGLOC
Unused
0
RGPOSLOC
Unused
—
24
—
7
RGNEGLOC
Unused
H2/H4DRV
H2/H4 drive strength (resolution = 4.3 mA/Step):
0 = Off
1 = 4.3 mA
2 = 8.6 mA
…
15 =64.5 mA
[7:4]
7
H1/H3DRV
H1/H3 drive strength (resolution = 4.3 mA/Step):
0 = Off
1 = 4.3 mA
2 = 8.6 mA
…
15 = 64.5 mA
20
[5:0]
[6]
[7]
0
—
0
H1POSLOC
Unused
H1/H3POL
H1 positive edge location
H1/H3 polarity:
0 = normal
1 = inverted
(H2/H4 is opposite polarity of H1/H3)
H1 negative edge location
21
22
23
[5:0]
[7:6]
[5:0]
[7:6]
[5:0]
[7:6]
[7:0]
[7:0]
[7:0]
32
—
32
0
H1NEGLOC
Unused
SHPLOC
Unused
SHP sampling location
SHD sampling location
0
—
0
SHDLOC
Unused
24
25
26
TESTMODE
TESTMODE
TESTMODE
Always set = 0
Always set = 0
Always set = 0
0
0
Rev. 0 | Page 11 of 20
AD9940
SERIAL INTERFACE TIMING
All the internal registers of the AD9940 are accessed through
a 3-wire serial interface. Each register consists of an 8-bit data
byte starting with the LSB bit. As shown in Figure 5, the data
bits are clocked in on the rising edge of SCK after SL is asserted
low and the entire 8-bit word is latched in on the rising edge
of SL after the last MSB bit. Consecutive serial writes are per-
formed starting with Address 0 and ending with an address
MSB bit prior to asserting SL high.
Every write operation must begin with a write to Address 0 to
specify Part select bit and Bank location, then followed with any
number of consecutive data words. Address 0 is always followed
by Address 01 or Address 14 depending on the value specified
for WRITEMODE (used for Bank selection).
A hard reset is recommended after power-up to reset the
AD9940 prior to performing a serial interface write. A hard
reset is performed by asserting the RST pin low for a mini-
mum of 10 μs. The serial interface pins SCK, SL, and SDI
must be in a know state after the RST has been applied.
The AD9940 contains two banks of registers, which are
programmed independently. Bank 1 consists of the registers
located at Address 0 to Address 13, and Bank 2 consists of
Address 14 to Address 26. The WRITEMODE register located
at Address 0 is used to select which register bank is written to.
ADDR 00
ADDR 01
D2 D3
ADDR N
ADDR N+1
...
...
...
...
SDATA
D7 D0 D1
D3
D7
D3
D7 D0
D3
D7
D0
D2
D0 D1
D2
D1 D2
D1
tDS
tDH
...
...
...
...
SCK
SL
tLS
tLH
...
NOTES
1. ANY NUMBER OF ADJACENT REGISTERS CAN BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS 00.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED
FOR EACH REGISTER.
3. ALL LOADED REGISTERS ARE SIMULTANEOUSLY UPDATED ON THE RISING EDGE OF SL.
Figure 5. Serial Interface Operation
Rev. 0 | Page 12 of 20
AD9940
SYSTEM OVERVIEW
Figure 6 shows the typical system block diagram for the
AD9940. The CCD output is processed by the AD9940’s
AFE circuitry, which consists of a correlated double sam-
pler (CDS) and output buffer. The differential output of the
AD9940 provides good signal integrity when interfaced with
the AD9941.
ANALOG FRONT END OPERATION
The AD9940 signal-processing chain is shown in Figure 7,
consisting of a dc restore circuit, CDS, and output buffer.
DC Restore
To reduce the large dc offset of the CCD output signal, a
dc restore circuit is used with an external 0.1 μF series
coupling capacitor. This restores the dc level of the CCD
signal to approximately 1.5 V to be compatible with the 3 V
analog supply of the AD9940.
To operate the AD9940, all CCD and AFE timing parameters
are programmed into the AD9940 from the system micro-
processor through the 3-wire serial interface. From the system
master clock, CLI, provided by the image processor or external
crystal, the AD9940 generates the CCD’s horizontal and reset
gate clocks and all internal AFE clocks.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract
the video information and reject low frequency noise. The
timing diagram in Figure 10 illustrates how the two internally
generated CDS clocks, SHP and SHD, are used to sample the
reference level and the data level, respectively, of the CCD
signal. The placement of the SHP and SHD sampling edges
is determined by the setting of the SHPLOC (Address 22)
and SHDLOC (Address 23) control registers. Placement of
these two clock edges is critical to achieve the best perform-
ance from the CCD.
The H-drivers for H1 to H4, HL and RG, are included in the
AD9940, allowing these clocks to be directly connected to the
CCD. An H-drive voltage of up to 3.6 V is supported.
DIGITAL
OUTPUTS
AD9941
AD9940
DIGITAL IMAGE
PROCESSING
ASIC
CCD
DIFFN
DIFFP
ADC
BUF
OUT
OUT
V
0.1μF
OUT
CCDIN
SERIAL
INTERFACE
C
IN
REGISTER
DATA
BUFFER
H1–H4, HL, RG
REGISTER
DATA
TIMING
GENERATOR
Figure 6. Typical System Block Diagram
0.1μF
0.1μF
REFT
2V
REFB
1V
DC RESTORE
+
INTERNAL
1.5V
V
REF
AD9940
SHP
CDS
SHD
DIFFN
DIFFP
CCDIN
0.1μF
BUF
SHP
SHD
H1–H4, HL, RG
TIMING
GENERATION
PRECISION
TIMING
GENERATION
SERIAL INTERFACE
Figure 7. AD9940 Signal-Processing Chain
Rev. 0 | Page 13 of 20
AD9940
PRECISION TIMING, HIGH SPEED TIMING GENERATION
The AD9940 generates flexible, high speed timing signals
using the Precision Timing core. This core is the foundation for
generating the timing used for both the CCD and the AFE: the
reset gate RG, horizontal drivers H1 to H4, and the SHP/SHD
sample clocks. A unique architecture makes it routine for the
system designer to optimize image quality by providing precise
control over the horizontal CCD readout and the AFE corre-
lated double sampling.
HIGH SPEED CLOCK PROGRAMMABILITY
Figure 9 shows how the high speed clocks, RG, HL, H1–H4, SHP,
and SHD are generated. The RG pulse has programmable rising
and falling edges, and can be inverted using the polarity control.
The horizontal clocks H1/H3 have programmable rising and
falling edges, and polarity control. The H2/H4 clocks are always
inverses of the H1/H3 H-driver outputs.
Table 8 summarizes the high speed timing registers and their
parameters. Each edge location setting is 6 bits wide, but only
48 valid edge locations are available. Therefore, the register
values are mapped into four quadrants, with each quadrant
containing 12 edge locations. Table 9 shows the correct reg-
ister values for the corresponding edge locations.
TIMING RESOLUTION
The Precision Timing core uses a 1× master clock input (CLI)
as a reference. This clock should be the same as the CCD pixel
clock frequency. Figure 8 illustrates how the internal timing
core divides the master clock period into 48 steps or edge
positions. Therefore, the edge resolution of the Precision
Timing core is (tCLI/48).
POSITION
CLI
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
...
tCLIDLY
...
1 PIXEL
PERIOD
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6 ns TYP).
Figure 8. High Speed Clock Resolution from CLI Master Clock Input
Rev. 0 | Page 14 of 20
AD9940
4
CCD SIGNAL
5
1
2
RG
3
6
H1/H3
H2/H4
HL
7
8
9
11
10
PROGRAMMABLE CLOCK POSITIONS:
1
RG POLARITY.
RG RISING EDGE.
RG FALLING EDGE.
SHP SAMPLE LOCATION.
SHD SAMPLE LOCATION.
H1/H3 POLARITY.
H1/H3 RISING EDGE POSITION.
H1/H3 FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3).
2
3
4
5
6
7
8
9
HL POLARITY.
HL RISING EDGE.
10
11
HL FALLING EDGE.
Figure 9. High Speed Clock Programmable Locations
CCD
SIGNAL
N
N+1
N+2
N+9
N+10
SHPLOC
SHDLOC
tS1
DIFFP
DIFFN
VALID
ADCLK
(FOR AD9941)
tREC
Figure 10. SHP, SHD, and Data Output Timing
Rev. 0 | Page 15 of 20
AD9940
The RG and HL output drive strength registers are divided into
seven 3-bit values, each adjustable in 2.2 mA increments. The
minimum setting of 0 is equal to off or three-state, and the
maximum setting of 7 is 15.4 mA.
H-DRIVER AND RG OUTPUTS
In addition to the programmable timing positions, the AD9940
features on-chip output drivers for the RG and H1 to H4 out-
puts. These drivers are powerful enough to directly drive the
CCD inputs. The H-driver and RG driver current can be
adjusted for optimum rise/fall time into a particular load using
the H1/H3DRV, H2/H4DRV, RGDRV, and HLDRV registers
The horizontal output drive strength register is divided into
fifteen different 4-bit values, each one adjustable in 4.3 mA
increments. The minimum setting of 0 is off or three-state, and
the maximum setting of 15 is 64.5 mA.
As shown in Figure 11, the H2/H4 outputs are inverses of
H1/H3. The internal propagation delay resulting from the
signal inversion is less than l ns, which is significantly less
than the typical rise time driving the CCD load. This results
in an H1/H2 crossover voltage at approximately 50% of the
output swing. The crossover voltage is not programmable.
Table 8. Timing Core Register Parameters for H1, H3, RG1, RG2, and SHP/SHD
Parameter
Length (Bits)
Range
Description
Polarity
1
High/low
Polarity control for H1/H3, RG1, and RG2:
0 = no inversion.
1 = inversion.
Positive Edge
6
6
6
4
3
3
0 to 47 edge location
0 to 47 edge location
0 to 47 sample location
0 to 15 current steps
0 to 7 current steps
0 to 7 current steps
Positive edge location for H1/H3, RG1, and RG2.
Negative edge location for H1/H3, RG1, and RG2.
Sampling location for SHP and SHD.
Drive current for H1 to H4, 0 to 15 steps of 4.3 mA each.
Drive current for RG, 0 to 7 steps of 2.2 mA each.
Drive current for HL, 0 to 7 steps of 2.2 mA each.
Negative Edge
Sample Location
H-Drive Control
RG-Drive Control
HL-Drive Control
H1/H3
tRISE
H2/H4
tPD << tRISE
tPD
H1/H3
H2/H4
FIXED CROSSOVER VOLTAGE
Figure 11. H-Clock Inverse Phase Relationship
Table 9. Precision Timing Edge Locations
Quadrant
Edge Location (Decimal)
Register Value (Decimal)
0 to 11
16 to 27
32 to 43
48 to 59
Register Value (Binary)
00 0000 to 00 1011
01 0000 to 01 1011
10 0000 to 10 1011
11 0000 to 11 1011
I
II
III
IV
0 to 11
12 to 23
24 to 35
36 to 47
Rev. 0 | Page 16 of 20
AD9940
Individual HBLK Sequences
HBLK SEQUENCES
Up to three individual HBLK sequences are available in each
line. This allows special H-blanking as shown in Figure 14. The
HBLK sequences are sequential starting with Sequence 0. To
ensure proper HBLK operation, the following sequence is
required for values programmed in the HBLKTOG registers:
The HBLK programmable timing shown in Figure 12 is
programmed using the HBLKTOG registers. Only the toggle
positions are used to designate the start and the stop posi-
tions of the blanking period. Additionally, a polarity control,
HBLKMASKPOL, designates the polarity of the horizontal
clock signals H1 to H4 during the blanking period. Setting
HBLKMASKPOL high sets H1 = H3 = high and
HBLKTOG1_0 < HBLKTOG2_0 < HBLKTOG1_1 <
HBLKTOG2_1 < HBLKTOG1_2 < HBLKTOG2_2
H2 = H4 = low during the blanking.
CLI
0
1
2
3
4
5
6
7
8
9
tCLIDLY
PIXEL
CLOCK
0
1
2
3
4
5
6
7
3
8
9
HD
1
2
H1/H3
H2/H4
PROGRAMMABLE SETTINGS:
1
HBLKTOG1_n (n = 0, 1, 2)
2
HBLKMASKPOL
3
HBLKTOG2_n (n = 0, 1, 2)
Figure 12. Horizontal Blanking Example Showing HBLKTOG1_0 = 0, HBLKMASKPOL = 0, and HBLKTOG2_0 = 3
HD
HBLK
H1/H3
...
H1/H3
H2/H4
...
NOTE
1. THE POLARITY OF H1 DURING THE BLANKING REGION IS PROGRAMMABLE (H2 HAS THE OPPOSITE POLARITY OF H1).
Figure 13. HBLK Masking Control
Rev. 0 | Page 17 of 20
AD9940
HD
1
2
3
4
5
6
HBLK
H1/H3
H2/H4
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS.
PROGRAMMABLE SETTINGS:
1
HBLKTOG1_0
2
HBLKTOG2_0
3
HBLKTOG1_1
4
HBLKTOG2_1
5
HBLKTOG1_2
6
HBLKTOG2_2
Figure 14. Generating Special HBLK Patterns
Rev. 0 | Page 18 of 20
AD9940
APPLICATIONS INFORMATION
All signals should be carefully routed on the PCB to main-
tain low noise performance. The CCD output signal should be
connected to the CCDIN pin through a 0.1 μF capacitor. The
CCD timing signals H1A/B to H2A/B and RG1 to RG2 should
be routed directly to the CCD with minimum trace lengths. The
clock inputs are located on the other side of the package, where
the analog pins are located, and should be connected to the
digital ASIC away from the analog and CCD clock signals.
All decoupling capacitors should be located as close as possible
to the package pins. Careful use of a split ground plane can be
effective to avoid the return current of horizontal driver flows
into analog ground, thereby reducing coupling noise.
Power-supply decoupling is very important for achieving low
noise performance. Figure 15 shows the local high frequency
decoupling capacitors, but additional capacitance is recom-
mended for lower frequencies. Additional capacitors and
ferrite beads can further reduce noise.
A single ground plane is recommended for the AD9940. This
ground plane should be as continuous as possible, particularly
where analog pins are concentrated, to ensure that all analog
decoupling capacitors provide the lowest possible impedance
path between the power and bypass pins and their respective
ground pins.
When using the LFCSP package, it is recommended that the
exposed paddle on the bottom of the package be soldered
to a large pad, with multiple vias connecting the pad to the
ground plane.
0.1μF
0.1μF
0.1μF
3V ANALOG SUPPY
48 47 46 45 44 43 42 41 40 39 38 37
NC
AVSS
AVDD
DIFFN
DIFFP
OVSS
OVDD
TCVDD
CLI
AVSS
CCDIN
AVSS
SHP
SHD
AVSS
H1
1
2
36
35
34
33
32
31
30
29
28
27
26
25
ANALOG OUTPUT
FROM CCD
PIN 1
0.1μF
3
3V ANALOG SUPPLY
4
DIFFN OUTPUT
DIFFP OUTPUT
5
2
AD9940
TOP VIEW
(Not to Scale)
CCD SAMPLING INPUTS
6
0.1μF
7
3V ANALOG SUPPLY
3V ANALOG SUPPLY
H2
8
0.1μF
0.1μF
HVSS
HVDD
H3
MASTER
9
CLOCK INPUT
4.7μF
0.1μF
TCVSS
DVSS
DVDD
+
10
11
12
3V ANALOG
SUPPLY
4.7μF
H4
+
3V ANALOG SUPPLY
13 14 15 16 17 18 19 20 21 22 23 24
4
HORIZONTAL
CLOCKS TO CCD
3V ANALOG SUPPLY
3
SERIAL
INTERFACE
0.1μF
RST INPUT
HD INPUT
RG
HL
Figure 15. Recommended Circuit Configuration NC pin and supply name consistency
Rev. 0 | Page 19 of 20
AD9940
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.00
BSC SQ
1.60
MAX
37
48
36
1
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
25
12
0.15
0.05
13
24
SEATING
PLANE
0.08 MAX
COPLANARITY
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 16. 48-Lead Low Profile Quad Flat Package [LQFP}
(ST-48)
Dimensions shown in millimeters
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
5.25
5.10 SQ
4.95
TOP
VIEW
6.75
BSC SQ
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 17. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm x 7mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9940BSTZ1
AD9940BSTZRL1
AD9940BCPZ1
AD9940BCPZRL1
Temperature Range
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
Package Description
Package Option
48-lead Low Profile Quad Flat Package [LQFP]
48-lead Low Profile Quad Flat Package [LQFP]
48-lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-lead Lead Frame Chip Scale Package [LFCSP_VQ]
ST-48
ST-48
CP-48-1
CP-48-1
1 Z = Pb-free part.
©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05261–0–7/05(0)
Rev. 0 | Page 20 of 20
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