AD9862BST_技术文档

Mixed-Signal Front-End (MxFE^™) Processor

for Broadband Communications

a

AD9860/AD9862^*

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Mixed-Signal Front-End Processor with Dual Converter

Receive and Dual Converter Transmit Signal Paths

Receive Signal Path Includes:

Two 10-/12-Bit, 64 MSPS Sampling A/D Converters

with Internal or External Independent References,

Input Buffers, Programmable Gain Amplifiers,

Low-Pass Decimation Filters, and a Digital Hilbert Filter

Transmit Signal Path Includes:

VIN+A

VIN–A

PGA

ADC

RxA DATA

[0:11]

1x

BYPASSABLE LOW-PASS

DECIMATION FILTER

HILBERT

FILTER

VIN+B

VIN–B

ADC

RxB DATA

[0:11]

LOGIC LOW

SIGDELT

ꢀ-ꢁ

AD9860/AD9862

Two 12-/14-Bit, 128 MSPS D/A Converters with

Programmable Full-Scale Output Current, Channel

Independent Fine Gain and Offset Control, Digital

Hilbert and Interpolation Filters, and Digitally Tunable

Real or Complex Up-Converters

Delay-Locked Loop Clock Multiplier and Integrated

Timing Generation Circuitry Allow for Single Crystal

or Clock Operation

Programmable Output Clocks, Serial Programmable

Interface, Programmable Sigma-Delta, Three Auxiliary

DAC Outputs and Two Auxiliary ADCs with Dual

Multiplexed Inputs

SPI

SPI REGISTERS

AUX_DAC_A

AUX_DAC_B

AUX_DAC_C

AUX DAC

INTERFACE

Rx PATH

TIMING

CLOCK

DISTRIBUTION

BLOCK

OSC1

OSC2

DLL

1ꢂ, 2ꢂ, 4ꢂ

Tx PATH

TIMING

AUX_ADC_A1

AUX_ADC_A2

AUX ADC

AUX_ADC_B1

AUX_ADC_B2

CLKOUT1

CLKOUT2

AUX ADC

BYPASSABLE BYPASSABLE

DIGITAL DIGITAL

QUADRATURE QUADRATURE

MIXER MIXER

IOUT+A

IOUT–A

PGA

DAC

Tx DATA

[0:13]

HILBERT

FILTER

IOUT+B

IOUT–B

APPLICATIONS

Broadband Wireless Systems

Fixed Wireless, WLAN, MMDS, LMDS

Broadband Wireline Systems

Cable Modems, VDSL, PowerPlug

Digital Communications

BYPASSABLE

FS/4

FS/8

LOW-PASS

INTERPOLATION

FILTER

NCO

Set-Top Boxes, Data Modems

range for both channels. The output data bus can be multi-

plexed to accommodate a variety of interface types.

GENERAL DESCRIPTION

The AD9860/AD9862 transmit path (Tx) consists of two chan-

nels that contain high performance, 12-/14-bit, 128 MSPS

digital-to-analog converters (DAC), programmable gain amplifiers

(TxPGA), interpolation filters, a Hilbert filter, and digital mixers

for complex or real signal frequency modulation. The Tx latch

and demultiplexer circuitry can process real or I/Q data. Interpo-

lation rates of 2ꢀ and 4ꢀ are available to ease requirements on

an external reconstruction filter. For single channel systems, the

digital Hilbert filter can be used with an external quadrature

modulator to create an image rejection architecture. The two

12-/14-bit, high performance DACs produce an output signal

that can be scaled over a 20 dB range by the TxPGA.

The AD9860 and AD9862 (AD9860/AD9862) are versatile

integrated mixed-signal front-ends (MxFE) that are optimized

for broadband communication markets. The AD9860/AD9862

are cost effective, mixed signal solutions for wireless or wireline

standards based or proprietary broadband modem systems where

dynamic performance, power dissipation, cost, and size are all

critical attributes. The AD9860 has 10-bit ADCs and 12-bit DACs;

the AD9862 has 12-bit ADCs and 14-bit DACs.

The AD9860/AD9862 receive path (Rx) consists of two channels

that each include a high performance, 10-/12-bit, 64 MSPS analog-

to-digital converter (ADC), input buffer, Programmable Gain

Amplifier (RxPGA), digital Hilbert filter, and decimation filter. The

Rx can be used to receive real, diversity, or I/Q data at baseband or

low IF. The input buffers provide a constant input impedance for

both channels to ease impedance matching with external com-

ponents (e.g., SAW filter). The RxPGA provides a 20 dB gain

A programmable delay-locked loop (DLL) clock multiplier and

integrated timing circuits enable the use of a single external

reference clock or an external crystal to generate clocking for all

internal blocks and also provides two external clock outputs.

Additional features include a programmable sigma-delta output,

four auxiliary ADC inputs and three auxiliary DAC outputs.

Device programmability is facilitated by a serial port interface

(SPI) combined with a register bank. The AD9860/AD9862 is

available in a space saving 128-lead LQFP.

*Protected by U.S.Patent No. 5,969,657; other patents pending.

MxFE is a trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

(V_A= 3.3 V ꢃ 5%, V_D= 3.3 V ꢃ 10%, f_DAC= 128 MHz, f_ADC= 64 MHz

Normal Timing Mode, 2ꢂ DLL Setting, R_SET= 4 kꢄ, 50 ꢄ DAC Load,

RxPGA = +6 dB Gain, TxPGA = +20 dB Gain.)

AD9860/AD9862–SPECIFICATIONS

Test

AD9860/AD9862

Typ

Tx PARAMETERS

Temp

Level

Min

Max

Unit

12-/14-BIT DAC CHARACTERISTICS

Resolution

Maximum Update Rate

NA

12/14

Bits

MSPS

mA

128

2

Full-Scale Output Current

Full

I

20

Gain Error (Using Internal Reference)

Offset Error

Reference Voltage (REFIO Level)

Negative Differential Nonlinearity (–DNL)

Positive Differential Nonlinearity (+DNL)

Integral Nonlinearity (INL)

25ºC

I

III

–5.5

–1

1.15

+0.5

0.0

1.22

–0.5/–0.5

1/2

±1/±3

5

+5.5

+1

1.28

%FS

V

LSB

pF

Output Capacitance

Phase Noise @ 1 kHz Offset, 6 MHz Tone

Crystal and OSC IN Multiplier Enabled at 4ꢀ

Output Voltage Compliance Range

25ºC

Full

III

II

–115

dBc/Hz

V

–0.5

+1.5

TRANSMIT TxPGA CHARACTERISTICS

Gain Range

Step Size Accuracy

Step Size

25ºC

III

20

±0.1

0.08

dB

Tx DIGITAL FILTER CHARACTERISTICS

Hilbert Filter Pass Band (<0.1 dB Ripple)

2ꢀ/4ꢀ Interpolator Stop Band²

1

Full

II

12.5

38

±38

% f_DATA

DYNAMIC PERFORMANCE (A_OUT= 20 mA FS, f = 1 MHz)

Differential Phase

Differential Gain

25ºC

Full

III

I

<0.1

<1

70.7

66.1

–74.5

Degree

LSB

dB

AD9860 Signal-to-Noise Ratio (SNR)

AD9860 Signal-to-Noise and Distortion Ratio

AD9860 Total Harmonic Distortion (THD)

AD9860 Wideband SFDR (to Nyquist)

1 MHz Analog Out, I_OUT= 2 mA

1 MHz Analog Out, I_OUT= 20 mA

6 MHz Analog Out, I_OUT= 20 mA

AD9860 Narrowband SFDR (1 MHz Window)

1 MHz Analog Out, I_OUT= 2 mA

1 MHz Analog Out, I_OUT= 20 mA

AD9862 Signal-to-Noise Ratio (SNR)

AD9862 Signal-to-Noise and Distortion Ratio

AD9862 Total Harmonic Distortion (THD)

AD9862 Wideband SFDR (to Nyquist)

1 MHz Analog Out, I_OUT= 2 mA

1 MHz Analog Out, I_OUT= 20 mA

6 MHz Analog Out, I_OUT= 20 mA

AD9862 Narrowband SFDR (1 MHz Window)

1 MHz Analog Out, I_OUT= 2 mA

68.2

62.5

–64.0

25ºC

III

I

III

70.6

75

dBc

64.4

25ºC

Full

III

I

70.2

90

72.0

69.8

–75.5

dBc

dB

83

68.9

64.75

–65.0

25ºC

III

I

III

70.6

76.0

dBc

64.9

83

25ºC

III

I

70.2

90

dBc

1 MHz Analog Out, I_OUT= 20 mA

Rx PARAMETERS

RECEIVE BUFFER

Input Resistance (Differential)

Input Capacitance (Each Input)

Maximum Input Bandwidth (–3 dB)

Analog Input Range (Best Noise Performance)

Analog Input Range (Best THD Performance)

Full

III

II

200

5

140

2

1

W

pF

MHz

V p-p Diff

II

RECEIVE PGA CHARACTERISTICS

Gain Error

Gain Range

Step Size Accuracy

Step Size

25ºC

I

±0.3

20

±0.2

1

dB

19

64

21

Input Bandwidth (–3 dB, Rx Buffer Bypassed)

III

250

MHz

10-/12-BIT ADC CHARACTERISTICS

Resolution

Maximum Conversion Rate

NA

Full

NA

I

10/12

Bits

MHz

–2–

REV. 0

AD9860/AD9862

Test

Level

AD9860/AD9862

Typ

Rx PARAMETERS (continued)

Temp

Min

Max

Unit

DC ACCURACY

Differential Nonlinearity

Integral Nonlinearity

Offset Error

Gain Error

Aperture Delay

Aperture Uncertainty (Jitter)

Input Referred Noise

Reference Voltage Error

REFT-REFB Error (1 V)

25ºC

III

±0.3/±0.4

±1.2/±5

±0.1

LSB

%FSR

ns

ps rms

µV

±0.2

2.0

1.2

250

25ºC

I

±1

±4

mV

AD9860 DYNAMIC PERFORMANCE (A_IN= –0.5 dBFS, f = 5 MHz)

Signal-to-Noise Ratio

25∞C

I

59.0

56.0

60.66

58.0

–76.5

81.0

dBc

Signal-to-Noise and Distortion Ratio

Total Harmonic Distortion

Spurious Free Dynamic Range

25∞C

–70.5

70.3

AD9862 DYNAMIC PERFORMANCE (A_IN= –0.5 dBFS, f = 5 MHz)

Signal-to-Noise Ratio

25∞C

I

62.6

62.5

64.2

dBc

Signal-to-Noise and Distortion Ratio

Total Harmonic Distortion

Spurious Free Dynamic Range

64.14

–79.22

85.13

–73.2

77.09

CHANNEL-TO-CHANNEL ISOLATION

Tx-to-Rx (A_OUT= 0 dBFS, f_OUT= 7 MHz)

Rx Channel Crosstalk (f₁= 6 MHz, f₂= 9 MHz)

25ºC

III

>90

>80

dB

PARAMETERS

CMOS LOGIC INPUTS

Logic “1” Voltage, V_IH

Logic “0” Voltage, V_IL

Logic “1” Current

Logic “0” Current

Input Capacitance

25ºC

II

DRVDD – 0.7

DRVDD – 0.6

V

µA

pF

0.4

12

III

3

CMOS LOGIC OUTPUTS (1 mA Load)

Logic “1” Voltage, V_OH

Logic “0” Voltage, V_OL

25ºC

II

V

0.4

POWER SUPPLY

Analog Supply Currents

Tx (Both Channels, 20 mA FS Output)

Tx Powered Down

Rx (Both Channels, Input Buffer Enabled)

Rx (Both Channels, Input Buffer Disabled)

Rx (32 MSPS, Low Power Mode, Buffer Disabled)

Rx (16 MSPS, Low Power Mode, Buffer Disabled)

Rx Path Powered Down

25ºC

I

III

I

70

76

5.0

307

mA

2.5

275

245

155

80

5.0

12

6.0

DLL

III

Digital Supply Current

AD9860 Both Rx and Tx Path (All Channels Enabled)

2ꢀ Interpolation, f_DAC= f_ADC= 64 MSPS

AD9862 Both Rx and Tx Path (All Channels Enabled)

2ꢀ Interpolation, f_DAC= f_ADC= 64 MSPS

Tx Path (f_DAC= 128 MSPS)

25ºC

I

92

112

124

mA

104

Processing Blocks Disabled

4ꢀ Interpolation

4ꢀ Interpolation, Coarse Modulation

4ꢀ Interpolation, Fine Modulation

4ꢀ Interpolation, Coarse and Fine Modulation

25ºC

III

45

90

110

130

mA

REV. 0

–3–

AD9860/AD9862

Test

Level

AD9860/AD9862

Typ

PARAMETERS (continued)

Temp

Min

Max

Unit

POWER SUPPLY (continued)

Rx Path (f_ADC= 64 MSPS)

Processing Blocks Disabled

Decimation Filter Enabled

Hilbert Filter Enabled

25ºC

III

9

mA

15

16

18.5

Hilbert and Decimation Filter Enabled

NOTES

¹% f_DATArefers to the input data rate of the digital block.

²Interpolation filter stop band is defined by image suppression of 50 dB or greater.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

Test

AD9860/AD9862

(20 pF Load)

Temp

Level

Min

Typ

Max

Unit

Minimum Reset Pulsewidth Low (t_RL

Digital Output Rise/Fall Time

DLL Output Clock

)

NA

III

5

2.8

32

Clock Cycles

ns

MHz

%

25ºC

4

128

DLL Output Duty Cycle

50

Tx–/Rx–Interface (See Figures 11 and 12)

TxSYNC/TxIQ Setup Time (t_Tx1, t_Tx3

TxSYNC/TxIQ Hold Time (t_Tx2, t_Tx4

RxSYNC/RxIQ/IF to Valid Time(t_Rx1, t_Rx3

)

25ºC

III

3

ns

)

5.2

16

1

RxSYNC/RxIQ/IF Hold Time (t_Rx2, t_Rx4

)

0.2

Serial Control Bus (See Figures 1 and 2)

Maximum SCLK Frequency (f_SCLK

)

Full

III

MHz

ns

ms

ns

Minimum Clock Pulsewidth High (t_HI

)

30

Minimum Clock Pulsewidth Low (t_LOW

Maximum Clock Rise/Fall Time

)

Minimum Data/SEN Setup Time (t_S)

Minimum SEN/Data Hold Time (t_H)

25

0

25

0

Minimum Data/SCLK Setup Time (t_DS

Minimum Data Hold Time (t_DH

Output Data Valid/SCLK Time (t_DV

)

30

AUXILARY ADC

Conversion Rate

Input Range

Resolution

25ºC

III

1.25

3

10

MHz

V

Bits

AUXILARY DAC

Settling Time

Output Range

Resolution

25ºC

III

8

3

8

ms

V

Bits

ADC TIMING

Latency (All Digital Processing Blocks Disabled)

25ºC

III

7

Cycles

DAC Timing

Latency (All Digital Processing Blocks Disabled)

Latency (2ꢀ Interpolation Enabled)

Latency (4ꢀ Interpolation Enabled)

Additional Latency (Hilbert Filter Enabled)

Additional Latency (Coarse Modulation Enabled)

Additional Latency (Fine Modulation Enabled)

Output Settling Time (TST) (to 0.1%)

25ºC

III

3

Cycles

ns

30

72

36

5

8

35

Specifications subject to change without notice.

–4–

REV. 0

AD9860/AD9862

EXPLANATION OF TEST LEVELS

ABSOLUTE MAXIMUM RATINGS¹

Power Supply (V_AS, V_DS) . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA

Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DRVDD + 0.3 V

Analog Inputs . . . . . . . . . . . . . . –0.3 V to AVDD (IQ) + 0.3 V

Operating Temperature². . . . . . . . . . . . . . . . . –40ꢅC to +70ꢅC

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150ꢅC

Storage Temperature . . . . . . . . . . . . . . . . . . . –65ꢅC to +150ꢅC

Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300ꢅC

I.

Devices are 100% production tested at 25ºC and guaranteed

by design and characterization testing for the extended

industrial temperature range (–40ºC to +70ºC).

II. Parameter is guaranteed by design and/or characterization

testing.

III. Parameter is a typical value only.

NA. Test level definition is not applicable.

NOTES

¹Absolute maximum ratings are limiting values, to be applied individually, and

beyond which the serviceability of the circuit may be impaired. Functional operability

under any of these conditions is not necessarily implied. Exposure to absolute

maximum rating conditions for extended periods of time may affect device

reliability.

THERMAL CHARACTERISTICS

Thermal Resistance

128-Lead LQFP ꢁ_JA= 29ºC/W

²The AD9860/AD9862 have been characterized to operate over the industrial

temperature range (–40ꢅC to +85ꢅC) when operated in Half Duplex Mode.

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD9860BST

AD9862BST

AD9860PCB

AD9862PCB

–40∞C to +70∞C*

128-Lead Low Profile Plastic Quad Flatpack (LQFP)

Evaluation Board with AD9860

ST-128B

Evaluation Board with AD9862

*The AD9860/AD9862 have been characterized to operate over the industrial temperature range (–40ꢅC to +85ꢅC) when operated in Half Duplex Mode.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

AD9860/AD9862 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

REV. 0

–5–

AD9860/AD9862

PIN CONFIGURATION

REFB_B

REFT_B

AGND

AUX_ADC_A1

102

101

100

99

98

97

96

1

2

PIN 1

IDENTIFIER

AGND

3

AVDD

4

AVDD

5

SIGDELT

AUX_DAC_A

6

AUX_SPI_csb

AUX_SPI_clk

AUX_SPI_do

DGND

7

AUX_DAC_B

8

95

94

93

92

91

AUX_DAC_C

AGND

9

DVDD

10

DLL_Lock

RxSYNC

D9/D11B (MSB)

D8/D10B

D7/D9B

AGND 11

12

13

NC

90

89

88

87

86

AVDD

OSC1 14

15

D6/D8B

OSC2

AGND 16

D5/D7B

D4/D6B

17

18

19

20

CLKSEL

AD9860/AD9862

85 D3/D5B

D2/D4B

AVDD

AGND

TOP VIEW

(Not to Scale)

84

83 D1/D3B

AVDD

82

81

80

79

78

77

76

D0/D2B

REFIO 21

22

NC/D1B

FSADJ

NC/D0B

23

24

25

26

27

28

29

30

AVDD

AGND

D9/D11A (MSB)

D8/D10A

D7/D9A

IOUT–A

IOUT+A

D6/D8A

AGND

75 D5/D7A

74 D4/D6A

73 D3/D5A

72 D2/D4A

71 D1/D3A

70 D0/D2A

AGND

IOUT+B

IOUT–B

AGND 31

32

AVDD

DVDD 33

DGND 34

69

NC/D1A

DGND

35

68 NC/D0A

67 DGND

66 DVDD

DVDD 36

37

Tx11/13 (MSB)

Tx10/12 38

65

CLKOUT1

NC = NO CONNECT

–6–

REV. 0

AD9860/AD9862

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

Receive Pins

Pin No.

Mnemonic

Function

Clock Pins

68/70–79 D0A to

D9A/D11A Receive Channel A

80/82–91 D0B to 10-/12-Bit ADC Output of

D9B/D11B Receive Channel B

10-/12-Bit ADC Output of

10

11, 16

12

13

14

DLL_Lock

AGND

NC

AVDD

OSC1

DLL Lock Indicator Pin

DLL Analog Ground Pins

No Connect

DLL Analog Supply Pin

Single Ended Input Clock

(or Crystal Oscillator Input)

92

RxSYNC

Synchronization Clock for

Channel A and Channel B Rx Paths

98, 99,

AVDD

Analog Supply Pins

15

17

64

OSC2

CLKSEL

CLKOUT2

Crystal Oscillator Input

Controls CLKOUT1 Rate

104, 105,

117, 118,

123, 124,

Clock Output Generated from Input

Clock (DLL Multiplier Setting

and CLKOUT2 Divide Factor)

Clock Output Generated from

Input Clock (1ꢀ if CLKSEL = 1

or /2 if CLKSEL = 0)

100, 103, AGND

106, 109,

Analog Ground Pins

65

CLKOUT1

110, 112,

113, 116,

119, 122,

101

REFT_B

REFB_B

Top Reference Decoupling for

Channel B ADC

Bottom Reference Decoupling

for Channel B ADC

Various Pins

1

AUX_ADC_A1 Auxiliary ADC A Input 1

AVDD

AGND

SIGDELT

102

3, 4, 13

2, 9

5

Analog Power Pins

Analog Ground Pins

Digital Output from

107

108

111

114

115

120

VIN+B

VIN–B

VREF

VIN–A

VIN+A

REFB_A

Receive Channel B Differential (+) Input

Receive Channel B Differential (

Internal ADC Voltage Reference

Receive Channel A Differential ( ) Input

ꢆ) Input

Programmable Sigma-Delta

6

7

8

AUX_DAC_A

AUX_DAC_B

AUX_DAC_C

Auxiliary DAC A Output

Auxiliary DAC B Output

Auxiliary DAC C Output

Digital Power Supply Pin

ꢆ

Receive Channel A Differential (+) Input

Bottom Reference Decoupling for

Channel A ADC

Top Reference Decoupling for

Channel A ADC

33, 36, 53, DVDD

59, 61, 66,

93

34, 35, 52, DGND

58, 60, 67,

94

121

REFT_A

Digital Ground Pin

Transmit Pins

18, 20

23, 32

19, 24,

AVDD

Analog Supply Pins

54

55

56

57

63

95

SCLK

SDO

SDIO

SEN

RESETB

AUX_SPI_do

Serial Bus Clock Input

Serial Bus Data Bit

Serial Bus Enable

Reset (SPI Registers and Logic)

AGND

Analog Ground Pins

27, 28, 31

21

22

25

REFIO

FSADJ

IOUT–A

Reference Output, 1.2 V Nominal

Full-Scale Current Adjust

Transmit Channel A DAC

Optional Auxiliary ADC Serial Bus

Data Out Bit

Differential (ꢆ) Output

96

97

AUX_SPI_clk

AUX_SPI_csb

Optional Auxiliary ADC Serial Bus

Data Out Latch Clock

Optional Auxiliary ADC Serial Bus

Chip Select Bit

26

29

30

IOUT+A

IOUT+B

IOUT–B

Transmit Channel A DAC

Differential (+) Output

Transmit Channel B DAC

Differential (+) Output

128

126

125

127

AUX_ADC_A2 Auxiliary ADC A Input 2

AUX_ADC_B1 Auxiliary ADC B Input 1

AUX_ADC_B2 Auxiliary ADC B Input 2

AUX_ADC_REF Auxiliary ADC Reference

Transmit Channel B DAC

Differential (ꢆ) Output

37–48/50 Tx11/Tx13 12-/14-Bit Transmit DAC Data

to Tx0

TxSYNC

MODE/

(Interleaved Data when Required)

Synchronization Input for Transmitter

Configures Default Timing Mode,

51

62

TxBLANK* Controls Tx Digital Power Down

*The logic level of the Mode/TxBLANK pin at power up defines the default timing

mode; a logic low configures Normal Operation, logic high configures Alternate

Operation Mode.

REV. 0

–7–

AD9860/AD9862

DEFINITIONS OF SPECIFICATIONS

Aperture Delay

Differential Nonlinearity Error (DNL, No Missing Codes)

An ideal converter exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Guaranteed no

missing codes to 10-bit resolution indicate that all 1024 codes

respectively, must be present over all operating ranges.

The aperture delay is a measure of the Sample-and-Hold Ampli-

fier (SHA) performance and specifies the time delay between the

rising edge of the sampling clock input to when the input signal

is held for conversion.

Aperture Uncertainty (Jitter)

Integral Nonlinearity Error (INL)

Aperture jitter is the variation in aperture delay for successive

samples and is manifested as noise on the input to the ADC.

Linearity error refers to the deviation of each individual code from

a line drawn from “negative full scale” through “positive full

scale.” The point used as “negative full scale” occurs 1/2 LSB

before the first code transition. “Positive full scale” is defined as

a level 1 1/2 LSB beyond the last code transition. The deviation

is measured from the middle of each particular code to the true

straight line.

Input Referred Noise

The rms output noise is measured using histogram techniques.

The ADC output code’s standard deviation is calculated in LSB

and converted to an equivalent voltage. This results in a noise

figure that can be referred directly to the input of the AD9860/

AD9862.

Phase Noise

Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio

S/N+D is the ratio of the rms value of the measured input signal

to the rms sum of all other spectral components below the Nyquist

frequency, including harmonics but excluding dc. The value for

S/N+D is expressed in decibels.

Single-sideband phase noise power is specified relative to the

carrier (dBc/Hz) at a given frequency offset (1 kHz) from the

carrier. Phase noise can be measured directly in Single Tone Trans-

mit Mode with a spectrum analyzer that supports noise marker

measurements. It detects the relative power between the carrier

and the offset (1 kHz) sideband noise and takes the resolution

bandwidth (rbw) into account by subtracting 10 log(rbw). It also

adds a correction factor that compensates for the implementation

of the resolution bandwidth, log display, and detector characteristic.

Effective Number of Bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the number

of bits. Using the following formula:

SINAD –1.76 dB

(

)

N =

Output Compliance Range

6.02

The range of allowable voltage at the output of a current-output

DAC. Operation beyond the maximum compliance limits may

cause either output stage saturation or breakdown, resulting in

nonlinear performance.

it is possible to get a measure of performance expressed as N,

the effective number of bits. Thus, effective number of bits for

a device for sine wave inputs at a given input frequency can be

calculated directly from its measured SINAD.

Spurious-Free Dynamic Range (SFDR)

Signal-to-Noise Ratio (SNR)

The difference, in dB, between the rms amplitude of the DAC’s

output signal (or ADC’s input signal) and the peak spurious

signal over the specified bandwidth (Nyquist bandwidth unless

otherwise noted).

SNR is the ratio of the rms value of the measured input signal to

the rms sum of all other spectral components below the Nyquist

frequency, excluding harmonics and dc. The value for SNR is

expressed in decibels.

Pipeline Delay (Latency)

The number of clock cycles between conversion initiation and

the associated output data being made available.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic

components to the rms value of the measured input signal and

is expressed as a percentage or in decibels.

Offset Error

First transition should occur for an analog value 1/2 LSB above

–full scale. Offset error is defined as the deviation of the actual

transition from that point.

Power Supply Rejection

Power supply rejection specifies the converter’s maximum full-scale

change when the supplies are varied from nominal to minimum

and maximum specified voltages.

Gain Error

The first code transition should occur at an analog value 1/2 LSB

above –full scale. The last transition should occur for an analog

value 1 1/2 LSB below the nominal full scale. Gain error is the

deviation of the actual difference between first and last code

transitions and the ideal difference between first and last code

transitions.

Channel-to-Channel Isolation (Crosstalk)

In an ideal multichannel system, the signal in one channel will

not influence the signal level of another channel. The channel-

to-channel isolation specification is a measure of the change that

occurs to a grounded channel as a full-scale signal is applied to

another channel.

–8–

REV. 0

Typical Performance Characteristics–AD9860/AD9862

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

f_DATA= 32MSPS

4ꢂ INTERPOLATION

0

20 40

60

80 100 110 120 140

FREQUENCY – MHz

0

20 40

80 100 110 120 140

FREQUENCY – MHz

60

0

20 40

60

80 100 110 120 140

FREQUENCY – MHz

TPC 1. AD9862 Tx Output 6 MHz

Single Tone; CLKIN = 32 MHz;

DLL 4ꢀ Setting

TPC 2. AD9862 Tx Output 6 MHz

Single Tone; CLKIN = 64 MHz;

DLL 2ꢀ Setting

TPC 3. AD9862 Tx Output 6 MHz

Single Tone; CLKIN = 128 MHz;

DLL 1ꢀ Setting

0

f_DATA= 32MSPS

4ꢂ INTERPOLATION

1ꢂ INTERPOLATION

–20

–40

–60

–80

–60

–80

–100

–120

–100

–120

7.90 7.92 7.94 7.96 7.98 8.00 8.02 8.04 8.06 8.08

0

20 40 60

80 100 110 120 140

0

20 40 60

80 100 110 120 140

FREQUENCY – MHz

TPC 6. Zoomed in Plot of Four

Notched Carriers of OFDM Signal;

CLKIN = 64 MHz, DLL 2ꢀ Setting

TPC 4. TxDAC Generating an

OFDM Signal; CLKIN = 64 MHz,

DLL 2ꢀ Setting

TPC 5. TxDAC Generating an

OFDM Signal; CLKIN = 64 MHz,

DLL 2ꢀ Setting

74

–60

–50

f_DATA= 64MSPS

2ꢂ INTERPOLATION

THD

2nd

3rd

f_DATA= 64MSPS

2ꢂ INTERPOLATION

f_DATA= 64MSPS

2ꢂ INTERPOLATION

–55

73

–65

–70

–75

–80

–85

–90

–60

–65

–70

–75

–80

AD9862

72

71

70

–85

AD9860

AVDD = 3.0V

AVDD = 3.3V

AVDD = 3.6V

69

–90

–95

68

0

5

10

15

20

25

30

5

15

20

25

30

35

5

10

15

20

25

30

10

FREQUENCY – MHz

CARRIER FREQUENCY – MHz

f_OUT– MHz

TPC 8. Signal-to-Noise Ratio (SNR)

vs. f_OUT

TPC 9. Two Tone Intermodulation

vs. f_OUT1(f_OUT2= f_OUT1+ 1 MHz)

TPC 7. TxDAC Harmonic

Distortion vs. f_OUT

REV. 0

–9–

AD9860/AD9862

0

–20

–40

–60

–80

0

–20

–40

–60

–80

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

5

10

15

20

25

30

0

5

10

15

20

25

30

0

5

10

15

20

25

30

FFT OUTPUT – MHz

TPC 10. ADC Dual Tone FFT with

Buffer Tones at 4.5 MHz and 5.5 MHz

TPC 11. ADC Dual Tone FFT without

Buffer Tones at 4.5 MHz and 5.5 MHz

TPC 12. ADC Dual Tone FFT

(undersampling) without Buffer

Tones at 69.5 MHz and 70.5 MHz

70

68

66

64

62

60

58

56

54

11.0

10.5

LOW POWER MODE 1, BUFFER BYPASSED,

2V p-p INPUT, 1ꢂ RxPGA GAIN

LOW POWER MODE 2, BUFFER BYPASSED,

2V p-p INPUT, 1ꢂ RxPGA GAIN

68

66

64

62

60

68

66

64

62

60

BUFFERED BYPASS

2V INPUT, 1ꢂ GAIN

BUFFER BYPASSED, 2V p-p,

1ꢂ RxPGA GAIN

BUFFER BYPASSED, 2V p-p,

1ꢂ RxPGA GAIN

LOW POWER MODE 1, BUFFER

ENABLED, 1V p-p INPUT,

2ꢂ RxPGA GAIN

LOW POWER MODE 2, BUFFER

ENABLED, 1V p-p INPUT,

2ꢂ RxPGA GAIN

10.0

9.5

9.0

8.5

8.0

BUFFERED BYPASS

1V INPUT, 2ꢂ GAIN

58

56

54

58

56

54

BUFFERED

2V INPUT,

1ꢂ GAIN

BUFFER ENABLED,

1V p-p INPUT,

2ꢂ RxPGA GAIN

BUFFER ENABLED,

1V p-p INPUT,

2ꢂ RxPGA GAIN

52

50

52

50

52

50

BUFFERED 1V

INPUT, 2ꢂ GAIN

0

50

100

150

200

250

300

0

50

100

150

200

250

300

0

50

100

150

200

250 300

f_IN– MHz

TPC 14. AD9862 Rx SINAD

vs. f_INat 32 MSPS

TPC 15. AD9862 Rx SINAD

vs. f_INat 16 MSPS

TPC 13. AD9862 Rx SINAD

vs. f_INat 64 MSPS

10.0

9.5

62

60

58

56

54

52

50

48

46

44

62

60

62

60

LOW POWER MODE 1, BUFFER BYPASSED,

2V p-p INPUT, 1ꢂ RxPGA GAIN

LOW POWER MODE 2, BUFFER BYPASSED,

2V p-p INPUT, 1ꢂ RxPGA GAIN

BUFFERED BYPASS

1V INPUT, 2ꢂ GAIN

BUFFER BYPASSED, 2V p-p,

1ꢂ RxPGA GAIN

BUFFER BYPASSED, 2V p-p,

1ꢂ RxPGA GAIN

58

56

54

52

50

48

58

56

54

52

50

48

9.0

8.5

8.0

7.5

7.0

BUFFERED 1V

INPUT, 2ꢂ GAIN

BUFFERED 2V

INPUT, 1ꢂ GAIN

BUFFERED BYPASS

2V INPUT, 1ꢂ GAIN

LOW POWER

MODE 1,

BUFFER ENABLED,

1V p-p INPUT,

2ꢂ RxPGA GAIN

LOW POWER

MODE 2,

BUFFER ENABLED,

1V p-p INPUT,

2ꢂ RxPGA GAIN

BUFFER ENABLED,

1V p-p INPUT,

2ꢂ RxPGA GAIN

BUFFER ENABLED,

1V p-p INPUT,

2ꢂ RxPGA GAIN

46

44

46

44

0

50

100

150

200

250

300

0

50

100

150

200

250

300

0

50

100

150

200

250 300

f_IN– MHz

TPC 17. AD9860 Rx SINAD

vs. f_INat 32 MSPS

TPC 18. AD9860 Rx SINAD

vs. f_INat 16 MSPS

TPC 16. AD9860 Rx SINAD

vs. f_INat 64 MSPS

–10–

REV. 0

AD9860/AD9862

–50

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

–50

–55

–50

–55

AD9860 LOW POWER

MODE 1, BUFFER

ENABLED,

1V p-p INPUT,

2ꢂ RxPGA GAIN

AD9862 LOW POWER

MODE 1, BUFFER

AD9860 LOW POWER

MODE 2, BUFFER

ENABLED,

1V p-p INPUT,

2ꢂ RxPGA GAIN

AD9862

LOW POWER

MODE 2,

BUFFER

ENABLED

BUFFERED BYPASS

2V INPUT, 1ꢂ GAIN

ENABLED

,

1V p-p INPUT,

2ꢂ RxPGA GAIN

BUFFERED 2V

INPUT, 1ꢂ GAIN

–60

–65

–70

–75

–80

–60

–65

–70

–75

–80

,

1V p-p INPUT,

2ꢂ RxPGA GAIN

AD9860 LOW POWER MODE 1,

BUFFER BYPASSED, 2V p-p INPUT,

1ꢂ RxPGA GAIN

AD9860 LOW POWER MODE 2,

BUFFER BYPASSED, 2Vp-p INPUT,

1ꢂ RxPGA GAIN

BUFFERED 1V

INPUT, 2ꢂ GAIN

BUFFERED BYPASS

1V INPUT, 2ꢂ GAIN

AD9862 LOW POWER MODE 1,

BUFFER BYPASSED, 2V p-p INPUT,

AD9862 LOW POWER MODE 2,

BUFFER BYPASSED, 2V p-p INPUT,

1ꢂ RxPGA GAIN

–85

–90

–85

–90

1ꢂ RxPGA GAIN

0

50

100

150

200

250

300

0

50

100

150

IN

200

250

300

0

10

100

1000

f

– MHz

f

– MHz

INPUT FREQUENCY – MHz

IN

TPC 19. Rx THD vs. f_IN,

_ADC= 64 MSPS

TPC 20. Rx THD vs. f_IN,

F_ADC= 32 MSPS

TPC 21. Rx THD vs. f_IN,

F_ADC= 16 MSPS

F

–50

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

–50

–55

–50

–55

AD9862 LOW POWER MODE 1,

BUFFER ENABLED, 1V p-p

INPUT, 2ꢂ RxPGA GAIN

AD9860 LOW POWER MODE 2,

BUFFER BYPASSED, 1V p-p

INPUT, 2ꢂ RxPGA GAIN

AD9860

LOW POWER

MODE 1,

AD9860

–60

–65

–70

–75

–80

–85

–60

–65

–70

–75

–80

–85

BUFFER BYPASSED,

2V p-p INPUT,

LOW POWER MODE 1,

BUFFER ENABLED,

1V p-p INPUT,

LOW POWER MODE 2,

BUFFER ENABLED,

1V p-p INPUT,

BUFFERED BYPASS

1V INPUT, 2ꢂ GAIN

1ꢂ RxPGA GAIN

2ꢂ RxPGA GAIN

BUFFERED BYPASS

2V INPUT, 1ꢂ GAIN

AD9862 LOW POWER

MODE 2, BUFFER BYPASSED,

2V p-p INPUT, 1ꢂ RxPGA GAIN

BUFFERED 1V

AD9862 LOW POWER MODE 1,

BUFFER BYPASSED, 2V p-p INPUT,

1ꢂ RxPGA GAIN

AD9862 LOW POWER MODE 2,

BUFFER ENABLED, 1V p-p INPUT,

2ꢂ RxPGA GAIN

–90

–95

–90

–95

INPUT, 2ꢂ GAIN

BUFFERED 2V

INPUT, 1ꢂ GAIN

0

50

100

150

200

250

300

0

50

100

150

200

250 300

0

10

100

1000

f_IN– MHz

INPUT FREQUENCY – MHz

TPC 22. Rx SFDR @ 64 MSPS

TPC 23. Rx SFDR @ 32 MSPS

TPC 24. Rx SFDR @ 16 MSPS

1

0

280

800

270

260

250

240

230

220

210

200

NOMINAL

700

600

500

400

300

200

–1

32MSPS LP MODE

–2

–3

–4

–5

–6

16MSPS LP MODE

NO BUFF 2V ꢂ1

BUFF 1V ꢂ2

BUFF 2V ꢂ1

100

0

190

180

1

10

100

1000

0

20

40

f_IN– MHz

60

80

100

0

10

20

30

40

50

60

70

INPUT FREQUENCY – MHz

f_ADC– MSPS

TPC 25. Rx Input Attenuation

TPC 26. Rx Input Buffer

Impedance vs. f_IN

TPC 27. Rx Analog Power

Consumption

REV. 0

–11–

AD9860/AD9862

REGISTER MAP (0x00–0x3F)¹

Register Name Address²Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Purpose

SPI Setup

General

Rx Power Down

Rx A

0

1

2

3

4

5

SDIO BiDir

V_REF(diff)

LSB First

V_REF

Soft Reset

Rx Digital

Rx Channel B Rx Channel A Buffer B

Buffer A

All Rx

Byp Buffer A

Byp Buffer B

RxPGA A

RxPGA B

Receive

Path

Setup

Rx B

Rx Misc

Rx I/F

HS Duty Cycle Shared Ref

Clk Duty

Three State

Rx Retime

2 Channel

Twos

Complement

Inv RxSync Mux Out

Rx Digital

RSV

6

7

8

Keep –ve

Hilbert Decimate

Reserved for Future Use

Tx Power Down

Alt Timing

Mode

TxOff Enable Tx Digital

Tx Analog Power Down [2:0]

RSV

9

Reserved for Future Use

Tx A Offset

10

DAC A Offset [1:0]

DAC B Offset [1:0]

DAC A Offset

Direction

Tx A Offset

Tx B Offset

11

12

DAC A Offset [9:2]

DAC B Offset

Direction

Transmit

Path

Setup

Tx B Offset

Tx A Gain

Tx B Gain

Tx PGA Gain

Tx Misc

13

14

15

16

17

18

DAC B Offset [9:2]

Tx PGA Gain

DAC A Coarse Gain

DAC B Coarse Gain

DAC A Fine Gain

DAC B Fine Gain

Slave Enable Tx PGA Fast

2 Edges Interleaved

Tx I/F

Tx Retime Q/I Order

Inv TxSync

Twos

Inverse

Complement Sample

Tx Digital

19

20

2 Data Paths Keep –ve

Neg. Fine Tune Fine Mode Real Mix

Hilbert

Interpolation Control

Tx Modulator

Neg. Coarse Tune Coarse Modulation

NCO Tuning

Word

21

22

FTW [7:0]

NCO Tuning

Word

NCO

Setup

FTW [15:8]

NCO Tuning

Word

23

24

FTW [23:16]

DLL Multiplier

DLL

Reserved

Input Control ADC Div 2

Clock

DLL

Power Down

DLL

FAST

Clock

Setup

CLKOUT

25

26

27

28

29

30

31

32

33

CLKOUT2 Divide Factor

Aux ADC A2 Data [1:0]

Inv2

Dis2

Inv1

Dis1

Aux ADC A2

Aux ADC A1

Aux ADC B2

Aux ADC B1

Aux ADC A2 Data [9:2]

Aux ADC A1 Data [9:2]

Aux ADC B2 Data [9:2]

Aux ADC B1 Data [9:2]

Aux ADC A1 Data [1:0]

Aux ADC B2 Data [1:0]

Aux ADC B1 Data [1:0]

Auxiliary

ADC Data

and Setup

Aux ADC Control 34

Aux SPI

SelBnot A

Refsel B

Select B

Start B

Refsel A

Select A

Start A

CLK/4

Aux ADC Clock

Aux DAC A

Aux DAC B

Aux DAC C

Aux DAC

35

36

37

38

39

Aux DAC A

Aux DAC B

Aux DAC C

Auxiliary

DAC Data

and Setup

Slave Enable

Update C

Update B

Update A

Update Aux DAC 40

Power Down C Power Down B Power Down A

DAC Control

41

Inv C

Inv B

Inv A

SigDelt

42

Sigma-Delta Control Word [3:0]

Flag

Sigma-

Delta Data

and Setup

SigDelt

43

Sigma-Delta Control Word [11:4]

ADC Low Power 49, 50

Low Power Register for Rx Path Operation below 32 MSPS

Rx Low

Power

RSV

44–62

Reserved for Future Use

Chip Rev ID

Reserved

Chip ID

63

NOTES

1

When writing to a register with unassigned register bit(s), a logic low must be written to the unassigned bit(s). By default, after power up or RESET, all registers

are set low, except for the bits in the shaded boxes, which are set high.

Decimal

2

–12–

REV. 0

AD9860/AD9862

REGISTER BIT DEFINITIONS

REGISTER 0: GENERAL

high speed applications when clock duty cycle affects noise and

distortion performance the most. This bit should be set high in

conjunction with Clk Dut Enable register bit.

BIT 7: SDIO BiDir (Bidirectional)

BIT 1: Shared Ref

Default setting is low, which indicates SPI serial port uses dedi-

cated input and output lines (i.e., 4-wire interface), SDIO and

SDO Pins, respectively. Setting this bit high configures the

serial port to use the SDIO Pin as a bidirectional data pin.

Setting this bit high forces the dual receive ADCs into a mode

to share their differential references to provide superior gain

matching. When this option is enabled, the REFT of Channel A

and Channel B should be connected together off-chip and the

REFB of both channels should be connected.

BIT 6: LSB First

Default setting is low, which indicates MSB first SPI Port Access

Mode. Setting this bit high configures the SPI port access to

LSB first mode.

BIT 0: Clk Duty

Setting this bit high enables an on-chip duty cycle stabilizer (DCS)

circuit to generate the internal clock for the Rx block. This option

is useful for adjusting for high speed input clocks with skewed

duty cycle. The DCS Mode can be used with ADC sampling

frequencies over 40 MHz.

BIT 5: Soft Reset

Writing a high to this register resets all the registers to their

default values and forces the DLL to relock to the input clock.

The Soft Reset Bit is a one shot register and is cleared immediately

after the register write is completed.

REGISTER 5: Rx I/F (INTERFACE)

BIT 4: Three-state

REGISTER 1: Rx PWRDWN

Setting this bit high will force both Rx data output buses, including

the RxSYNC Pin, into a three-state mode.

BIT 3: Rx Retime

BIT 7: V_REF, diff (Power-Down)

Setting this bit high will power down the ADC’s differential

references (i.e., REFT and REFB).

The Rx path can use either of the clock outputs, CLKOUT1 or

CLKOUT2, to latch the Rx output data. Since CLKOUT1 and

CLKOUT2 have slight phase offsets, this provides some timing

flexibility with the interface. By default, this bit is low and the

Rx output latches use CLKOUT1. Setting this bit will force the

Rx output latches to use CLKOUT2.

BIT 2: Twos Complement

Default data format for the Rx data is straight binary. Setting this

bit high will generate two’s complement data.

BIT 6: V_REF(Power-Down)

Setting this register bit high will power down the ADC reference

circuit (i.e., V_REF).

BIT 5: Rx Digital (Power-Down)

Setting this bit high will power down the digital section of the

receive path of the chip. Typically, any unused digital blocks are

automatically powered down.

BIT 4/3: Rx Channel B/Rx Channel A (Power-Down)

Either ADC or both ADCs can be powered down by setting the

appropriate register bit high. The entire Rx channel is powered

down, including the differential references, input buffer, and the

internal digital block. The bandgap reference remains active for

quick recovery.

BIT 1: Inv RxSync

When the receive data is multiplexed onto one data port (i.e., Mux

Mode Enabled), the RxSYNC Pin can be used to decode which

channel generated the current output data at the active port.

Default condition is that RxSYNC is high when Channel A is at

the output and is low when Channel B is at the output. Setting

this bit high reverses this synchronization.

BIT 2/1: Buffer B/Buffer A (Power-Down)

Setting either of these bits high will power down the input buffer

circuits for the respective channel. The input buffer should be

powered down when bypassed. By default, these bits are low and

the input buffers are enabled.

BIT 0: All Rx (Power-Down)

Setting this bit high powers down all circuits related to the

receive path.

BIT 0: Mux Out

Setting this bit high enables the Rx Mux Mode. Default setting

is low, which is Dual Port Mode, (i.e., non Rx Mux Mode). When in

Rx Mux Mode, both Rx channels share the same output data bus,

pins D0A to D9A (for AD9860) or D0A to D11A (for AD9862).

The other Rx output bus (pins D0B to D9B or D0B to D11B)

outputs a low logic.

REGISTER 2/3: Rx A/Rx B

BIT 7: Bypass Buffer A/Bypass Buffer B

REGISTER 6: Rx Digital

Setting either of these bits high will bypass the respective input buf-

fer circuit. When the buffer is bypassed, the input signal is routed

directly to the switched capacitor SHA input of the RxPGA. When

operating with buffer bypassed, it should be powered down.

BIT 3: 2 Channel

Setting this bit low disables the Rx B output data port (pins D0B

to D9B or D11B), forcing the output pins to zero. By default, the

bit is high and both data paths are active.

BIT 0–4: RxPGA A/RxPGA B

BIT 2: Keep –ve

These 5-bit straight binary registers (Bit 0 is the LSB, Bit 4 is the

MSB) provide control for the programmable gain amplifiers in

the dual receive paths. A 0 dB to 20 dB gain range is accom-

plished through a switched capacitor network with fast settling

of a few clock cycles. The step size is approximately 1 dB. The

register default setting is minimum gain or hex00. The maximum

setting for these registers is hex14.

This bit selects whether the receive Hilbert filter will filter positive

or negative frequencies, assuming the filter is enabled. By default

this bit is low, which passes positive frequencies. Setting this bit

high will configure the filter to pass negative frequencies.

BIT 1: Hilbert

This bit enables or disables the Hilbert filter in the receive path.

By default, this bit is low, which disables the receive Hilbert filter.

Setting this bit high enables the receive Hilbert filter.

BIT 0: Decimate

This register enables or disables the decimation filters. By default,

the register setting is low and the decimation filter is disabled.

REGISTER 4: Rx MISC

BIT 2: HS (High Speed) Duty Cycle

Setting this bit high optimizes duty cycle of the internal ADC

sampling clock. It is recommended that this bit be set high in

REV. 0

–13–

AD9860/AD9862

Setting this bit high enables the decimation filters and decimates

the receive data by two.

DAC A/DAC B Offset Direction

This bit determines to which of the differential output pins for

the selected channel the offset current will be applied. Setting this

bit low will apply the offset to the negative differential pin. Setting

this bit high will apply the offset to the positive differential pin.

REGISTER 8: Tx PWRDWN

BIT 5: Alt Timing Mode

The timing section in the data sheet describes two timing modes,

the “Normal Operation” and the “Alternate Operation” modes.

At power up, the default configuration is established from the

logic level of the Mode/TxBlank pin. If Mode/TxBlank is logic

low, the Normal Operation mode is the default; if the Mode/

TxBlank pin is held at a logic high, the Alternative Operation

mode is configured at power-up (the DLL is forced to multiply

by 4 at power-up by default in this mode). After power up, the

operation mode can be configured so that the Mode/TxBlank pin

can be used for other functions. To allow this, set this bit high.

REGISTER 14/15: DAC GAIN A/B

BIT 6, 7: DAC A/DAC B Coarse Gain Control

These register bits will scale the full-scale output current (I_OUTFS

of either Tx channel independently. I_OUTof the Tx channels is a

function of the R_SETresistor, the TxPGA setting, and the Coarse

Gain Control setting.

)

MSB, LSB

10 or 11

01

Tx Channel Current Scaling

Does not scale output current

Scales output current by 1/2

Scales output current by 1/11

BIT 4: TxOff Enable

00

By default, the Mode/TxBlank pin is not used for any transmit

synchronization. The Mode/TxBlank pin input can be used to

serve two functions, blanking the DAC outputs and slaving the

TxPGA gain control. When this bit is set high, a logic high on the

Mode/TxBlank pin forces the Tx digital block to stop clocking. In

this mode, the Tx outputs will be static, holding their last update

values. To slave the TxPGA gain control to the Mode/TxBlank

pin input, register Slave Enable (Register 17, Bit 1) needs to also

be programmed. See that register for more information.

BIT 5–0: DAC A/DAC B Fine Gain

The DAC output curve can be adjusted fractionally through the

Gain Trim Control. Gain trim of up to ±4% can be achieved on

each channel individually. The Gain Trim register bits are a twos

complement attention control word.

MSB, LSB

100000

111111

000000

000001

011111

Maximum positive gain adjustment

Minimum positive gain adjustment

No adjustment (default)

Minimum negative gain adjustment

Maximum negative gain adjustment

BIT 3: Tx Digital (Power-Down)

By default this bit is low, enabling the transmit path digital to

operate as programmed through other registers. By setting this

bit high, the digital blocks are not clocked to reduce power con-

sumption. When enabled, the Tx outputs will be static, holding

their last update values.

REGISTER 16: TxPGA GAIN

BIT 0–7: TxPGA Gain

This 8 bit, straight binary (Bit 0 is the LSB, Bit 7 is the MSB) reg-

ister controls for the Tx programmable gain amplifier (TxPGA).

The TxPGA provides a 20 dB continuous gain range with 0.1 dB

steps (linear in dB) simultaneously to both Tx channels. By

default, this register setting is hex00.

BIT 0-2: Tx Analog (Power-Down)

Three options are available to reduce analog power consumption

for the Tx channels. The first two options disable the analog output

from Tx channel A or B independently, and the third option

disables the output of both channels and reduces the power

consumption of some of the additional analog support circuitry

for maximum power savings. With all three options, the DAC bias

current is not powered down so recovery times are fast (typically

a few clock cycles). The list below explains the different modes

and settings used to configure them.

MSB, LSB

000000

111111

Minimum gain scaling –20 dB

Maximum gain scaling 0 dB

REGISTER 17: Tx MISC

BIT 1: Slave Enable

The TxPGA Gain is controlled through register TxPGA Gain

setting and by default is updated immediately after the register

write. If this bit is set, the TxPGA Gain update is synchronized

with the rising edge of a signal applied to the Mode/TxBlank

pin. Setting TxOff enable in Register 8 is also required.

Tx Analog

Power-Down

Bits Setting [2:0]

Power-Down Option

Power-Down Tx B Channel Analog Output [1 0 0]

Power-Down Tx A Channel Analog Output [0 1 0]

Power-Down Tx A and Tx B Analog Outputs [1 1 1]

BIT 0: TxPGA Fast (Update Mode)

The TxPGA Fast bit controls the update speed of the TxPGA.

When Fast Update mode is enabled, the TxPGA provides fast gain

settling within a few clock cycles. Default setting for this bit

is low, which indicates Normal Update mode. Fast mode is

enabled when this bit is set high.

REGISTER 10/11/12/13: DAC OFFSET A/B

DAC A/DAC B Offset

These 10-bit, twos complement registers control a dc current

offset that is combined with the Tx A or Tx B output signal. An

offset current of up to ±12% I_OUTFS(2.4 mA for a 20 mA full-

scale output) can be applied to either differential pin on each

channel. The offset current can be used to compensate for offsets

that are present in an external mixer stage, reducing LO leakage

at its output. Default setting is hex00, no offset current. The

offset current magnitude is set using the lower nine bits. Setting

the MSB high will add the offset current to the selected differen-

tial pin, while an MSB low setting will subtract the offset value.

REGISTER 18: Tx IF (INTERFACE)

BIT 6: Tx Retime

The Tx path can use either of the clock outputs, CLKOUT1 or

CLKOUT2, to latch the Tx input data. Since CLKOUT1 and

CLKOUT2 have slight phase offsets, this provides some timing

flexibility with the interface. By default, this bit is high and the

Tx input latches use CLKOUT1. Setting this bit low will force

the Tx latches to use CLKOUT2.

–14–

REV. 0

AD9860/AD9862

BIT 5: Q/I Order

BIT 3: Real Mix Mode

This register indicates the order of received complex transmit

data. By default this bit is low, representing I data preceding

Q data. Alternatively, if this bit is set high, the data format is

defined as Q data preceding I data.

This bit determines if the coarse modulation (controlled by register

Coarse Modulation, will perform a separate real mix on each

channel or a complex mix using the dual channel data. By default,

this bit is set low and a complex mix will be performed. Setting

this bit high will enable the Real Mix mode. Note, the Fine

Modulator Block only performs complex mixing.

BIT 4: Inv TxSync

This register identifies how the first and second data sets are

identified in a complex data set using the TxSYNC bit. By default

this bit is low, and TxSYNC low indicates the first data set is at

the Tx port; TxSYNC high indicates the second data set is at the

Tx port. Setting this bit high inverts the TxSYNC bit. TxSYNC

high indicates the first of the data set, and TxSYNC low indicates

the second of the data set.

BIT 3: Twos Complement

The default data format for Tx data is straight binary. Set this bit

high when providing twos complement Tx data.

BIT 2: Negative Coarse Tune

When this bit is low (default), the coarse modulator provides

positive shifts in frequency. Setting this bit high will shift the coarse

modulator processed data negative in frequency.

BIT 1,0: Coarse Modulation

These bits control what coarse modulation processing will be

performed on the transmit data. A setting of binary 00 (default)

will bypass the modulation block, a setting of binary 01 will shift

the transmit data by f_DAC/4, and a setting of binary 10 will shift

the transmit data by f_DAC/8.

BIT 2: Inverse Sample

By default, the transmit data is sampled on the rising edge of the

CLKOUT. Setting this bit high will change this, and the transmit

data will be sampled on the falling edge.

REGISTER 21/22/23: NCO TUNING WORD

FTW [23:0]

These three registers set the 24-bit frequency tuning word (FTW)

for the NCO in the fine modulator stage of the Tx path. The

NCO full-scale tuning word is straight binary and produces

a frequency equivalent to f_DAC/4 with a resolution of f_DAC/2²⁶.

BIT 1: 2 Edges

If the CLKOUT rate is running at half the interleaved data rate,

both edges of the CLKOUT must latch transmit data. Setting

this bit high allows this clocking configuration.

REGISTER 24: DLL

BIT 0: Interleaved

BIT 6: Input Clock Control

By default, the AD9860/AD9862 powers up in single DAC

operation. If dual transmit data is to be used, the interleaved data

option needs to be enabled by setting this bit high.

This bit defines what type of clock will be driving the AD9860/

AD9862. The default state is low, which allows either crystal con-

nected to OSC1 and OSC2 or single-ended reference clock driving

OSC1 to drive the internal timing circuits. If a crystal will not be

used, the internal oscillator should be disabled after power-up

by setting this bit high.

REGISTER 19: Tx DIGITAL

BIT 4: 2 Data Paths

Setting this bit high enables both transmit digital paths. By default,

this bit is low and the transmit path utilizes only a single channel.

BIT 5: ADC Div2

BIT 3: Keep –ve

By default, the ADC is driven directly by the input clock in Normal

Timing Operation mode or the DLL output in the Alternative

Timing Operation mode. Setting this bit high will clock the ADC

at one half the previous clock rate. This is described further in

the timing section.

This bit configures the Tx Hilbert filter for either positive or nega-

tive frequencies pass band, assuming it is enabled. By default

this bit is low, which selects the positive frequencies. Setting this

bit high will setup the Hilbert filter to pass negative frequencies.

BIT 2: Hilbert

BIT 4,3: DLL Multiplier

This bit enables or disables the Hilbert filter in the transmit path.

By default, this bit is low, which disables the transmit Hilbert

filter. Setting this bit high enables the transmit Hilbert filter.

These bits control the DLL multiplication factor. A setting of

binary 00 will bypass the DLL, a setting of binary 01 will multiply

the input clock by 2, and a setting of binary 10 will multiply the

input clock by 4. Default mode is defined by Mode/TxBlank

logic level at power-up or RESET, which configures either Normal

Operation Timing mode or Alternative Timing mode. In Alter-

native Timing mode, the DLL will lock to 4ꢀ multiplication

factor (the DLL FAST register remains low by default). If the

Mode/TxBlank pin is low, by default the DLL will be bypassed

and a 1ꢀ clock is used internally.

BIT 1,0: Interpolation Control

These register bits control the interpolation rate of the transmit

path. Default settings are both bits low, indicating that both inter-

polation filters are bypassed. The MSB and LSB are address D19,

Bits 1 and 0, respectively. Setting binary 01 provides an interpo-

lation rate of 2ꢀ; binary 10 provides an interpolation rate of 4ꢀ.

REGISTER 20: Tx MODULATOR

BIT 2: DLL Power-Down

BIT 5: Negative Fine Tune

Setting this register bit high forces the CLK IN multiplier to a

power-down state. This mode can be used to conserve power or

to bypass the internal DLL. To operate the AD9860/AD9862

when the DLL is bypassed, an external clock equal to the fastest

on-chip clock is supplied to the OSC pin(s).

When this bit is low (default), the Numerically Controlled Oscil-

lator (NCO) provides positive shifts in frequency, assuming fine

modulation is enabled. Setting this bit high will use a negative

frequency shift in the Fine Complex Modulator.

BIT 4: Fine Mode

BIT 0: DLL FAST

By default, the NCO and fine modulation stage are bypassed. Setting

this bit high will enable the use of the digital complex modulator,

enabling tuning with the NCO.

The DLL can be used to generate output frequencies between

32 MHz to 128 MHz. Because of the large range of locking fre-

quencies allowed, the DLL is separated into two output frequency

ranges, a “slow” range between 32 MHz to 64 MHz and a “fast”

range starting at frequencies above 64 MHz to 128 MHz. By

REV. 0

–15–

AD9860/AD9862

default, this bit is low, setting up the DLL in “slow” mode. This

bit must be set high for DLL output frequencies over 64 MHz.

the Auxiliary ADCs with a clock that is 1/4 of the receive ADC

conversion rate. The conversion rate of the auxiliary ADCs

should be less than 20 MHz.

REGISTER 25: CLKOUT

REGISTER 36, 37, 38: AUX DAC A/B/C

BIT 7, 6: CLKOUT2 Divide Factor

These bits control what rate the CLKOUT2 Pin will operate at

relative to the DLL output rate. The DLL output rate can be

output directly or divided by 2, 4, or 8. Bit 7 is the MSB and

Bit 6 is the LSB.

Auxiliary DAC A, B, and C Output Control Word

Three 8-bit, straight binary words are used to control the output

of three on-chip auxiliary DACs. The auxiliary DAC output

changes take effect immediately after any of the serial write is

completed. The DAC output control words have default values

of 0. The smaller programmed output controlled words corre-

spond to lower DAC output levels.

MSB, LSB

00 (Default)

Relative CLKOUT2 Frequency

Equals DLL output rate

01

10

11

Equals DLL output rate divided by 2

Equals DLL output rate divided by 4

Equals DLL output rate divided by 8

REGISTER 39: AUX DAC UPDATE

BIT 7: Slave Enable

BIT 5, 1: Inv 2/Inv 1

The output clocks from CLKOUT1 and CLKOUT2 can be

inverted by setting the appropriate one of these bits high.

A low setting (default) updates the auxiliary DACs after the respec-

tive register is written to. To synchronize the auxiliary DAC outputs

to each other, a slave mode can be enabled by setting this bit

high and then setting a high to the appropriate update registers.

BIT 4, 0: Dis 2/Dis 1

The output clocks from CLKOUT1 and CLKOUT2 can be

disabled and a logic low output is forced by setting the appro-

priate one of these bits high.

BIT 2/1/0: Update C, B, and A

Setting a high bit to any of these registers initiates an update of the

respective Auxiliary DAC, A, B, or C, when Slave mode is enabled

using the Slave Enable register. The register bit is a one shot

and always reads back a low. Note: be sure to keep the Slave Enable

bit high when using the auxiliary DAC synchronization option.

REGISTER 26–33: AUXILIARY ADC A2/A1/B2/B1

AUX ADC A2, A1, B2, B1 Data

These registers are read only registers that are used for read

back of the 10-bit auxiliary ADC. The 10 bits are broken into a

two registers, one containing the upper eight bits and the other

containing the lower two bits.

REGISTER 40: AUX DAC POWER-DOWN

BIT 2/1/0: Power Down C, B, and A

Setting any of these bits high will power down the appropriate

auxiliary DAC. By default, these bits are low and the auxiliary

DACs are enabled.

REGISTER 34: AUX ADC CONTROL

BIT 7: Aux SPI (Enable)

One of the Auxiliary ADCs can be controlled through an dedi-

cated Auxiliary Serial Port. Setting this bit high enables this mode.

REGISTER 41: AUX DAC CONTROL

BIT 4, 2, 0: Inv C, B, and A

Setting any of these bits high will invert the appropriate Auxiliary

DAC control word setting. By default, these bits are low and the

output control word is decoded as noninverted, straight binary.

BIT 6: Sel BnotA

If the auxiliary Serial port is used, this bit selects which Auxiliary

ADC, A or B, will be using the dedicated Auxiliary Serial port.

The Auxiliary Serial port by default (low setting) controls Auxil-

iary ADC A. Setting this bit high will allow the Auxiliary Serial

Port to control Auxiliary ADC B.

REGISTER 42/43: SIGDELT (SIGMA-DELTA)

Sigma-Delta Output Control Word

A 12-bit straight binary word is used to control the output of an

on-chip sigma-delta converter. The sigma-delta output changes

take effect immediately after any serial write is completed. The

sigma-delta output control words have default values of 0. The

smaller programmed output controlled words correspond to lower

integrated sigma-delta output levels.

BIT 5, 2: Refsel B/A

By default, the auxiliary ADCs use an external reference applied to

the AUX_REF pin. This voltage will act as the full-scale reference

for the selected auxiliary ADC. Either auxiliary ADC can use an

internally generated reference, which is a buffered version of the

analog supply voltage. To enable use of the internal reference for

either of the auxiliary ADCs, the respective Refsel register should

be set high.

REGISTER 49,50 : RX LOW POWER MODE

Setting these bits will scale down the bias current to the ADC

analog block when the device is operated at lower speeds. By

default, these bits are low and the bias is at a nominal setting.

BIT 4, 1: Select B/A

These bits select which of the two inputs will be connected to the

respective auxiliary ADC. By default (setting low), the AUX_ADC_A2

pin is connected to Auxiliary ADC A and AUX_ADC_B2 pin is

connected to Auxiliary ADC B. Setting the respective bit high

will connect the AUX_ADC_A1 pin to Auxiliary ADC A and/or

AUX_ADC_B1 pin to Auxiliary ADC B.

For ADC operation at or below 32 MSPS, Register 49 can be set

to 0x03 and Register 50 can be set to 0xEC; this will reduce Rx

AVDD power consumption by about 30% relative to nominal.

For ADC operation at or below 16 MSPS, Register 49 can be set

to 0x03 and Register 50 can be set to 0x9E; this will reduce Rx

AVDD power consumption by about 60% relative to nominal.

BIT 3, 0: Start B/A

Setting a high bit to either of these registers initiates a conversion

of the respective auxiliary ADC, A or B. The register bit always

reads back a low.

REGISTER 63: CHIP ID

BIT 7–0: Rev ID

This read only register indicates the revision of the AD9860/AD9862.

Reserved Registers

Reserved registers are held for future development and should

never be written to.

REGISTER 35: AUX ADC CLOCK

BIT 0: CLK/4

By default (setting low), the auxiliary ADCs are run at the receive

ADC conversion rate divided by 2. Setting this bit high will run

–16–

REV. 0

AD9860/AD9862

Blank Registers

SDO is a serial output pin used for read back operations in 4-wire mode

and is three-stated when SDIO is configured for bidirectional operation.

Blank registers, i.e., the registers with 0 settings and no indicated

function, are placeholders used throughout the register map for

spacing the AD9860/AD9862 control bits in a logic fashion and,

potentially can be used for future development. A low should

always be written to these registers if a write needs to take place.

Instruction Header

Each SPI read or write consists of an instruction header and

data. The instruction header is made up of an 8-bit word and is

used to set up the register data transfer. The 8-bit word consists

of a read/not write bit, R/nW (the MSB), followed by a double/

not single bit (2/n1) and the 6-bit register address.

SERIAL PORT INTERFACE

The Serial Port Interface (SPI) is used to write to and read from

the AD9860/AD9862 internal programmable registers. The serial

interface uses four pins: SEN, SCLK, SDIO, and SDO by default.

SEN is a serial port enable pin, SCLK is the serial clock pin,

SDIO is a bidirectional data line and SDO is a serial output pin.

Write Operations

The SPI write operation uses the instruction header to configure

a one or two register write using the 2/n1 bit. The instruction

byte followed by the register data, is written serially into the

device through the SDIO pin on rising edges of the interface

clock at SCLK. The data can be transferred MSB first or LSB first

depending on the setting of the LSB First register.

SEN is an active low control gating read and write cycles. When

SEN is high, SDO and SDIO are three-stated.

SCLK is used to synchronize SPI read and writes at a maximum

bit rate of 16 MHz. Input data is registered on the rising edge and

output data transitions on the falling edge. During write opera-

tions, the registers are updated after the 16th rising clock edge

(and 24th rising clock edge for the dual byte case). Incomplete

write operations are ignored.

Figure 1 includes a few examples of writing data into the device.

Figure 1a shows a write using 1 Byte and MSB First mode set;

Figure 1b shows an MSB first, 2 Byte write; and Figure 1c

shows an LSB first, 2 Byte write. Note the differences between

LSB and MSB First modes: instruction header and data are

reversed, and in 2 Byte writes, the first data byte is written to

the address in the header, N and the second data byte is written

to the n–1 address. In LSB First mode, the first data byte is still

written to the address in the instruction header, but the second

data byte is written to the N+1 address.

SDIO is an input only by default. Optionally, a 3-pin interface may

be configured using the SDIO for both input and output opera-

tions and three-stating the SDO pin (see SDIO BiDir register).

t_LO

t_DH

t_CLK

t_S

t_H

t_DS

t_HI

SEN

DON’T CARE

SCLK

DON’T CARE R/nW 2/n1 A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

DON’T CARE

SDIO

INSTRUCTION HEADER

REGISTER DATA

t_DH

t_LO

t_CLK

t_S

t_H

t_DS

t_HI

SEN

DON’T CARE

SCLK

2/n1

DON’T CARE R/nW

A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

DON’T CARE

SDIO

INSTRUCTION HEADER (REGISTER N)

REGISTER (N) DATA

REGISTER (N–1) DATA

t_DH

t_LO

t_CLK

t_S

t_H

t_DS

t_HI

SEN

SCLK

DON’T CARE

A0 A1 A2 A3 A4 A5 2/n1 R/nW D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

SDIO

INSTRUCTION HEADER (REGISTER N)

REGISTER (N) DATA

REGISTER (N+1) DATA

Figure 1. SPI Write Examples a. (top) 1 Byte, MSB First Mode; b. (middle) 2 Byte, MSB First Mode;

c. (bottom) 2 Byte, LSB First Mode

REV. 0

–17–

AD9860/AD9862

t_LO

t_CLK

t_DH

t_S

t_H

t_DV

t_DS

t_HI

SEN

SCLK

SDIO

DON’T CARE

2/n1

A5

A4

A3

A2

A1

A0

DON’T CARE

R/nW

INSTRUCTION HEADER (REGISTER N)

DON’T CARE

D7

D6

D5

D4

D3

D2

D1

D0

SDO

DON’T CARE

OUTPUT REGISTER DATA

t_LO

t_DH

t_CLK

t_S

t_H

t_DV

t_DS

t_HI

SEN

DON’T CARE

SCLK

2/n1

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

R/nW

SDIO

INSTRUCTION HEADER

OUTPUT REGISTER DATA

t_LO

t_DH

t_CLK

t_S

t_H

t_DV

t_DS

t_HI

SEN

DON’T CARE

SCLK

A0

A1

A2

A3

A4

A5

2/n1

R/nW

DON’T CARE

SDIO

SDO

INSTRUCTION HEADER

DON’T CARE

D0

D1

D2

D3

D4

D5

D6

D7

DON’T CARE

OUTPUT REGISTER DATA

Figure 2. SPI Read Examples a. (top) 4-Wire Interface, MSB first; b. (middle) 3-Wire Interface, MSB first;

c. (bottom) 4-Wire Interface, LSB first

Read Operation

features include two auxiliary ADCs, a programmable sigma-delta

output, three auxiliary DACs, integrated clock circuitry to generate

all internal clocks, and buffered output clocks from a single input

reference.

The read back of registers is a single data byte operation. The

readback can be configured to use three pins or four pins and can

be formatted as MSB first or LSB first. The instruction header

is written to the device either MSB or LSB first (depending on

the mode) followed by the 8-bit output data (appropriately MSB

or LSB justified). By default, the output data is sent to the dedicated

output pin (SDO). 3-wire operation can be configured by set-

ting the SDIO BiDir register. In 3-wire mode, the SDIO pin

will become an output pin after receiving the 8-bit instruction

header with a read back request.

The AD9860/AD9862 system functionality is described in the

following four sections: the Transmit Block, Receive Block, Timing

Generation Block, and the Auxiliary Function Block. The following

sections provide a brief description of the blocks and applications

for the four sections.

TRANSMIT SECTION COMPONENTS

Figure 2a shows an MSB first, 4-pin SPI read; Figure 2b shows an

MSB first, 3-pin read; and Figure 2c shows an LSB first, 4-pin read.

The transmit block (Tx) accepts and can process real or complex

data. The Tx interface is configurable for a variety of data formats

and has special processing options such as interpolation and Hilbert

filters. A detailed block diagram of the AD9860/AD9862 transmit

path is shown in Figure 3. The transmit block diagram is broken

into these stages: DAC (Block A), Coarse Modulation (Block B),

SYSTEM BLOCK DESCRIPTION

The AD9860/AD9862 integrates transmit and receive paths with

digital signal processing blocks and auxiliary features. The auxiliary

–18–

REV. 0

AD9860/AD9862

BLOCK A

DAC

BLOCK B

BLOCK C

BLOCK D

BLOCK E

BYPASSABLE

DIGITAL

BYPASSABLE

LOW-PASS

BYPASSABLE

DIGITAL

HILBERT

FILTER

QUADRATURE INTERPOLATION QUADRATURE

MIXER

FILTER

MIXER

IOUT+A

IOUT–A

PGA

TxDAC

I

TxDATA

[0:13]

HILBERT

FILTER

IOUT+B

IOUT–B

Q

TxDAC

f_S/4,

f_S/8

DDS

Figure 3. Transmit Section Block Diagram

Interpolation Stage (Block C), Fine Modulation Stage (Block D),

Hilbert filter (Block E), and the Latch/Demultiplexing circuitry.

Fine Gain controls and dc offset controls can be used to compen-

sate for mismatches (for system level calibration), allowing improved

matching characteristics of the two Tx channels and aiding in suppres-

sing LO feedthrough. This is especially useful in image rejection

architectures. The 10-bit dc offset control of each DAC can be used

independently to provide a ±12% I_OUTFSMAXof offset to either

differential pin, thus allowing calibration of any system offsets. The

fine gain control with 5-bit resolution allows the I_OUTFSMAXof each

DAC to be varied over a ±4% range, thus allowing compensation

of any DAC or system gain mismatches. Fine gain control is set

through the DAC A/B Fine Gain registers and the offset control

of each DAC is accomplished using DAC A/B Offset registers.

DAC

The DAC stage of the AD9860/AD9862 integrates a high perfor-

mance TxDAC core, a programmable gain control through a

Programmable Gain Amplifier (TxPGA), coarse gain control, and

offset adjustment and fine gain control to compensate for system

mismatches.

The TxDAC core of the AD9860/AD9862 provides dual, differen-

tial, complementary current outputs generated from the 12-/14-bit

data. The 12-/14-bit Dual DACs support update rates up to

128 MSPS. The differential outputs (i.e., IOUT+ and IOUT–)

of each dual DAC are complementary, meaning they always sum

to the full-scale current output of the DAC, I_OUTFS. Optimum

ac performance is achieved with the differential current interface

drives balanced loads or a transformer.

A power-down option allows the user to power down the analog

supply current to both DACs or either DAC, individually. A digital

power-down is also possible through either the Tx PwrDwn

register or the Mode/TxBlank pin.

Coarse Modulator

The maximum full-scale output current, I_OUTFSMAX, is set by the

external resistor (R_SET), which sets the DAC reference current.

The R_SETresistor is connected between the FSADJ Pin to ground.

The relationship between I_OUTFSMAXand R_SETis:

A digital coarse modulator is available in the transmit path to

shift the spectrum of the input data by ±f_DAC/4 or ±f_DAC/8. If the

input data consists of complex data, the modulator can be con-

figured to perform a complex modulation of the input spectrum.

If the data in the transmit path is not complex, a real mix can be

performed separately on each channel thereby frequency shifting

the real data and images by f_DAC/4 or f_DAC/8. Real or complex

mixing is configured by setting the Real Mix register.

Ê1.23V ˆ

I_OUTFSMAX~ 67 ¥

Á

˜

R_SET

Ë

¯

Typically, R_SETis 4 kW, which sets I_OUTFSMAXto 20 mA, the

optimal dynamic setting for the TxDACs. Increasing R_SETby a

factor of 2 will proportionally decrease I_OUTFSMAXby a factor of

2. I_OUTFSMAXof each DAC can be re-scaled either simulta-

neously with the TxPGA Gain register or independently with

DAC A/B Coarse Gain registers.

By default, the coarse modulator is bypassed. It can be configured

using Coarse Modulation and Neg Coarse Tune registers.

Interpolation Stage

Interpolation filters are available for use in the AD9860/AD9862

transmit path, providing 1ꢀ (bypassed), 2ꢀ, or 4ꢀ interpolation.

The interpolation filters effectively increase the Tx data rate while

suppressing the original images. The interpolation filters digitally

shift the worst case image further away from the desired signal,

thus reducing the requirements on the analog output reconstruc-

tion filter.

The TxPGA function provides 20 dB of simultaneous gain

range for both DACs and is controlled by writing to SPI register

TxPGA Gain for a programmable full-scale output of 10% to

100% I_OUTFSMAX. The gain curve is linear in dB, with steps of

about 0.1 dB. Internally, the gain is controlled by changing the

main DAC bias currents with an internal TxPGA DAC whose

output is heavily filtered via an on-chip R-C filter to provide

continuous gain transitions. Note, the settling time and band-

width of the TxPGA DAC can be improved by a factor of 2 by

writing to the TxPGA Fast register.

There are two 2ꢀ interpolation filters available in the Tx path.

An interpolation rate of 4ꢀ is achieved using both interpolation

filters; an interpolation rate of 2ꢀ is achieved by enabling only

the first 2ꢀ interpolation filter.

The first interpolation filter provides 2ꢀ interpolation using a

39 tap filter. It suppresses out-of-band signals by 60 dB or more

and has a flat passband response (less than 0.1 dB ripple) extend-

ing to 38% of the AD9860/AD9862 input Tx data rate (19% of

the DAC update rate, f_DAC). The maximum input data rate is

64 MSPS per channel when using 2ꢀ interpolation.

Each DAC has independent coarse gain control. Coarse gain

control can be used to accommodate different I_OUTFSfrom the

dual DACs. The coarse full-scale output control can be adjusted

using the DAC A/B Coarse Gain registers to 1/2 or 1/11th of

the nominal full scale current.

REV. 0

–19–

AD9860/AD9862

The second interpolation filter will provide an additional 2ꢀ inter-

polation for an overall 4ꢀ interpolation. The second filter is a

15 tap filter. It suppresses out-of-band signals by 60 dB or more.

The flat passband response (less than 0.1 dB attenuation) is 38%

of the Tx input data rate (9.5% of f_DAC). The maximum input

data rate per channel is 32 MSPS per channel when using

4ꢀ interpolation.

Hilbert Filter

The Hilbert filter is available to provide a Hilbert transform of

“real” input data at a low intermediate frequency (IF) between

12.5% to 38% of the input data rate. The Hilbert filter essentially

transforms this “real,” single channel input data into a complex

representation (i.e., I and Q components) that can be used as

part of an image rejection architecture. The complex data can than

be processed further using the on-chip digital complex modulators.

The Hilbert filter requires 4ꢀ interpolation to be enabled and

accepts data at a maximum 32 MSPS. Figure 5 shows a spectral

plot of the Hilbert filter impulse response.

The 2ꢀ and 4ꢀ Interpolation Filter Transfer function plots are

shown in Figure 4a and 4b, respectively.

10

INTERPOLATION

0

FILTER

100

80

–10

–20

60

INCLUDUNG SIN (X)/X

–30

40

–40

–50

–60

–70

20

0

–20

–40

–60

–80

–100

–80

–90

–100

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

NORMALIZED – f_S

–20

–15

–10

–5

0

5

10

15

20

FREQUENCY – MHz

10

0

Figure 5. Tx Hilbert Filter, Keeping Positive

Frequencies Spectral Plot

INTERPOLATION

FILTER

–10

–20

Latch/Demultiplexer

The AD9860/AD9862 Tx path accepts dual or single channel

data. The dual channel data can represent two independent real

signals or a complex signal. Various input data latching schemes

relative to one of the output clocks, CLKOUT1 or CLKOUT2,

are allowed, including using any combination of rising and falling

clock edges.

–30

–40

–50

–60

–70

INCLUDUNG SIN (X)/X

Associated Tx timing is discussed in detail in the Clock Overview

section of the data sheet.

–80

–90

–100

TRANSMIT APPLICATIONS SECTION

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

NORMALIZED – f_S

The AD9860/AD9862 transmit path (Tx) includes two, high speed,

high performance, 12-/14-bit TxDACs. Figure 3 shows a detailed

block diagram of the transmit data path and can be referred to

throughout the explanation of the various modes of operation.

The various Tx modes of operation are broken into three parts,

determined by the format of the input data. They are:

Figure 4. Spectral Response of 2ꢀ Interpolation Filter

(top) and 4ꢀ Interpolation Filter (bottom)

Fine Modulation Stage

A digital fine modulation stage is available in the transmit path to

shift the complex Tx output spectrum using a 24-bit numerically

controlled oscillator (NCO). To utilize the Fine Modulation

Block, 4ꢀ interpolation is required. Therefore, the maximum

input date rate is 32 MSPS per channel, which generates a DAC

update rate, f_DAC, of 128 MSPS. The NCO can tune up to 1/4 of

f_DAC, providing a step resolution of f_DAC/2²⁶. Since the Fine

Modulation Stage precedes the Interpolation Filters, care must

be taken to ensure the entire desired signal is placed within the

pass band of the Interpolation Filter.

1. Single Channel DAC Data

2. Two Independent Real Signal DAC Data (diversity or dual

channel

3. Dual Channel Complex DAC Data (I and Q or Single Sideband)

Single Channel DAC Data

In this mode, 12-/14-bit single channel Tx data is provided to

the AD9860/AD9862 and latched using either CLKOUT1 or

CLKOUT2 edges as defined in the Clock Overview section of

the data sheet. All Tx digital signal processing blocks can be

utilized to address reconstruction filtering at the DAC output

and aid in frequency tuning.

By default, the Fine Modulation Block is bypassed. To enable it

to perform a complex mix of the Tx I and Q data, Register 2’s data

paths, Fine Mod and Fine, should be configured. The NCO

frequency tuning word is set in the three FTW registers.

–20–

REV. 0

AD9860/AD9862

In most systems, the DAC (and each up-converter stage) requires

analog filtering to meet spectral mask and out-of-band spurious

emissions requirements. Digital interpolation (Block C) and

Hilbert filtering (Block E) can be used to relax some of the system

analog filtering.

independently. The Tx digital processing blocks available in this

mode are the Interpolation Filters (Block C) and the Coarse

Modulator (Block D).

As mentioned previously, the interpolation filters can be used to

relax requirements on the external analog filters. The maximum

rate of the Tx interface is 128 MSPS, i.e., 64 MSPS/channel

with interleaved data. Therefore to fully take advantage of the

DACs maximum update rate of 128 MSPS, 2ꢀ interpolation is

required. The 4ꢀ interpolation filter is recommended for input

data rates equal to or less than 32 MSPS/channel (64 MSPS

interleaved). The data bandwidth with 2ꢀ or 4ꢀ interpolation

enabled is up to 37.5% of the channel input data rate. If no

interpolation is enabled, the data bandwidth will be the full

Nyquist band with Sinc ꢀ limitations. The interpolation filters

are configured through the Interpolation Serial register.

Digital 2ꢀ interpolation with input data rates of up to 64 MSPS or

4ꢀ interpolation with input data rates of 32 MSPS is available

in this mode (or interpolation filters can be bypassed to achieve

a 128 MSPS input data rate). The data bandwidth with 2ꢀ or

4ꢀ interpolation enabled is up to 38% of the input data rate. If

no interpolation is enabled, the data bandwidth will be the full

Nyquist band with Sinc ꢀ limitations. The interpolation filters

are configured through the Interpolation Serial register.

The Hilbert filter can be enabled in this mode to suppress the

positive or negative image that naturally occurs with real data.

The single sideband signal when combined with a quadrature

modulator can upconvert the desired signal and suppressed image,

forming a Hartley Image Rejection Architecture (both Tx paths

need to be enabled to produce the Image Rejection Architecture).

The Hilbert filter will provide over 50 dB image suppression for

signals between 12.5% to 38% of the input data rate. The Hil-

bert filter can be enabled and configured using the Hilbert and

Keep –ve Serial registers.

The coarse modulation will perform a real mix of each channel,

independently, with either f_DAC/4 or f_DAC/8.

Dual Channel Complex DAC Data

The Dual Channel Complex DAC Data (also known as Single

Sideband Data) is used to generate complex Tx signals (i.e., I and

Q). In this mode, 12-/14-bit, interleaved I and Q data is provided

to the AD9860/AD9862 and latched using either CLKOUT1 or

CLKOUT2 edges as defined in the Clock Overview section of

the data sheet. Both Tx paths are enabled and the two signals

will be processed as a complex waveform. The Tx digital pro-

cessing blocks available in this mode are the Fine Modulator

(Block B), the Interpolation Filters (Block C), and the Coarse

Modulator (Block D).

Digital frequency tuning the Tx output is also possible in this

mode using the coarse modulation block. The coarse modulation

block can be used to frequency shift the Tx signal either –f_DAC/4,

–f_DAC/8, +f_DAC/8 or +f_DAC/4. The coarse modulator does not

require the Hilbert filter to be enabled, in which case the real

signal and image will shift. If the Hilbert filter is enabled, a

complex mix can be performed on the single sideband signal by

the coarse modulator (Note: the Hilbert filter does not need to

be enabled if single sideband data is provided externally).

As mentioned previously, the interpolation filters can be used to

relax requirements on the external analog filters. The maximum

rate of the Tx interface is 128 MSPS, i.e., 64 MSPS/channel with

interleaved data (as is the case in this mode). Therefore, to fully

take advantage of the DAC’s maximum update rate of 128 MSPS,

2ꢀ interpolation is required. The 4ꢀ interpolation is recommended

for input data rates equal to or less than 32 MSPS/channel

(64 MSPS interleaved). The data bandwidth with 2ꢀ or 4ꢀ

interpolation enabled is up to 37.5% of the channel input data

rate. If no interpolation is enabled, the data bandwidth will be

the full Nyquist band with Sinc ꢀ limitations. The interpolation

filters are configured through the Interpolation Serial register.

The fine modulator can be used to accurately place the output

signal shifting the Tx data spectrum in the positive or negative

direction with a resolution of f_DAC/2²⁶. The fine modulator

requires both 4ꢀ interpolation and the Hilbert filter enabled to

be used in this mode. The coarse modulator and fine modulator

can both be used and provide a tuning range between ±68% of

the DAC Nyquist frequency.

If all Tx DSP blocks are bypassed, the AD9860/AD9862 oper-

ates similar to a standard TxDAC. In Single Channel DAC Data

mode, only the Channel A DAC is used; Channel B is powered

down to reduce power consumption.

A complex mix can be performed on the single sideband signal

by the coarse and/or fine modulator. The coarse modulation

block can be used to frequency shift the Tx signal either –f_DAC/4,

–f_DAC/8, +f_DAC/8 or + f_DAC/4. The fine modulator can be used to

accurately place the output signal shifting the Tx data spectrum

in the positive or negative direction with a resolution of 1/2²⁶of

the DAC update rate. The fine modulator requires 4ꢀ interpola-

tion to be enabled. The coarse modulator and fine modulator

can both be used and provide a tuning range between ±70% of

the DAC Nyquist frequency.

Two Independent Real Signal DAC Data

The Dual Channel Real DAC Data mode is used to transmit

diversity or dual channel signals. In this mode, 12-/14-bit, dual

channel, interleaved Tx data is provided to the AD9860/AD9862

and latched using either CLKOUT1 or CLKOUT2 edges as

defined in the Clock Overview section of the data sheet. Both

Tx paths are enabled and the two signals will be processed

REV. 0

–21–

AD9860/AD9862

BLOCK A BLOCK B

BLOCK C

BLOCK D

BLOCK E

LOW-PASS

DECIMATION

FILTER

VIN+A

VIN–A

RxA DATA

[0:11]

1ꢂ

PGA

ADC

HILBERT

FILTER

VIN+B

VIN–B

RxB DATA

[0:11]

Figure 6. Receive Section Block Diagram

RECEIVE SECTION COMPONENTS

RxPGA

The receive block is configurable to process input signals of dif-

ferent formats and has special features such as an input buffer,

gain stage, and decimation filters. The AD9860/AD9862 receive

path block diagram is shown in Figure 6. The block diagram can

be broken into the following stages: Input Buffer (Block A),

RxPGA (Block B), dual, 10-/12-bit, 64 MSPS ADC (Block C),

Decimation filter (Block D), Digital Hilbert Block (Block E),

and a Data Output Multiplexer. The function of each stage is

explained in the following paragraphs.

The RxPGA stage has a Programmable Gain Amplifier that can be

used to amplify the input signal to utilize the entire input range

of the ADC. The RxPGA stage provides a 0 dB to 20 dB gain

range in steps of about 1 dB. The Rx channel independent gain

control is accomplished through two 5-bit SPI programmable

RxPGA A/B registers. The gain curve is linear in dB with a minimum

gain setting (0 dB, nominally) of hex00 and a maximum gain

setting (20 dB, nominally) of hex14.

The RxPGA stage can provide up to a 2 V p-p signal to the

ADC input.

Input Buffer Stage

The input buffer stage buffers the input signal on-chip for both

receive paths. The buffer stage has two main benefits, providing

a constant input impedance and reducing any “kick-back” noise

that might be generated on-chip, affecting the analog input signal.

Analog-to-Digital (A/D) Converter

The analog-to-digital converter (ADC) stage consists of two

high performance 10-/12-bit, 64 MSPS analog-to-digital (A/D)

converters. The dual A/D converter paths are fully independent,

except for a shared internal bandgap reference source, V_REF. Each

of the A/D converter’s paths consists of a front-end sample and

hold amplifier followed by a pipelined, switched capacitor, A/D

converter. The pipelined A/D converter is divided into three sections,

consisting of a 4-bit first stage followed by eight 1.5-bit stages and

a final 3-bit flash. Each stage provides sufficient overlap to correct

for flash errors in the preceding stages. The quantized outputs

from each stage are combined into a final 12-bit result through

a digital correction logic block. The pipelined architecture permits

the first stage to operate on a new input sample while the remain-

ing stages operate on preceding samples. Sampling occurs on the

rising clock edge.

The Rx path sampling mode can be split into two categories,

depending on the frequency of the input signal. When sampling

input signals up to Nyquist of the ADC, the sampling is referred to

as Nyquist sampling. When sampling at rates above ADC Nyquist

rate, the sampling is referred to as IF sampling or undersampling.

For Nyquist sampling, the input buffer provides a constant 200 W

impedance over the entire input signal range. The constant input

impedance accommodates matching networks to ensure proper

transfer of signal to the input of the device. The input buffer is

self-biased to ~ 2 V, and therefore the input signal should be

ac-coupled to the Rx differential input or have a common-mode

voltage of about 2 V. If an external buffer is present, the internal

input buffer can be bypassed and powered down to reduce power

consumption. The input buffer accepts up to a 2 V p-p input

signal for maximum SNR performance. Optimal THD perfor-

mance occurs with 1 V p-p input signal.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash A/D connected to a switched capacitor DAC and

interstage residue amplifier (MDAC). The residue amplifier magni-

fies the difference between the reconstructed DAC output and the

flash input for the next stage in the pipeline. One bit of redundancy

is used in each one of the stages to facilitate digital correction of

flash errors. The last stage simply consists of a flash A/D.

For IF sampling, the input buffer can be used with input signals

up to about 100 MHz, the 3 dB bandwidth of the buffer. When

undersampling the input signal, the output spectrum will contain

an aliased version of the original, higher frequency signal. As was

the case with Nyquist sampling, the input signal should be

ac-coupled to the Rx differential input or have a common-mode

voltage of ~ 2 V. For input signals over 100 MHz to about 250 MHz,

the input buffer needs to be bypassed and an external input

buffer is required. In the case that the input buffer is bypassed,

the input circuit is a switched capacitor network. The switching

input impedance during the sample phase is about 1/(2(ꢂ)FC),

where F is the input frequency and C is the input capacitance

(about 4 pF). During hold mode, the input impedance is > 1 MW.

A stable and accurate 1.0 V bandgap voltage reference is built into

the AD9860/AD9862 and is used to set a 2 V p-p differential input

range. The internally generated reference should be decoupled

at the V_REFpin using a 10 mF and a 0.1 mF capacitor in parallel

to ground. Separate top and bottom references, V_RTand V_RB

,

for each converter are generated from V_REFand should also be

decoupled. Recommended decoupling for the top and bottom

references consists of using 10 mF and 0.1 mF capacitors in parallel

between the differential reference pins, and a 0.1 mF capacitor

–22–

REV. 0

AD9860/AD9862

from each to ground. The internal references can also be disabled

(powered down) and driven externally to provide a different input

voltage range or low drift reference. If an external V_REFreference

is used, it should not exceed 1.0 V.

The output data from the dual ADCs can be multiplexed onto

a single 10-/12-bit output bus. The multiplexing is synchronized

using the RxSYNC output pin that indicates which channel data

is on the output bus.

A Shared Reference mode allows the user to connect the differen-

tial references from both ADCs together externally for superior

gain matching performance. If the ADCs are to function inde-

pendently, then the reference can be left separate and will provide

superior isolation between the dual channels. Shared Reference

mode can be enabled through the Shared Ref register.

RECEIVE APPLICATIONS SECTION

The AD9860/AD9862 receive path (Rx) includes two high speed,

high performance, 10-/12-bit ADCs. Figure 6 shows a detailed

block diagram of the Rx data path and can be referred to through-

out the explanation of the various modes of operation. The various

Rx modes of operation are broken into three parts determined by

the type of input signal:

A power-down option allows the user to power down both ADCs

(sleep mode) or either ADC individually to reduce power

consumption.

1. Single Channel ADC Signal

2. Dual Channel Real ADC Signal (diversity or dual channel)

Decimation Stage

3. Dual Channel Complex ADC Signal (I and Q or Single

Sideband).

Each one of these parts is further divided into two cases, sampling

input signals up to Nyquist of the ADC (Nyquist sampling) and

sampling at rates above ADC Nyquist rate (IF sampling or

undersampling).

For signals with maximum frequencies less than or equal to 3/16 the

ADC sampling rate, f_ADC, the decimate by 2 filter (or half-band

filter) can be used to provide on-chip suppression of out-of- band

images and noise. When data is present in frequencies greater

than 1/4 f_ADC, the decimate by 2 filter can be disabled by switching

the filter out of the circuit. The decimation filter allows the ADC

to oversample the input while decreasing the output data rate by

half. The two main benefits are a simplification of the input anti-

aliasing filter and a slower data interface rate with the external

digital ASIC. The decimation filter is an 11 tap filter and suppresses

out of band noise by 38 dB.

The AD9860/AD9862 uses oversampling and decimation filters to

ease requirements on external filtering components. The decima-

tion filters (for both receive paths) can be used or bypassed so as

to accommodate different signal bandwidths and provide different

output data rates to allow easy integration with several different

data processing schemes.

Hilbert Block

The Hilbert filter is available to provide a Hilbert Transform of the

data from the ADC in Channel B. The Digital Hilbert Transform,

in combination with an external complex downconverter, enables

a receive image rejection architecture (similar to Hartley image

rejection architecture). The Hilbert filter pass-band (< 0.1 dB

ripple) is between 25% to 75% of the Nyquist rate of its input data

rate. The maximum data rate of the Rx Hilbert filter is 32 MSPS.

At ADC rates higher than this, the decimation filters should be

enabled. The Hilbert filter transfer function plots are shown in

Figure 7.

Nonbaseband data can be used in an effort to avoid the dc offsets

in the receive signal path that can cause errors. By receiving

nonbaseband data, the requirements of external filtering may be

greatly reduced.

In each of the different receive modes, the input buffer, Program-

mable Gain Amplifier (RxPGA), and output multiplexer remain

within the receive path.

Single Channel ADC Signal

In this mode, a single input signal to be digitized is connected to

the differential input pins, VIN+A and VIN–A. The 10-/12-bit

output Rx data is latched using either CLKOUT1 or CLKOUT2

edges as defined in the Clock Overview section. The Rx path

available options include bypassing the input buffer, Rx PGA

control and using the Decimation Filter. By default, both Rx paths

are enabled and the unused one should be powered down using

the appropriate bit in the Rx Power-Down register, d1.

0

–40

The input buffer description above explains the conditions under

which the buffer should be bypassed.

–80

If the input signal, or the undersampled alias signal for the

IF sampling case, falls below 40% of the ADC Nyquist rate, the

decimation filter can be enabled to suppress out-of-band noise and

spurious signals by 40 dB or more. With the decimation filter

enabled, the SNR of the Rx path improves by about 2.3 dB.

–120

–0.5 –0.4 –0.3 –0.2 –0.1

0

0.1

0.2

0.3

0.4 0.5

Dual Channel Real ADC Signal

NORMALIZED – f_S

The Dual Channel Real ADC Signal mode is used to receive

diversity signals or dual independent channel signals that will be

processed independent of each other. In this mode, the two input

signals to be digitized are connected to the differential input pins

of the AD9860/AD9862, VIN+A, VIN–A, VIN+B, and VIN–B.

The two 10-/12-bit Rx outputs can be either interleaved onto a

single 10-/12-bit bus or output in parallel on two 10-/12-bit buses.

Figure 7. Rx Hilbert Filter, Keeping Positive Frequencies

Response

Data Output Multiplexer Stage

The Rx data output format can be configured for either twos

complement or offset binary. This is controlled by the Rx Twos

Complement register.

REV. 0

–23–

AD9860/AD9862

The output will be latched using some configuration of CLKOUT1

or CLKOUT2 edges as defined in the Clock Overview section of

the data sheet. The Rx path available options include bypassing

the input buffer, RxPGA control and using the decimation filter.

An internal Delay Lock Loop (DLL) based clock multiplier pro-

vides a low noise, 2ꢀ or 4ꢀ multiplication of the input clock over

an output frequency range of 32 MHz to 128 MHz. The DLL

Fast register should be used to optimize the DLL performance.

For DLL output frequencies between 32 MHz and 64 MHz, this

bit should be set low. For output frequencies between 64 MHz

to 128 MHz, the Fast bit should be set high (for a 64 MHz out-

put frequency, the register can be set either high or low). The DLL

can be bypassed by setting a 1ꢀ multiplication factor in the DLL

Multiplier register. The DLL can be powered down when it is

bypassed for power savings by setting the DLL PwrDwn register.

The input buffer description above explains the conditions under

which the buffer should be bypassed.

If the input signal, or the undersampled alias signal for the

IF sampling case, falls below 40% of the ADC Nyquist rate, the

decimation filter can be enabled to suppress out-of-band noise

and spurious signals by 40 dB or more. With the decimation

filter enabled the SNR of the Rx path improves by about 2.3 dB.

For applications where an external crystal is desired, the AD9860/

AD9862 internal oscillator circuit and the DLL clock multiplier

enable a low frequency, lower cost quartz crystal to be used to

generate the input reference clock. The quartz crystal would be

connected between the OSC1 and OSC2 pins with parallel

resonant load capacitors as specified by the crystal manufacturer.

Dual Channel Complex ADC Signal

The Dual Channel Complex ADC Signal mode is used to receive

baseband I and Q signals or a single sideband signal at some IF.

In this mode, a complex input signal is generated from an external

quadrature demodulator. The in-phase channel (I channel) is

connected to VIN+A and VIN–A, and the Quadrature Data

(Q channel) is connected to the VIN+B and VIN–B differential

pins. The Rx path available options include bypassing the input

buffer, RxPGA control, the decimation filter, and using the digital

Hilbert filter. Shared Reference mode is also discussed below.

An internal Duty Cycle Stabilizer (DCS) can be enabled on the

AD9860 by setting the Clk Duty register. This provides a stable

50% duty cycle to the ADC for high speed clock rates between

40 MSPS to 64 MSPS when proper duty cycle is more critical.

System Clock Distribution Circuitry

The RxPGA provides 0 dB to 20 dB gain control for both chan-

nels. The input buffer description above explains the conditions

under which the buffer should be bypassed.

There are many variables involved in the timing distribution.

External variables include CLKIN, CLKOUT1, CLKOUT2,

Rx Data Rate, Tx Data Rate. Internal variables include ADC

conversion rate, DAC update rate, interpolation rate, decimation

rate, Rx data multiplexing and Tx data demultiplexing. Many of

these parameters are interrelated and based on CLKIN. Optimal

power versus performance and ease of integration options can

be chosen to suit a particular application.

If the input signal, or the undersampled alias signal for the IF sam-

pling case, falls below 40% of the ADC Nyquist rate, the decimation

filter can be enabled to suppress out-of-band noise and spurious

signals by 40 dB or more. With the decimation filter enabled,

the SNR of the Rx path improves by about 2.3 dB.

A digital Hilbert filter can be enabled to provide a receive image

rejection architecture on-chip. The digital Hilbert filter combines

the I data and a phase shifted version of the Q data to produce a

single combined Rx signal. The filter can provide 50 dB image

suppression in the pass band (less than 0.1 dB ripple). The pass

band of the filter is from 25% to 75% of Nyquist rate of the data

entering the Hilbert filter. Note, the Hilbert filter’s maximum

input data rate is 32 MSPS, at ADC rates above 32 MSPS. The

decimation filter is required to reduce the data rate. With the

decimation filter also enabled, the pass band of the Hilbert filter

will be 12.5% to 37.5% of the ADC Nyquist rate (still 25% to 75%

of the Nyquist rate of the data entering the Hilbert filter).

NO DECIMATION,

2

DATA

MUX

Rx DATA

[0:23]

ADC

AND

LATCH

DECIMATE:

REG D6 B0

MUX OUT:

REG D5 B0

Rx RETIME:

REG D5 B3

NO INVERSION,

INVERT

1ꢂ, 1/2ꢂ

DIV

INV

CLKOUT1

CLKSEL

INV1: REG D25 B1

NO INVERSION,

INVERT

1ꢂ, 1/2ꢂ

1ꢂ, 2ꢂ, 4ꢂ

1ꢂ, 1/2ꢂ, 1/4ꢂ

CLKIN

An optional Shared Reference mode allows the user to connect the

differential references from the dual ADC together externally for

superior gain matching performance. To enable the Shared Ref-

erence mode, the Shared Ref register (d4, b1) should be set high.

CLKOUT2

INV

DIV

DLL

DIV

ADC DIV2:

DLL MULTIPLIER:

REG D24 B5 REG D24 B3, 4

CLKOUT2

DIV FACTOR:

REG 25 B6, 7

INV2:

REG D25 B5

NO INTERP

2,

4

DATA

LATCH

AND

TIMING GENERATION BLOCK

Tx DATA

[0:13]

DAC

The AD9860/AD9862 Timing Generation block uses a single

external clock reference to derive all internal clocks to operate

the transmit and receive channels. The input clock reference

can consist of either an external single ended clock applied to

the OSC1 pin, with the OSC2 pin left floating or an external

crystal connected between the clock input pins (OSC1 and OSC2).

DEMUX

INTERPOLATION:

REG D19 B0, 1

CLOCK PATH

DATA PATH

2 DATA PATHS: REG D19 B4

Q/I ORDER:

Tx RETIME:

REG D18 B5

REG D18 B6

Figure 8. Normal Operation Timing Block Diagram

By default, the AD9860/AD9862 can accept either an external

reference clock or a crystal to generate the input clock. The

internal oscillator, if not used, should be disabled by setting the

Input Control Clock register. The OSC1 input impedance is a

relatively high resistive impedance (typically, about 500 kW).

One of two possible timing operation modes can be selected. The

typical timing mode is called Normal Operation mode; a block

diagram is shown in Figure 8. The other mode is called Alterna-

tive Operation mode, and a block diagram is shown in Figure 12.

–24–

REV. 0

AD9860/AD9862

Table I. Rx Data Timing Table

Table Ia. CLKSEL Set Logic Low

Table Ib. CLKSEL Set Logic High

ADC

Div 2

See Figure 8 for

Relative Timing

ADC

Div 2

See Figure 8 for

Relative Timing

CLKSEL

Decimate

Multiplex

CLKSEL

Decimate Multiplex

Timing No. 4

Timing No. 3

No Mux

Rx Data = 2 ꢀ CLKOUT1

CLKOUT1 = 1⁄2 ꢀ CLKIN

No Mux

Rx Data = CLKOUT1

CLKOUT1 = CLKIN

No

Timing No. 4

Decimation

Mux

No Mux

Mux

Not Allowed

Rx Data(MUXED) = 2 ꢀ CLKOUT1

CLKOUT1 = CLKIN

No

Timing No. 3

Timing No. 2

Div

Rx Data = 2 ꢀ CLKOUT1

CLKOUT1 = 1⁄2 ꢀ CLKIN

No Mux

Rx Data = 1⁄2 ꢀ CLKOUT1

CLKOUT1 = CLKIN

Decimation

Mux

Timing No. 4

Timing No. 3

Rx Data(MUXED) = 2 ꢀ CLKOUT1

CLKOUT1 = 1⁄2 ꢀ CLKIN

Rx Data(MUXED) = CLKOUT1

CLKOUT1 = CLKIN

Low

High

Timing No. 3

Timing No. 2

No Mux

Mux

Rx Data = CLKOUT1

CLKOUT1 = 1⁄2 ꢀ CLKIN

No Mux

Rx Data = 1⁄2 ꢀ CLKOUT1

CLKOUT1 = CLKIN

No

Timing No. 4

Timing No. 3

Rx Data(MUXED) = CLKOUT1

CLOUT1 = CLKIN

Decimation

Mux

Rx Data(MUXED) = 2 ꢀ CLKOUT1

CLOUT1 = 1⁄2 ꢀ CLKIN

Div

Timing No. 2

Timing No. 1

Rx Data = 1⁄4 ꢀ CLKOUT1

CLOUT1 = CLKIN

No Mux

Mux

Rx Data = 1⁄2 ꢀ CLKOUT1

CLOUT1 = 1⁄2 ꢀ CLKIN

No Mux

Decimation

Timing No. 3

Timing No. 2

Rx Data(MUXED) = CLKOUT1

CLKOUT1 = 1⁄2 ꢀ CLKIN

Mux Rx Data(MUXED) = 1⁄2 ꢀ CLKOUT1

CLKOUT1 = CLKIN

f_CLKOUT1

Rx DATATIMING No. 1

f_Rx= CLKOUTꢇ4

Rx DATATIMING No. 2

f_Rx= CLKOUTꢇ2

Rx DATATIMING No. 3

f_Rx= CLKOUT

Rx DATATIMING No. 4

f_Rx= 2ꢂCLKOUT

t_R

ꢂ

1

ꢂ3

t_R

ꢂ

2

ꢂ

1

Figure 9. Rx Timing Diagram

ADC DIV2

A

DLL MULT

00: C = B

01: C = B/2

10: C = B/4

CLKOUT2 DIV

INTERP

B

C

D

E

TxDAC UPDATE RATE

SINGLE CHANNEL

(CANNOT EXCEED

DLL OUTPUT RATE)

00: D = C

01: D = C/2

10: D = C/4

00: E = D

01: E = 2 ꢂ D

10: E = 4 ꢂ D

0: B = A

1: B = A/2

CLKIN

ADC SAMPLE RATE

(NOTTO EXCEED 64MHz)

DLL OUTPUT RATE

(NOTTO EXCEED 128MHz)

CLKOUT2

INPUT Tx DATA RATE

(SINGLE CHANNEL)

Figure 10. Single Tx Timing Block Diagram, Alternative Operation

–25–

REV. 0

AD9860/AD9862

For the Normal Operation mode, the Tx timing is based on

a clock derived from the DLL output, while the Rx clock is

unaffected by the DLL setting.

The Rx data (unless re-timed using the Rx Retime register) is

timed relative to the CLKOUT1 pin output. The Rx output data

can be decimated (halving the data rate) or both channels can be

multiplexed onto the channel A data bus (doubling the data rate).

The Alternative Operation mode, timing utilizes the output of

the DLL to generate both Rx and Tx clocks. It also sets default

operation of the DLL to 4ꢀ mode.

Decimation enables oversampling while maintaining a slower

external data transfer rate and provides superior suppression of

out of band signals and noise. Multiplexing enables fewer digital

output bits to be used to transfer data from the Rx path to the

digital ASIC collecting the data.

Normal Operation is typically recommended because the Rx ADC

is more sensitive to the jitter and noise that the DLL may gener-

ate, so its performance may degrade. The Mode/TxBlank pin

logic level at power up or RESET defines in which mode the

device powers up. If Mode/TxBlank is low at power up, the

Normal Operation mode is configured. Otherwise, the Alternative

Operation mode is configured.

When Mux Mode is enabled with an output data rate equal to

CLKOUT1 (Timing No. 3 in Figure 9) then the RxSync pin is

required to identify which channel’s output data is on the output

data bus. RxSync output is aligned with the output data, and by

default a logic low indicates data from Rx Channel B is currently

on the output data bus. If RxSync is logic high, then data from

Rx Channel A is currently on the output data bus. The Inv RxSync

register can be used to switch this notation.

Rx Path (Normal Operation)

The ADC sampling rate, the Rx data output rate, and the rate of

CLKOUT1 (clock used to latch output data) are the parameters

of interest for the receive path data. These parameters in addition

to the data bandwidth are related to CLKIN by decimation filters,

divide by two circuits, data multiplexer logic and retiming latches.

The Rx path timing can be broken into two separate relation-

ships: the ADC sample rate relative to the input clock, CLKIN

and the output data rate relative to CLKOUT1.

The CLKOUT1 pin outputs a clock at the frequency of CLKIN or

CLKIN/2 depending on the voltage level applied to the CLKSEL

pin. If a logic low is applied to CLKSEL, CLKOUT1 will run

at half the CLKIN rate, if CLKSEL is set to logic high CLKOUT1

outputs a clock equal to CLKIN.

The ADCs sample rate relative to CLKIN is controlled by the

ADC Div2 register and the sample rate can be equal to or one half

of the input clock rate.

This timing flexibility along with the invert option for CLKOUT1,

controlled by the Inv 1 register allow for various methods of latch-

ing data from the Rx path to the digital ASIC, which will process

the data. These options are shown in Table Ia and Ib along with

a timing diagram in Figure 9. Not shown is the option to invert

CLKOUT1, controlled by the Inv 1 register. For this mode, relative

timing remains the same except the opposite edges of CLKOUT1

would be used.

The output data relative to CLKOUT1 has many configurations

providing a flexible interface. The different options are shown in

Figure 8. Table Ia and Ib describe the setup required to obtain

the desired data timing. RxSync is available when the Rx data is

decimated and multiplexed to identify which channel data is

present at the output bus.

DUAL CHANNEL

FACTOR

ADC DIV2

DLL MULT

CLKOUT2 DIV

2 EDGES

INTERP

A

B

C

D

E

F

G

TxDAC UPDATE RATE

EACH CHANNEL

(CANNOT EXCEED

DLL OUTPUT RATE)

00: C = B

01: C = 2 ꢂ B

10: C = 4 ꢂ B

00: D = C

01: D = C/2

10: D = C/4

00: G = F

01: G = 2 ꢂ F

10: G = 4 ꢂ F

0: B = A

1: B = A/2

0: E = D

1: E = 2 ꢂ D

CLKIN

F = E/2

ADC SAMPLE RATE

(NOTTO EXCEED 64MHz)

DLL OUTPUT RATE

(NOTTO EXCEED 128MHz)

CLKOUT2

INPUT

Tx DATA RATE

INPUT Tx DATA RATE

EACH CHANNEL

Figure 11. Dual Tx Timing Block Diagram, Alternative Operation

f_CLKOUT2

Tx DATATIMING No. 1

f_Tx= CLKOUT2

Tx DATATIMING No. 2

f_Tx= 2ꢂCLKOUT2

f_T

ꢂ1

f_T

ꢂ3

f_T

ꢂ2

f_T

ꢂ4

Figure 12. Tx Timing Diagram

–26–

REV. 0

AD9860/AD9862

Tx Path (Normal Operation)

Table II. CLKOUT2 Timing Relative to CLKIN

for Normal Operation Mode

The DAC update rate, the Tx input data rate, and the rate of

CLKOUT2 (clock used to latch Tx input data) are the parameters

of interest for the transmit path data. These parameters, in addition

to the output signal bandwidth, are related to CLKIN by the settings

of the ADC Div2, the DLL multiplier, the CLKOUT2 Div, the

two edges, and the interpolation registers.

DLL

Mult

CLKOUT2

Div Factor

CLK DIV2

CLKOUT2

ꢃ1

ꢃ2

ꢃ4

CLKIN

CLKIN/2

CLKIN/4

1ꢀ

2ꢀ

4ꢀ

1ꢀ

2ꢀ

4ꢀ

The Tx data is timed relative to the CLKOUT2 pin (unless it is

retimed relative to CLKOUT1 by setting Tx Retime register) and

the input Tx data is latched on either each rising edge, each

falling edge or both edges (controlled through the Inverse Sample

and two edges registers). The timing diagrams for these cases

are shown in Figure 12.

ꢃ1

ꢃ2

ꢃ4

2ꢀCLKIN

CLKIN

CLKIN/2

No Div

ꢃ1

ꢃ2

ꢃ4

4ꢀCLKIN

2ꢀCLKIN

CLKIN

The Dual Tx data is multiplexed onto a single bus so that fewer

digital bits are necessary to transfer data. Throughout this discus-

sion of Tx path timing, Tx digital processing options other than

interpolation are ignored because they do not change data timing;

Tx data timing reflects whether single or dual channel data is

latched into the AD9860/AD9862.

ꢃ1

ꢃ2

ꢃ4

CLKIN/2

CLKIN/4

CLKIN/8

ꢃ1

ꢃ2

ꢃ4

CLKIN

CLKIN/2

CLKIN/4

The rates of CLKOUT2 (and the input data rate) are related

to CLKIN by the DLL Multiplier Register, the setting of the

CLKOUT2 Divide Factor Register and the register ADC Div2.

These relationships are shown in Table II.

Div by 2

ꢃ1

ꢃ2

ꢃ4

2ꢀCLKIN

CLKIN

CLKIN/2

NO DECIMATION,

2

Rx DATA

[0:23]

DATA MUX

AND

LATCH

ADC

1ꢂ, 1/2ꢂ

DIV

DECIMATE:

REG D6 B0

MUX OUT: REG D5 B0

Rx RETIME: REG D5 B3

ADC DIV2:

REG D24 B5

1ꢂ, 1/2ꢂ

NO INVERSION, INVERT

INV

DIV

CLKOUT1

1ꢂ, 2ꢂ, 4ꢂ

CLKIN

CLKSEL

INV1: REG D25 B1

DLL

1ꢂ, 1/2ꢂ, 1/4ꢂ

NO INVERSION, INVERT

DLL MULTIPLIER:

REG D24 B3, 4

CLKOUT2

DIV

INV

CLKOUT2 DIV FACTOR:

REG 25 B6, 7

INV2: REG D25 B5

NO INTERP, 2,

4

DATA LATCH

AND

DEMUX

Tx DATA

[0:13]

DAC

INTERPOLATION:

REG D19 B0, 1

2 DATA PATHS: REG D19 B4

Q/I ORDER: REG D18 B5

Tx RETIME: REG D18 B6

CLOCK PATH

DATA PATH

Figure 13. Alternative Operation Timing Block Diagram

REV. 0

–27–

AD9860/AD9862

The timing block diagrams in Figures 10 and 11 show how the

various clocks of the single and dual Tx path are affected by the

various register settings.

pin. If a logic low is applied to CLKSEL, CLKOUT1 will run at

half the CLKIN rate; if CLKSEL is set to logic high, CLKOUT1

outputs a clock equal to CLKIN.

For dual Tx data, an option to redirect demultiplexed data to

either path is available. For example, the AD9860/AD9862 can

accept complex data in the form of I then Q data or Q then I data,

controlled through QI Order register.

This timing flexibility, along with the invert option for CLKOUT1

controlled by the Inv 1 Register, allows for various methods of

latching data from the Rx path to the digital ASIC, which will pro-

cess the data. These options are shown in Table Ia and Ib along

with a timing diagram in Figure 9. Not shown is the option to

invert CLKOUT1, controlled by the Inv 1 register. For this

mode, relative timing remains the same except the opposite edges

of CLKOUT1 would be used.

For the dual Tx data cases, the Tx_SYNC Pin input logic level

defines what data is currently on the Tx data bus. By default, when

Tx_SYNC is low, Channel A data (first of the set) should be on

the data bus; if TxSYNC is high, Channel B data (or the second of

the set) should be on the Tx bus. This can be reversed be setting

the Inv TxSYNC register.

Overall, relative timing can be found by using the Alternative

Operation Mode Master Timing Guide in Table V and using Rx

timing shown in Figure 9.

Rx Path (Alternative Timing Operation)

The ADC sampling rate, the Rx data output rate and the rate of

CLKOUT1 (clock used to latch output data) are the parameters of

interest for the receive path data. These parameters, in addition

to the data bandwidth, are related to CLKIN by decimation filters,

divide by two circuits, data multiplexer logic retiming latches and

also the DLL multiplication setting (which is not the case for

Normal Operation mode). This mode can be configured by

default by forcing the Tx_Blank_In pin to a logic high level during

power up.

Tx Path (Alternative Timing Operation)

The DAC update rate, the Tx input data rate and the rate of

CLKOUT2 (clock used to latch Tx input data) are the parameters

of interest for the transmit path data. These parameters in addi-

tion to the output signal bandwidth are related to CLKIN by the

settings of the DLL multiplier, the CLKOUT2 Div, the two edge

and the Interpolation registers (in this mode, the ADC Div2

register does not affect Tx timing).

The Tx data is timed relative to the CLKOUT2 pin (unless it is

retimed relative to CLKOUT1 by setting Tx Retime register) and

remains the same as it does in Normal Operation Mode. The input

Tx data is latched on each rising edge, each falling edge or both

edges (controlled through the Inverse Sample and two edge regis-

ters). The timing diagrams for these cases are shown in Figure 12.

The Rx path timing can be broken into two separate relationships:

the ADC sample rate relative to the input clock, CLKIN and

the output data rate relative to CLKOUT1.

The ADCs sample rate relative to CLKIN is controlled by the ADC

Div2 register and the DLL Multiplier register. The sample rate

can be equal to or one half of the DLL output clock rate.

The Dual Tx data is multiplexed onto a single bus so that fewer

digital bits are necessary to transfer data. Throughout this discus-

sion of Tx path timing, Tx digital processing options other than

interpolation are ignored because they do not change data timing;

Tx data timing reflects whether single or dual channel data is

latched into the AD9860/AD9862.

The output data rate relative to CLKOUT1 for the Alternative

Operation Mode has the same configuration options as in the

Normal Operation Mode. The different options are shown in

Figure 9. Table Ia. and Ib. describe the setup required to obtain

the desired data timing.

The rates of CLKOUT2 (and the input data rate) are related to

CLKIN by the DLL Multiplier register and the setting of the

CLKOUT2 Divide Factor register. These relationships are shown

in Table III.

The Rx data (unless retimed using the Rx Retime register) is

timed relative to the CLKOUT1 pin output. The Rx output data

can be decimated (halving the data rate) or both channels can be

multiplexed onto the Channel A data bus (doubling the data rate).

Decimation enables oversampling while maintaining a slower

external data transfer rate and provides superior suppression of

out of band signals and noise. Multiplexing enables fewer digital

output bits to be used to transfer data from the Rx path to the

digital ASIC collecting the data.

Table III. CLKOUT2 Timing Relative to CLKIN

In Alternative Operation Mode

DLL

Mult

CLKOUT2

Div Factor

CLKOUT2

When Multiplexing mode is enabled with an output data rate equal

to CLKOUT1 (Timing No. 3 in Figure 9), then the RxSync pin

is required to identify which channel’s output data is on the

output data bus. RxSync output is aligned with the output data

and by default, a logic low indicates data from Rx Channel B is

currently on the output data bus. If RxSync is logic high, then data

from Rx Channel A is currently on the output data bus. The Inv

RxSync register can be used to switch this notation.

1ꢀ

2ꢀ

4ꢀ

ꢃ1

ꢃ2

ꢃ4

CLKIN

CLKIN/2

CLKIN/4

ꢃ1

ꢃ2

ꢃ4

2ꢀCLKIN

CLKIN

CLKIN/2

ꢃ1

ꢃ2

ꢃ4

4ꢀCLKIN

2ꢀCLKIN

CLKIN

The CLKOUT1 pin outputs a clock at a frequency of CLKIN or

CLKIN/2 depending on the voltage level applied to the CLKSEL

–28–

REV. 0

AD9860/AD9862

Table IV. Normal Operation Mode Master Timing Guide

ADC Data Rate¹(MSPS)

Dual DAC Data Rate²

(MSPS)

CLKOUT1

2 CLKOUT2

ADC

Clock

Rate

DAC

Update

Rate

DLL

Mult

ADC2

Non-MUX Mode

MeUX Mode

4ꢀ

Interp

1ꢀ

2ꢀ

CLKSEL CLKSEL CLKDIV CLKDIV CLKDIV

No Deci Deci by 2 No Deci Deci by 2

Interp Interp

= Low

= High

= 1ꢀ

= 1⁄ 2ꢀ = 1⁄ 4ꢀ

2ꢀ

CLKIN

ꢄ2

CLKIN CLKIN

1ꢀ

2ꢀ

4ꢀ

1ꢀ

2ꢀ

4ꢀ

0

1

CLKIN

ꢄ2

CLKIN

2ꢀ

ꢄ4

4ꢀ

2ꢀ

CLKIN

2ꢀ

CLKIN

ꢄ2

2ꢀ

CLKIN

CLKIN CLKIN CLKIN

CLKIN

CLKIN CLKIN

CLKIN

ꢄ2

4ꢀ

8ꢀ

2ꢀ

CLKIN

4ꢀ

CLKIN

4ꢀ

CLKIN CLKIN

CLKIN CLKIN CLKIN

CLKIN CLKIN

ꢄ2

CLKIN CLKIN CLKIN

CLKIN CLKIN CLKIN CLKIN

ꢄ2

ꢄ4

ꢄ8

ꢄ2

ꢄ4

2ꢀ

CLKIN

CLKIN CLKIN

CLKIN CLKIN CLKIN CLKIN CLKIN

CLKIN CLKIN

CLKIN

ꢄ2

ꢄ4

ꢄ2

ꢄ4

ꢄ2

2ꢀ

CLKIN

2ꢀ

4ꢀ

2ꢀ

CLKIN

ꢄ2

CLKIN

CLKIN CLKIN

CLKIN

NOTES

1

100 MHz rate max.

Single DAC data rate = 1⁄2 dual DAC data rate.

2

Table V. Alternative Operation Mode Master Timing Guide

ADC Data Rate¹(MSPS)

Dual DAC Data Rate²

(MSPS)

CLKOUT1

2 CLKOUT2

ADC

Clock

Rate

DAC

Update

Rate

DLL

Mult

ADC2

Non-MUX Mode

(two buses)

MUX Mode

(one bus)

2ꢀ

Interp

1ꢀ

Interp

4ꢀ

Interp

CLKSEL CLKSEL CLKDIV CLKDIV CLKDIV

= Low = High = 1ꢀ = 1⁄ 2ꢀ = 1⁄ 4ꢀ

No Deci Deci by 2 No Deci Deci by 2

2ꢀ

CLKIN

0

1

1ꢀ CLKIN CLKIN CLKIN

ꢄ2

2ꢀ

CLKIN

CLKIN CLKIN

CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN

ꢄ2

ꢄ4

2ꢀ

CLKIN

2ꢀ

4ꢀ

2ꢀ

CLKIN

4ꢀ

2ꢀ

CLKIN CLKIN

CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN

2ꢀ

CLKIN

2ꢀ

4ꢀ

1ꢀ

CLKIN

CLKIN CLKIN

ꢄ2

4ꢀ

CLKIN

8ꢀ

4ꢀ

2ꢀ

4ꢀ

CLKIN

2ꢀ

CLKIN

8ꢀ

4ꢀ

2ꢀ

4ꢀ

CLKIN CLKIN CLKIN

CLKIN

CLKIN CLKIN CLKIN CLKIN

CLKIN

2ꢀ

CLKIN

CLKIN CLKIN CLKIN CLKIN CLKIN

CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN

ꢄ2

ꢄ4

ꢄ2

ꢄ4

2ꢀ

CLKIN

ꢄ2

2ꢀ

4ꢀ

2ꢀ

CLKIN

2ꢀ CLKIN CLKIN

CLKIN

CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN

CLKIN

ꢄ2

2ꢀ

CLKIN

2ꢀ

8ꢀ

4ꢀ

2ꢀ

CLKIN

4ꢀ

CLKIN CLKIN

4ꢀ

2ꢀ

4ꢀ

2ꢀ

4ꢀ

CLKIN

CLKIN CLKIN

CLKIN

CLKIN CLKIN CLKIN

CLKIN

NOTES

1

100 MHz rate max.

Single DAC data rate = 1⁄2 dual DAC data rate.

2

REV. 0

–29–

AD9860/AD9862

The timing block diagrams in Figures 14 and 15 show how the

various clocks of the single and dual Tx path are affected by the

various register settings.

The AUX ADC A multiplexer controls whether pin AUX_ADC_A1

or pin AUX_ADC_A2 is connected to the input of Auxiliary

ADC A. The multiplexer is programmed through Register D34

B1, SelectA. By default, the register is low, which connects the

AUX_ADC_A2 Pin to the input. Similarly, AUX ADC B has a

multiplexed input controlled by Register D34 B4, SelectB. The

default setting for SelectB is low, which connects the AUX_ADC_B2

input pin to AUX ADC B. If the SelectA or SelectB register bit

is set high, then the AUX_ADC_A1 Pin or the AUX_ADC_B1

pin is connected to the respective AUX ADC input.

For dual Tx data, an option to redirect demultiplexed data to

either path is available. For example, the AD9860/AD9862 can

accept complex data in the form of I then Q data or Q then I data,

controlled through QI Order register.

For the dual Tx data cases, the Tx_SYNC pin input logic level

defines what data is currently on the Tx data bus. By default, when

Tx_SYNC is low, Channel A data (first of the set) should be on the

data bus. If TxSYNC is high, Channel B data (or the second of

the set) should be on the Tx bus. This can be reversed by setting

the Inv TxSYNC register.

An internal reference buffer provides a full-scale reference for

both of the auxiliary ADCs that is equal to the supply voltage for

the auxiliary ADCs. An external full-scale reference can be applied

to either or both of the AUX ADCs by setting the appropriate

bit(s), RefselB for the AUX ADC B and Refsel A for the AUX

ADC B in the Register Map. Setting either or both of these bits

high will disconnect the internal reference buffer and enable the

externally applied reference from the AUX_REF Pin to the

respective channel(s).

ADDITIONAL FEATURES

In addition to the features mentioned above in the transmit,

receive and clock paths, the AD9860/AD9862 also integrates

components typically required in communication systems. These

components include auxiliary analog-to-digital converters (AUX

ADC), auxiliary digital-to-analog converters (AUX DAC), and

a sigma-delta output.

Timing for the auxiliary ADCs is generated from a divided down

Rx ADC clock. The divide down ratio is controlled by register

D35 B0, CLK/4 and is used to maintain a maximum clock rate of

20 MHz. By default, CLK/4 is set low dividing the Rx ADC clock

by 2; this is acceptable when running the Rx ADC at rate of

40 MHz or less. At Rx ADC rate greater than 40 MHz, the CLK/4

register bit should be set high and will divide the Rx ADC clock

by 4 to derive the auxiliary ADC Clock. The conversion time,

including setup, takes 16 clock cycles (16 Rx ADC clock cycles);

when CLK/4 is set low, divide by 2 mode, or 32 clock cycles

when CLK/4 is set high.

Auxiliary ADC

Two auxiliary 10-bit SAR ADCs are available for various external

signals throughout the system, such as a Receive Signal Strength

Indicator (RSSI) function or Temperature Indicator. The auxil-

iary ADCs can convert at rates up to 1.25 MSPS and have a

bandwidth of around 200 kHz. The two auxiliary ADCs (AUX

ADC A and AUX ADC B) have multiplexed inputs, so that up

to four system signals can be monitored.

DLL MULT

CLKOUT2 DIV

INTERP

A

B

C

D

TxDAC UPDATE RATE

SINGLE CHANNEL

(CANNOT EXCEED

DLL OUTPUT RATE)

00: B = A

01: B = 2 ꢂ A

10: B = 4 ꢂ A

00: C = B

01: C = B/2

10: C = B/4

00: D = C

01: D = 2 ꢂ C

10: D = 4 ꢂ C

CLKIN

ADC SAMPLE RATE

(NOTTO EXCEED 64MHz)

DLL OUTPUT RATE

(NOTTO EXCEED 128MHz)

CLKOUT2

INPUT Tx DATA RATE

(SINGLE CHANNEL)

Figure 14. Single Tx Timing Block Diagram, Alternative Operation

DUAL CHANNEL

FACTOR

DLL MULT

CLKOUT2 DIV

2 EDGES

INTERP

A

B

C

D

E

F

TxDAC UPDATE RATE

00: B = A

01: B = 2 ꢂ A

10: B = 4 ꢂ A

00: C = B

01: C = B/2

10: C = B/4

00: F = G

01: F = 2 ꢂ G

10: F = 4 ꢂ G

0: D = C

1: D = 2 ꢂ C

EACH CHANNEL

CLKIN

E = D/2

(CANNOT EXCEED

DLL OUTPUT RATE)

ADC SAMPLE RATE

(NOTTO EXCEED 64MHz)

DLL OUTPUT RATE

(NOTTO EXCEED 128MHz)

CLKOUT2

INPUT

Tx DATA RATE

INPUT Tx DATA RATE

EACH CHANNEL

Figure 15. Dual Tx Timing Block Diagram, Alternative Operation

–30–

REV. 0

AD9860/AD9862

Conversion is initiated by writing a logic high to one or both of

the Start register bits, Register D34 B0 (StartA) and D34 B3

(StartB). When the conversion is complete, the straight binary,

10-bit output data of the AUX ADC is written to one of four

reserved locations in the register map depending on which auxil-

iary ADC and which multiplexed input is selected. Because the

auxiliary ADCs output 10 bits, two register addresses are needed

for each data location.

AUX DAC

The AD9860/AD9862 has three 8-bit voltage output auxiliary

DACs, AUX DACs. The AUX DACs are available for supplying

various control voltages throughout the system such as a VCXO

voltage control or external VGA gain control and can typically

sink or source up to 1 mA.

An internal voltage reference buffer provides a full-scale voltage

reference for both of the AUX DACs equal to the supply voltage

for the AUX DACs. The straight binary input codes are written

to the appropriate registers. If the Slave Mode register bit is

high, slave mode enabled, the AUX DAC(s) update will occur

when the appropriate update register is written to. Otherwise,

the update will occur at the conclusion of the data being written

to the register. Typical maximum settling time for the auxiliary

DAC is around 6 ms.

Initiating a conversion or retrieving data can also be accomplished

either through the standard Serial Port Interface by reading and

writing to the appropriate registers or through a dedicated

Auxiliary Serial Port Interface (AUX SPI). The AUX SPI can

be configured to allow fast access and control of either one of the

auxiliary ADCs and is available so that the SPI is not tied up

retrieving auxiliary ADC data.

The AUX SPI can be enabled and configured by setting register

AUX ADC CTRL. Setting register use pins high enables the

AUX SPI port. Setting register Sel BnotA low connects auxiliary

ADC A to the AUX SPI port, while setting it high connects

auxiliary ADC B to the AUX SPI port. As mentioned above,

setting the appropriate Select bit selects which of the multiplexed

input is connected to the auxiliary ADC.

Other optional controls include an invert register control and a

power down option. The invert register control, i.e., instead of

hexFF being high and hex00 being low, hex00 is high, and hexFF

will be minimum setting.

Sigma-Delta

A 12-bit sigma-delta (SD) output is available to provide an

additional control voltage. The SD control word is written to

Registers D42, 43; SD [11:4] are the 8 MSBs and SD [3:0] are

the 4 LSBs. The 12-bit word is processed by a sigma-delta

modulator and produces 1-bit data at an oversampled rate equal

to 1/8 of the receive ADC’s sampling rate (up to 8 MSPS). The

1-bit data then feeds a 1-bit DAC. The 1-bit DAC exhibits

perfect linearity. An external low-pass filter at the output should

be used to low-pass filter the pulse modulated data to produce a

linear output control voltage.

The AUX SPI consists of a chip select pin (AUX_SPI_csb),

a clock pin (AUX_SPI_clk), and a data output pin (AUX_SPI_do).

A conversion is initiated by pulsing the AUX_SPI_csb pin low.

When the conversion is complete, the data pin, AUX_SPI_do,

previously a logic low, will go high. At this point, the user supplies

an external clock, previously tied low, no data is present on the

first rising edge. The data output bit is updated on the falling

edge of the clock pulse and is settled and can be latched on the

next clock rising edge. The data arrives serially, MSB first. The

AUX SPI runs up to a rate of 16 MHz.

REV. 0

–31–

AD9860/AD9862

OUTLINE DIMENSIONS

128-Lead Plastic Quad Flatpack [LQFP]

(ST-128B)

Dimensions shown in millimeters

16.00 BSC

1.60

0.75

0.60

0.45

MAX

14.00 BSC

128

1

103

102

SEATING

PLANE

20.00

BSC

TOP VIEW

(PINS DOWN)

22.00

BSC

10ꢅ

6ꢅ

2ꢅ

1.45

1.40

1.35

0.20

0.09

VIEW A

7ꢅ

0ꢅ

38

39

65

64

SEATING

PLANE

0.08 MAX

COPLANARITY

0.27

0.22

0.17

0.50

BSC

VIEW A

ROTATED 90ꢅ CCW

COMPLIANT TO JEDEC STANDARDS MS-026BHB

–32–

REV. 0


型号：	AD9862BST
厂家：	ADI
描述：	Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications 混合信号前端（ MxFE⑩ ）处理器的宽带通信通信
文件：	总32页 (文件大小：588K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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