AD9859_17 [ADI]
CMOS Direct Digital Synthesizer;
| 型号： | AD9859_17 |
| 厂家： | 
ADI |
| 描述： | CMOS Direct Digital Synthesizer |
| 文件： | 总24页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
400 MSPS, 10-Bit, 1.8 V CMOS
Direct Digital Synthesizer
Data Sheet
AD9859
FEATURES
APPLICATIONS
400 MSPS internal clock speed
Integrated 10-bit DAC
32-bit tuning word
Phase noise ≤ –120 dBc/Hz at 1 kHz offset (DAC output)
Excellent dynamic performance
>75 dB SFDR at 160 MHz ( 100 kHz offset) AOUT
Serial input/output (I/O) control
1.8 V power supply
Software and hardware controlled power-down
48-lead TQFP/EP package
PLL REFCLK multiplier (4× to 20×)
Internal oscillator; can be driven by a single crystal
Phase modulation capability
Agile LO frequency synthesis
Programmable clock generators
Test and measurement equipment
Commercial and amateur radio exciter
GENERAL DESCRIPTION
The AD9859 is a direct digital synthesizer (DDS) featuring a
10-bit DAC operating at up to 400 MSPS. The AD9859 uses
advanced DDS technology, coupled with an internal high speed,
high performance DAC to form a digitally programmable,
complete high frequency synthesizer capable of generating a
frequency-agile analog output sinusoidal waveform at up to
200 MHz. The AD9859 is designed to provide fast frequency
hopping and fine tuning resolution (32-bit frequency tuning
word). The frequency tuning and control words are loaded into
the AD9859 via a serial I/O port.
Multichip synchronization
The AD9859 is specified to operate over the extended industrial
temperature range of –40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM
DDS CORE
AD9859
PHASE
ACCUMULATOR
DAC_R
PHASE
OFFSET
SET
–1
Z
IOUT
IOUT
32
19
10
COS(X)
DAC
14
SYSTEM
CLOCK
10
–1
Z
32
SYNC_IN
14
OSK
TIMING AND CONTROL LOGIC
I/O UPDATE
SYNC_CLK
PWRDWNCTL
0
M
U
X
SYNC
CONTROL REGISTERS
÷ 4
OSCILLATOR/BUFFER
M
U
X
SYSTEM
CLOCK
4–20
REFCLK
REFCLK
CLOCK
MULTIPLIER
ENABLE
CRYSTAL OUT
I/O PORT
RESET
Figure 1.
Rev. B
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Tel: 781.329.4700 ©2004–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9859
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 11
Component Blocks..................................................................... 11
Modes of Operation ................................................................... 16
Programming AD9859 Features .............................................. 16
Serial Port Operation................................................................. 19
Instruction Byte.......................................................................... 21
Serial Interface Port Pin Description....................................... 21
MSB/LSB Transfers .................................................................... 21
Suggested Application Circuits..................................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
AD9859—Electrical Specifications ................................................ 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration............................................................................. 6
Pin Function Descriptions .............................................................. 7
Typical Performance Characteristics ............................................. 8
REVISION HISTORY
1/2017—Rev. A to Rev. B
Change to Features Section ............................................................. 1
Changes to Ordering Guide .......................................................... 24
5/2009—Rev. 0 to Rev. A
Changes to Absolute Maximum Ratings Section......................... 5
Changes to Table 3............................................................................ 7
Changes to Table 5.......................................................................... 13
Changes to Figure 19...................................................................... 18
Changes to Figure 20...................................................................... 19
Changes to Serial Port Operation................................................. 19
Changes to Serial Interface Port Pin Description Section ........ 21
Changes to Figure 27...................................................................... 23
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 24
1/2004—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
AD9859
AD9859—ELECTRICAL SPECIFICATIONS
Unless otherwise noted, AVDD, DVDD = 1.8 V 5%, DVDD_I/O = 3.3 V 5%, RSET = 3.92 kΩ, External Reference Clock Frequency =
20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND.
Table 1.
Parameter
Temp
Min
Typ
Max
Unit
REF CLOCK INPUT CHARACTERISTICS
Frequency Range
REFCLK Multiplier Disabled
REFCLK Multiplier Enabled at 4×
REFCLK Multiplier Enabled at 20×
Input Capacitance
Input Impedance
Duty Cycle
FULL
FULL
FULL
25°C
25°C
25°C
25°C
FULL
1
20
4
400
100
20
MHz
MHz
MHz
pF
kΩ
%
3
1.5
50
Duty Cycle with REFCLK Multiplier Enabled
REFCLK Input Power1
35
–15
65
+3
%
dBm
0
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
10
10
Bits
mA
%FS
µA
LSB
LSB
pF
25°C
25°C
25°C
25°C
25°C
25°C
5
–10
15
+10
0.6
1
2
5
Integral Nonlinearity
Output Capacitance
Residual Phase Noise @ 1 kHz Offset, 40 MHz AOUT
REFCLK Multiplier Enabled @ 20×
REFCLK Multiplier Enabled @ 4×
REFCLK Multiplier Disabled
Voltage Compliance Range
Wideband SFDR
25°C
25°C
25°C
25°C
–105
–115
–132
dBc/Hz
dBc/Hz
dBc/Hz
V
AVDD – 0.5
AVDD + 0.5
1 MHz to 10 MHz Analog Out
10 MHz to 40 MHz Analog Out
40 MHz to 80 MHz Analog Out
80 MHz to 120 MHz Analog Out
120 MHz to 160 MHz Analog Out
Narrow-Band SFDR
25°C
25°C
25°C
25°C
25°C
64
63
61
55
50
dBc
dBc
dBc
dBc
dBc
40 MHz Analog Out ( 1 MHz)
40 MHz Analog Out ( 250 kHz)
40 MHz Analog Out ( 50 kHz)
40 MHz Analog Out ( 10 kHz)
80 MHz Analog Out ( 1 MHz)
80 MHz Analog Out ( 250 kHz)
80 MHz Analog Out ( 50 kHz)
80 MHz Analog Out ( 10 kHz)
120 MHz Analog Out ( 1 MHz)
120 MHz Analog Out ( 250 kHz)
120 MHz Analog Out ( 50 kHz)
120 MHz Analog Out ( 10 kHz)
160 MHz Analog Out ( 1 MHz)
160 MHz Analog Out ( 250 kHz)
160 MHz Analog Out ( 50 kHz)
160 MHz Analog Out ( 10 kHz)
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
82
82
94
87
82
84
87
87
80
82
86
89
80
82
84
86
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Rev. B | Page 3 of 24
AD9859
Data Sheet
Parameter
Temp
Min
Typ
25
2
Max
Unit
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
Mbps
ns
ns
ns
ns
ns
ns
ns
Minimum Clock Pulse Width Low
Minimum Clock Pulse Width High
Maximum Clock Rise/Fall Time
Minimum Data Setup Time DVDD_I/O = 3.3 V
Minimum Data Setup Time DVDD_I/O = 1.8 V
Minimum Data Hold Time
7
7
3
5
0
Maximum Data Valid Time
Wake-Up Time2
25
1
ms
Minimum Reset Pulse Width High
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE, SYNC_CLK Hold Time
Latency
5
4
6
0
SYSCLK Cycles3
ns
ns
ns
I/O UPDATE to Frequency Change Prop Delay
I/O UPDATE to Phase Offset Change Prop Delay
I/O UPDATE to Amplitude Change Prop Delay
25°C
25°C
25°C
24
24
16
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
CMOS LOGIC INPUTS
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 1 Current
25°C
25°C
25°C
25°C
25°C
25°C
25°C
1.25
2.2
V
V
V
V
µA
µA
pF
0.6
0.8
12
12
3
2
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V
Logic 1 Voltage
Logic 0 Voltage
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V
Logic 1 Voltage
Logic 0 Voltage
25°C
25°C
1.35
2.8
V
V
0.4
0.4
25°C
25°C
V
V
POWER CONSUMPTION (AVDD = DVDD = 1.8 V)
Single-Tone Mode
Rapid Power-Down Mode
25°C
25°C
25°C
162
150
20
171
160
27
mW
mW
mW
Full-Sleep Mode
SYNCHRONIZATION FUNCTION4
Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V)
Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V)
SYNC_CLK Alignment Resolution5
25°C
25°C
25°C
62.5
100
MHz
MHz
SYSCLK Cycles
1
1 To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude reduces the phase noise
performance of the device.
2 Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions of the AD9859 section). The longest time required is for the
reference clock multiplier PLL to relock to the reference. The wake-up time assumes that there is no capacitor on DACBP and that the recommended PLL loop filter
values are used.
3 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK
frequency is the same as the external reference clock frequency.
4 SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set.
5 This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock
edges are aligned, the synchronization function should not increase the skew between the two edges.
Rev. B | Page 4 of 24
Data Sheet
AD9859
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
Maximum Junction Temperature
DVDD_I/O (Pin 43)
AVDD, DVDD
Digital Input Voltage (DVDD_I/O = 3.3 V)
Digital Input Voltage (DVDD_I/O = 1.8 V)
Digital Output Current
Storage Temperature
Operating Temperature
Lead Temperature (10 sec Soldering)
θJA
150°C
4 V
2 V
–0.7 V to +5.25 V
–0.7 V to +2.2 V
5 mA
–65°C to +150°C
–40°C to +105°C
300°C
ESD CAUTION
38°C/W
θJC
15°C/W
DIGITAL
INPUTS
DAC OUTPUTS
DVDD_I/O
IOUT
IOUT
INPUT
AVOID OVERDRIVING
MUST TERMINATE
OUTPUTS TO AVDD. DO
NOT EXCEED THE
DIGITAL INPUTS.
FORWARD BIASING
ESD DIODES MAY
OUTPUT VOLTAGE
COUPLE DIGITAL NOISE
ONTO POWER PINS.
COMPLIANCE RATING.
Figure 2. Equivalent Input and Output Circuits
Rev. B | Page 5 of 24
AD9859
Data Sheet
PIN CONFIGURATION
48 47 46 45 44
42
40 39 38 37
43
41
I/O UPDATE
DVDD
1
2
3
4
5
6
7
8
9
RESET
PWRDWNCTL
DVDD
36
35
34
DGND
AVDD
DGND
33
32
31
30
29
AGND
AGND
AD9859
AVDD
AGND
TOP VIEW
(Not to Scale)
AGND
AGND
OSC/REFCLK
OSC/REFCLK
AVDD
AGND
28
27
26
CRYSTAL OUT 10
CLKMODESELECT 11
LOOP_FILTER
AVDD
AGND
AVDD
12
25
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3. 48-Lead TQFP/EP
Note that the exposed paddle on the bottom of the package forms an electrical connection for the DAC and must be attached to
analog ground. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or 3.3 V; however, the DVDD pins (Pin 2 and Pin 34) can
only be powered to 1.8 V.
Rev. B | Page 6 of 24
Data Sheet
AD9859
PIN FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions—48-Lead TQFP/EP
Pin No.
Mnemonic
I/O Description
1
I/O UPDATE
I
The rising edge transfers the contents of the internal buffer memory to the I/O registers. This
pin must be set up and held around the SYNC_CLK output signal.
2, 34
3, 33, 42, 47,
48
DVDD
DGND
I
I
Digital Power Supply Pins (1.8 V).
Digital Power Ground Pins.
4, 6, 13, 16, 18, AVDD
19, 25, 27, 29
5, 7, 14, 15, 17, AGND
22, 26, 28, 30,
31, 32
I
I
Analog Power Supply Pins (1.8 V).
Analog Power Ground Pins.
8
OSC/REFCLK
I
I
Complementary Reference Clock/Oscillator Input. When the REFCLK port is operated in single-
ended mode, REFCLKB should be decoupled to AVDD with a 0.1 µF capacitor.
Reference Clock/Oscillator Input. See the Clock Input section for details on the
OSCILLATOR/REFCLK operation.
9
OSC/REFCLK
10
11
CRYSTAL OUT
CLKMODESELECT
O
I
Output of the Oscillator Section.
Control Pin for the Oscillator Section. When high, the oscillator section is enabled. When low,
the oscillator section is bypassed.
12
LOOP_FILTER
I
This pin provides the connection for the external zero compensation network of the REFCLK
multiplier’s PLL loop filter. The network consists of a 1 kΩ resistor in series with a 0.1 µF
capacitor tied to AVDD.
20
21
23
24
IOUT
O
O
I
Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND.
DAC Output. Should be biased through a resistor to AVDD, not AGND.
DAC Band Gap Decoupling Pin. A 0.1 μF capacitor to AGND is recommended.
A resistor (3.92 kΩ nominal) connected from AGND to DAC_RSET establishes the reference
current for the DAC.
IOUT
DACBP
DAC_RSET
I
35
36
PWRDWNCTL
RESET
I
I
Input Pin Used as an External Power-Down Control (see Table 8 for details).
Active High Hardware Reset Pin. Asserting the RESET pin forces the AD9859 to the initial state,
as described in the I/O port register map.
37
38
IOSYNC
SDO
I
Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O
operation is immediately terminated, enabling a new I/O operation to commence once IOSYNC
is returned low. If unused, ground this pin; do not allow this pin to float.
When operating the I/O port as a 3-wire serial port, this pin serves as the serial data output.
When operated as a 2-wire serial port, this pin is unused and can be left unconnected.
O
39
40
41
CS
I
I
This pin functions as an active low chip select that allows multiple devices to share the I/O bus.
This pin functions as the serial data clock for I/O operations.
SCLK
SDIO
I/O When operating the I/O port as a 3-wire serial port, this pin serves as the serial data input only.
When operated as a 2-wire serial port, this pin is the bidirectional serial data pin.
43
44
DVDD_I/O
SYNC_IN
I
I
Digital Power Supply (for I/O Cells Only, 3.3 V).
Input Signal Used to Synchronize Multiple AD9859s. This input is connected to the SYNC_CLK
output of a master AD9859.
45
46
SYNC_CLK
OSK
O
I
Clock Output Pin Serves as a Synchronizer for External Hardware.
Input Pin Used to Control the Direction of the Shaped On-Off Keying Function when
Programmed for Operation. OSK is synchronous to the SYNC_CLK pin. When OSK is not
programmed, this pin should be tied to DGND.
<49>
AGND
I
The exposed paddle on the bottom of the package is a ground connection for the DAC and
must be attached to AGND in any board layout.
Rev. B | Page 7 of 24
AD9859
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
RBW
VBW
SWT
RBW
VBW
SWT
10kHz RF ATT 20dB
10kHz
10kHz RF ATT 20dB
10kHz
5s UNIT
dB
DELTA [T1]
–65.10dB
DELTA [T1]
–60.96dB
79.75951904MHz
REF LVL
–5dBm
REF LVL
–5dBm
5s UNIT
dB
98.19639279MHz
0
0
1
1
–10
–10
–20
–30
–20
–30
–40
–50
–60
–70
–40
–50
–60
–70
1
1
–80
–90
–80
–90
–100
–100
CENTER 100MHz
20MHz/
SPAN 200MHz
CENTER 100MHz
20MHz/
SPAN 200MHz
Figure 4. FOUT = 1 MHz FCLK = 400 MSPS, WBSFDR
Figure 7. FOUT = 80 MHz FCLK = 400 MSPS, WBSFDR
RBW
VBW
SWT
RBW
VBW
SWT
10kHz RF ATT 20dB
10kHz
10kHz RF ATT 20dB
10kHz
DELTA [T1]
–65.02dB
81.36272545MHz
DELTA [T1]
–55.04dB
43.28657315MHz
REF LVL
–5dBm
REF LVL
–8dBm
5s UNIT
dB
5s UNIT
dB
0
0
1
1
–10
–10
–20
–30
–20
–30
–40
–50
–60
–70
–40
–50
–60
–70
1
1
–80
–90
–80
–90
–100
–100
CENTER 100MHz
20MHz/
SPAN 200MHz
CENTER 100MHz
20MHz/
SPAN 200MHz
Figure 5. FOUT = 10 MHz, FCLK = 400 MSPS, WBSFDR
Figure 8 FOUT = 120 MHz, FCLK = 400 MSPS, WBSFDR
RBW
VBW
SWT
RBW
VBW
SWT
10kHz RF ATT 20dB
10kHz
10kHz RF ATT 20dB
10kHz
DELTA [T1]
–63.85dB
100.20040080MHz
DELTA [T1]
–50.48dB
–76.95390782MHz
REF LVL
–5dBm
REF LVL
–8dBm
5s UNIT
dB
5s UNIT
dB
0
0
1
1
–10
–10
–20
–30
–20
–30
–40
–50
–60
–70
–40
–50
–60
–70
1
1
–80
–90
–80
–90
–100
–100
CENTER 100MHz
20MHz/
SPAN 200MHz
CENTER 100MHz
20MHz/
SPAN 200MHz
Figure 6. FOUT = 40 MHz, FCLK = 400 MSPS, WBSFDR
Figure 9. FOUT = 160 MHz, FCLK = 400 MSPS, WBSFDR
Rev. B | Page 8 of 24
Data Sheet
AD9859
RBW
VBW
SWT
RBW
VBW
SWT
1kHz RF ATT 20dB
1kHz
1kHz RF ATT 20dB
1kHz
5s UNIT
dB
DELTA [T1]
–81.87dB
96.19238477kHz
DELTA [T1]
–81.71dB
–601.20240481kHz
REF LVL
–4dBm
0
REF LVL
–4dBm
5s UNIT
dB
0
1
1
–10
–10
–20
–30
–20
–30
–40
–50
–60
–70
–40
–50
–60
–70
–80
–90
–80
–90
1
1
–100
–100
CENTER 1.16MHz
200kHz/
SPAN 2MHz
CENTER 79.76MHz
200kHz/
SPAN 2MHz
Figure 10. FOUT = 1.1 MHz, FCLK = 400 MSPS, NBSFDR, 1 MHz
Figure 13. FOUT = 80.3 MHz, FCLK = 400 MSPS, NBSFDR, 1 MHz
RBW
VBW
SWT
RBW
VBW
SWT
1kHz RF ATT 20dB
1kHz
1kHz RF ATT 20dB
1kHz
DELTA [T1]
–89.33dB
–801.60320641kHz
DELTA [T1]
–80.37dB
–1.00200401MHz
REF LVL
–4dBm
REF LVL
–8dBm
5s UNIT
dB
5s UNIT
dB
0
0
1
1
–10
–10
–20
–30
–20
–30
–40
–50
–60
–70
–40
–50
–60
–70
1
–80
–90
–80
–90
1
–100
–100
CENTER 10MHz
200kHz/
SPAN 2MHz
CENTER 119.42MHz
200kHz/
SPAN 2MHz
Figure 11. FOUT = 10 MHz, FCLK = 400 MSPS, NBSFDR, 1 MHz
Figure 14. FOUT = 120.2 MHz, FCLK = 400 MSPS, NBSFDR, 1 MHz
RBW
VBW
SWT
1kHz RF ATT 20dB
1kHz
RBW
VBW
SWT
1kHz RF ATT
1kHz
5s UNIT
20dB
dB
DELTA [T1]
–84.92dB
997.99599198kHz
DELTA [T1]
–83.64dB
144.28857715kHz
REF LVL
–4dBm
REF LVL
–8dBm
5s UNIT
dB
0
0
1
1
–10
–10
–20
–30
–20
–30
–40
–50
–60
–70
–40
–50
–60
–70
–80
–90
–80
–90
1
1
–100
–100
CENTER 39.58MHz
200kHz/
SPAN 2MHz
CENTER 159.08MHz
200kHz/
SPAN 2MHz
Figure 12. FOUT = 39.9 MHz, FCLK = 400 MSPS, NBSFDR, 1 MHz
Figure 15. FOUT = 160 MHz, FCLK = 400 MSPS, NBSFDR, 1 MHz
Rev. B | Page 9 of 24
AD9859
Data Sheet
Figure 16. Residual Phase Noise with FOUT = 159.5 MHz, FCLK = 400 MSPS
(Green), 4 × 100 MSPS (Red), and 20 × 20 MSPS (Blue)
Figure 17. Residual Phase Noise with FOUT = 9.5 MHz, FCLK = 400 MSPS (Green),
4 ×100 MSPS (Red), and 20 × 20 MSPS (Blue)
Rev. B | Page 10 of 24
Data Sheet
AD9859
THEORY OF OPERATION
COMPONENT BLOCKS
DDS Core
Clock Input
The output frequency (fO) of the DDS is a function of the
frequency of the system clock (SYSCLK), the value of the
frequency tuning word (FTW), and the capacity of the
accumulator (232 in this case). The exact relationship is given
below with fS defined as the frequency of SYSCLK.
The AD9859 supports various clock methodologies. Support for
differential or single-ended input clocks and enabling of an
on-chip oscillator and/or a phase-locked loop (PLL) multiplier
are all controlled via user programmable bits. The AD9859 may
be configured in one of six operating modes to generate the system
clock. The modes are configured using the CLKMODESELECT
pin, CFR1<4>, and CFR2<7:3>. Connecting the external pin
CLKMODESELECT to Logic High enables the on-chip crystal
oscillator circuit. With the on-chip oscillator enabled, users of
the AD9859 connect an external crystal to the REFCLK and
REFCLKB inputs to produce a low frequency reference clock in
the range of 20 MHz to 30 MHz. The signal generated by the
oscillator is buffered before it is delivered to the rest of the chip.
This buffered signal is available via the CRYSTAL OUT pin. Bit
CFR1<4> can be used to enable or disable the buffer, turning on
or off the system clock. The oscillator itself is not powered
down in order to avoid long startup times associated with
turning on a crystal oscillator. Writing CFR2<9> to Logic High
enables the crystal oscillator output buffer. Logic Low at
CFR2<9> disables the oscillator output buffer.
fO
fO = fS ×
= FTW fS
( )( )
/232 with 0 ≤ FTW ≤ 231
1–
FTW /232 with 231 < FTW < 232 –1
The value at the output of the phase accumulator is translated to
an amplitude value via the COS(x) functional block and routed
to the DAC.
In certain applications, it is desirable to force the output signal
to zero phase. Simply setting the FTW to 0 does not accomplish
this; it only results in the DDS core holding its current phase
value. Thus, a control bit is required to force the phase accumula-
tor output to zero.
At power-up, the clear phase accumulator bit is set to Logic 1,
but the buffer memory for this bit is cleared (Logic 0). There-
fore, upon power-up, the phase accumulator remains clear until
the first I/O UPDATE is issued.
Connecting CLKMODESELECT to Logic Low disables the
on-chip oscillator and the oscillator output buffer. With the
oscillator disabled, an external oscillator must provide the
REFCLK and/or REFCLKB signals. For differential operation,
these pins are driven with complementary signals. For single-
ended operation, a 0.1 µF capacitor should be connected
between the unused pin and the analog power supply. With the
capacitor in place, the clock input pin bias voltage is 1.35 V. In
addition, the PLL may be used to multiply the reference
frequency by an integer value in the range of 4 to 20. Table 4
summarizes the clock modes of operation. Note that the PLL
multiplier is controlled via the CFR2<7:3> bits, independent of
the CFR1<4> bit.
Phase-Locked Loop (PLL)
The PLL allows multiplication of the REFCLK frequency.
Control of the PLL is accomplished by programming the 5-bit
REFCLK multiplier portion of Control Function Register No. 2,
Bits <7:3>.
When programmed for values ranging from 0x04 to 0x14
(4 decimal to 20 decimal), the PLL multiplies the REFCLK
input frequency by the corresponding decimal value. However,
the maximum output frequency of the PLL is restricted to
400 MHz. Whenever the PLL value is changed, the user should
be aware that time must be allocated to allow the PLL to lock
(approximately 1 ms).
The PLL is bypassed by programming a value outside the range
of 4 to 20 (decimal). When bypassed, the PLL is shut down to
conserve power.
Table 4. Clock Input Modes of Operation
CFR1<4>
CLKMODESELECT
CFR2<7:3>
3 < M < 21
M < 4 or M > 20
3 < M < 21
M < 4 or M > 20
X
Oscillator Enabled?
System Clock
FCLK = FOSC × M
FCLK = FOSC
FCLK = FOSC × M
FCLK = FOSC
Frequency Range (MHz)
80 < FCLK < 400
20 < FCLK < 30
80 < FCLK < 400
10 < FCLK < 400
N/A
Low
Low
Low
Low
High
High
Low
Low
X
Yes
Yes
No
No
No
High
FCLK = 0
Rev. B | Page 11 of 24
AD9859
Data Sheet
DAC Output
Serial I/O Port
The AD9859 incorporates an integrated 10-bit current output
DAC. Unlike most DACs, this output is referenced to AVDD,
not AGND.
The AD9859 serial port is a flexible, synchronous serial
communications port that allows easy interface to many industry-
standard microcontrollers and microprocessors. The serial I/O port
is compatible with most synchronous transfer formats, including
both the Motorola 6905/11 SPI® and Intel® 8051 SSR protocols.
Two complementary outputs provide a combined full-scale
output current (IOUT). Differential outputs reduce the amount of
common-mode noise that might be present at the DAC output,
offering the advantage of an increased signal-to-noise ratio. The
The interface allows read/write access to all registers that configure
the AD9859. MSB first or LSB first transfer formats are supported.
The AD9859’s serial interface port can be configured as a single pin
I/O (SDIO), which allows a 2-wire interface or two unidirectional
pins for in/out (SDIO/SDO), which in turn enables a 3-wire
full-scale current is controlled by an external resistor (RSET
)
connected between the DAC_RSET pin and the DAC ground
(AGND_DAC). The full-scale current is proportional to the
resistor value as follows:
interface. Two optional pins, IOSYNC and , enable greater
CS
flexibility for system design in the AD9859.
Register Map and Descriptions
The register map is listed in Table 5.
RSET = 39.19/IOUT
The maximum full-scale output current of the combined DAC
outputs is 15 mA, but limiting the output to 10 mA provides the
best spurious-free dynamic range (SFDR) performance. The DAC
output compliance range is AVDD + 0.5 V to AVDD – 0.5 V.
Voltages developed beyond this range cause excessive DAC
distortion and could potentially damage the DAC output circui-
try. Proper attention should be paid to the load termination to
keep the output voltage within this compliance range.
Rev. B | Page 12 of 24
Data Sheet
AD9859
Table 5. Register Map
Register
Name
(Serial
Bit
Range
(MSB)
Bit 7
(LSB)
Bit 0
Default
Value
0x00
Address)
Bit 6
Bit 5
DAC
Power-
Down
Bit 4
Bit 3
Bit 2
Bit 1
External
Power-
Down
Digital
Power-
Down
Clock Input
Power-
SYNC_CLK
Out
Disable
Not
Used
<7:0>
Not Used
Not Used
Down
Mode
Control
Function
Register
No.1
(CFR1)
(0x00)
AutoClr
Phase
Accum
Clear
Phase
Accum.
SDIO
Input
Only
0x00
Enable SINE
Output
<15:8>
<23:16>
<31:24>
<7:0>
Not Used
Not Used
Not Used
LSB First
Automatic
Sync
Enable
Software
Manual
Sync
0x00
0x00
0x00
Not Used
Auto
OSK
Keying
Load ARR
@ I/O UD
OSK
Enable
Not Used
REFCLK Multiplier
0x00 or 0x01, or 0x02 or 0x03: Bypass Multiplier
0x04 to 0x14: 4× to 20× Multiplication
VCO
Range
Charge Pump Current
<1:0>
Control
Function
Register No.
2 (CFR2)
(0x01)
High
Speed
Sync
Hardware
Manual
Sync
0x00
CRYSTAL
Not
<15:8>
Not Used
OUT Pin
Used
Active
Enable
Enable
<23:16>
<7:0>
Not Used
Amplitude Scale Factor Register <7:0>
0x18
0x00
0x00
Amplitude
Scale Factor
(ASF)
Auto Ramp Rate Speed
Control <1:0>
<15:8>
Amplitude Scale Factor Register <13:8>
(0x02)
Amplitude
Ramp Rate
(ARR)
0x00
<7:0>
Amplitude Ramp Rate Register <7:0>
(0x03)
Frequency
Tuning
Word
(FTW0)
(0x04)
<7:0>
Frequency Tuning Word No. 0 <7:0>
Frequency Tuning Word No. 0 <15:8>
Frequency Tuning Word No. 0 <23:16>
0x00
0x00
0x00
0x00
<15:8>
<23:16>
<31:24>
<7:0>
Frequency Tuning Word No. 0 <31:24>
Phase Offset Word No. 0 <7:0>
Phase
0x00
0x00
Offset Word
(POW0)
(0x05)
<15:8>
Not Used<1:0>
Phase Offset Word No. 0 <13:8>
Rev. B | Page 13 of 24
AD9859
Data Sheet
Control Register Bit Descriptions
Control Function Register No. 1 (CFR1)
CFR1<22> = 1. The software controlled manual synchroniza-
tion feature is executed. The SYNC_CLK rising edge is
advanced by one SYNC_CLK cycle and this bit is cleared. To
advance the rising edge multiple times, this bit needs to be set
for each advance. See the Synchronizing Multiple AD9859s
section for details.
The CFR1 is used to control the various functions, features,
and modes of the AD9859. The functionality of each bit is
detailed below.
CFR1<31:27>: Not Used
CFR1<26>: Amplitude Ramp Rate Load Control Bit
CFR1<21:14>: Not Used
CFR1<26> = 0 (default). The amplitude ramp rate timer is
loaded only upon timeout (timer == 1) and is not loaded due to
an I/O UPDATE input signal.
CFR1<13>: Auto-Clear Phase Accumulator Bit
CFR1<13> = 0 (default), the current state of the phase accumula-
tor remains unchanged when the frequency tuning word is
applied.
CFR1<26> = 1. The amplitude ramp rate timer is loaded upon
timeout (timer == 1) or at the time of an I/O UPDATE input signal.
CFR1<13> = 1. This bit automatically synchronously clears
(loads 0s into) the phase accumulator for one cycle upon
receiving an I/O UPDATE signal.
CFR1<25>: Shaped On-Off Keying Enable Bit
CFR1<25> = 0 (default). Shaped on-off keying is bypassed.
CFR1<12>: Sine/Cosine Select Bit
CFR1<25> = 1. Shaped on-off keying is enabled. When enabled,
CFR1<24> controls the mode of operation for this function.
CFR1<12> = 0 (default). The angle-to-amplitude conversion
logic employs a COSINE function.
CFR1<24>: Auto Shaped On-Off Keying Enable Bit (Only Valid
when CFR1<25> Is Active High)
CFR1<12> = 1. The angle-to-amplitude conversion logic
employs a SINE function.
CFR1<24> = 0 (default). When CFR1<25> is active, a Logic 0
on CFR1<24> enables the manual shaped on-off keying
operation. Each amplitude sample sent to the DAC is multiplied
by the amplitude scale factor. See the Shaped On-Off Keying
section for details.
CFR1<11>: Not Used
CFR1<10>: Clear Phase Accumulator
CFR1<10> = 0 (default). The phase accumulator functions as
normal.
CFR1<24> = 1. When CFR1<25> is active, a Logic 1 on
CFR1<24> enables the auto shaped on-off keying operation.
Toggling the OSK pin high causes the output scalar to ramp up
from zero scale to the amplitude scale factor at a rate deter-
mined by the amplitude ramp rate. Toggling the OSK pin low
causes the output to ramp down from the amplitude scale factor
to zero scale at the amplitude ramp rate. See the Shaped On-Off
Keying section for details.
CFR1<10> = 1. The phase accumulator memory elements are
cleared and held clear until this bit is cleared.
CFR1<9>: SDIO Input Only
CFR1<9> = 0 (default). The SDIO pin has bidirectional
operation (2-wire serial programming mode).
CFR1<9> = 1. The serial data I/O pin (SDIO) is configured as
an input-only pin (3-wire serial programming mode).
CFR1<23>: Automatic Synchronization Enable Bit
CFR1<8>: LSB First
CFR1<23> = 0 (default). The automatic synchronization feature
of multiple AD9859s is inactive.
CFR1<8> = 0 (default). MSB first format is active.
CFR1<8> = 1. The serial interface accepts serial data in LSB
first format.
CFR1<23> = 1. The automatic synchronization feature of mul-
tiple AD9859s is active. The device synchronizes its internal
synchronization clock (SYNC_CLK) to align to the signal
present on the SYNC_IN input. See the Synchronizing Multiple
AD9859s section for details.
CFR1<7>: Digital Power-Down Bit
CFR1<7> = 0 (default). All digital functions and clocks are active.
CFR1<7> = 1. All non-IO digital functionality is suspended,
lowering the power significantly.
CFR1<22>: Software Manual Synchronization of Multiple
AD9859s
CFR1<22> = 0 (default). The manual synchronization feature is
inactive.
Rev. B | Page 14 of 24
Data Sheet
AD9859
CFR1<6>: Not Used
CFR2<11> = 1. The high speed sync enhancement is on. This
bit should be set when attempting to use the auto-synchronization
feature for SYNC_CLK inputs beyond 50 MHz, (200 MSPS
SYSCLK). See the Synchronizing Multiple AD9859s section
for details.
CFR1<5>: DAC Power-Down Bit
CFR1<5> = 0 (default). The DAC is enabled for operation.
CFR1<5> = 1. The DAC is disabled and is in its lowest power
dissipation state.
CFR2<10>: Hardware Manual Sync Enable Bit
CFR1<4>: Clock Input Power-Down Bit
CFR2<10> = 0 (default). The hardware manual sync function is off.
CFR1<4> = 0 (default). The clock input circuitry is enabled for
operation.
CFR2<10> = 1. The hardware manual sync function is enabled.
While this bit is set, a rising edge on the SYNC_IN pin causes
the device to advance the SYNC_CLK rising edge by one REFCLK
cycle. Unlike the software manual sync enable bit, this bit does
not self-clear. Once the hardware manual sync mode is enabled,
it stays enabled until this bit is cleared. See the Synchronizing
Multiple AD9859s section for details.
CFR1<4> = 1. The clock input circuitry is disabled, and the
device is in its lowest power dissipation state.
CFR1<3>: External Power-Down Mode
CFR1<3> = 0 (default). The external power-down mode
selected is the rapid recovery power-down mode. In this mode,
when the PWRDWNCTL input pin is high, the digital logic
and the DAC digital logic are powered down. The DAC bias
circuitry, PLL, oscillator, and clock input circuitry are not
powered down.
CFR2<9>: CRYSTAL OUT Enable Bit
CFR2<9> = 0 (default). The CRYSTAL OUT pin is inactive.
CFR2<9> = 1. The CRYSTAL OUT pin is active. When active,
the crystal oscillator circuitry output drives the CRYSTAL OUT
pin, which can be connected to other devices to produce a
reference frequency. The oscillator responds to crystals in the
range of 20 MHz to 30 MHz.
CFR1<3> = 1. The external power-down mode selected is the
full power-down mode. In this mode, when the PWRDWNCTL
input pin is high, all functions are powered down. This includes
the DAC and PLL, which take a significant amount of time to
power up.
CFR2<8>: Not Used
CFR2<7:3>: Reference Clock Multiplier Control Bits
CFR1<2>: Not Used
This 5-bit word controls the multiplier value out of the clock-
multiplier (PLL) block. Valid values are decimal 4 to 20 (0x04 to
0x14). Values entered outside this range bypass the clock
multiplier. See the Phase-Locked Loop (PLL) section for details.
CFR1<1>: SYNC_CLK Disable Bit
CFR1<1> = 0 (default). The SYNC_CLK pin is active.
CFR1<1> = 1. The SYNC_CLK pin assumes a static Logic 0
state to keep noise generated by the digital circuitry at a
minimum. However, the synchronization circuitry remains
active (internally) to maintain normal device timing.
CFR2<2>: VCO Range Control Bit
This bit is used to control the range setting on the VCO.
When CFR2<2> == 0 (default), the VCO operates in a range of
100 MHz to 250 MHz. When CFR2<2> == 1, the VCO operates
in a range of 250 MHz to 400 MHz.
CFR1<0>: Not Used, Leave at 0
Control Function Register No. 2 (CFR2)
CFR2<1:0>: Charge Pump Current Control Bits
The CFR2 is used to control the various functions, features, and
modes of the AD9859, primarily related to the analog sections
of the chip.
These bits are used to control the current setting on the charge
pump. The default setting, CFR2<1:0>, sets the charge pump
current to the default value of 75 µA. For each bit added (01, 10,
11), 25 µA of current is added to the charge pump current:
100 µA, 125 µA, and 150 µA.
CFR2<23:12>: Not Used
CFR2<11>: High Speed Sync Enable Bit
CFR2<11> = 0 (default). The high speed sync enhancement is off.
Rev. B | Page 15 of 24
AD9859
Data Sheet
Other Register Descriptions
The second method of phase control is where the user regularly
updates the phase offset register via the I/O port. By properly
modifying the phase offset as a function of time, the user can
implement a phase modulated output signal. However, both the
speed of the I/O port and the frequency of SYSCLK limit the
rate at which phase modulation can be performed.
Amplitude Scale Factor (ASF)
The ASF register stores the 2-bit auto ramp rate speed value
and the 10-bit amplitude scale factor used in the output shaped
keying (OSK) operation. In auto OSK operation, ASF <15:14>
tells the OSK block how many amplitude steps to take for each
increment or decrement. ASF<13:0> sets the maximum value
achievable by the OSK internal multiplier. In manual OSK
mode, ASF<15:14> has no effect. ASF <13:0> provide the
output scale factor directly. If the OSK enable bit is cleared,
CFR1<25> = 0, this register has no effect on device operation.
The AD9859 allows a programmable continuous zeroing of the
phase accumulator as well as a clear and release or automatic
zeroing function. Each feature is individually controlled via the
CFR1 bits. CFR1<13> is the automatic clear phase accumulator
bit. CFR1<10> clears the phase accumulator and holds the value
to zero.
Amplitude Ramp Rate (ARR)
Continuous Clear Bit
The ARR register stores the 8-bit amplitude ramp rate used in
the auto OSK mode. This register programs the rate at which
the amplitude scale factor counter increments or decrements. If
the OSK is set to manual mode, or if OSK enable is cleared, this
register has no effect on device operation.
The continuous clear bit is simply a static control signal that,
when active high, holds the phase accumulator at zero for the
entire time the bit is active. When the bit goes low, inactive, the
phase accumulator is allowed to operate.
Clear and Release Function
Frequency Tuning Word 0 (FTW0)
When set, the auto-clear phase accumulator clears and releases
the phase accumulator upon receiving an I/O UPDATE. The
automatic clearing function is repeated for every subsequent
I/O UPDATE until the appropriate auto-clear control bit is
cleared.
The frequency tuning word is a 32-bit register that controls the
rate of accumulation in the phase accumulator of the DDS core.
Its specific role is dependent on the device mode of operation.
Phase Offset Word (POW)
The phase offset word is a 14-bit register that stores a phase
offset value. This offset value is added to the output of the phase
accumulator to offset the current phase of the output signal. The
exact value of phase offset is given by the following formula:
Shaped On-Off Keying
The shaped on-off keying function of the AD9859 allows the
user to control the ramp-up and ramp-down time of an on-off
emission from the DAC. This function is used in burst transmis-
sions of digital data to reduce the adverse spectral impact of
short, abrupt bursts of data.
POW
Φ =
×360°
214
Auto and manual shaped on-off keying modes are supported.
The auto mode generates a linear scale factor at a rate
determined by the amplitude ramp rate (ARR) register
controlled by an external pin (OSK). Manual mode allows the
user to directly control the output amplitude by writing the
scale factor value into the amplitude scale factor (ASF) register.
MODES OF OPERATION
Single-Tone Mode
In single-tone mode, the DDS core uses a single tuning word.
Whatever value is stored in FTW0 is supplied to the phase
accumulator. This value can only be changed manually, which is
done by writing a new value to FTW0 and by issuing an I/O
UPDATE. Phase adjustment is possible through the phase
offset register.
The shaped on-off keying function may be bypassed (disabled)
by clearing the OSK enable bit (CFR1<25> = 0).
The modes are controlled by two bits located in the most signifi-
cant byte of the control function register (CFR). CFR1<25> is
the shaped on-off keying enable bit. When CFR1<25> is set, the
output scaling function is enabled and CFR1<25> bypasses the
function. CFR1<24> is the internal shaped on-off keying active
bit. When CFR1<24> is set, internal shaped on-off keying mode
is active; CFR1<24> is cleared, external shaped on-off keying
mode is active. CFR1<24> is a Don’t Care if the shaped
PROGRAMMING AD9859 FEATURES
Phase Offset Control
A 14-bit phase offset (θ) may be added to the output of the phase
accumulator by means of the control registers. This feature
provides the user with two different methods of phase control.
The first method is a static phase adjustment, where a fixed
phase offset is loaded into the appropriate phase offset register
and left unchanged. The result is that the output signal is offset
by a constant angle relative to the nominal signal. This allows
the user to phase align the DDS output with some external
signal, if necessary.
on-off keying enable bit (CFR1<25>) is cleared. The power-up
condition is shaped on-off keying disabled (CFR1<25> = 0).
Figure 18 shows the block diagram of the OSK circuitry.
Rev. B | Page 16 of 24
Data Sheet
AD9859
AUTO Shaped On-Off Keying Mode Operation
OSK Ramp Rate Timer
The auto-shaped on-off keying mode is active when CFR1<25>
and CFR1<24> are set. When auto-shaped on-off keying mode
is enabled, a single scale factor is internally generated and
applied to the multiplier input for scaling the output of the DDS
core block (see Figure 18). The scale factor is the output of a
10-bit counter that increments/decrements at a rate determined
by the contents of the 8-bit output ramp rate register. The scale
factor increases if the OSK pin is high and decreases if the OSK
pin is low. The scale factor is an unsigned value such that all 0s
multiply the DDS core output by 0 (decimal) and 0x3FFF multip-
lies the DDS core output by 16383 (decimal).
The OSK ramp rate timer is a loadable down-counter, which
generates the clock signal to the 10-bit counter that generates
the internal scale factor. The ramp rate timer is loaded with the
value of the ASFR every time the counter reaches 1 (decimal).
This load and countdown operation continues for as long as the
timer is enabled, unless the timer is forced to load before
reaching a count of 1.
If the load OSK timer bit (CFR1<26>) is set, the ramp rate
timer is loaded upon an I/O UPDATE or upon reaching a value
of 1. The ramp timer can be loaded before reaching a count of 1
by three methods.
For users who use the full amplitude (10-bits) but need fast
ramp rates, the internally generated scale factor step size
is controlled via the ASF<15:14> bits. Table 6 describes the
increment/decrement step size of the internally generated scale
factor per the ASF<15:14> bits.
Method one is by changing the OSK input pin. When the OSK
input pin changes state, the ASFR value is loaded into the ramp
rate timer, which then proceeds to count down as normal.
The second method in which the sweep ramp rate timer can be
loaded before reaching a count of 1 is if the load OSK timer bit
(CFR1<26>) is set and an I/O UPDATE is issued.
A special feature of this mode is that the maximum output
amplitude allowed is limited by the contents of the amplitude
scale factor register. This allows the user to ramp to a value less
than full scale.
The last method in which the sweep ramp rate timer can be
loaded before reaching a count of 1 is when going from the
inactive auto-shaped on-off keying mode to the active auto-
shaped on-off keying mode; that is, when the sweep enable bit is
being set.
Table 6. Auto-Scale Factor Internal Step Size
ASF<15:14> (Binary)
Increment/Decrement Size
00
01
10
11
1
2
4
8
DDS CORE
AUTO DESK
ENABLE
CFR1<24>
TO DAC
COS(X)
OSK ENABLE
CFR<25>
SYNC_CLK
LOAD OSK TIMER
CFR1<26>
0
1
OSK PIN
AMPLITUDE RAMP
RATE REGISTER
(ASF)
AMPLITUDE SCALE
FACTOR REGISTER
(ASF)
0
HOLD
UP/DN
OUT
LOAD DATA
EN
INC/DEC ENABLE
CLOCK
RAMP RATE TIMER
AUTO SCALE
FACTOR GENERATOR
Figure 18. On-Off Shaped Keying, Block Diagram
Rev. B | Page 17 of 24
AD9859
Data Sheet
External Shaped On-Off Keying Mode Operation
contents into the control registers of the device. The combina-
tion of the SYNC_CLK and I/O UPDATE pins provides the
user with constant latency relative to SYSCLK, and also ensures
phase continuity of the analog output signal when a new tuning
word or phase offset value is asserted. Figure 19 demonstrates
an I/O UPDATE timing cycle and synchronization.
The external shaped on-off keying mode is enabled by writing
CFR1<25> to a Logic 1 and writing CFR1<24> to a Logic 0.
When configured for external shaped on-off keying, the
content of the ASFR becomes the scale factor for the data path.
The scale factors are synchronized to SYNC_CLK via the
I/O UPDATE functionality.
Notes on synchronization logic:
Synchronization; Register Updates (I/O UPDATE)
•
The I/O UPDATE signal is edge detected to generate a
single rising edge clock signal that drives the register bank
flops. The I/O UPDATE signal has no constraints on duty
cycle. The minimum low time on I/O UPDATE is one
SYNC_CLK clock cycle.
The I/O UPDATE pin is set up and held around the rising
edge of SYNC_CLK and has zero hold time and 4 ns setup
time.
Functionality of the SYNC_CLK and I/O UPDATE
Data into the AD9859 is synchronous to the SYNC_CLK signal
(supplied externally to the user on the SYNC_CLK pin). The
I/O UPDATE pin is sampled on the rising edge of the
SYNC_CLK.
•
Internally, SYSCLK is fed to a divide-by-4 frequency divider to
produce the SYNC_CLK signal. The SYNC_CLK signal is
provided to the user on the SYNC_CLK pin. This enables
synchronization of external hardware with the device’s internal
clocks. This is accomplished by forcing any external hardware
to obtain its timing from SYNC_CLK. The I/O UPDATE signal
coupled with SYNC_CLK is used to transfer internal buffer
SYNC_CLK
DISABLE
0
SYSCLK
÷ 4
OSK
I/O UPDATE
D
Q
D
D
Q
Q
EDGE
DETECTION
LOGIC
TO CORE LOGIC
SYNC_CLK
GATING
SCLK
SDI
CS
REGISTER
MEMORY
I/O BUFFER
LATCHES
Figure 19. I/O Synchronization Block Diagram
Rev. B | Page 18 of 24
Data Sheet
AD9859
SYSCLK
A
B
A
B
SYNC_CLK
I/O UPDATE
DATA IN
I/O BUFFERS
DATA 1
DATA 2
DATA 3
DATA IN
REGISTERS
DATA 0
DATA 1
DATA 2
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE I/O BUFFERS AT POINT B.
Figure 20. I/O Synchronization Timing Diagram
Synchronizing Multiple AD9859s
The AD9859 allows easy synchronization of multiple AD9859s.
There are three modes of synchronization available to the user:
an automatic synchronization mode, a software controlled
manual synchronization mode, and a hardware controlled
manual synchronization mode. In all cases, when a user wants
to synchronize two or more devices, the following considera-
tions must be observed. First, all units must share a common
clock source. Trace lengths and path impedance of the clock
tree must be designed to keep the phase delay of the different
clock branches as closely matched as possible. Second, the I/O
UPDATE signal’s rising edge must be provided synchronously
to all devices in the system. Finally, regardless of the internal
synchronization method used, the DVDD_I/O supply should
be set to 3.3 V for all devices that are to be synchronized.
AVDD and DVDD should be left at 1.8 V.
In hardware manual synchronization mode, the SYNC_IN
input pin is configured such that it advances the rising edge of
the SYNC_CLK signal each time the device detects a rising edge
on the SYNC_IN pin. To put the device into hardware manual
synchronization mode, set the hardware manual synchronization
bit (CFR2<10> = 1). Unlike the software manual synchroniza-
tion bit, this bit does not self-clear. Once the hardware manual
synchronization mode is enabled, all rising edges detected on
the SYNC_IN input cause the device to advance the rising edge
of the SYNC_CLK by one SYSCLK cycle until this enable bit is
cleared (CFR2<10> = 0).
Using a Single Crystal to Drive Multiple AD9859 Clock
Inputs
The AD9859 crystal oscillator output signal is available on the
CRYSTAL OUT pin, enabling one crystal to drive multiple
AD9859s. In order to drive multiple AD9859s with one crystal,
the CRYSTAL OUT pin of the AD9859 using the external crystal
should be connected to the REFCLK input of the other AD9859.
In automatic synchronization mode, one device is chosen as a
master; the other device(s) is slaved to this master. When
configured in this mode, the slaves automatically synchronize
their internal clocks to the SYNC_CLK output signal of the
master device. To enter automatic synchronization mode, set
the slave device’s automatic synchronization bit (CFR1<23> = 1).
Connect the SYNC_IN input(s) to the master SYNC_CLK
output. The slave device continuously updates the phase
relationship of its SYNC_CLK until it is in phase with the
SYNC_IN input, which is the SYNC_CLK of the master device.
When attempting to synchronize devices running at SYSCLK
speeds beyond 250 MSPS, the high speed sync enhancement
enable bit should be set (CFR2<11> = 1).
The CRYSTAL OUT pin is static until the CFR2<9> bit is set,
enabling the output. The drive strength of the CRYSTAL OUT
pin is typically very low, so this signal should be buffered prior
to using it to drive any loads.
SERIAL PORT OPERATION
With the AD9859, the instruction byte specifies read/write
operation and register address. Serial operations on the AD9859
occur only at the register level, not the byte level. For the
AD9859, the serial port controller recognizes the instruction
byte register address and automatically generates the proper
register byte address. In addition, the controller expects that all
bytes of that register will be accessed. It is a required that all
bytes of a register be accessed during serial I/O operations,
with one exception. The IOSYNC function can be used to
abort an I/O operation, thereby allowing less than all bytes
to be accessed.
In software manual synchronization mode, the user forces the
device to advance the SYNC_CLK rising edge one SYSCLK
cycle (1/4 SYNC_CLK period). To activate the manual
synchronization mode, set the slave device’s software manual
synchronization bit (CFR1<22> = 1). The bit (CFR1<22>) is
cleared immediately. To advance the rising edge of the SYNC_CLK
multiple times, this bit needs to be set multiple times.
Rev. B | Page 19 of 24
AD9859
Data Sheet
There are two phases to a communication cycle with the
AD9859. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9859, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9859 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming data
transfer is read or write and the serial address of the register
being accessed.
during Phase 2 of the communication cycle is a function of the
register being accessed. For example, when accessing the Control
Function Register 2, which is three bytes wide, Phase 2 requires that
three bytes be transferred. If accessing the frequency tuning word,
which is four bytes wide, Phase 2 requires that four bytes be
transferred. After transferring all data bytes per the instruction,
the communication cycle is completed.
At the completion of any communication cycle, the AD9859
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9859 is registered on the rising edge of
SCLK. All data is driven out of the AD9859 on the falling edge
of SCLK. Figure 21 through Figure 24 are useful in understand-
ing the general operation of the AD9859 serial port.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9859. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9859
and the system controller. The number of bytes transferred
INSTRUCTION CYCLE
CS
DATA TRANSFER CYCLE
SCLK
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
0
SDIO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
Figure 21. Serial Port Write Timing—Clock Stall Low
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
I
I
I
I
I
I
I
I
0
DON'T CARE
SDIO
SDO
7
6
5
4
3
2
1
D
D
D
D
D
D
D
D
O 0
O 7
O 6
O 5
O 4
O 3
O 2
O 1
Figure 22. 3-Wire Serial Port Read Timing—Clock Stall Low
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
0
SDIO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
Figure 23. Serial Port Write Timing—Clock Stall High
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
SDIO
7
6
5
4
3
2
1
0
O 7
O 6
O 5
O 4
O 3
O 2
O 1 O 0
Figure 24. 2-Wire Serial Port Read Timing—Clock Stall High
Rev. B | Page 20 of 24
Data Sheet
AD9859
INSTRUCTION BYTE
The instruction byte contains the following information:
Table 7.
MSB
D6
D5
D4
D3
D2
D1
LSB
A0
W
X
X
A4
A3
A2
A1
R/
W
written in the format indicated by Control Register 0x00 <8>. If
the AD9859 is in LSB first mode, the instruction byte must be
written from least significant bit to most significant bit.
R/ —Bit 7 of the instruction byte determines whether a read
or write data transfer occurs after the instruction byte write.
Logic High indicates read operation. Logic 0 indicates a write
operation.
For MSB first operation, the serial port controller generates the
most significant byte (of the specified register) address first
followed by the next lesser significant byte addresses until the
I/O operation is complete. All data written to (read from) the
AD9859 must be (is) in MSB first order. If the LSB mode is
active, the serial port controller generates the least significant
byte address first followed by the next greater significant byte
addresses until the I/O operation is complete. All data written to
(read from) the AD9859 must be (is) in LSB first order.
X, X—Bits 6 and 5 of the instruction byte are Don’t Cares.
A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte
determine which register is accessed during the data transfer
portion of the communications cycle.
SERIAL INTERFACE PORT PIN DESCRIPTION
SCLK—Serial Clock. The serial clock pin is used to synchronize
data to and from the AD9859 and to run the internal state
machines. SCLK maximum frequency is 25 MHz.
Example Operation
CSB—Chip Select Bar. CSB is active low input that allows more
than one device on the same serial communications line. The
SDO and SDIO pins go to a high impedance state when this
input is high. If driven high during any communications cycle,
To write the amplitude scale factor register in MSB first format,
apply an instruction byte of 0x02 [serial address is 00010(b)].
From this instruction, the internal controller knows to use the
first byte as the most significant byte. The first two bits are
recorded as the auto ramp rate speed control bits, and the next
six bits are the most significant bits of the amplitude scale
factor. The second byte is applied as the eight less significant
bits of the amplitude scale factor ASF<7:0>.
CS
that cycle is suspended until
is reactivated low. Chip select
can be tied low in systems that maintain control of SCLK.
SDIO—Serial Data I/O. Data is always written to the AD9859
on this pin. However, this pin can be used as a bidirectional
data line. Bit 9 of Register Address 0x00 controls the
configuration of this pin. The default is Logic 0, which
configures the SDIO pin as bidirectional.
To write the amplitude scale factor register in LSB first format,
assuming the control register has already been set for LSB first
format, apply an instruction byte of 0x40. From this instruction,
the internal controller knows to use the first byte as the least
significant byte of the amplitude scale factor ASF<0:7>. The
second byte is split into the first six bits ASF<8:13> and the last
two provide the auto-ramp rate speed control bits ARRSC<0:1>.
SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In
the case where the AD9859 operates in a single bidirectional
I/O mode, this pin does not output data and is set to a high
impedance state.
Power-Down Functions of the AD9859
IOSYNC—It synchronizes the I/O port state machines without
affecting the addressable register’s contents. An active high
input on the IOSYNC pin causes the current communication
cycle to abort. After IOSYNC returns low (Logic 0), another
communication cycle may begin, starting with the instruction
byte write.
The AD9859 supports an externally controlled or hardware
power-down feature as well as the more common software
programmable power-down bits found in previous Analog Devices,
Inc., DDS products.
The software control power-down allows the DAC, PLL, input
clock circuitry, and digital logic to be individually powered
down via unique control bits (CFR1<7:4>). With the exception
of CFR1<6>, these bits are not active when the externally
controlled power-down pin (PWRDWNCTL) is high. External
power-down control is supported on the AD9859 via the
PWRDWNCTL input pin. When the PWRDWNCTL input pin
is high, the AD9859 enters a power-down mode based on the
CFR1<3> bit. When the PWRDWNCTL input pin is low, the
external power-down control is inactive.
MSB/LSB TRANSFERS
The AD9859 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by the Control Register 0x00 <8> bit.
The default value of Control Register 0x00 <8> is low (MSB
first). When Control Register 0x00 <8> is set high, the AD9859
serial port is in LSB first format. The instruction byte must be
Rev. B | Page 21 of 24
AD9859
Data Sheet
When the CFR1<3> bit is 0 and the PWRDWNCTL input pin is
high, the AD9859 is put into a fast recovery power-down mode.
In this mode, the digital logic and the DAC digital logic are
powered down. The DAC bias circuitry, PLL, oscillator, and
clock input circuitry is NOT powered down.
Table 8 indicates the logic level for each power-down bit that
drives out of the AD9859 core logic to the analog section and
the digital clock generation section of the chip for the external
power-down operation.
Layout Considerations
When the CFR1<3> bit is high and the PWRDWNCTL input
pin is high, the AD9859 is put into the full power-down mode.
In this mode, all functions are powered down. This includes
the DAC and PLL, which take a significant amount of time to
power up.
For the best performance, these layout guidelines should be
observed. Always provide the analog power supply (AVDD) and
the digital power supply (DVDD) on separate supplies, even if
just from two different voltage regulators driven by a common
supply. Likewise, the ground connections (AGND, DGND)
should be kept separate as far back to the source as possible (i.e.,
separate the ground planes on a localized board, even if the
grounds connect to a common point in the system). Bypass
capacitors should be placed as close to the device pin as possi-
ble. Usually, a multitiered bypassing scheme consisting of a
small high frequency capacitor (100 pF) placed close to the
supply pin and progressively larger capacitors (0.1 µF, 10 µF)
further away from the actual supply source works best.
When the PWRDWNCTL input pin is high, the individual
power-down bits (CFR1<7>, <5:4>) are invalid (Don’t Care)
and unused. When the PWRDWNCTL input pin is low, the
individual power-down bits control the power-down modes of
operation.
Note that the power-down signals are all designed such that a
Logic 1 indicates the low power mode and a Logic 0 indicates
the active or power-up mode.
Table 8. Power-Down Control Functions
Control
Mode Active
Description
PWRDWNCTL = 0 CFR1<3> Don’t Care
Software Control
Digital Power-Down = CFR1<7>
DAC Power-Down = CFR1<5>
Input Clock Power-Down = CFR1<4>
Digital Power-Down = 1’b1
PWRDWNCTL = 1 CFR1<3> = 0
PWRDWNCTL = 1 CFR1<3> = 1
External Control,
Fast Recovery Power-Down Mode
DAC Power-Down = 1’b0
Input Clock Power-Down = 1’b0
Digital Power-Down = 1’b1
DAC Power-Down = 1’b1
External Control,
Full Power-Down Mode
Input Clock Power-Down = 1’b1
Rev. B | Page 22 of 24
Data Sheet
AD9859
SUGGESTED APPLICATION CIRCUITS
FREQUENCY
TUNING
WORD
PHASE
OFFSET
WORD 1
MODULATED/
RF/IF INPUT
DEMODULATED
SIGNAL
I/I
BASEBAND
LPF
AD9859
REFCLK
IOUT
IOUT
REFCLK
CRYSTAL
LPF
AD9859 DDS
REFCLK
Figure 25. Synchronized LO for Up Conversion/Down Conversion
CRYSTAL OUT SYNC OUT
RF OUT
SYNC IN
IOUT
AD9859 DDS
IOUT
PHASE
COMPARATOR
LOOP
FILTER
LPF
REF
SIGNAL
VCO
REFCLK
Q/Q
BASEBAND
FILTER
AD9859
FREQUENCY
TUNING
WORD
PHASE
OFFSET
WORD 2
Figure 27. Two AD9859s Synchronized to Provide I and
Q Carriers with Independent Phase Offsets for Nulling
TUNING
WORLD
Figure 26. Digitally Programmable Divide-by-N Function in PLL
Rev. B | Page 23 of 24
AD9859
Data Sheet
OUTLINE DIMENSIONS
1.20
MAX
9.00
BSC SQ
0.75
0.60
0.45
BOTTOM VIEW
(PINS UP)
37
36
48
37
36
48
1
1
7.00
BSC SQ
PIN 1
TOP VIEW
(PINS DOWN)
3.50
SQ
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
3.5°
0°
EXPOSED
PAD
12
25
24
25
24
12
13
13
0.15
0.05
SEATING
PLANE
VIEW A
0.08 MAX
COPLANARITY
0.50 BSC
LEAD PITCH
0.27
0.22
0.17
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
VIEW A
ROTATED 90° CCW
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MS-026-ABC
Figure 28. 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-48-4)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Ordering
Quantity
Package
Option
Model1
Package Description
AD9859YSVZ
AD9859YSVZ-REEL7
−40°C to +105°C
−40°C to +105°C
48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
SV-48-4
SV-48-4
500
1 Z = RoHS Compliant Part
©2004–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03375-0-1/17(B)
Rev. B | Page 24 of 24
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