AD9760ARUZ50RL7 [ADI]
10-Bit, 100 MSPS+ TxDAC® D/A Converter;
| 型号： | AD9760ARUZ50RL7 |
| 厂家： | 
ADI |
| 描述： | 10-Bit, 100 MSPS+ TxDAC® D/A Converter 光电二极管 转换器 |
| 文件： | 总24页 (文件大小：441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, 125 MSPS
®
a
TxDAC D/A Converter
AD9760
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
+5V
0.1F
10-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 40 MHz Output: 52 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 25 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages: 28-Lead SOIC and TSSOP
Edge-Triggered Latches
REFLO
+1.20V REF
COMP1
AVDD ACOM
AD9760
50pF
0.1F
REFIO
0.1F
CURRENT
COMP2
SOURCE
FS ADJ
ARRAY
R
SET
DVDD
+5V
I
I
OUTA
SEGMENTED
SWITCHES
LSB
SWITCHES
DCOM
OUTB
CLOCK
SLEEP
CLOCK
LATCHES
APPLICATIONS
Communication Transmit Channel:
Basestations
DIGITAL DATA INPUTS (DB9–DB0)
The AD9760 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kΩ output impedance.
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25 V.
Set Top Boxes
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
PRODUCT DESCRIPTION
The AD9760 and AD9760-50 are the 10-bit resolution members
of the TxDAC series of high performance, low power CMOS
digital-to-analog converters (DACs). The AD9760-50 is a lower
performance option that is guaranteed and specified for 50 MSPS
operation. The TxDAC family that consists of pin compatible 8-,
10-, 12- and 14-bit DACs is specifically optimized for the trans-
mit signal path of communication systems. All of the devices
share the same interface options, small outline package and
pinout, thus providing an upward or downward component
selection path based on performance, resolution and cost. Both
the AD9760 and AD9760-50 offer exceptional ac and dc
performance while supporting update rates up to 125 MSPS
and 60 MSPS respectively.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9760 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier that provides a wide
(>10:1) adjustment span allows the AD9760 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9760 may oper-
ate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9760 is available in a 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
The AD9760’s flexible single-supply operating range of 2.7 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW without a significant degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 25 mW.
PRODUCT HIGHLIGHTS
1. The AD9760 is a member of the TxDACproduct family that
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.
2. Manufactured on a CMOS process, the AD9760 uses a pro-
prietary switching technique that enhances dynamic perfor-
mance beyond what was previously attainable by higher
power/cost bipolar or BiCMOS devices.
3. On-chip, edge-triggered input CMOS latches interface readily
to +3 V and +5 V CMOS logic families. The AD9760 can
support update rates up to 125 MSPS.
4. A flexible single-supply operating range of 2.7 V to 5.5 V and
a wide full-scale current adjustment span of 2 mA to 20 mA
allow the AD9760 to operate at reduced power levels.
The AD9760 is manufactured on an advanced CMOS process. A
segmented current source architecture is combined with a propri-
etary switching technique to reduce spurious components and
enhance dynamic performance. Edge-triggered input latches and a
1.2 V temperature compensated bandgap reference have been inte-
grated to provide a complete monolithic DAC solution. Flexible
supply options support +3 V and +5 V CMOS logic families.
TxDAC is a registered trademark of Analog Devices, Inc.
REV. B
5. The current output(s) of the AD9760 can be easily config-
ured for various single-ended or differential circuit topologies.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
AD9760* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
REFERENCE MATERIALS
Informational
• Advantiv™ Advanced TV Solutions
Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
EVALUATION KITS
• AD9760 Evaluation Board
DOCUMENTATION
Application Notes
DESIGN RESOURCES
• AD9760 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
• AN-237: Choosing DACs for Direct Digital Synthesis
• AN-320A: CMOS Multiplying DACs and Op Amps Combine
to Build Programmable Gain Amplifier, Part 1
• AN-414: Low Cost, Low Power Devices for HDSL
Applications
DISCUSSIONS
View all AD9760 EngineerZone Discussions.
• AN-420: Using the AD9708/AD9760/AD9701/AD9764-EB
Evaluation Board
• AN-595: Understanding Pin Compatibility in the TxDAC®
Line of High Speed D/A Converters
SAMPLE AND BUY
Visit the product page to see pricing options.
• AN-912: Driving a Center-Tapped Transformer with a
Balanced Current-Output DAC
TECHNICAL SUPPORT
Data Sheet
Submit a technical question or find your regional support
number.
• AD9760: 10-Bit, 125 MSPS+ TxDAC® D/A Converter Data
Sheet
DOCUMENT FEEDBACK
TOOLS AND SIMULATIONS
Submit feedback for this data sheet.
• AD9760 IBIS Models
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
AD9760/AD9760-50–SPECIFICATIONS
(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
DC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
RESOLUTION
10
Bits
DC ACCURACY1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
–1.0
–0.5
0.5
0.25
+1.0
+0.5
LSB
LSB
MONOTONICITY
Guaranteed Over Specified Temperature Range
ANALOG OUTPUT
Offset Error
–0.025
–10
–10
2.0
–1.0
+0.025
+10
+10
20.0
1.25
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
2
1
100
5
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
1.08
0.1
1.20
100
1.32
1.25
V
nA
Reference Output Current3
REFERENCE INPUT
Input Compliance Range
V
Reference Input Resistance
Small Signal Bandwidth (w/o CCOMP1
1
1.4
MΩ
MHz
4
)
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
0
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
50
100
50
POWER SUPPLY
Supply Voltages
AVDD5
2.7
2.7
5.0
5.0
25
3
5.5
5.5
30
V
V
mA
mA
DVDD
Analog Supply Current (IAVDD
Digital Supply Current (IDVDD
)
)
6
5
Supply Current Sleep Mode (IAVDD
)
8.5
175
mA
mW
mW
mW
% of FSR/V
% of FSR/V
Power Dissipation6 (5 V, IOUTFS = 20 mA)
Power Dissipation7 (5 V, IOUTFS = 20 mA)
Power Dissipation7 (3 V, IOUTFS = 2 mA)
Power Supply Rejection Ratio—AVDD
Power Supply Rejection Ratio—DVDD
140
190
45
–0.04
–0.025
+0.04
+0.025
OPERATING RANGE
–40
+85
°C
NOTES
1Measured at IOUTA, driving a virtual ground.
2Nominal full-scale current, IOUTFS, is 32 × the IREF current.
3Use an external buffer amplifier to drive any external load.
4Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41.
5For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.
6Measured at fCLOCK = 50 MSPS and fOUT = 1.0 MHz.
7Measured as unbuffered voltage output into 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.
Specifications subject to change without notice.
–2–
REV. B
AD9760
MIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer Coupled Output,
DYNAMIC SPECIFICATIONS (5T0 ⍀ Doubly Terminated, unless otherwise noted)
Model
AD9760
Typ
AD9760-50
Typ
Parameter
Min
Max
Min
Max
Units
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK
)
125
50
60
35
1
MSPS
ns
ns
pV-s
ns
ns
Output Settling Time (tST) (to 0.1%)1
35
1
5
2.5
2.5
50
30
Output Propagation Delay (tPD
Glitch Impulse
)
5
Output Rise Time (10% to 90%)1
Output Fall Time (10% to 90%)1
Output Noise (IOUTFS = 20 mA)
Output Noise (IOUTFS = 2 mA)
2.5
2.5
50
30
pA/√Hz
pA/√Hz
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fCLOCK = 50 MSPS; fOUT = 1.00 MHz
TA = +25°C
70
68
73
68
66
73
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
TMIN to TMAX
fCLOCK = 50 MSPS; fOUT = 2.51 MHz
73
68
55
74
68
60
52
73
68
55
N/A
N/A
N/A
N/A
f
f
CLOCK = 50 MSPS; fOUT = 5.02 MHz
CLOCK = 50 MSPS; fOUT = 20.2 MHz
fCLOCK = 100 MSPS; fOUT = 2.51 MHz
f
f
CLOCK = 100 MSPS; fOUT = 5.04 MHz
CLOCK = 100 MSPS; fOUT = 20.2 MHz
fCLOCK = 100 MSPS; fOUT = 40.4 MHz
Spurious-Free Dynamic Range within a Window
f
f
CLOCK = 50 MSPS; fOUT = 1.00 MHz
TA = +25°C
74
72
78
72
70
78
dBc
dBc
dBc
dBc
TMIN to TMAX
CLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span
76
76
76
N/A
fCLOCK = 100 MSPS; fOUT = 5.04 MHz; 4 MHz Span
Total Harmonic Distortion
f
CLOCK = 50 MSPS; fOUT = 1.00 MHz
TA = +25°C
–76
–73
–71
–76
–70
–68
dBc
dBc
dBc
dBc
TMIN to TMAX
f
CLOCK = 50 MHz; fOUT = 2.00 MHz
–71
–71
–71
N/A
fCLOCK = 100 MHz; fOUT = 2.00 MHz
NOTES
1Measured single ended into 50 Ω load.
Specifications subject to change without notice.
REV. B
–3–
AD9760
(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted)
DIGITAL SPECIFICATIONS
Parameter
Min
Typ
Max
Units
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V
Logic “1” Voltage @ DVDD = +3 V
Logic “0” Voltage @ DVDD = +5 V
Logic “0” Voltage @ DVDD = +3 V
Logic “1” Current
Logic “0” Current
Input Capacitance
3.5
2.1
5
3
0
0
V
V
V
V
µA
µA
pF
ns
ns
ns
1.3
0.9
+10
+10
–10
–10
5
Input Setup Time (tS)
Input Hold Time (tH)
2.0
1.5
3.5
Latch Pulsewidth (tLPW
)
Specification subject to change without notice.
DB0–DB9
tH
tS
CLOCK
tLPW
tST
tPD
I
OR
OUTB
0.1%
OUTA
I
0.1%
Figure 1. Timing Diagram
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*
With
Temperature
Range
Package
Descriptions
Package
Options
Parameter
Respect to Min
Max
Units
Model
AVDD
DVDD
ACOM
AVDD
CLOCK, SLEEP
Digital Inputs
ACOM
DCOM
DCOM
DVDD
DCOM
DCOM
ACOM
ACOM
ACOM
ACOM
–0.3
+6.5
+6.5
+0.3
+6.5
DVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
+0.3
V
V
V
V
V
V
V
V
AD9760AR
–40°C to +85°C 28-Lead 300 mil R-28
–0.3
–0.3
–6.5
–0.3
–0.3
–1.0
–0.3
–0.3
–0.3
SOIC
–40°C to +85°C 28-Lead 170 mil RU-28
TSSOP
AD9760ARU
AD9760AR50
–40°C to +85°C 28-Lead 300 mil R-28
SOIC
I
OUTA, IOUTB
AD9760ARU50 –40°C to +85°C 28-Lead 170 mil RU-28
COMP1, COMP2
REFIO, FSADJ
REFLO
TSSOP
V
V
AD9760-EB
Evaluation Board
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
+150
+150
°C
°C
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 mil (7.5 mm) SOIC
–65
+300
°C
θ
JA = 71.4°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
θ
JC = 23°C/W
28-Lead 170 mil (4.4 mm) TSSOP
θ
θ
JA = 97.9°C/W
JC = 14.0°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9760 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–4–
AD9760
PIN CONFIGURATION
1
2
(MSB) DB9
DB8
28 CLOCK
27 DVDD
DB7
3
26
25
DCOM
NC
4
DB6
5
DB5
24 AVDD
AD9760
DB4
6
23
22
21
20
19
18
17
16
15
COMP2
TOP VIEW
(Not to Scale)
7
DB3
I
OUTA
8
DB2
I
OUTB
9
DB1
ACOM
COMP1
FS ADJ
REFIO
10
DB0
NC 11
12
13
14
NC
NC
NC
REFLO
SLEEP
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
Most Significant Data Bit (MSB).
1
DB9
2–9
10
DB8–DB1 Data Bits 1–8.
DB0 Least Significant Data Bit (LSB).
No Internal Connection.
11–14, 25 NC
15
SLEEP
Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if
not used.
16
17
REFLO
REFIO
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1 µF capacitor to ACOM when internal reference activated.
Full-Scale Current Output Adjust.
Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance.
Analog Common.
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.
Analog Supply Voltage (+2.7 V to +5.5 V).
18
19
20
21
22
23
24
26
27
28
FS ADJ
COMP1
ACOM
IOUTB
IOUTA
COMP2
AVDD
DCOM
DVDD
CLOCK
Digital Common.
Digital Supply Voltage (+2.7 V to +5.5 V).
Clock Input. Data latched on positive edge of clock.
REV. B
–5–
AD9760
DEFINITIONS OF SPECIFICATIONS
Temperature Drift
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1s.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Output Compliance Range
Total Harmonic Distortion
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured output signal. It is
expressed as a percentage or in decibels (dB).
+5V
0.1F
REFLO
+1.20V REF
REFIO
COMP1
AVDD
ACOM
AD9760
50pF
0.1F
PMOS
0.1F
COMP2
CURRENT SOURCE
ARRAY
FS ADJ
MINI-CIRCUITS
T1-1T
R
2k⍀
SET
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50⍀ INPUT
+5V
DVDD
I
OUTA
LSB
SWITCHES
SEGMENTED SWITCHES
100⍀
DCOM
I
OUTB
FOR DB11–DB3
CLOCK
SLEEP
LATCHES
DVDD
DCOM
50⍀
50⍀
20pF
50⍀
RETIMED
20pF
CLOCK
DIGITAL
DATA
OUTPUT*
CLOCK
OUTPUT
* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
LECROY 9210
PULSE GENERATOR
TEKTRONIX
AWG-2021
Figure 2. Basic AC Characterization Test Setup
REV. B
–6–
AD9760
Typical AC Characterization Curves @ +5 V Supplies
(AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, 50 ⍀Doubly Terminated Load, Differential Output, TA = +25؇C, SFDR up to Nyquist, unless otherwise noted)
85
90
80
70
85
0dBFS
80
75
70
80
75
70
65
5MSPS
–6dBFS
25MSPS
–6dBFS
–12dBFS
–12dBFS
50MSPS
0dBFS
65
60
100MSPS
60
55
50
60
50
125MSPS
55
50
0.00 2.00 4.00 6.00 8.00 10.00 12.00
0.1
1
10
100
0.00
0.50
1.00
1.50
2.00
2.50
FREQUENCY – MHz
FREQUENCY – MHz
FREQUENCY – MHz
Figure 3. SFDR vs. fOUT @ 0 dBFS
Figure 4. SFDR vs. fOUT @ 5 MSPS
Figure 5. SFDR vs. fOUT @ 25 MSPS
85
85
85
80
75
80
75
70
80
–6dBFS
75
–12dBFS
70
70
–6dBFS
–12dBFS
–6dBFS
65
65
65
0dBFS
60
60
60
0dBFS
–12dBFS
55
50
55
55
50
0dBFS
50
0.00
10.00
20.00
30.00
40.00 50.00
0.00 10.00 20.00 30.00 40.00 50.00 60.00
0.00
5.00
10.00
15.00
20.00 25.00
FREQUENCY – MHz
FREQUENCY – MHz
FREQUENCY – MHz
Figure 6. SFDR vs. fOUT @ 50 MSPS
Figure 7. SFDR vs. fOUT @100 MSPS
Figure 8. SFDR vs. fOUT @ 125 MSPS
85
85
85
6.75/7.25MHz
@ 50MSPS
455kHz
@ 5MSPS
1MHz
@ 5MSPS
0.675/0.725MHz
@ 5MSPS
4.55MHz
75
75
75
@ 50MSPS
2.5MHz
3.38/3.63MHz
@ 25MSPS
@ 25MSPS
2.27MHz
@ 25MSPS
25MHz
@ 125MSPS
65
65
65
9.1MHz
13.5/14.5MHz
@ 100MSPS
@ 100MSPS
10MHz
11.37MHz
@ 125MSPS
55
55
16.9/18.1MHz
@ 125MSPS
55
45
@ 50MSPS
20MHz
@ 100MSPS
45
–30
45
–30
–25
–20
A
–15
–10
–5
0
–30
–25
–20
A
–15
OUT
–10
– dBFS
–5
0
–25
–20
A
–15 –10
– dBFS
OUT
–5
0
– dBFS
OUT
Figure 9. Single-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/11
Figure 10. Single-Tone SFDR vs.
Figure 11. Dual-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/7
A
OUT @ fOUT = fCLOCK/5
REV. B
–7–
AD9760
80
75
75
–70
IDIFF @ 0dBFS
IDIFF @ –6dBFS
2.5MHz
10MHz
70
65
60
55
50
45
–75
–80
–85
–90
–95
70
65
2ND
HARMONIC
I
@ 0dBFS
OUTA
3RD
60
55
50
HARMONIC
28.6MHz
I
@ –6dBFS
OUTA
4TH
HARMONIC
40MHz
45
40
2
4
6
8
10 12 14 16 18 20
1
10
100
0
20
40
60
80 100 120 140
I
– mA
OUTPUT FREQUENCY – MHz
FREQUENCY – MSPS
OUTFS
Figure 12. THD vs. fCLOCK
fOUT = 2 MHz
@
Figure 13. SFDR vs. fOUT and IOUTFS
@ 100 MSPS, 0 dBFS
Figure 14. Differential vs. Single-
Ended SFDR vs. fOUT @ 100 MSPS
0.5
80
0.5
0.4
0.3
0.4
0.3
0.2
75
2.5MHz
0.2
0.1
70
0
65
0.1
0
10MHz
–0.1
60
–0.2
–0.3
–0.1
55
40MHz
–0.4
–0.5
–0.2
50
–40 –20
0
20
40
60
80
0
125 250 375 500 625 750 875 1000
CODE
0
125 250 375 500 625 750 875 1000
CODE
TEMPERATURE – ؇C
Figure 15. Typical INL
Figure 16. Typical DNL
Figure 17. SFDR vs. Temperature
@ 100 MSPS, 0 dBFS
0
0
–10
f
f
f
= 100MSPS
= 13.5MHz
= 14.5MHz
f
f
= 125MSPS
= 9.95MHz
CLOCK
OUT1
OUT2
CLOCK
OUT
f
f
f
f
f
= 50MSPS
CLOCK
SFDR = 62dBc
AMPLITUDE = 0dBFS
= 6.25MHz
= 6.75MHz
= 7.25MHz
= 7.75MHz
OUT1
OUT2
OUT3
OUT4
SFDR = 61dBc
AMPLITUDE = 0dBFS
SFDR = 70dBc
AMPLITUDE = 0dBFS
–100
–100
–110
START: 0.3MHz
STOP: 50.0MHz
START: 0.3MHz
STOP: 62.5MHz
START: 0.3MHz
STOP: 25.0MHz
Figure 18. Single-Tone SFDR
Figure 19. Dual-Tone SFDR
Figure 20. Four-Tone SFDR
REV. B
–8–
AD9760
Typical AC Characterization Curves @ +3 V Supplies
(AVDD = +3 V, DVDD = +3 V, IOUTFS = 20 mA, 50 ⍀ Doubly Terminated Load, Differential Output, TA = +25؇C, SFDR up to Nyquist, unless otherwise noted)
85
85
90
80
70
0dBFS
5MSPS
80
75
70
80
75
70
–6dBFS
–6dBFS
25MSPS
–12dBFS
–12dBFS
65
60
55
50
65
60
55
50
0dBFS
100MSPS
50MSPS
60
50
125MSPS
0.00
0.50
1.00
1.50
2.00
2.50
0.1
1
10
100
0.00 2.00 4.00 6.00 8.00 10.00 12.00
FREQUENCY – MHz
FREQUENCY – MHz
FREQUENCY – MHz
Figure 21. SFDR vs. fOUT @ 0 dBFS
Figure 22. SFDR vs. fOUT @ 5 MSPS
Figure 23. SFDR vs. fOUT @ 25 MSPS
85
80
75
85
85
80
80
75
75
70
65
60
55
–6dBFS
–12dBFS
–6dBFS
–6dBFS
70
65
60
70
–12dBFS
–12dBFS
65
0dBFS
60
0dBFS
55
50
0dBFS
55
50
50
0.00
0.00
10.00 20.00
30.00
40.00 50.00
0.00 10.00 20.00 30.00 40.00 50.00 60.00
5.00
10.00 15.00
FREQUENCY – MHz
20.00 25.00
FREQUENCY – MHz
FREQUENCY – MHz
Figure 25. SFDR vs. fOUT @ 100 MSPS
Figure 24. SFDR vs. fOUT @ 50 MSPS
Figure 26. SFDR vs. fOUT @ 125 MSPS
90
90
90
3.38/3.63MHz
@ 25MSPS
2.27MHz
@ 25MSPS
1MHz
80
70
60
50
40
80
0.675/0.725MHz
@ 5MSPS
80
70
60
50
40
@ 5MSPS
4.55MHz
@ 50MSPS
2.5MHz
6.75/7.25MHz
@ 50MSPS
455kHz
70
@ 25MSPS
@ 5MSPS
10MHz
@ 50MSPS
20MHz
@ 100MSPS
9.1MHz
@ 100MSPS
60
13.5/14.5MHz
@ 100MSPS
11.37MHz
@ 125MSPS
25MHz
@ 125MSPS
50
16.9/18.1MHz
@ 125MSPS
40
–30
–30
–25
–20
–15
OUT
–10
–5
0
–25
–20
A
–15
OUT
–10
–5
0
–30
–25
–20
A
–15
–10
– dBFS
–5
0
A
– dBFS
– dBFS
OUT
Figure 27. Single-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/11
Figure 28. Single-Tone SFDR vs.
AOUT @ fOUT = fCLOCK/5
Figure 29. Dual-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/7
REV. B
–9–
AD9760
–70
80
75
2.5MHz
I
@
OUTA
–6dBFS
75
70
65
70
65
60
55
50
45
–75
2ND
HARMONIC
IDIFF @
–6dBFS
10MHz
3RD
–80
–85
–90
–95
HARMONIC
60
55
22.4MHz
28.6MHz
IDIFF @
0dBFS
50
45
40
4TH
I
@
OUTA
HARMONIC
0dBFS
2
4
6
8
10 12 14 16 18 20
– mA
0
20
40
60
80 100 120 140
1
10
100
I
FREQUENCY – MSPS
REF
OUTPUT FREQUENCY – MHz
Figure 30. THD vs. fCLOCK
fOUT = 2 MHz
Figure 31. SFDR vs. fOUT and IOUTFS
@ 100 MSPS, 0 dBFS
Figure 32. Differential vs. Single
Ended SFDR vs. fOUT @ 100 MSPS
0.5
0.4
0.3
0.2
80
0.5
0.4
0.3
75
70
65
2.5MHz
0.2
0.1
10MHz
28.6MHz
60
55
0
0.1
0
–0.1
–0.2
–0.3
50
45
40
–0.1
–0.4
–0.5
–0.2
0
125 250 375 500 625 750 875 1000
CODE
–40
–20
0
20
40
60
80
0
125 250 375 500 625 750 875 1000
CODE
TEMPERATURE – ؇C
Figure 33. Typical INL
Figure 34. Typical DNL
Figure 35. SFDR vs. Temperature
@ 100 MSPS, 0 dBFS
–10
0
0
f
f
f
f
f
= 50MSPS
f
f
= 125MSPS
= 9.95MHz
f
f
f
= 100MSPS
= 13.5MHz
= 14.5MHz
CLOCK
CLOCK
OUT
CLOCK
OUT1
OUT2
= 6.25MHz
= 6.75MHz
= 7.25MHz
= 7.75MHz
OUT1
OUT2
OUT3
OUT4
SFDR = 62dBc
AMPLITUDE = 0dBFS
SFDR = 59.0dBc
AMPLITUDE = 0dBFS
SFDR = 71dBc
AMPLITUDE = 0dBFS
–110
–100
–100
START: 0.3MHz
STOP: 25.0MHz
START: 0.3MHz
STOP: 62.5MHz
START: 0.3MHz
STOP: 50.0MHz
Figure 36. Single-Tone SFDR
Figure 37. Dual-Tone SFDR
Figure 38. Four-Tone SFDR
REV. B
–10–
AD9760
FUNCTIONAL DESCRIPTION
DAC TRANSFER FUNCTION
Figure 39 shows a simplified block diagram of the AD9760.
The AD9760 consists of a large PMOS current source array that
is capable of providing up to 20 mA of total current. The array
is divided into 31 equal currents that make up the 5 most sig-
nificant bits (MSBs). The next 4 bits or middle bits consist
of 15 equal current sources whose value is 1/16th of an MSB
current source. The remaining LSBs is a binary weighted frac-
tion of the middle-bits current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances its dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 kΩ).
The AD9760 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current output,
IOUTFS, when all bits are high (i.e., DAC CODE = 1023) while
IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function of
both the input code and IOUTFS and can be expressed as:
I
I
OUTA = (DAC CODE/1024) × IOUTFS
(1)
(2)
OUTB = (1023 – DAC CODE)/1024 × IOUTFS
where DAC CODE = 0 to 1023 (i.e., Decimal Representation).
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage,
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS differen-
tial current switches. The switches are based on a new architec-
ture that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the dif-
ferential current switches.
V
REFIO and external resistor RSET. It can be expressed as:
I
OUTFS = 32 × IREF
(3)
(4)
where IREF = VREFIO/RSET
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, that are tied to analog common, ACOM. Note,
The analog and digital sections of the AD9760 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 volt to 5.5 volt range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V bandgap
voltage reference and a reference control amplifier.
R
LOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50 Ω or 75 Ω cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply:
V
OUTA = IOUTA × RLOAD
OUTB = IOUTB × RLOAD
(5)
(6)
V
Note the full-scale value of VOUTA and VOUTB should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, RSET. The external resistor, in combination with
both the reference control amplifier and voltage reference
VREFIO, sets the reference current IREF, which is mirrored over to
the segmented current sources with the proper scaling factor.
The full-scale current, IOUTFS, is thirty-two times the value of IREF
.
+5V
0.1F
REFLO
+1.20V REF
REFIO
COMP1
AVDD
ACOM
AD9760
50pF
V
REFIO
0.1F
PMOS
COMP2
I
CURRENT SOURCE
ARRAY
REF
FS ADJ
0.1F
R
V
= V
– V
SET
DIFF
OUTA OUTB
2k⍀
+5V
DVDD
I
I
OUTA
OUTA
V
LSB
SWITCH
SEGMENTED SWITCHES
OUTA
DCOM
I
I
OUTB
OUTB
FOR DB9–DB1
V
R
OUTB
LOAD
50⍀
CLOCK
SLEEP
R
50⍀
LOAD
CLOCK
LATCHES
DIGITAL DATA INPUTS (DB9–DB0)
Figure 39. Functional Block Diagram
REV. B
–11–
AD9760
The differential voltage, VDIFF, appearing across IOUTA and
REFERENCE CONTROL AMPLIFIER
I
OUTB is:
The AD9760 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, IOUTFS
.
V
DIFF = (IOUTA – IOUTB) × RLOAD
(7)
(8)
The control amplifier is configured as a V-I converter as shown
in Figure 41, so that its current output, IREF, is determined by
the ratio of the VREFIO and an external resistor, RSET, as stated
in Equation 4. IREF is copied over to the segmented current
sources with the proper scaling factor to set IOUTFS as stated in
Equation 3.
Substituting the values of IOUTA, IOUTB and IREF; VDIFF can be
expressed as:
V
DIFF = {(2 DAC CODE – 1023)/1024} ×
(32 RLOAD/RSET) × VREFIO
These last two equations highlight some of the advantages of
AVDD
operating the AD9760 differentially. First, the differential op-
eration will help cancel common-mode error sources associated
with IOUTA and IOUTB such as noise, distortion and dc offsets.
Second, the differential code dependent current and subsequent
voltage, VDIFF, is twice the value of the single-ended voltage
output (i.e., VOUTA or VOUTB), thus providing twice the signal
power to the load.
0.1F
REFLO
+1.2V REF
COMP1
AVDD
AVDD
50pF
V
REFIO
REFIO
FS ADJ
EXTERNAL
REF
CURRENT
SOURCE
ARRAY
Note, the gain drift temperature performance for a single-ended
(VOUTA and VOUTB) or differential output (VDIFF) of the AD9760
can be enhanced by selecting temperature tracking resistors for
RLOAD and RSET due to their ratiometric relationship as shown
in Equation 8.
R
SET
I
V
=
REF
/R
REFERENCE
CONTROL
AMPLIFIER
REFIO SET
AD9760
Figure 41. External Reference Configuration
REFERENCE OPERATION
The control amplifier allows a wide (10:1) adjustment span of
The AD9760 contains an internal 1.20 V bandgap reference
that can be easily disabled and overridden by an external refer-
ence. REFIO serves as either an input or output depending on
whether the internal or an external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 40, the internal
reference is activated and REFIO provides a 1.20 V output. In
this case, the internal reference must be compensated externally
with a ceramic chip capacitor of 0.1 µF or greater from REFIO
to REFLO. Also, REFIO should be buffered with an external
amplifier having an input bias current less than 100 nA if any
additional loading is required.
I
OUTFS over a 2 mA to 20 mA range by setting IREF between
62.5 µA and 625 µA. The wide adjustment span of IOUTFS pro-
vides several application benefits. The first benefit relates
directly to the power dissipation of the AD9760, which is
proportional to IOUTFS (refer to the Power Dissipation section).
The second benefit relates to the 20 dB adjustment, which is
useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 1.4 MHz and can be reduced by connecting an
external capacitor between COMP1 and AVDD. The output of
the control amplifier, COMP1, is internally compensated via a
50 pF capacitor that limits the control amplifier small-signal
bandwidth and reduces its output impedance. Any additional
external capacitance further limits the bandwidth and acts as a
filter to reduce the noise contribution from the reference ampli-
fier. Figure 42 shows the relationship between the external
capacitor and the small signal –3 dB bandwidth of the refer-
ence amplifier. Since the –3 dB bandwidth corresponds to the
dominant pole, and hence the time constant, the settling time of
the control amplifier to a stepped reference input response can
be approximated.
+5V
0.1F
OPTIONAL
EXTERNAL
REF BUFFER
REFLO
+1.2V REF
COMP1
AVDD
50pF
REFIO
FS ADJ
CURRENT
SOURCE
ARRAY
ADDITIONAL
LOAD
0.1F
2k⍀
AD9760
Figure 40. Internal Reference Configuration
1000
The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may be applied to
REFIO as shown in Figure 41. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1 µF compensation capacitor is not required
since the internal reference is disabled, and the high input im-
pedance (i.e., 1 MΩ) of REFIO minimizes any loading of the
external reference.
10
0.1
0.1
1
10
100
1000
COMP1 CAPACITOR – nF
Figure 42. External COMP1 Capacitor vs. –3 dB Bandwidth
REV. B
–12–
AD9760
AVDD
OPTIONAL
BANDLIMITING
CAPACITOR
AVDD
REFLO
COMP1
AVDD
+1.2V REF
R
V
DD
FB
50pF
1.2V
OUT1
OUT2
0.1V TO 1.2V
REFIO
AD7524
V
REF
CURRENT
SOURCE
ARRAY
FS ADJ
AD1580
AGND
R
I
V
=
SET
REF
AD9760
/R
REF SET
DB7–DB0
Figure 43. Single-Supply Gain Control Circuit
The optimum distortion performance for any reconstructed
waveform is obtained with a 0.1 µF external capacitor installed.
Thus, if IREF is fixed for an application, a 0.1 µF ceramic chip
capacitor is recommended. Also, since the control amplifier is
optimized for low power operation, multiplying applications
requiring large signal swings should consider using an external
control amplifier to enhance the application’s overall large signal
multiplying bandwidth and/or distortion performance.
In some applications, the user may elect to use an external con-
trol amplifier to enhance the multiplying bandwidth, distortion
performance and/or settling time. External amplifiers capable of
driving a 50 pF load such as the AD817 are suitable for this
purpose. It is configured in such a way that it is in parallel with
the weaker internal reference amplifier as shown in Figure 45.
In this case, the external amplifier simply overdrives the weaker
reference control amplifier. Also, since the internal control
amplifier has a limited current output, it will sustain no damage
if overdriven.
There are two methods in which IREF can be varied for a fixed
RSET. The first method is suitable for a single-supply system in
which the internal reference is disabled, and the common-mode
voltage of REFIO is varied over its compliance range of 1.25 V
to 0.10 V. REFIO can be driven by a single-supply amplifier or
DAC, allowing IREF to be varied for a fixed RSET. Since the
input impedance of REFIO is approximately 1 MΩ, a simple,
low cost R-2R ladder DAC configured in the voltage mode
topology may be used to control the gain. This circuit is shown
in Figure 43 using the AD7524 and an external 1.2 V reference,
the AD1580.
EXTERNAL
CONTROL AMPLIFIER
AVDD
V
REF
INPUT
COMP1
REFLO
+1.2V REF
REFIO
AVDD
50pF
CURRENT
SOURCE
ARRAY
FS ADJ
R
SET
AD9760
The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed and IREF is
varied by an external voltage, VGC, applied to RSET via an ampli-
fier. An example of this method is shown in Figure 44 where
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, VGC, is
referenced to ACOM and should not exceed 1.2 V. The value
of RSET is such that IREFMAX and IREFMIN do not exceed 62.5 µA
and 625 µA, respectively. The associated equations in Figure 44
Figure 45. Configuring an External Reference Control
Amplifier
ANALOG OUTPUTS
The AD9760 produces two complementary current outputs,
OUTA and IOUTB, which may be configured for single-ended or
I
differential operation. IOUTA and IOUTB can be converted into
complementary single-ended voltage outputs, VOUTA and VOUTB
via a load resistor, RLOAD, as described in the DAC Transfer
Function section by Equations 5 through 8. The differential
voltage, VDIFF, existing between VOUTA and VOUTB can also be
converted to a single-ended voltage via a transformer or differ-
ential amplifier configuration. The ac performance of the AD9760
is optimum and specified using a differential transformer
coupled output in which the voltage swing at IOUTA and IOUTB is
,
can be used to determine the value of RSET
.
AVDD
OPTIONAL
BANDLIMITING
CAPACITOR
COMP1
AVDD
REFLO
+1.2V REF
50pF
limited to 0.5 V. If a single-ended unipolar output is desirable,
IOUTA should be selected.
REFIO
CURRENT
SOURCE
ARRAY
FS ADJ
1F
R
The distortion and noise performance of the AD9760 can be
enhanced when the AD9760 is configured for differential opera-
tion. The common-mode error sources of both IOUTA and IOUTB
can be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
SET
I
AD9760
REF
I
= (1.2 – V )/R
GC
SET
REF
V
GC
WITH V < V
AND 62.5A
I
625A
REF
GC
REFIO
Figure 44. Dual-Supply Gain Control Circuit
REV. B
–13–
AD9760
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed wave-
form increases. This is due to the first order cancellation of
various dynamic common-mode distortion mechanisms, digi-
tal feedthrough and noise.
clock cycle as long as the specified minimum times are met
although the location of these transition edges may affect digital
feedthrough and distortion performance. Best performance is
typically achieved when the input data transitions on the falling edge
of a 50% duty cycle clock.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the re-
constructed signal power to the load (i.e., assuming no source
termination). Since the output currents of IOUTA and IOUTB are
complementary, they become additive when processed differ-
entially. A properly selected transformer will allow the AD9760
to provide the required power and voltage levels to different
loads. Refer to Applying the AD9760 section for examples of
various output configurations.
The digital inputs are CMOS compatible with logic thresholds,
VTHRESHOLD set to approximately half the digital positive supply
(DVDD) or
VTHRESHOLD = DVDD/2 ( 20%)
The internal digital circuitry of the AD9760 is capable of oper-
ating over a digital supply range of 2.7 V to 5.5 V. As a result,
the digital inputs can also accommodate TTL levels when
DVDD is set to accommodate the maximum high level voltage
VOH(MAX). A DVDD of 3 V to 3.3 V will typically ensure proper
The output impedance of IOUTA and IOUTB is determined by the
equivalent parallel combination of the PMOS switches associ-
ated with the current sources and is typically 100 kΩ in parallel
with 5 pF. It is also slightly dependent on the output voltage
(i.e., VOUTA and VOUTB) due to the nature of a PMOS device.
As a result, maintaining IOUTA and/or IOUTB at a virtual ground
via an I-V op amp configuration will result in the optimum dc
linearity. Note the INL/DNL specifications for the AD9760 are
measured with IOUTA maintained at a virtual ground via an
op amp.
compatibility with most TTL logic families. Figure 46 shows the
equivalent digital input circuit for the data and clock inputs.
The sleep mode input is similar with the exception that it con-
tains an active pull-down circuit, ensuring that the AD9760
remains enabled if this input is left disconnected.
DVDD
DIGITAL
INPUT
I
OUTA and IOUTB also have a negative and positive voltage com-
pliance range that must be adhered to in order to achieve opti-
mum performance. The negative output compliance range of
–1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break-
down of the output stage and affect the reliability of the AD9760.
Figure 46. Equivalent Digital Input
Since the AD9760 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. The drivers of the digital
data interface circuitry should be specified to meet the mini-
mum setup and hold times of the AD9760 as well as its required
min/max input logic level thresholds. Typically, the selection of
the slowest logic family that satisfies the above conditions will
result in the lowest data feedthrough and noise.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from
its nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an
I
OUTFS = 2 mA. The optimum distortion performance for a
single-ended or differential output is achieved when the maximum
full-scale signal at IOUTA and IOUTB does not exceed 0.5 V. Ap-
plications requiring the AD9760’s output (i.e., VOUTA and/or
VOUTB) to extend its output compliance range should size RLOAD
accordingly. Operation beyond this compliance range will ad-
versely affect the AD9760’s linearity performance and subse-
quently degrade its distortion performance.
Digital signal paths should be kept short and run lengths
matched to avoid propagation delay mismatch. The insertion of
a low value resistor network (i.e., 20 Ω to 100 Ω) between the
AD9760 digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs that
contribute to data feedthrough. For longer run lengths and high
data update rates, strip line techniques with proper termination
resistors should be considered to maintain “clean” digital in-
puts. Also, operating the AD9760 with reduced logic swings and
a corresponding digital supply (DVDD) will also reduce data
feedthrough.
DIGITAL INPUTS
The AD9760’s digital input consists of 10 data input pins and a
clock input pin. The 10-bit parallel data inputs follow standard
positive binary coding where DB9 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). IOUTA pro-
duces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the full-
scale current split between the two outputs as a function of the
input code.
The external clock driver circuitry should provide the AD9760
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a recon-
structed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.
The digital interface is implemented using an edge-triggered
master slave latch. The DAC output is updated following the
rising edge of the clock as shown in Figure 1 and is designed to
support a clock rate as high as 125 MSPS. The clock can be
operated at any duty cycle that meets the specified latch pulse-
width. The setup and hold times can also be varied within the
REV. B
–14–
AD9760
Note, the clock input could also be driven via a sine wave that is
centered around the digital threshold (i.e., DVDD/2), and
meets the min/max logic threshold. This will typically result in a
slight degradation in the phase noise, that becomes more notice-
able at higher sampling rates and output frequencies. Also, at
higher sampling rates, the 20% tolerance of the digital logic
threshold should be considered since it will affect the effective
clock duty cycle and subsequently cut into the required data
setup and hold times.
Conversely, IDVDD is dependent on both the digital input wave-
form, fCLOCK, and digital supply DVDD. Figures 48 and 49
show IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note how IDVDD is reduced by more
than a factor of 2 when DVDD is reduced from 5 V to 3 V.
18
125MSPS
16
14
SLEEP MODE OPERATION
100MSPS
The AD9760 has a power-down function that turns off the out-
put current and reduces the supply current to less than 8.5 mA
over the specified supply range of 2.7 V to 5.5 V and tempera-
ture range. This mode can be activated by applying a logic level
“1” to the SLEEP pin. This digital input also contains an active
pull-down circuit that ensures that the AD9760 remains enabled
if this input is left disconnected. The SLEEP input with active
pull-down requires <40 µA of drive current.
12
10
8
50MSPS
6
4
25MSPS
2
5MSPS
The power-up and power-down characteristics of the AD9760
are dependent upon the value of the compensation capacitor
connected to COMP1. With a nominal value of 0.1 µF, the
AD9760 takes less than 5 µs to power down and approximately
3.25 ms to power back up. Note, the SLEEP MODE should not
be used when the external control amplifier is used as shown in
Figure 45.
0
0.01
0.1
RATIO (f
1
/f
)
OUT CLK
Figure 48. IDVDD vs. Ratio @ DVDD = 5 V
8
125MSPS
100MSPS
6
POWER DISSIPATION
The power dissipation, PD, of the AD9760 is dependent on
several factors that include: (1) AVDD and DVDD, the power
supply voltages; (2) IOUTFS, the full-scale current output; (3)
fCLOCK, the update rate; (4) and the reconstructed digital input
waveform. The power dissipation is directly proportional to the
analog supply current, IAVDD, and the digital supply current,
IDVDD. IAVDD is directly proportional to IOUTFS as shown in Fig-
4
2
50MSPS
25MSPS
5MSPS
ure 47 and is insensitive to fCLOCK
.
0
0.01
0.1
RATIO (f
1
30
/f
)
OUT CLK
25
20
Figure 49. IDVDD vs. Ratio @ DVDD = 3 V
15
10
5
0
2
4
6
8
10
12
– mA
14
16
18
20
I
OUTFS
Figure 47. IAVDD vs. IOUTFS
REV. B
–15–
AD9760
APPLYING THE AD9760
DIFFERENTIAL USING AN OP AMP
OUTPUT CONFIGURATIONS
An op amp can also be used to perform a differential to single-
ended conversion as shown in Figure 51. The AD9760 is con-
figured with two equal load resistors, RLOAD, of 25 Ω. The
differential voltage developed across IOUTA and IOUTB is con-
verted to a single-ended signal via the differential op amp con-
figuration. An optional capacitor can be installed across IOUTA
and IOUTB, forming a real pole in a low-pass filter. The addition
of this capacitor also enhances the op amps distortion perfor-
mance by preventing the DACs high slewing output from over-
loading the op amp’s input.
The following sections illustrate some typical output configura-
tions for the AD9760. Unless otherwise noted, it is assumed
that IOUTFS is set to a nominal 20 mA. For applications requir-
ing the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the opti-
mum high frequency performance and is recommended for any
application allowing for ac coupling. The differential op amp
configuration is suitable for applications requiring dc coupling, a
bipolar output, signal gain and/or level shifting.
500⍀
AD9760
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor, RLOAD, referred to ACOM. This configura-
tion may be more suitable for a single-supply system requiring
a dc coupled, ground referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter, thus convert-
ing IOUTA or IOUTB into a negative unipolar voltage. This con-
figuration provides the best dc linearity since IOUTA or IOUTB is
maintained at a virtual ground. Note that IOUTA provides slightly
225⍀
22
I
OUTA
AD8047
225⍀
21
I
OUTB
C
OPT
500⍀
25⍀
25⍀
Figure 51. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differ-
ential op amp circuit using the AD8047 is configured to provide
some additional signal gain. The op amp must operate off of a
dual supply since its output is approximately 1.0 V. A high
speed amplifier capable of preserving the differential perfor-
mance of the AD9760 while meeting other system level objec-
tives (i.e., cost, power) should be selected. The op amps
differential gain, its gain setting resistor values, and full-scale
output swing capabilities should all be considered when opti-
mizing this circuit.
better performance than IOUTB
.
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-to-
single-ended signal conversion as shown in Figure 50. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the transformer’s passband. An RF transformer such
as the Mini-Circuits T1-1T provides excellent rejection of com-
mon-mode distortion (i.e., even-order harmonics) and noise
over a wide frequency range. It also provides electrical isolation
and the ability to deliver twice the power to the load. Trans-
formers with different impedance ratios may also be used for
impedance matching purposes. Note that the transformer
provides ac coupling only.
The differential circuit shown in Figure 52 provides the neces-
sary level-shifting required in a single supply system. In this
case, AVDD which is the positive analog supply for both the
AD9760 and the op amp is also used to level-shift the differ-
ential output of the AD9760 to midsupply (i.e., AVDD/2). The
AD8041 is a suitable op amp for this application.
MINI-CIRCUITS
T1-1T
22
21
I
OUTA
500⍀
R
AD9760
LOAD
AD9760
225⍀
22
I
I
OUTA
OUTB
OPTIONAL R
AD8041
1k⍀
DIFF
225⍀
21
I
OUTB
C
OPT
Figure 50. Differential Output Using a Transformer
AVDD
25⍀
25⍀
1k⍀
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages appear-
ing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetri-
cally around ACOM and should be maintained with the specified
output compliance range of the AD9760. A differential resistor,
RDIFF, may be inserted in applications where the output of the
transformer is connected to the load, RLOAD, via a passive re-
construction filter or cable. RDIFF is determined by the
transformer’s impedance ratio and provides the proper source
termination that results in a low VSWR. Note that approxi-
Figure 52. Single-Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 53 shows the AD9760 configured to provide a unipolar
output range of approximately 0 V to +0.5 V for a doubly termi-
nated 50 Ω cable since the nominal full-scale current, IOUTFS, of
20 mA flows through the equivalent RLOAD of 25 Ω. In this case,
LOAD represents the equivalent load resistance seen by IOUTA or
OUTB. The unused output (IOUTA or IOUTB) can be connected
to ACOM directly or via a matching RLOAD. Different values of
R
I
mately half the signal power will be dissipated across RDIFF
.
REV. B
–16–
AD9760
the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be de-
coupled to ACOM, the analog common, as close to the chip as
physically possible. Similarly, DVDD, the digital supply, should
be decoupled to DCOM as close as physically possible.
IOUTFS and RLOAD can be selected as long as the positive compli-
ance range is adhered to. One additional consideration in this
mode is the integral nonlinearity (INL) as discussed in the Ana-
log Output section of this data sheet. For optimum INL perfor-
mance, the single-ended, buffered voltage output configuration
is suggested.
For those applications that require a single +5 V or +3 V supply
for both the analog and digital supply, a clean analog supply
may be generated using the circuit shown in Figure 55. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained using low
ESR type electrolytic and tantalum capacitors.
AD9760
I
= 20mA
OUTFS
V
= 0 TO +0.5V
OUTA
I
22
21
OUTA
50⍀
50⍀
I
OUTB
25⍀
FERRITE
BEADS
AVDD
TTL/CMOS
LOGIC
CIRCUITS
Figure 53. 0 V to +0.5 V Unbuffered Voltage Output
10-22F
TANT.
0.1F
CER.
100F
ELECT.
ACOM
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 54 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9760 output current. U1 maintains IOUTA (or IOUTB) at a
virtual ground, thus minimizing the nonlinear output impedance
effect on the DAC’s INL performance as discussed in the Ana-
log Output section. Although this single-ended configuration
typically provides the best dc linearity performance, its ac distor-
tion performance at higher DAC update rates may be limited by
U1’s slewing capabilities. U1 provides a negative unipolar out-
put voltage and its full-scale output voltage is simply the product
of RFB and IOUTFS. The full-scale output should be set within
U1’s voltage output swing capabilities by scaling IOUTFS and/or
+5V OR +3V
POWER SUPPLY
Figure 55. Differential LC Filter for Single +5 V or +3 V
Applications
Maintaining low noise on power supplies and ground is critical
to obtain optimum results from the AD9760. If properly imple-
mented, ground planes can perform a host of functions on high
speed circuit boards: bypassing, shielding, current transport,
etc. In mixed signal design, the analog and digital portions of
the board should be distinct from each other, with the analog
ground plane confined to the areas covering the analog signal
traces, and the digital ground plane confined areas covering the
digital interconnects.
R
FB. An improvement in ac distortion performance may result
with a reduced IOUTFS since the signal current U1 will be required
to sink will be subsequently reduced.
All analog ground pins of the DAC, reference and other analog
components should be tied directly to the analog ground plane.
The two ground planes should be connected by a path 1/8 to
1/4 inch wide underneath or within 1/2 inch of the DAC to
maintain optimum performance. Care should be taken to ensure
that the ground plane is uninterrupted over crucial signal paths.
On the digital side, this includes the digital input lines running
to the DAC as well as any clock signals. On the analog side, this
includes the DAC output signal, reference signal and the supply
feeders.
C
OPT
R
200⍀
FB
I
= 10mA
AD9760
OUTFS
22
21
I
OUTA
U1
V
= I
؋
R OUT
OUTFS FB
I
OUTB
200⍀
The use of wide runs or planes in the routing of power lines is
also recommended. This serves the dual role of providing a low
series impedance power supply to the part and providing some
“free” capacitive decoupling to the appropriate ground plane. It
is essential that care be taken in the layout of signal and power
ground interconnects to avoid inducing extraneous voltage
drops in the signal ground paths. It is recommended that all
connections be short, direct and as physically close to the pack-
age as possible to minimize the sharing of conduction paths
between different currents. When runs exceed an inch in length,
strip line techniques with proper termination resistor should be
considered. The necessity and value of this resistor will be de-
pendent upon the logic family used.
Figure 54. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS
In systems seeking to simultaneously achieve high speed and
high performance, the implementation and construction of the
printed circuit board design is often as important as the circuit
design. Proper RF techniques must be used in device selection,
placement and routing, and supply bypassing and grounding.
The evaluation board for the AD9760, which uses a four-layer
PC board, serves as a good example for the above-mentioned
considerations. Figures 60–65 illustrate the recommended
printed circuit board ground, power and signal plane layouts
that are implemented on the AD9760 evaluation board.
For a more detailed discussion of the implementation and con-
struction of high speed, mixed signal printed circuit boards,
refer to Analog Devices’ application notes AN-280 and AN-333.
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9760 features
separate analog and digital supply and ground pins to optimize
REV. B
–17–
AD9760
APPLICATIONS
Using the AD9760 for QAM Modulation
REFLO
QAM is one of the most widely used digital modulation schemes
in digital communication systems. This modulation technique
can be found in both FDM spreadspectrum (i.e., CDMA) based
systems. A QAM signal is a carrier frequency that is both
modulated in amplitude (i.e., AM modulation) and in phase
(i.e., PM modulation). It can be generated by independently
modulating two carriers of identical frequency but with a 90°
phase difference. This results in an in-phase (I) carrier compo-
nent and a quadrature (Q) carrier component at a 90° phase
shift with respect to the I component. The I and Q components
are then summed to provide a QAM signal at the specified car-
rier frequency.
TO
I
I
REFIO
OUTA
U1
I-CHANNEL
NYQUIST
FILTER
AND MIXER
FS ADJ
OUTB
R
SET
2k⍀*
CLOCK
50⍀**
LOAD
50⍀**
LOAD
R
R
CLOCK
R
CAL1
AVDD
50⍀
REFLO CLOCK
TO
I
REFIO
OUTA
NYQUIST
FILTER
AND MIXER
U2
0.1F
Q-CHANNEL
I
FS ADJ
OUTB
R
2k⍀*
SET
50⍀**
LOAD
50⍀**
LOAD
R
R
R
CAL2
100⍀
* OHMTEK ORNA1001F
** OHMTEK TOMC1603-50F
A common and traditional implementation of a QAM modu-
lator is shown in Figure 56. The modulation is performed in the
analog domain in which two DACs are used to generate the
baseband I and Q components, respectively. Each component is
then typically applied to a Nyquist filter before being applied to
a quadrature mixer. The matching Nyquist filters shape and
limit each component’s spectral envelope while minimizing
intersymbol interference. The DAC is typically updated at the
QAM symbol rate or possibly a multiple of it if an interpolating
filter precedes the DAC. The use of an interpolating filter typi-
cally eases the implementation and complexity of the analog
filter, which can be a significant contributor to mismatches in
gain and phase between the two baseband channels. A quadra-
ture mixer modulates the I and Q components with in-phase
and quadrature phase carrier frequency and sums the two out-
puts to provide the QAM signal.
Figure 57. Baseband QAM Implementation Using Two
AD9760s
are Digital ASICs which implement other digital modulation
schemes such as PSK and FSK. This digital implementation has
the benefit of generating perfectly matched I and Q components
in terms of gain and phase, which is essential in maintaining
optimum performance in a communication system. In this
implementation, the reconstruction DAC must be operating at a
sufficiently high clock rate to accommodate the highest specified
QAM carrier frequency. Figure 58 shows a block diagram of
such an implementation using the AD9760.
10
12
I DATA
STEL-1130
QAM
TO
LPF
12
MIXER
Q DATA
50⍀
50⍀
AD9760
10
12 12
SIN
AD9760
COS
DSP
OR
ASIC
0
CARRIER
FREQUENCY
TO
MIXER
12
Σ
STEL-1177
NCO
CARRIER
FREQUENCY
90
10
AD9760
CLOCK
NYQUIST
FILTERS
QUADRATURE
MODULATOR
Figure 58. Digital QAM Architecture
Figure 56. Typical Analog QAM Architecture
AD9760 EVALUATION BOARD
General Description
In this implementation, it is much more difficult to maintain
proper gain and phase matching between the I and Q channels.
The circuit implementation shown in Figure 57 helps improve
on the matching and temperature stability characteristics be-
tween the I and Q channels. Using a single voltage reference
derived from U1 to set the gain for both the I and Q channels
will improve the gain matching and stability. Further enhance-
ments in gain matching and stability are achieved by using sepa-
The AD9760-EB is an evaluation board for the AD9760 10-bit
D/A converter. Careful attention to layout and circuit design,
combined with a prototyping area, allow the user to easily and
effectively evaluate the AD9760 in any application where high
resolution, high speed conversion is required.
This board allows the user the flexibility to operate the AD9760
in various configurations. Possible output configurations include
transformer coupled, resistor terminated, inverting/noninverting
and differential amplifier outputs. The digital inputs are designed
to be driven directly from various word generators with the on-
board option to add a resistor network for proper load termina-
tion. Provisions are also made to operate the AD9760 with
either the internal or external reference or to exercise the power-
down feature.
rate matching resistor networks for both RSET and RLOAD
.
Additional trim capability via RCAL1 and RCAL2 can be added to
compensate for any initial mismatch in gain between the two
channels. This may be attributed to any mismatch between U1
and U2’s gain setting resistor (RSET), effective load resistance,
(RLOAD), and/or voltage offset of each DAC’s control amplifier.
The differential voltage outputs of U1 and U2 are fed into their
respective differential inputs of a quadrature mixer via matching
50 Ω filter networks.
Refer to the application note AN-420, “Using the AD9760/
AD9760/AD9764-EB Evaluation Board,” for a thorough
description and operating instructions for the AD9760 evalua-
tion board.
It is also possible to generate a QAM signal completely in the
digital domain via a DSP or ASIC, in which case only a single
DAC of sufficient resolution and performance is required to
reconstruct the QAM signal. Also available from several vendors
REV. B
–18–
AD9760
Figure 59. Evaluation Board Schematic
REV. B
–19–
AD9760
Figure 60. Silkscreen Layer—Top
Figure 61. Component Side PCB Layout (Layer 1)
REV. B
–20–
AD9760
Figure 62. Ground Plane PCB Layout (Layer 2)
Figure 63. Power Plane PCB Layout (Layer 3)
REV. B
–21–
AD9760
Figure 64. Solder Side PCB Layout (Layer 4)
Figure 65. Silkscreen Layer—Bottom
–22–
REV. B
AD9760
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead, 300 Mil SOIC
(R-28)
0.7125 (18.10)
0.6969 (17.70)
28
15
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
1
14
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
؋
45؇ 0.0500 (1.27)
0.0157 (0.40)
8؇
0؇
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
28-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-28)
0.386 (9.80)
0.378 (9.60)
15
14
28
1
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8؇
0؇
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
REV. B
–23–
相关型号：
AD9760ARZ
PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28, 0.300 INCH, SOIC-28
ROCHESTER
AD9760ARZ50
PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28, 0.300 INCH, SOIC-28
ROCHESTER
AD9760ARZRL
PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28, 0.300 INCH, SOIC-28
ROCHESTER
AD9761ARS
DUAL, PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28, SSOP-28
ROCHESTER
©2020 ICPDF网 联系我们和版权申明