AD9684BBPZ-500_技术文档

14-Bit, 500 MSPS LVDS,

Dual Analog-to-Digital Converter

Data Sheet

AD9684

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD1

(1.25V)

AVDD2

(2.5V)

AVDD3

(3.3V)

DVDD

DRVDD

(1.25V)

SPIVDD

Parallel LVDS (DDR) outputs

(1.25V)

(1.8V TO 3.4V)

1.1 W total power per channel at 500 MSPS (default settings)

SFDR = 85 dBFS at 170 MHz f_IN(500 MSPS)

SNR = 68.6 dBFS at 170 MHz f_IN(500 MSPS)

ENOB = 10.9 bits at 170 MHz f_IN

DNL = ±0.5 LSB

INL = ±±.5 LSB

Noise density = −153 dBFS/Hz at 500 MSPS

1.±5 V, ±.50 V, and 3.3 V supply operation

No missing codes

BUFFER

VIN+A

VIN–A

14

D0±

ADC

D1±

CORE

D2±

DIGITAL

DOWN-

D3±

D4±

CONVERTER

D5±

16

FD_A

FD_B

D6±

D7±

D8±

D9±

D10±

D11±

D12±

D13±

DCO±

STATUS±

DIGITAL

DOWN-

CONVERTER

BUFFER

VIN+B

VIN–B

14

ADC

CORE

CONTROL

REGISTERS

Internal analog-to-digital converter (ADC) voltage reference

Flexible input range and termination impedance

1.46 V p-p to ±.06 V p-p (±.06 V p-p nominal)

400 Ω, ±00 Ω, 100 Ω, and 50 Ω differential

SYNC± input allows multichip synchronization

DDR LVDS (ANSI-644 levels) outputs

± GHz usable analog input full power bandwidth

>96 dB channel isolation/crosstalk

Amplitude detect bits for efficient AGC implementation

Two integrated wideband digital processors per channel

1±-bit numerically controlled oscillator (NCO)

3 cascaded half-band filters

FAST

DETECT

V_1P0

SYNC+

SYNC–

SIGNAL MONITOR

CLOCK

GENERATION

CLK+

CLK–

SPI CONTROL

÷2

÷4

÷8

PDWN/

STBY

AD9684

DGND

AGND DRGND

SDIO

SCLK CSB

Figure 1.

GENERAL DESCRIPTION

The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has

an on-chip buffer and a sample-and-hold circuit designed for

low power, small size, and ease of use. This product is designed

for sampling wide bandwidth analog signals. The AD9684 is

optimized for wide input bandwidth, a high sampling rate,

excellent linearity, and low power in a small package.

Differential clock inputs

Serial port control

Integer clock divide by ±, 4, or 8

Small signal dither

APPLICATIONS

The dual ADC cores feature a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth buffered inputs, supporting a

variety of user selectable input ranges. An integrated voltage

reference eases design considerations. Each ADC data output is

internally connected to an optional decimate by 2 block.

Communications

Diversity multiband, multimode digital receivers

3G/4G, TD-SCDMA, W-CDMA, MC-GSM, LTE

General-purpose software radios

Ultrawideband satellite receiver

Instrumentation (spectrum analyzers, network analyzers,

integrated RF test solutions)

Radar

Digital oscilloscopes

High speed data acquisition systems

DOCSIS CMTS upstream receiver paths

HFC digital reverse path receivers

The analog input and clock signals are differential inputs. Each

ADC data output is internally connected to two digital

downconverters (DDCs). Each DDC consists of four cascaded

signal processing stages: a 12-bit frequency translator (NCO),

and three half-band decimation filters supporting a divide by

factor of two, four, and eight.

Rev. 0

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Tel: 781.3±9.4700

Technical Support

www.analog.com

AD9684* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

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DESIGN RESOURCES

• AD9684 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

EVALUATION KITS

• AD9684 Evaluation Board

DOCUMENTATION

Application Notes

DISCUSSIONS

View all AD9684 EngineerZone Discussions.

• AN-1386: The Effects of the Sample Clock Spectrum on

Measured Signal Spectrum in ADCs, a Simple

Mathematical Description

SAMPLE AND BUY

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Data Sheet

• AD9684: 14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital

Converter

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AD9684

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

DDC I/Q Output Selection ....................................................... 31

DDC General Description ........................................................ 31

Frequency Translation ................................................................... 37

General Description................................................................... 37

DDC NCO Plus Mixer Loss and SFDR................................... 38

Numerically Controlled Oscillator .......................................... 38

FIR Filters ........................................................................................ 40

General Description................................................................... 40

Half-Band Filters ........................................................................ 41

DDC Gain Stage ......................................................................... 42

DDC Complex to Real Conversion Block............................... 42

DDC Example Configurations ................................................. 43

Digital Outputs ............................................................................... 47

Digital Outputs ........................................................................... 47

ADC Overrange.......................................................................... 47

Multichip Synchronization............................................................ 48

SYNC Setup and Hold Window Monitor............................. 49

Test Modes....................................................................................... 51

ADC Test Modes ........................................................................ 51

Serial Port Interface (SPI).............................................................. 52

Configuration Using the SPI..................................................... 52

Hardware Interface..................................................................... 52

SPI Accessible Features.............................................................. 52

Memory Map .................................................................................. 53

Reading the Memory Map Register Table............................... 53

Memory Map Register Table..................................................... 54

Applications Information .............................................................. 63

Power Supply Recommendations............................................. 63

Outline Dimensions....................................................................... 64

Ordering Guide .......................................................................... 64

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Product Highlights ........................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications.......................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 7

Timing Specifications .................................................................. 8

Absolute Maximum Ratings.......................................................... 16

Thermal Characteristics ............................................................ 16

ESD Caution................................................................................ 16

Pin Configuration and Function Descriptions........................... 17

Typical Performance Characteristics ........................................... 19

Equivalent Circuits ......................................................................... 22

Theory of Operation ...................................................................... 24

ADC Architecture ...................................................................... 24

Analog Input Considerations.................................................... 24

Voltage Reference ....................................................................... 26

Clock Input Considerations ...................................................... 27

Power-Down/Standby Mode..................................................... 28

Temperature Diode .................................................................... 28

ADC Overrange and Fast Detect.................................................. 29

ADC Overrange.......................................................................... 29

Fast Threshold Detection (FD_A and FD_B) ........................ 29

Signal Monitor ................................................................................ 30

Digital Downconverters (DDCs).................................................. 31

DDC I/Q Input Selection .......................................................... 31

REVISION HISTORY

5/15—Revision 0: Initial Version

Rev. 0 | Page 2 of 64

Data Sheet

AD9684

The AD9684 has several functions that simplify the automatic

gain control (AGC) function in a communications receiver. The

programmable threshold detector allows monitoring of the

incoming signal power using the fast detect output bits of the

ADC. If the input signal level exceeds the programmable

threshold, the fast detect indicator goes high. Because this

threshold indicator has low latency, the user can quickly reduce

the system gain to avoid an overrange condition at the ADC

input. In addition to the fast detect outputs, the AD9684 also

offers signal monitoring capability. The signal monitoring block

provides additional information about the signal that the ADC

digitized.

The AD9684 has flexible power-down options that allow

significant power savings when desired. All of these features can

be programmed using a 1.8 V to 3.4 V capable 3-wire serial port

interface (SPI).

The AD9684 is available in a Pb-free, 196-ball ball grid array

(BGA) and is specified over the −40°C to +85°C industrial

temperature range. This product is protected by a U.S. patent.

PRODUCT HIGHLIGHTS

1. Wide full power bandwidth supports intermediate

frequency (IF) sampling of signals up to 2 GHz.

2. Buffered inputs with programmable input termination ease

filter design and implementation.

3. Four integrated wideband decimation filters and NCO

blocks supporting multiband receivers.

4. Flexible SPI controls various product features and functions

to meet specific system requirements.

5. Programmable fast overrange detection and signal

The dual ADC output data is routed directly to the one external,

14-bit LVDS output port, supporting double data rate (DDR)

formatting. An external data clock and status bit are offered for

data capture flexibility.

The LVDS outputs have several configurations, depending on

the acceptable rate of the receiving logic device and the sampling

rate of the ADC. Multiple device synchronization is supported

through the SYNC input pins.

monitoring.

6. SYNC input allows synchronization of multiple devices.

7. 12 mm × 12 mm, 196-ball BGA_ED.

Rev. 0 | Page 3 of 64

AD9684

Data Sheet

SPECIFICATIONS

DC SPECIFICATIONS

AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling

rate (500 MSPS), 1.7 V p-p full-scale differential input, 1.0 V internal reference, A_IN= −1.0 dBFS, default SPI settings, T_A= 25°C, unless

otherwise noted.

Table 1.

Parameter

Temperature Min

Typ

Max

Unit

RESOLUTION

Full

14

Bits

ACCURACY

No Missing Codes

Offset Error

Offset Matching

Gain Error

Gain Matching

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

TEMPERATURE DRIFT

Offset Error

Full

Guaranteed

−0.3

−6.5

0

+0.3

+6.5

+5.0

+0.7

+5.0

% FSR

LSB

−0.6

−4.5

0.5

2.5

LSB

25°C

Full

3

−39

1.0

ppm/°C

V

Gain Error

INTERNAL VOLTAGE REFERENCE

INPUT-REFERRED NOISE

V_REF= 1.0 V

25°C

2.63

LSB rms

ANALOG INPUTS

Differential Input Voltage Range (Programmable)

Full

1.46

2.06

2.05

1.5

2

2.06

V p-p

V

pF

Common-Mode Voltage (V_CM

)

25°C

Differential Input Capacitance¹

Analog Input Full Power Bandwidth

GHz

POWER SUPPLY

AVDD1

AVDD2

AVDD3

DVDD

DRVDD

SPIVDD

I_AVDD1

I_AVDD2

I_AVDD3

I_DVDD

I_DRVDD

I_SPIVDD

Full

1.22

2.44

3.2

1.22

1.25

2.50

3.3

1.25

1.8

448

396

103

108

106

2

1.28

2.56

3.4

1.28

3.4

503

455

124

127

119

6

V

mA

POWER CONSUMPTION

Total Power Dissipation²

Power-Down Dissipation

Standby

Full

2.2

710

1.0

W

mW

W

¹Differential capacitance is measured between the VIN+x and VIN−x pins (x = A or B).

²Parallel interleaved LVDS mode. The power dissipation on DRVDD changes with the output data mode used.

Rev. 0 | Page 4 of 64

Data Sheet

AD9684

AC SPECIFICATIONS

AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling

rate (500 MSPS), 1.7 V p-p full-scale differential input, 1.0 V internal reference, A_IN= −1.0 dBFS, default SPI settings, T_A= 25°C, unless

otherwise noted.

Table 2.

Parameter¹

Temperature Min

Typ

Max

Unit

ANALOG INPUT FULL SCALE

NOISE DENSITY²

SIGNAL-TO-NOISE RATIO (SNR)³

f_IN= 10 MHz

f_IN= 170 MHz

f_IN= 340 MHz

f_IN= 450 MHz

f_IN= 765 MHz

f_IN= 985 MHz

f_IN= 1950 MHz

Full

2.06

−153

V p-p

dBFS/Hz

25°C

Full

69.2

68.6

68.4

68.0

64.4

63.8

60.5

dBFS

67.5

25°C

SIGNAL-TO-NOISE RATIO AND DISTORTION RATIO (SINAD)³

f_IN= 10 MHz

f_IN= 170 MHz

f_IN= 340 MHz

f_IN= 450 MHz

f_IN= 765 MHz

f_IN= 985 MHz

f_IN= 1950 MHz

25°C

Full

68.7

68.5

67.6

67.2

63.8

62.5

58.3

dBFS

67

25°C

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 10 MHz

f_IN= 170 MHz

f_IN= 340 MHz

f_IN= 450 MHz

f_IN= 765 MHz

f_IN= 985 MHz

f_IN= 1950 MHz

25°C

Full

11.1

10.9

10.8

10.3

10.1

9.5

Bits

10.8

25°C

SPURIOUS-FREE DYNAMIC RANGE (SFDR)³

f_IN= 10 MHz

f_IN= 170 MHz

f_IN= 340 MHz

f_IN= 450 MHz

f_IN= 765 MHz

f_IN= 985 MHz

f_IN= 1950 MHz

25°C

Full

83

85

82

86

81

76

69

dBFS

76

25°C

WORST HARMONIC, SECOND OR THIRD³

f_IN= 10 MHz

f_IN= 170 MHz

f_IN= 340 MHz

f_IN= 450 MHz

f_IN= 765 MHz

f_IN= 985 MHz

f_IN= 1950 MHz

25°C

Full

−83

−85

−82

−86

−81

−76

−69

dBFS

−76

25°C

Rev. 0 | Page 5 of 64

AD9684

Data Sheet

Parameter¹

Temperature Min

Typ

Max

Unit

WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC³

f_IN= 10 MHz

f_IN= 170 MHz

f_IN= 340 MHz

f_IN= 450 MHz

25°C

Full

−93

−92

−90

−92

−89

−85

dBFS

−76

25°C

f_IN= 765 MHz

f_IN= 985 MHz

f_IN= 1950 MHz

TWO-TONE INTERMODULATION DISTORTION (IMD), A_IN1AND A_IN2= −7 dBFS

f_IN1= 185 MHz, f_IN2= 188 MHz

f_IN1= 338 MHz, f_IN2= 341 MHz

CROSSTALK⁴

25°C

−88

−87

96

dBFS

dB

FULL POWER BANDWIDTH

2

GHz

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

²Noise density is measured at a low analog input frequency (30 MHz).

³See Table 9 for the recommended settings for full-scale voltage and buffer current control.

⁴Crosstalk is measured at 170 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel.

DIGITAL SPECIFICATIONS

AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling

rate (500 MSPS), 1.7 V p-p full-scale differential input, 1.0 V internal reference, A_IN= −1.0 dBFS, default SPI settings, T_A= 25°C, unless

otherwise noted.

Table 3.

Parameter

Temperature

Min

Typ

LVDS/LVPECL

1200

0.85

35

Max

1800

2.5

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

Differential Input Voltage

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

Full

600

mV p-p

V

kΩ

pF

SYNC INPUTS (SYNC+, SYNC−)

Logic Compliance

Full

LVDS/LVPECL

Differential Input Voltage

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance (Differential)

LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY)

Logic Compliance

Logic 1 Voltage

Logic 0 Voltage

Input Resistance

400

0.6

1200

0.85

35

1800

2.0

mV p-p

V

kΩ

pF

2.5

Full

CMOS

0.8 × SPIVDD

0.2 × SPIVDD

30

V

kΩ

0

LOGIC OUTPUT (SDIO)

Logic Compliance

Logic 1 Voltage (I_OH= 800 µA)

Logic 0 Voltage (I_OL= 50 µA)

LOGIC OUTPUTS (FD_A, FD_B)

Logic Compliance

Logic 1 Voltage

Logic 0 Voltage

Input Resistance

Full

CMOS

0.8 × SPIVDD

0.2 × SPIVDD

V

Full

CMOS

SPIVDD

0

30

0.8

0

V

kΩ

Rev. 0 | Page 6 of 64

Data Sheet

AD9684

Parameter

Temperature

Min

Typ

Max

Unit

DIGITAL OUTPUTS (Dx ,¹DCO , STATUS )

Logic Compliance

Differential Output Voltage

Full

LVDS

230

430

mV p-p

Output Common-Mode Voltage (V_CM

AC-Coupled

)

25°C

Full

0

1.8

+100

V

Short-Circuit Current (I_DSHORT

Differential Return Loss (RL_DIFF

Common-Mode Return Loss (RL_CM

)

−100

8

6

mA

dB

Ω

2

)

2

)

Differential Termination Impedance

80

100

120

¹Where x = 0 to 13.

²Differential and common-mode return loss is measured from 100 MHz to 0.75 MHz × baud rate.

SWITCHING SPECIFICATIONS

AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling

rate, 1.7 V p-p full-scale differential input, 1.0 V internal reference, A_IN= −1.0 dBFS, default SPI settings, T_A= 25°C, unless otherwise

noted.

Table 4.

Parameter

Temperature

Min

Typ

Max

Unit

CLOCK

Clock Rate (at CLK+/CLK− Pins)

Maximum Sample Rate¹

Minimum Sample Rate²

Clock Pulse Width

High

Full

0.25

500

250

4

GHz

MSPS

Full

1000

ps

Low

LVDS DATA OUTPUT PARAMETERS

Data Propagation Delay (t_PD)³

DCO Propagation Delay (t_DCO

Full

2.225

2.2

ns

3

)

DCO to Data Skew

Rising Edge Data (t_SKEWR

Falling Edge Data (t_SKEWF

3

)

Full

−150

850

−25

1.025

2.2

−25

2.225

2.2

+100

1100

ps

ns

ps

ns

3

)

4

STATUS Propagation Delay (t_STATUS

)

4

DCO to STATUS Skew (t_FRAME

Data Propagation Delay (t_PD)³

)

−150

+100

3

DCO Propagation Delay (t_DCO

LATENCY⁵

)

Pipeline Latency

Full

35

Clock cycles

Fast Detect Latency

HB1 Filter Latency³

HB1 + HB2 Filter Latency³

28

50

101

217

433

28

HB1 + HB2 + HB3 Filter Latency³

HB1 + HB2 + HB3 + HB4 Filter Latency³

Fast Detect Latency

Wake-Up Time⁶

Standby

Power-Down

25°C

1

ms

4

Rev. 0 | Page 7 of 64

AD9684

Data Sheet

Parameter

Temperature

Min

Typ

Max

Unit

APERTURE

Aperture Delay (t_A)

Aperture Uncertainty (Jitter, t_j)

Out of Range Recovery Time

Full

530

55

1

ps

fs rms

Clock Cycles

¹The maximum sample rate is the clock rate after the divider.

²The minimum sample rate operates at 300 MSPS.

³This specification is valid for parallel interleaved, channel multiplexed, and byte mode output modes.

⁴This specification is valid for byte mode output mode only.

⁵No DDCs used.

⁶Wake-up time is defined as the time required to return to normal operation from power-down mode or standby mode.

TIMING SPECIFICATIONS

Table 5.

Parameter

Description

Min Typ Max Unit

CLK to SYNC TIMING REQUIREMENTS

See Figure 2

t_{SU_SR}

t_{H_SR}

Device clock to SYNC setup time

Device clock to SYNC hold time

117

−96

ps

SPI TIMING REQUIREMENTS

See Figure 3

t_DS

t_DH

t_CLK

t_S

t_H

t_HIGH

t_LOW

t_{EN_SDIO}

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

Minimum period that SCLK must be in a logic high state

Minimum period that SCLK must be in a logic low state

Time required for the SDIO pin to switch from an input to an

2

40

2

10

ns

output relative to the SCLK falling edge (not shown in Figure 3)

t_{DIS_SDIO}

Time required for the SDIO pin to switch from an output to an

input relative to the SCLK rising edge (not shown in Figure 3)

10

ns

Timing Diagrams

CLK–

CLK+

t_{SU_SR}

t_{H_SR}

SYNC–

SYNC+

Figure 2. SYNC Setup and Hold Timing

t_DS

t_HIGH

t_CLK

t_H

t_S

t_DH

t_LOW

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

A14

A13

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

DON’T CARE

Figure 3. Serial Port Interface Timing Diagram

Rev. 0 | Page 8 of 64

Data Sheet

AD9684

APERTURE DELAY

N + x

N + 39

N + 35

N

N + 36

N + 40

N – 1

VIN±x

N + 37

N + y

N + 38

N + 41

SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF

THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET

SYNC+

SYNC–

CLK+

CLK–

t_CLK

FIXED DELAY FROM SYNC EVENT TO DCO KNOWN PHASE

CONSTANT LATENCY = X CLK CYCLES

t_DCO

t_PD

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

1

90° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

2

270° PHASE ADJUST

t_SKEWR

t_SKEWF

CONVERTER 0 CONVERTER 0 CONVERTER 0 CONVERTER 0 CONVERTER 0

SAMPLE

[N]

SAMPLE

[N + 1]

SAMPLE

[N + 2]

SAMPLE

[N + 3]

SAMPLE

[N + 4]

STATUS+

(OVERRANGE/STATUS BIT)

STATUS

D13

STATUS

D13

STATUS

D13

STATUS

D13

STATUS

D13

STATUS

D13

STATUS

D13

STATUS–

D13±

D0±

D0

1

90° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.

270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.

2

Figure 4. Parallel Interleaved Mode—One Converter, ≤14-Bit Data

Rev. 0 | Page 9 of 64

AD9684

Data Sheet

APERTURE DELAY

N + 36

N

N + 38

VIN±x

N + x

N + 37

SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF

THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET

SYNC+

SYNC–

CLK+

CLK–

CONSTANT LATENCY = X CLK CYCLES

t_DCO

t_CLK

t_PD

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

t_SKEWR

t_SKEWF

STATUS BIT SELECTED BY

REGISTER 0x559, BITS[2:0]

IN THE REGISTER MAP

CONVERTER 0 CONVERTER 1 CONVERTER 0 CONVERTER 1 CONVERTER 0

SAMPLE

[N]

SAMPLE

[N]

SAMPLE

[N + 1]

SAMPLE

[N + 1]

SAMPLE

[N + 2]

STATUS+

(OVERRANGE/STATUS BIT)

STATUS

D13

STATUS STATUS

STATUS

D13

STATUS

D13

STATUS

D13

STATUS

D13

STATUS–

D13

D13±

D0±

D0

Figure 5. Parallel Interleaved Mode—Two Converters, ≤14-Bit Data, Output Sample Rate < 625 MSPS

Rev. 0 | Page 10 of 64

Data Sheet

AD9684

APERTURE DELAY

N + 36

N

N + 38

VIN±x

N + x

N + 37

SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF

THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET

SYNC+

SYNC–

CLK+

CLK–

CONSTANT LATENCY = X CLK CYCLES

t_DCO

t_PD

t_CLK

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

t_SKEWR

t_SKEWF

STATUS BIT SELECTED BY

REGISTER 0x559, BITS[2:0]

IN THE REGISTER MAP

CONVERTERS

SAMPLE

[N]

CONVERTERS CONVERTERS CONVERTERS

SAMPLE

[N]

CONVERTERS

SAMPLE

[N + 2]

SAMPLE

[N + 1]

SAMPLE

[N + 1]

STATUS+

(OVERRANGE/STAUS BIT)

STATUS

S[N – x]

STATUS STATUS

STATUS

STATUS–

CHANNEL A D12±/D13±

S[N – y]

S[N]

S[N + 1]

S[N + 2]

S[N – 1]

(ODD BITS) (EVEN BITS)

(EVEN BITS) (ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS)

(ODD BITS)

CHANNEL A D0±/D1±

Figure 6. Channel Multiplexed (Even/Odd) Mode—One Converter, ≤14-Bit Data

Rev. 0 | Page 11 of 64

AD9684

Data Sheet

APERTURE DELAY

N + 36

N

N + 38

VIN±x

N + x

N + 37

SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF

THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET

SYNC+

SYNC–

CLK+

CLK–

CONSTANT LATENCY = X CLK CYCLES

t_CLK

t_DCO

t_PD

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

t_SKEWR

t_SKEWF

STATUS BIT SELECTED BY

REGISTER 0x559, BITS[2:0]

IN THE REGISTER MAP

CONVERTERS

SAMPLE

[N]

CONVERTERS CONVERTERS CONVERTERS

SAMPLE

[N]

CONVERTERS

SAMPLE

[N + 2]

SAMPLE

[N + 1]

SAMPLE

[N + 1]

STATUS+

(OVERRANGE/STATUS BIT)

STATUS

S[N – y]

STATUS

S[N – x]

STATUS STATUS

STATUS

STATUS–

CHANNEL A D12±/D13±

S[N]

S[N + 1]

S[N + 2]

S[N – 1]

(ODD BITS) (EVEN BITS)

(EVEN BITS) (ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS)

(ODD BITS)

CHANNEL A D0±/D1±

CHANNEL B D12±/D13±

S[N – y]

S[N – x]

S[N]

S[N + 1]

S[N + 2]

S[N – 1]

(ODD BITS) (EVEN BITS)

(EVEN BITS) (ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS)

(ODD BITS)

CHANNEL B D0±/D1±

Figure 7. Channel Multiplexed (Even/Odd) Mode—Two Converters, ≤14-Bit Data, Output Sample Rate < 625 MSPS

Rev. 0 | Page 12 of 64

Data Sheet

AD9684

APERTURE DELAY

N + x

N + 39

N + z

N + 36

N + 40

N

N + 42

VIN±x

N – 1

N + 37

N + 38

N + y

N + 41

SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF

THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET

SYNC+

SYNC–

CLK+

CLK–

t_CLK

FIXED DELAY FROM SYNC EVENT

TO DCO KNOWN PHASE

CONSTANT LATENCY = X CLK CYCLES

t_DCO

t_PD

t_STATUS

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

1

90° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

2

270° PHASE ADJUST

t_FRAME

STATUS–

(FRAME CLOCK OUTPUT)

3

FRAME 0

FRAME 1

STAUS+

t_SKEWF

t_SKEWR

I [N]

0

I [N]

Q [N]

I [N + 1] I [N + 1] Q [N + 1] Q [N + 1]

0

EVEN

ODD

EVEN

ODD

EVEN

ODD

EVEN

ODD

STATUS+

4

(OVERRANGE STATUS BIT)

PAR

D15

STATUS

PAR

D15

STATUS

D14

PAR

D15

STATUS

D14

PAR

STATUS

D14

PAR

D15

STATUS–

D7±

D15

D1

D14

D0

D15

D1

D0±

D1

D0

D1

D0

D1

1

90° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.

270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.

FRAME CLOCK OUTPUT SUPPORTS 3 MODES OF OPERATION:

1) ENABLED (ALWAYS ON).

2

3

2) DISABLED (ALWAYS OFF).

3) GAPPED PERIODIC (CONDITIONALLY ENABLED BASED ON PSEUDO-RANDOM BIT).

STATUS BIT SELECTED BY REGISTER 0x559, BITS[2:0] IN THE REGISTER MAP.

4

Figure 8. LVDS Byte Mode—Two Virtual Converters, One DDC, I/Q Data Decimate by 4

Rev. 0 | Page 13 of 64

AD9684

Data Sheet

Figure 9. LVDS Byte Mode—Four Virtual Converters, Two DDCs, ≤16-Bit Data, I/Q Data Decimate by 8

Rev. 0 | Page 14 of 64

Data Sheet

AD9684

1 1 0

1

Figure 10. LVDS Byte Mode—Eight Virtual Converters, Four DDCs, ≤16-Bit Data, I/Q Data Decimate by 16

Rev. 0 | Page 15 of 64

AD9684

Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

Table 6.

Typical θ_JA, θ_JB, and θ_JCare specified vs. the number of printed

circuit board (PCB) layers in different airflow velocities (in

m/sec). Airflow increases heat dissipation effectively reducing

Parameter

Rating

Electrical

AVDD1 to AGND

AVDD2 to AGND

AVDD3 to AGND

DVDD to DGND

1.32 V

2.75 V

3.63 V

1.32 V

θ

_JAand θ_JB. The use of appropriate thermal management

techniques is recommended to ensure that the maximum

junction temperature does not exceed the limits shown in Table 7.

DRVDD to DRGND

SPIVDD to AGND

AGND to DRGND

VIN x to AGND

SCLK, SDIO, CSB to AGND

VIN x Maximum Swing

PDWN/STBY to AGND

Environmental

1.32 V

3.63 V

−0.3 V to +0.3 V

3.2 V

−0.3 V to SPIVDD + 0.3 V

4.3 V p-p

Table 7. Simulated Thermal Data

Airflow

Velocity

(m/sec)

PCB

Type

θ_JA

θ_JB

θ_{JC_TOP}

4.7^{1, 5}

N/A⁴

4.7

N/A⁴

θ_{JC_BOT}

1.2^{1, 5}

N/A⁴

1.2

N/A⁴

Unit

°C/W

JEDEC

2s2p

Board

0.0

1.0

2.5

0.0

1.0

2.5

17.8^{1, 2}

15.6^{1, 2}

15.0^{1, 2}

13.8

6.3^{1, 3}

5.9^{1, 3}

5.7^{1, 3}

4.6

−0.3 V to SPIVDD + 0.3 V

10-Layer

PCB

Operating Temperature Range

−40°C to +85°C

12.7

4.6

(T_CASE

)

12.0

4.6

Maximum Junction Temperature

Storage Temperature Range

(Ambient)

125°C

−65°C to +150°C

¹Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board.

²Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

³Per JEDEC JESD51-8 (still air).

⁴N/A means not applicable.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

⁵Per MIL-STD 883, Method 1012.1.

ESD CAUTION

Rev. 0 | Page 16 of 64

Data Sheet

AD9684

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AGND

AVDD2

AVDD1

AGND

CLK+

CLK–

AGND

AVDD1

AVDD2

AGND

A

B

C

D

E

F

A

B

C

D

E

F

AVDD3

AGND

VIN–B

VIN+B

AGND

FD_B

DGND

DVDD

D1+

AGND

DGND

DVDD

D1–

AGND

DGND

DVDD

D4–

AVDD2

AGND

CSB

AVDD1

AGND

SPIVDD

AGND

DRVDD

D6–

AGND

DRVDD

D0–

AGND

SYNC+

AVDD1

AGND

DRVDD

AGND

SYNC–

AGND

DRGND

AGND

DRGND

D7–

AVDD1

AGND

V_1P0

AVDD2

AGND

DRGND

D8–

AVDD2

AGND

SPIVDD

AGND

DRGND

D9–

AGND

DRGND

D10–

AGND

AVDD3

AGND

VIN–A

VIN+A

AGND

FD_A

AGND

G

H

J

G

H

J

AGND

SCLK

SDIO

PDWN/STBY

DCO–

DCO+

STATUS+

D13+

K

L

K

L

DGND

DVDD

D5–

STATUS–

D13–

M

N

P

M

N

P

D2–

D3–

D11–

D12–

D2+

1

D3+

2

D4+

3

D5+

4

D6+

5

D0+

6

DRVDD

7

DRGND

8

D7+

9

D8+

10

D9+

11

D10+

12

D11+

13

D12+

14

Figure 11. Pin Configuration (Top View)

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

Power Supplies

A5, A10, B5, B10, C5, C10, D5, D7,

D10, E5, E10

A4, A11, B4, B11, C4, C11, D4,

D11, E4, E11, F4, F11, G11, J10

AVDD1

AVDD2

Supply

Analog Power Supply (1.25 V Nominal).

Analog Power Supply (2.50 V Nominal).

B1, B14, C1, C14

L1, L2, M3, M4

M5, M6, M7, N7, P7

J5, J11

AVDD3

DVDD

Supply

Ground

Analog Power Supply (3.3 V Nominal)

Digital Power Supply (1.25 V Nominal).

DRVDD

SPIVDD

DGND

Digital Driver Power Supply (1.25 V Nominal).

Digital Power Supply for SPI (1.8 V to 3.4 V).

Ground Reference for DVDD.

K1, K2, L3, L4

M8 to M12, N8, P8

DRGND

Ground Reference for DRVDD.

A1, A2, A3, A6, A9, A12, A13, A14, AGND

B2, B3, B6, B7, B8, B9, B12, B13,

C2, C3, C6, C9, C12, C13, D1,

D2, D3, D6, D8, D9, D12, D13,

D14, E2, E3, E6 to E9, E12, E13,

F2, F3, F5 to F10, F12, F13, G1

to G10, G12, G13, G14, H1, H2,

H3, H5 to H9, H11 to H14, J2,

J3, J6 to J9, J12, K3, K5 to K12,

L5 to L12

Ground Reference for AVDD.

Analog

E14, F14

E1, F1

H10

VIN−A, VIN+A

VIN−B, VIN+B

V_1P0

Input

Input/DNC

ADC A Analog Input Complement/True.

ADC B Analog Input Complement/True.

1.0 V Reference Voltage Input/Do Not Connect. This pin is

configurable through the SPI as a no connect or as an input.

Do not connect this pin if using the internal reference. This pin

requires a 1.0 V reference voltage input if using an external

voltage reference source.

A7, A8

CLK+, CLK−

Input

Clock Input True/Complement.

Rev. 0 | Page 17 of 64

AD9684

Data Sheet

Pin No.

CMOS Outputs

J14, J1

Mnemonic

Type

Description

FD_A, FD_B

SYNC+, SYNC−

Output

Input

Fast Detect Outputs for Channel A and Channel B.

Active High LVDS SYNC Input—True/Complement.

Digital Inputs

C7, C8

Data Outputs

N6, P6

M1, M2

N1, P1

N2, P2

N3, P3

N4, P4

N5, P5

N9, P9

N10, P10

N11, P11

N12, P12

N13, P13

N14, P14

M13, M14

L13, L14

K13, K14

SPI Controls

K4

D0−, D0+

D1+, D1−

D2−, D2+

D3−, D3+

D4−, D4+

D5−, D5+

D6−, D6+

D7−, D7+

D8−, D8+

D9−, D9+

D10−, D10+

D11−, D11+

D12−, D12+

D13−, D13+

Output

LVDS Lane 0 Output Data—Complement/True.

LVDS Lane 1 Output Data—True/Complement.

LVDS Lane 2 Output Data—Complement/True.

LVDS Lane 3 Output Data—Complement/True.

LVDS Lane 4 Output Data—Complement/True.

LVDS Lane 5 Output Data—Complement/True.

LVDS Lane 6 Output Data—Complement/True.

LVDS Lane 7 Output Data—Complement/True.

LVDS Lane 8 Output Data—Complement/True.

LVDS Lane 9 Output Data—Complement/True.

LVDS Lane 10 Output Data—Complement/True.

LVDS Lane 11 Output Data—Complement/True.

LVDS Lane 12 Output Data—Complement/True.

LVDS Lane 13 Output Data—Complement/True.

LVDS Status Output Data—Complement/True.

LVDS Digital Clock Output Data—Complement/True.

STATUS−, STATUS+ Output

DCO−, DCO+

Output

SDIO

SCLK

Input/output

Input

SPI Serial Data Input/Output.

SPI Serial Clock.

J4

H4

CSB

Input

SPI Chip Select (Active Low).

J13

PDWN/STBY

Input

Power-Down Input (Active High). The operation of this pin

depends on the SPI mode and can be configured as power-

down or standby.

Rev. 0 | Page 18 of 64

Data Sheet

AD9684

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD1 = 1.2 V, AVDD2= 2.5 V, AVDD3 = 3.3 V, DVDD = 1.2 V, DRVDD = 1.2 V, SPIVDD = 1.8 V, sampling rate = 500 MHz, 1.6 V p-p

full-scale differential input, A_IN= −1.0 dBFS, default SPI settings, T_A= 25°C, 256k FFT sample, unless otherwise noted.

0

–20

0

A

= −1dBFS

A

= −1dBFS

IN

SNR = 68.9dBFS

ENOB = 10.9 BITS

SFDR = 83dBFS

SNR = 67.3dBFS

ENOB = 10.8 BITS

SFDR = 86dBFS

–20

BUFFER CONTROL 1 = 2.0×

BUFFER CONTROL 1 = 4.5×

–40

–60

–80

–100

–120

–140

–100

–120

–140

0

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

0

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

Figure 12. Single Tone FFT with f_IN= 10.3 MHz

Figure 15. Single Tone FFT with f_IN= 450.3 MHz

0

–20

0

–20

A

= −1dBFS

A

= −1dBFS

IN

SNR = 68.7dBFS

ENOB = 10.9 BITS

SFDR = 84dBFS

SNR = 63.9dBFS

ENOB = 10.3 BITS

SFDR = 81dBFS

BUFFER CONTROL 1 = 2.0×

BUFFER CONTROL 1 = 5.0×

–40

–60

–80

–100

–120

–140

–100

–120

–140

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

0

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

Figure 13. Single Tone FFT with f_IN= 170.3 MHz

Figure 16. Single Tone FFT with f_IN= 765.3 MHz

0

–20

A

= −1dBFS

0

–20

IN

SNR = 62.8dBFS

ENOB = 10.1 BITS

SFDR = 76dBFS

A

= −1dBFS

IN

SNR = 67.8dBFS

ENOB = 10.8 BITS

SFDR = 82dBFS

BUFFER CONTROL 1 = 5.0×

–40

BUFFER CONTROL 1 = 4.5×

–40

–60

–80

–100

–120

–140

–100

–120

–140

0

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

Figure 17. Single-Tone FFT with f_IN= 985.3 MHz

Figure 14. Single Tone FFT with f_IN= 340.3 MHz

Rev. 0 | Page 19 of 64

AD9684

Data Sheet

95

90

85

80

75

70

65

60

0

2.0×

3.0×

4.0×

A

= −1dBFS

IN

SNR = 61.7dBFS

ENOB = 9.9 BITS

SFDR = 70dBFS

BUFFER CONTROL 1 = 8.0×

–20

SFDR

–40

–60

–80

–100

–120

SNR

–140

0

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

0

100

200

300

400

500

ANALOG INPUT FREQUENCY (MHz)

Figure 18. Single Tone FFT with f_IN= 1205.3 MHz

Figure 21. SNR/SFDR vs. Analog Input Frequency (f_IN);

_IN< 500 MHz; Buffer Control 1 Setting = 2.0×, 3.0×, and 4.0×

f

0

–20

A

= −1dBFS

IN

SNR = 60.1dBFS

ENOB = 9.7 BITS

SFDR = 71dBFS

BUFFER CONTROL 1 = 8.0×

A

AND A

= –7dBFS

IN1

IN2

–20

–40

SFDR = 88dBFS

IMD2 = 95dBFS

IMD3 = 88dBFS

BUFFER CONTROL 1 = 2.0×

–40

–60

–80

–100

–120

–140

–100

–120

0

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

0

50

100

150

200

250

FREQUENCY (MHz)

Figure 19. Single Tone FFT with f_IN= 1630.3 MHz

Figure 22. Two-Tone FFT with f_IN1= 184 MHz and f_IN2= 187 MHz

0

–20

0

A

= −1dBFS

IN

A

AND A

= –7dBFS

IN2

SNR = 59.0dBFS

ENOB = 9.5 BITS

IN1

SFDR = 87dBFS

–20

–40

SFDR = 69dBFS

BUFFER CONTROL 1 = 8.0×

IMD2 = 94dBFS

IMD3 = 87dBFS

BUFFER CONTROL 1 = 2.0×

–40

–60

–80

–100

–120

–140

–100

–120

0

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

0

50

100

150

200

250

FREQUENCY (MHz)

Figure 20. Single Tone FFT with f_IN= 985.3 MHz

Figure 23. Two-Tone FFT; f_IN1= 338 MHz, f_IN2= 341 MHz

Rev. 0 | Page 20 of 64

Data Sheet

AD9684

0

–20

–40

90

85

80

75

70

65

SFDR

SFDR (dBc)

IMD3 (dBc)

–60

–80

SFDR (dBFS)

–100

–120

IMD3 (dBFS)

SNR

–140

–

–40

–25

–10

0

15

25

40

55

70

85

90

–84

–78

–72

–

66

–60 –54 –48 –42 –36 –30 –24 –18 –12 –6

TEMPERATURE (°C)

INPUT AMPLITUDE (dBFS)

Figure 24. Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN) with f_IN1= 184 MHz

and f_IN2= 187 MHz

Figure 27. SNR/SFDR vs. Temperature, f_IN= 170.3 MHz

0

2.30

2.25

2.20

2.15

2.10

2.05

2.00

1.95

1.90

1.85

1.80

–20

SFDR (dBc)

–40

IMD3 (dBc)

–60

–80

SFDR (dBFS)

–100

–120

IMD3 (dBFS)

–140

–

90

–84

–78

–72

–66

–60 –54 –48 –42 –36 –30 –24 –18 –12 –6

INPUT AMPLITUDE (dBFS)

SAMPLE RATE (MSPS)

Figure 25. Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN) with f_IN1= 338 MHz

and f_IN2= 341 MHz

Figure 28. Power Dissipation vs. Sample Rate (f_S) (Default SPI)

100

SFDR (dBc)

80

SNR (dBc)

60

SFDR (dBFS)

40

SNR (dBc)

20

0

–20

–40

INPUT AMPLITUDE (dBFS)

Figure 26. SNR/SFDR vs. Input Amplitude, f_IN= 170.3 MHz

Rev. 0 | Page 21 of 64

AD9684

Data Sheet

EQUIVALENT CIRCUITS

AVDD3

VIN+x

AVDD3

3pF 1.5pF

400Ω

V

CM

BUFFER

SPIVDD

10pF

ESD

PROTECTED

AVDD3

SPIVDD

1kꢀ

30kꢀ

SCLK

VIN–x

ESD

PROTECTED

A

IN

3pF 1.5pF

CONTROL

(SPI)

Figure 29. Analog Inputs

Figure 33. SCLK Inputs

AVDD1

SPIVDD

25ꢀ

ESD

CLK+

CLK–

PROTECTED

30kꢀ

1kꢀ

CSB

AVDD1

ESD

PROTECTED

25ꢀ

20kꢀ

V

= 0.85V

CM

Figure 30. Clock Inputs

Figure 34. CSB Input

AVDD1

1kꢀ

SPIVDD

SYNC+

ESD

PROTECTED

SDO

SPIVDD

SDI

20kꢀ

1kꢀ

SDIO

LEVEL

TRANSLATOR

30kꢀ

V

= 0.85V

CM

ESD

PROTECTED

AVDD1

1kꢀ

20kꢀ

SYNC–

Figure 31. SYNC Inputs

Figure 35. SDIO

SPIVDD

SWING CONTROL

(SPI)

ESD

PROTECTED

DRVDD

FD

DATA+

DATA–

FD_A/FD_B

Dx±

DRGND

DRVDD

TEMPERATURE DIODE

(FD_A ONLY)

OUTPUT

DRIVER

ESD

PROTECTED

Dx±

DRGND

FD_x PIN CONTROL (SPI)

Figure 32. LVDS Digital Outputs, STATUS , DCO

Figure 36. FD_A/FD_B Outputs

Rev. 0 | Page 22 of 64

Data Sheet

AD9684

AVDD2

SPIVDD

ESD

PROTECTED

ESD

PROTECTED

30kΩ

1kΩ

PDWN/

STBY

V_1P0

ESD

PROTECTED

ESD

PROTECTED

PDWN/STBY

CONTROL (SPI)

V_1P0 PIN

CONTROL (SPI)

Figure 38. V_1P0 Input/Output

Figure 37. PDWN/STBY Input

Rev. 0 | Page 23 of 64

AD9684

Data Sheet

THEORY OF OPERATION

The AD9684 has two analog input channels and 14 LVDS

output lane pairs. The ADC is designed to sample wide

bandwidth analog signals of up to 2 GHz. The AD9684 is

optimized for wide input bandwidth, a high sampling rate,

excellent linearity, and low power in a small package.

frequencies. Place either a differential capacitor or two single-

ended capacitors on the inputs to provide a matching passive

network. This ultimately creates a low-pass filter at the input, which

limits unwanted broadband noise. For more information, see the

AN-742 Application Note, the AN-827 Application Note, and the

Analog Dialogue article “Transformer-Coupled Front-End for

Wideband A/D Converters” (Volume 39, April 2005). In general,

the precise values depend on the application.

The dual ADC cores feature a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth inputs that support a variety of

user selectable input ranges. An integrated voltage reference

eases design considerations.

For best dynamic performance, the source impedances driving

VIN+x and VIN−x must be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC. An internal reference buffer

creates a differential reference that defines the span of the ADC core.

The AD9684 has several functions that simplify the AGC

function in a communications receiver. The programmable

threshold detector allows monitoring of the incoming signal

power using the fast detect output bits of the ADC. If the input

signal level exceeds the programmable threshold, the fast detect

indicator goes high. Because this threshold indicator has low

latency, the user can quickly reduce the system gain to avoid an

overrange condition at the ADC input.

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. In the case of the

AD9684, the available span is 2.06 V p-p differential.

Differential Input Configurations

There are several ways to drive the AD9684, either actively or

passively. However, optimum performance is achieved by

driving the analog input differentially.

The LVDS outputs can be configured depending on the

decimation ratio. Multiple device synchronization is supported

through the SYNC input pins.

For applications in which SNR and SFDR are key parameters,

differential transformer coupling is the recommended input

configuration because the noise performance of most amplifiers

is not adequate to achieve the true performance of the AD9684.

ADC ARCHITECTURE

The architecture of the AD9684 consists of an input buffered pipe-

lined ADC. The input buffer provides a termination impedance to

the analog input signal. This termination impedance can be

changed using the SPI to meet the termination needs of the driver/

amplifier. The default termination value is set to 400 Ω. The input

buffer is optimized for high linearity, low noise, and low power.

For low to midrange frequencies, a double balun or double

transformer network is recommended for optimum performance

of the AD9684 (see Figure 39). For higher frequencies in the

second and third Nyquist zones, it is better to remove some of

the front-end passive components to ensure wideband

operation (see Figure 40).

The input buffer provides a linear high input impedance (for

ease of drive) and reduces kickback from the ADC. The buffer

is optimized for high linearity, low noise, and low power. The

quantized outputs from each stage are combined into a final

14-bit result in the digital correction logic. The pipelined

architecture permits the first stage to operate with a new input

sample, whereas the remaining stages operate with the preceding

samples. Sampling occurs on the rising edge of the clock.

10Ω

ETC1-11-13/

MABA007159

0.1µF

4pF

25Ω

1:1Z

ADC

2pF

0.1µF

25Ω

10Ω

0.1µF

4pF

ANALOG INPUT CONSIDERATIONS

Figure 39. Differential Transformer-Coupled Configuration for First and

Second Nyquist Frequencies

The analog input to the AD9684 is a differential buffer. The

internal common-mode voltage of the buffer is 2.05 V. The

clock signal alternately switches the input circuit between

sample mode and hold mode. When the input circuit is switched

into sample mode, the signal source must be capable of charging

the sample capacitors and settling within one-half of a clock cycle.

A small resistor, in series with each input, helps reduce the peak

transient current injected from the output stage of the driving

source. In addition, low Q inductors or ferrite beads can be placed

on each leg of the input to reduce high differential capacitance

at the analog inputs and, thus, achieve the maximum bandwidth

of the ADC. Such use of low Q inductors or ferrite beads is

required when driving the converter front end at high IF

25Ω

0.1µF

25Ω

MARKI

BAL-0006

ADC

OR

0.1µF

25Ω

BAL-0006SMG

0.1µF

Figure 40. Differential Transformer-Coupled Configuration for Second and

Third Nyquist Frequencies

Rev. 0 | Page 24 of 64

Data Sheet

AD9684

95

85

75

65

55

45

35

Input Common Mode

The analog inputs of the AD9684 are internally biased to the

common mode as shown in Figure 41. The common-mode

buffer has a limited range in that the performance suffers greatly

if the common-mode voltage drops by more than 100 mV.

Therefore, in dc-coupled applications, set the common-mode

voltage to 2.05 V 100 mV to ensure proper ADC operation.

4.5×

3.0×

2.0×

1.5×

Analog Input Controls and SFDR Optimization

1.0×

The AD9684 offers flexible controls for the analog inputs, such

as input termination and buffer current. All of the available

controls are shown in Figure 41.

AVDD3

50

100

150

200

250

300

350

400

450

500

INPUT FREQUENCY (MHz)

Figure 43. Buffer Current Sweeps (SFDR vs. Input Frequency and I_BUFF),

10 MHz < f_IN< 500 MHz

VIN+x

3pF

90

AVDD3

4.5×

5.0×

6.0×

85

400Ω

V

CM

7.0×

8.0×

BUFFER

10pF

80

75

70

AVDD3

VIN–x

3pF

AIN CONTROL

(SPI) REGISTERS

(REG 0x008, REG 0x015,

REG 0x016, REG 0x018,

REG 0x025)

65

Figure 41. Analog Input Controls (Should the AIN

500 550 600 650 700 750 800 850 900 950 1000

INPUT FREQUENCY (MHz)

Using Register 0x018, the buffer currents on each channel can

be scaled to optimize the SFDR over various input frequencies

and bandwidths of interest. As the input buffer currents are set,

the amount of current required by the AVDD3 supply changes.

For a complete list of buffer current settings, see Table 29.

250

Figure 44. Buffer Current Sweeps (SFDR vs. Input Frequency and I_BUFF),

500 MHz < f_IN< 1000 MHz

80

75

70

65

60

230

210

190

170

150

130

110

90

4.5×

5.0×

6.0×

7.0×

8.0×

55

50

45

1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000

INPUT FREQUENCY (MHz)

70

Figure 45. Buffer Current Sweeps (SFDR vs. Input Frequency and I_BUFF),

1 GHz < f_IN< 2 GHz, Front-End Network Shown in Figure 40

50

1.5×

2.5×

3.5×

4.5×

5.5×

6.5×

7.5×

8.5×

BUFFER CURRENT SETTING

Figure 43, Figure 44, and Figure 45 show how the SFDR can be

optimized using the buffer current setting in Register 0x018 for

different Nyquist zones. At frequencies greater than 1 GHz, it is

better to run the ADC at input amplitudes less than −1 dBFS

(−3 dBFS, for example). This greatly improves the linearity of

the converted signal without sacrificing SNR performance.

Figure 42. AVDD3 Power (I_AVDD3) vs. Buffer Current Control Setting in

Register 0x018

Rev. 0 | Page 25 of 64

AD9684

Data Sheet

Table 9 shows the recommended buffer current and full-scale

voltage settings for the different analog input frequency ranges.

The use of an external reference may be necessary, in some

applications, to enhance the gain accuracy of the ADC or

improve thermal drift characteristics. Figure 47 shows the

typical drift characteristics of the internal 1.0 V reference.

Absolute Maximum Input Swing

The absolute maximum input swing allowed at the inputs of the

AD9684 is 4.3 V p-p differential. Signals operating near or at

this level can cause permanent damage to the ADC.

1.0010

1.0009

1.0008

1.0007

1.0006

1.0005

1.0004

1.0003

1.0002

1.0001

1.0000

0.9999

0.9998

VOLTAGE REFERENCE

A stable and accurate 1.0 V voltage reference is built into the

AD9684. This internal 1.0 V reference sets the full-scale input

range of the ADC. For more information on adjusting the input

swing, see Table 29. Figure 46 shows the block diagram of the

internal 1.0 V reference controls.

VIN+A/

VIN+B

VIN–A/

VIN–B

–50

0

25

90

ADC

CORE

TEMPERATURE (°C)

INTERNAL

V_1P0

GENERATOR

FULL-SCALE

VOLTAGE

ADJUST

Figure 47. Typical V_1P0 Drift

The external reference must be a stable 1.0 V reference. The

ADR130 is a good option for providing the 1.0 V reference.

Figure 48 shows how the ADR130 can be used to provide the

external 1.0 V reference to the AD9684. The grayed out areas

show unused blocks within the AD9684 while using the

ADR130 to provide the external reference.

INPUT FULL-SCALE

RANGE ADJUST

SPI REGISTER

(REGISTER 0x025)

V_1P0

V_1P0 PIN

CONTROL SPI

REGISTER

(REGISTER 0x024)

Figure 46. Internal Reference Configuration and Controls

Register 0x024 enables the user either to use this internal 1.0 V

reference, or to provide an external 1.0 V reference. When using

an external voltage reference, provide a 1.0 V reference. The

full-scale adjustment is made using the SPI, irrespective of the

reference voltage. For more information on adjusting the full-

scale level of the AD9684, see the Memory Map Register Table

section.

Table 9. SFDR Optimization for Input Frequencies

Buffer Control 1

(Register 0x018)

Input Full-Scale Range

(Register 0x0±5)

Input Full-Scale Control

(Register 0x030)

Input Termination

(Register 0x016)¹

Frequency

DC to 250 MHz

250 MHz to 500

MHz

0x20 (2.0×)

0x70 (4.5×)

0x0C (2.06 V p-p)

0x04

0x0C/0x1C/0x6C

500 MHz to

1 GHz

1 GHz to 2 GHz

0x80 (5.0×)

0xF0 (8.5×)

0x08 (1.46 V p-p)

0x18

0x0C/0x1C/0x6C

¹The input termination can be changed to accommodate the application with little or no impact to ac performance.

INTERNAL

V_1P0

GENERATOR

FULL-SCALE

VOLTAGE

ADJUST

ADR130

1

2

3

6

5

4

NC

GND SET

V_1P0

0.1µF

INPUT

V

OUT

IN

0.1µF

FULL-SCALE

CONTROL

Figure 48. External Reference Using the ADR130

Rev. 0 | Page 26 of 64

Data Sheet

AD9684

Input Clock Divider

CLOCK INPUT CONSIDERATIONS

The AD9684 contains an input clock divider with the ability to

divide the Nyquist input clock by 1, 2, 4, and 8. The divider

ratios can be selected using Register 0x10B. This is shown in

Figure 52.

For optimum performance, drive the AD9684 sample clock

inputs (CLK+ and CLK−) with a differential signal. This signal

is typically ac-coupled to the CLK+ and CLK− pins via a

transformer or clock drivers. These pins are biased internally

and require no additional biasing.

The maximum frequency at the CLK inputs is 4 GHz. This is

the limit of the divider. In applications where the clock input is

a multiple of the sample clock, the appropriate divider ratio

must be programmed into the clock divider before applying the

clock signal. This ensures that the current transients during

device startup are controlled.

Figure 49 shows a preferred method for clocking the AD9684. The

low jitter clock source is converted from a single-ended signal to

a differential signal using an RF transformer.

0.1µF

1:1Z

CLK+

ADC

CLK–

CLOCK

INPUT

CLK+

100Ω

50Ω

CLK–

÷2

÷4

÷8

0.1µF

Figure 49. Transformer Coupled Differential Clock

Another option is to ac couple a differential CML or LVDS

signal to the sample clock input pins, as shown in Figure 50 and

Figure 51.

REG 0x10B

Figure 52. Clock Divider Circuit

3.3V

The AD9684 clock divider can be synchronized using the external

SYNC input. A valid SYNC input causes the clock divider to

reset to a programmable state. This feature is enabled by setting

Bit 7 of Register 0x10D. This synchronization feature allows

multiple devices to have their clock dividers aligned to guarantee

simultaneous input sampling.

71Ω

33Ω

10pF

33Ω

Z

= 50Ω

0.1µF

0

CLK+

ADC

CLK–

0.1µF

= 50Ω

0

Input Clock Divider ½ Period Delay Adjustment

Figure 50. Differential CML Sample Clock

The input clock divider inside the AD9684 provides phase delay

in increments of ½ the input clock cycle. Program Register 0x10C

to enable this delay independently for each channel.

0.1µF

100Ω

0.1µF

CLOCK INPUT

CLK+

LVDS

CLK+

ADC

CLK–

Clock Fine Delay Adjustment

DRIVER

To adjust the AD9684 sampling edge instant, write to Register 0x117

and Register 0x118. Setting Bit 0 of Register 0x117 enables the fine

delay feature, and Register 0x118, Bits[7:0] set the value of the

delay. This value can be programmed individually for each channel.

The clock delay can be adjusted from −151.7 ps to +150 ps in

~1.7 ps increments. The clock delay adjust takes effect immediately

when it is enabled via SPI writes. Enabling the clock fine delay

adjustment in Register 0x117 causes a datapath reset.

CLK–

1

50Ω

1

50Ω RESISTORS ARE OPTIONAL.

Figure 51. Differential LVDS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to the clock duty cycle. Commonly, a 5% tolerance

is required on the clock duty cycle to maintain dynamic performance

characteristics. In applications where the clock duty cycle cannot

be guaranteed to be 50%, a higher multiple frequency clock can be

supplied to the device. The AD9684 can be clocked at 2 GHz with

the internal clock divider set to 2. The output of the divider offers

a 50% duty cycle, high slew rate (fast edge) clock signal to the

internal ADC. See the Memory Map section for more details on

using this feature.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given input

frequency (f_A) due only to aperture jitter (t_J) can be calculated by

SNR = 20 × log 10 (2 × π × f_A× t_J)

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter specifications. IF undersampling

applications are particularly sensitive to jitter (see Figure 53).

Rev. 0 | Page 27 of 64

AD9684

Data Sheet

130

RMS CLOCK JITTER REQUIREMENT

POWER-DOWN/STANDBY MODE

120

110

100

90

The AD9684 has a PDWN/STBY pin that configures the device

in power-down or standby mode. The default operation is the

power-down function. The PDWN/STBY pin is a logic high pin.

The power-down option can also be set via Register 0x03F and

Register 0x040.

16 BITS

14 BITS

12 BITS

80

70

TEMPERATURE DIODE

10 BITS

8 BITS

60

The AD9684 contains a diode-based temperature sensor for

measuring the temperature of the die. This diode can output a

voltage and serve as a coarse temperature sensor to monitor the

internal die temperature.

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

50

40

30

1

10

100

1000

ANALOG INPUT FREQUENCY (MHz)

The temperature diode voltage can be output to the FD_A pin

using the SPI. Use Register 0x028, Bit 0 to enable or disable the

diode. Register 0x028 is a local register. Channel A must be

selected in the device index register (Register 0x008) to enable

the temperature diode readout. Configure the FD_A pin to

output the diode voltage by programming Register 0x040,

Bits[2:0]. See Table 29 for more information.

Figure 53. Ideal SNR vs. Analog Input Frequency and Jitter

Treat the clock input as an analog signal when aperture jitter

may affect the dynamic range of the AD9684. Separate the power

supplies for the clock drivers from the ADC output driver

supplies to avoid modulating the clock signal with digital noise. If

the clock is generated from another type of source (by gating,

dividing, or other methods), retime the clock by the original clock

at the last step. For more in-depth information about jitter

performance as it relates to ADCs, see the AN-501 Application

Note and the AN-756 Application Note.

The voltage response of the temperature diode (with SPIVDD =

1.8 V) is shown in Figure 55.

0.90

0.85

0.80

0.75

0.70

0.65

0.60

Figure 54 shows the estimated SNR of the AD9684 across the

input frequency for different clock induced jitter values. Estimate

the SNR using the following equation:

−SNR

JITTER



_^







ADC

^^^+10^^



10









SNR(dBFS) =10log 10









75

70

65

60

55

50

45

–55 –45 –35 –25 –15 –5

5

15 25 35 45 55 65 75 85 95 105 115 125

TEMPERATURE (°C)

25fs

50fs

75fs

100fs

125fs

150fs

175fs

200fs

Figure 55. Diode Voltage vs. Temperature

1M

10M

100M

1G

10G

INPUT FREQUENCY (Hz)

Figure 54. Estimated SNR Degradation for the AD9684 vs. Input Frequency

and Clock Jitter

Rev. 0 | Page 28 of 64

Data Sheet

AD9684

ADC OVERRANGE AND FAST DETECT

In receiver applications, it is desirable to have a mechanism to

reliably determine when the converter is about to be clipped.

The standard overrange pin outputs information on the state of

the analog input. It is also helpful to have a programmable

threshold below full scale that allows time to reduce the gain

before the clip actually occurs. In addition, because input

signals can have significant slew rates, the latency of this

function is of major concern. Highly pipelined converters can

have significant latency. The AD9684 contains fast detect

circuitry for individual channels to monitor the threshold and

assert the FD_A and FD_B pins.

The operation of the upper threshold and lower threshold

registers, along with the dwell time registers, is shown in

Figure 56.

The FD_x indicator is asserted if the input magnitude exceeds

the value programmed in the fast detect upper threshold

registers, in Register 0x247 and Register 0x248. The selected

threshold register is compared with the signal magnitude at the

output of the ADC. The fast upper threshold detection has a

latency of 28 clock cycles (maximum). The approximate upper

threshold magnitude is defined by

Upper Threshold Magnitude (dBFS) = 20log(Threshold

Magnitude/2¹³)

ADC OVERRANGE

The ADC overrange indicator is asserted when an overrange is

detected on the input of the ADC. The overrange indicator can

be output on the STATUS pins (when CSB > 0). The latency of

this overrange indicator matches the sample latency.

The FD indicators are not cleared until the signal drops below

the lower threshold for the programmed dwell time. The lower

threshold is programmed in the fast detect lower threshold

registers, in Register 0x249 and Register 0x24A. The fast detect

lower threshold register is a 13-bit register that is compared with

the signal magnitude at the output of the ADC. This

comparison is subject to the ADC pipeline latency, but is

accurate in terms of converter resolution. The lower threshold

magnitude is defined by

The AD9684 also records any overrange condition in any of the

four virtual converters. The overrange status of each virtual

converter is registered as a sticky bit in Register 0x563. The

contents of Register 0x563 can be cleared using Register 0x562,

by toggling the bits corresponding to the virtual converter to set

and reset the position.

Lower Threshold Magnitude (dBFS) = 20log(Threshold

Magnitude/2¹³)

FAST THRESHOLD DETECTION (FD_A AND FD_B)

For example, to set an upper threshold of −6 dBFS, write 0xFFF

to Register 0x247 and Register 0x248. To set a lower threshold

of −10 dBFS, write 0xA1D to Register 0x249 and Register 0x24A.

The fast detect (FD) bit (enabled via the control bits in

Register 0x559) is immediately set whenever the absolute value

of the input signal exceeds the programmable upper threshold

level. The FD bit is cleared only when the absolute value of the

input signal drops below the lower threshold level for greater

than the programmable dwell time. This feature provides

hysteresis and prevents the FD bit from excessively toggling.

The dwell time can be programmed from 1 to 65,535 sample

clock cycles by placing the desired value in the fast detect dwell

time registers, in Register 0x24B and Register 0x24C. See the

Memory Map section (Register 0x040, and Register 0x245 to

Register 0x24C in Table 29) for more details.

UPPER THRESHOLD

DWELL TIME

TIMER RESET BY

RISE ABOVE

LOWER

THRESHOLD

LOWER THRESHOLD

TIMER COMPLETES BEFORE

SIGNAL RISES ABOVE

LOWER THRESHOLD

DWELL TIME

FD_A OR FD_B

Figure 56. Threshold Settings for FD_A and FD_B Signals

Rev. 0 | Page 29 of 64

AD9684

Data Sheet

SIGNAL MONITOR

The signal monitor block provides additional information about

the signal being digitized by the ADC. The signal monitor

computes the peak magnitude of the digitized signal. This

information can be used to drive an AGC loop to optimize the

range of the ADC in the presence of real-world signals.

monitor period register (SMPR). To enable the peak detector

function, set Bit 1 of Register 0x270 in the signal monitor

control register. The 24-bit SMPR must be programmed before

activating this mode.

After enabling this mode, the value in the SMPR is loaded into a

monitor period timer that decrements at the decimated clock

rate. The magnitude of the input signal is compared with the

value in the internal magnitude storage register (not accessible

to the user), and the greater of the two is updated as the current

peak level. The initial value of the magnitude storage register is

set to the current ADC input signal magnitude. This comparison

continues until the monitor period timer reaches a count of 1.

The results of the signal monitor block can be obtained by

reading back the internal values from the SPI port. A global, 24-bit

programmable period controls the duration of the measurement.

Figure 57 shows the simplified block diagram of the signal

monitor block.

The peak detector captures the largest signal within the

observation period. The detector only observes the magnitude

of the signal. The resolution of the peak detector is a 13-bit

value and the observation period is 24 bits and represents

converter output samples.

When the monitor period timer reaches a count of 1, the 13-bit

peak level value is transferred to the signal monitor holding

register, which can be read through the memory map. The

monitor period timer is reloaded with the value in the SMPR,

and the countdown is restarted. In addition, the magnitude of

the first input sample is updated in the magnitude storage

register.

Derive the peak magnitude using the following equation:

Peak Magnitude (dBFS) = 20log(Peak Detector Value/2¹³)

The magnitude of the input port signal is monitored over a

programmable time period, which is determined by the signal

SIGNAL MONITOR

FROM

PERIOD REGISTER

DOWN

COUNTER

IS

MEMORY

(SMPR)

MAP

COUNT = 1?

REG 0x271, REG 0x272, REG 0x273

LOAD

CLEAR

LOAD

MAGNITUDE

SIGNAL

MONITOR

HOLDING

REGISTER

TO STATUS± PINS

AND MEMORY MAP

FROM

STORAGE

INPUT

REGISTER

LOAD

COMPARE

A > B

Figure 57. Signal Monitor Block

Rev. 0 | Page 30 of 64

Data Sheet

AD9684

DIGITAL DOWNCONVERTERS (DDCs)

The AD9684 includes four digital downconverters that provide

filtering and reduce the output data rate. This digital processing

section includes an NCO, a half-band decimating filter, a finite

impulse response (FIR) filter, a gain stage, and a complex to real

conversion stage. Each of these processing blocks has a control

line that allows the block to be independently enabled and

disabled to provide the desired processing function. The DDCs

can be configured to output either real data or complex output data.

DDC GENERAL DESCRIPTION

The four DDC blocks extract a portion of the full digital

spectrum captured by the ADCs. They are intended for IF

sampling or oversampled baseband radios requiring wide

bandwidth input signals.

Each DDC block contains the following signal processing stages:

•

Frequency translation stage (optional)

Filtering stage

Gain stage (optional)

DDC I/Q INPUT SELECTION

The AD9684 has two ADC channels and four DDC channels.

Each DDC channel has two input ports that can be paired to

support both real and complex inputs through the I/Q crossbar

mux. For real signals, both DDC input ports must select the

same ADC channel (that is, DDC Input Port I = ADC Channel A

and DDC Input Port Q = ADC Channel A). For complex

signals, each DDC input port must select different ADC

channels (that is, DDC Input Port I = ADC Channel A and

DDC Input Port Q = ADC Channel B).

Complex to real conversion stage (optional)

Frequency Translation Stage (Optional)

This stage consists of a 12-bit complex NCO and quadrature

mixers that can be used for frequency translation of both real or

complex input signals. This stage shifts a portion of the available

digital spectrum down to baseband.

Filtering Stage

After shifting down to baseband, this stage decimates the

frequency spectrum using a chain of up to four half-band, low-

pass filters for rate conversion. The decimation process lowers

the output data rate, which, in turn, reduces the output interface

rate.

The inputs to each DDC are controlled by the DDC input selection

registers (Register 0x311, Register 0x331, Register 0x351, and

Register 0x371). See Table 29 for information on how to

configure the DDCs.

DDC I/Q OUTPUT SELECTION

Gain Stage (Optional)

Each DDC channel has two output ports that can be paired to

support both real or complex outputs. For real output signals,

only the DDC Output Port I is used (the DDC Output Port Q is

invalid). For complex I/Q output signals, both DDC Output

Port I and DDC Output Port Q are used.

Due to losses associated with mixing a real input signal down to

baseband, this stage compensates by adding an additional 0 dB

or 6 dB of gain.

Complex to Real Conversion Stage (Optional)

When real outputs are necessary, this stage converts the complex

outputs back to real outputs by performing an f_S/4 mixing

operation in addition to a filter to remove the complex

component of the signal.

The I/Q outputs to each DDC channel are controlled by the

DDC complex to real enable bit in the DDC control registers

(Bit 3 in Register 0x310, Register 0x330, Register 0x350, and

Register 0x370).

Figure 58 shows the detailed block diagram of the DDCs

implemented in the AD9684.

The Chip I only bit in the chip application mode register

(Register 0x200, Bit 5) controls the chip output muxing of all

the DDC channels. When all DDC channels use real outputs,

set this bit high to ignore all DDC Q output ports. When any of

the DDC channels are set to use complex I/Q outputs, the user

must clear this bit to use both DDC Output Port I and DDC

Output Port Q.

Rev. 0 | Page 31 of 64

AD9684

Data Sheet

DDC 0

DDC 1

DDC 2

DDC 3

REAL/I

I

REAL/I

CONVERTER 0

NCO

+

MIXER

(OPTIONAL)

REAL/Q

Q

Q CONVERTER 1

ADC

SAMPLING

AT f_S

REAL/I

SYNC±

I

REAL/I

CONVERTER 2

NCO

+

MIXER

(OPTIONAL)

REAL/Q

Q

Q CONVERTER 3

SYNC±

I

REAL/I

CONVERTER 4

NCO

+

MIXER

(OPTIONAL)

REAL/Q

Q

Q CONVERTER 5

ADC

SAMPLING

AT f_S

REAL/I

SYNC±

I

REAL/I

CONVERTER 6

NCO

+

MIXER

(OPTIONAL)

REAL/Q

Q

Q CONVERTER 7

SYNC±

SYNCHRONIZATION

CONTROL CIRCUITS

Figure 58. DDC Detailed Block Diagram

Figure 59 shows an example usage of one of the four DDC

blocks with a real input signal and four half-band filters (HB4 +

HB3 + HB2 + HB1). It shows both complex (decimate by 16)

and real (decimate by 8) output options.

Table 10 through Table 15 show the DDC samples when the

chip decimation ratio is set to 1, 2, 4, 8, or 16, respectively.

When DDCs have different decimation ratios, the chip

decimation ratio must be set to the lowest decimation ratio of

all the DDC channels. In this scenario, samples of higher

decimation ratio DDCs are repeated to match the chip

decimation ratio sample rate.

When DDCs have different decimation ratios, the chip decimation

ratio (Register 0x201) must be set to the lowest decimation ratio

for all the DDC blocks. In this scenario, samples of higher decima-

tion ratio DDCs are repeated to match the chip decimation ratio

sample rate. Whenever the NCO frequency is set or changed,

the DDC soft reset must be issued. If the DDC soft reset is not

issued, the output may potentially show amplitude variations.

Rev. 0 | Page 32 of 64

Data Sheet

AD9684

ADC

SAMPLING

AT f_S

ADC

REAL

REAL INPUT—SAMPLED AT f_S

BANDWIDTH OF

INTEREST

BANDWIDTH OF

INTEREST IMAGE

–

f_S/32

DC

–f_S/2

–f_S/3

–

f_S/4

–

f_S/8

–

f_S/16

f_S/8

f_S/4

f_S/3

f_S/2

FREQUENCY TRANSLATION STAGE (OPTIONAL)

I

DIGITAL MIXER + NCO FORf_S/3 TUNING, THE FREQUENCY

TUNING WORD = ROUND ((f_S/3)/f_S× 4096) = +1365 (0x555)

NCO TUNES CENTER OF

BANDWIDTH OF INTEREST

TO BASEBAND

cos(wt)

REAL

12-BIT

NCO

90°

0°

–sin(wt)

Q

BANDWIDTH OF

INTEREST IMAGE

(–6dB LOSS DUE TO

NCO + MIXER)

DIGITAL FILTER

RESPONSE

BANDWIDTH OF INTEREST

(–6dB LOSS DUE TO

NCO + MIXER)

–

f_S/32

DC

–

f_S/2

–f_S/3

–

f_S/4

–

f_S/8

–

f_S/16

f_S/8

f_S/4

f_S/3

f_S/2

FILTERING STAGE

4 DIGITAL HALF-BAND FILTERS

(HB4 + HB3 + HB2 + HB1)

HB4 FIR

HB3 FIR

HB2 FIR

HB1 FIR

HALF-

BAND

FILTER

HALF-

BAND

FILTER

BAND

I

FILTER

2

HB4 FIR

HB3 FIR

HB2 FIR

HB1 FIR

HALF-

BAND

FILTER

HALF-

BAND

FILTER

HALF-

BAND

FILTER

HALF-

BAND

FILTER

Q

6dB GAIN TO

COMPENSATE FOR

NCO + MIXER LOSS

COMPLEX (I/Q) OUTPUTS

GAIN STAGE (OPTIONAL)

0dB OR 6dB GAIN

DECIMATE BY 16

DIGITAL FILTER

RESPONSE

I

2

+6dB

GAIN STAGE (OPTIONAL)

0dB OR 6dB GAIN

Q

2

+6dB

–

f_S/32

–

f_S/32

DC

COMPLEX TO REAL

DC

–

f_S/8

–

f_S/16

f_S/8

–

f_S/16

CONVERSION STAGE (OPTIONAL)

DOWNSAMPLE BY 2

f_S/4 MIXING + COMPLEX FILTER TO REMOVE Q

I

+6dB

REAL (I) OUTPUTS

DECIMATE BY 8

COMPLEX

TO

REAL

REAL/I

Q

6dB GAIN TO

COMPENSATE FOR

NCO + MIXER LOSS

–

f_S/32

DC

–f_S/8

–

f_S/16

f_S/8

Figure 59. DDC Theory of Operation Example (Real Input, Decimate by 16)

Rev. 0 | Page 33 of 64

AD9684

Data Sheet

Table 10. DDC Samples When the Chip Decimation Ratio = 1

Real (I) Output (Complex to Real Enabled)

Complex (I/Q) Outputs (Complex to Real Disabled)

HB± FIR +

HB1 FIR

HB3 FIR + HB±

FIR + HB1 FIR

(DCM¹= 4)

HB4 FIR + HB3 FIR

+ HB± FIR + HB1

FIR (DCM¹= 8)

HB± FIR +

HB1 FIR

HB3 FIR + HB±

FIR + HB1 FIR

(DCM¹= 8)

HB4 FIR + HB3 FIR +

HB± FIR + HB1 FIR

(DCM¹= 16)

HB1 FIR

(DCM¹= 1)

(DCM¹= ±)

(DCM¹= 4)

N

N + 1

N + 2

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 3

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

N + 1

N + 2

N + 3

N + 2

N + 3

N + 4

N + 5

N + 4

N + 5

N + 6

N + 7

N + 6

N + 7

N + 8

N + 9

N + 8

N + 9

N + 10

N + 11

N + 10

N + 11

N + 12

N + 13

N + 12

N + 13

N + 14

N + 15

N + 14

N + 15

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 1

N + 2

N + 3

N + 2

N + 3

N + 4

N + 5

N + 4

N + 5

N + 6

N + 7

N + 6

N + 7

N + 8

N + 9

N + 8

N + 9

N + 10

N + 11

N + 10

N + 11

N + 12

N + 13

N + 12

N + 13

N + 14

N + 15

N + 14

N + 15

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 4

N + 5

N + 4

N + 5

N + 4

N + 5

N + 4

N + 5

N + 6

N + 7

N + 6

N + 7

N + 6

N + 7

N + 6

N + 7

N + 1

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 4

N + 5

N + 4

N + 5

N + 4

N + 5

N + 4

N + 5

N + 6

N + 7

N + 6

N + 7

N + 6

N + 7

N + 6

N + 7

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

N + 16

N + 17

N + 18

N + 19

N + 20

N + 21

N + 22

N + 23

N + 24

N + 25

N + 26

N + 27

N + 28

N + 29

N + 30

N + 31

N + 1

¹DCM means decimation.

Table 11. DDC Samples When the Chip Decimation Ratio = 2

Real (I) Output (Complex to Real Enabled)

HB4 FIR +

Complex (I/Q) Outputs (Complex to Real Disabled)

HB4 FIR +

HB3 FIR +

HB± FIR +

HB1 FIR

HB3 FIR +

HB± FIR +

HB1 FIR

HB3 FIR +

HB± FIR +

HB1 FIR

HB3 FIR +

HB± FIR +

HB1 FIR

HB± FIR +

HB1 FIR

HB± FIR +

HB1 FIR

(DCM¹= ±)

(DCM¹= 4)

(DCM¹= 8)

(DCM¹= ±)

(DCM¹= 4)

(DCM¹= 8)

(DCM¹= 16)

N

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N + 2

N + 3

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N + 2

N + 3

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N + 2

N + 3

N + 2

N + 3

N + 4

N + 5

N + 1

N + 2

N + 3

N + 2

N + 3

N + 4

N + 5

N + 1

Rev. 0 | Page 34 of 64

Data Sheet

AD9684

Real (I) Output (Complex to Real Enabled)

Complex (I/Q) Outputs (Complex to Real Disabled)

HB4 FIR +

HB3 FIR +

HB4 FIR +

HB3 FIR +

HB± FIR +

HB1 FIR

HB3 FIR +

HB± FIR +

HB1 FIR

HB3 FIR +

HB± FIR +

HB1 FIR

HB± FIR +

HB1 FIR

HB± FIR +

HB1 FIR

HB± FIR +

HB1 FIR

(DCM¹= ±)

(DCM¹= 4)

(DCM¹= 8)

(DCM¹= ±)

(DCM¹= 4)

(DCM¹= 8)

(DCM¹= 16)

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

N + 4

N + 5

N + 6

N + 7

N + 6

N + 7

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

N + 4

N + 5

N + 6

N + 7

N + 6

N + 7

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N

N + 1

N

N + 1

N

N + 1

¹DCM means decimation.

Table 12. DDC Samples When the Chip Decimation Ratio = 4

Real (I) Output (Complex to Real Enabled)

Complex (I/Q) Outputs (Complex to Real Disabled)

HB3 FIR + HB± FIR + HB1

FIR (DCM¹= 4)

HB4 FIR + HB3 FIR + HB± FIR HB± FIR + HB1 FIR

HB3 FIR + HB± FIR +

HB1 FIR (DCM¹= 8)

HB4 FIR + HB3 FIR + HB± FIR

+ HB1 FIR (DCM¹= 8)

(DCM¹= 4)

N

+ HB1 FIR (DCM¹= 16)

N

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 1

N

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N + 2

N + 3

N + 2

N + 3

N + 1

N + 2

N + 3

N + 2

N + 3

¹DCM means decimation.

Table 13. DDC Samples When the Chip Decimation Ratio = 8

Real (I) Output (Complex to Real Enabled)

Complex (I/Q) Outputs (Complex to Real Disabled)

HB4 FIR + HB3 FIR + HB± FIR + HB1

HB4 FIR + HB3 FIR + HB± FIR + HB1 FIR (DCM¹= 8)

HB3 FIR + HB± FIR + HB1 FIR(DCM¹= 8)

FIR (DCM¹= 16)

N

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 1

N

N + 1

N + 2

N + 3

N + 2

N + 3

¹DCM means decimation.

Table 14. DDC Samples When the Chip Decimation Ratio = 16

Real (I) Output (Complex to Real Enabled)

HB4 FIR + HB3 FIR + HB± FIR + HB1 FIR (DCM¹= 16)

Not applicable

Complex (I/Q) Outputs (Complex to Real Disabled)

HB4 FIR + HB3 FIR + HB± FIR + HB1 FIR (DCM¹= 16)

N

Not applicable

N + 1

N + 2

N + 3

¹DCM means decimation.

Rev. 0 | Page 35 of 64

AD9684

Data Sheet

For example, if the chip decimation ratio is set to decimate by 4,

DDC 0 is set to use HB2 + HB1 filters (complex outputs,

decimate by 4) and DDC 1 is set to use HB4 + HB3 + HB2 +

HB1 filters (real outputs, decimate by 8). DDC 1 repeats its

output data two times for every one DDC 0 output. The

resulting output samples are shown in Table 15.

Table 15. Chip Decimation Ratio = 4, DDC 0 Decimation = 4 (Complex), and DDC 1 Decimation = 8 (Real)

DDC 0

Output Port Q

DDC 1

DDC Input Samples

N

Output Port I

Output Port Q

Not applicable

I0 (N)

Q0 (N)

I1 (N)

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

I0 (N + 1)

I0 (N + 2)

I0 (N + 3)

Q0 (N + 1)

Q0 (N + 2)

Q0 (N + 3)

I1 (N + 1)

I1 (N)

Not applicable

N + 8

N + 9

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

I1 (N + 1)

Rev. 0 | Page 36 of 64

Data Sheet

AD9684

FREQUENCY TRANSLATION

Variable IF Mode

GENERAL DESCRIPTION

The NCO and the mixers are enabled. The NCO output

frequency can be used to digitally tune the IF frequency.

Frequency translation is accomplished using a 12-bit complex

NCO with a digital quadrature mixer. The frequency translation

translates either a real or complex input signal from an IF to a

baseband complex digital output (carrier frequency = 0 Hz).

0 Hz IF (ZIF) Mode

The mixers are bypassed and the NCO is disabled.

f_S/4 Hz IF Mode

The frequency translation stage of each DDC can be controlled

individually and supports four different IF modes using Bits[5:4] of

the DDC control registers (Register 0x310, Register 0x330,

Register 0x350, and Register 0x370). These IF modes are

The mixers and the NCO are enabled in a special downmixing

by f_S/4 mode to save power.

Test Mode

•

Variable IF mode

0 Hz IF, or zero IF (ZIF), mode

f_S/4 Hz IF mode

The input samples are forced to 0.999 × full scale to positive full

scale. The NCO is enabled. This test mode allows the NCOs to

drive the decimation filters directly.

Test mode

Figure 60 and Figure 61 show examples of the frequency

translation stage for both real and complex inputs.

NCO FREQUENCY TUNING WORD (FTW) SELECTION

12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096

I

cos(wt)

ADC

SAMPLING

AT f_S

ADC + DIGITAL MIXER + NCO

REAL INPUT—SAMPLED AT f_S

REAL

12-BIT

NCO

90°

0°

COMPLEX

–sin(wt)

Q

BANDWIDTH OF

INTEREST

BANDWIDTH OF

INTEREST IMAGE

–

f_S/32

DC

–f_S/2

–f_S/3

–

f_S/4

–f_S/8

–

f_S/16

f_S/8

f_S/4

f_S/3

f_S/2

–6dB LOSS DUE TO

NCO + MIXER

12-BIT NCO FTW =

ROUND ((f_S/3)/f_S× 4096) = +1365 (0x555)

POSITIVE FTW VALUES

–

f_S/32

DC

12-BIT NCO FTW =

ROUND ((f_S/3)/f_S× 4096) = –1365 (0xAAB)

NEGATIVE FTW VALUES

–

f_S/32

DC

Figure 60. DDC NCO Frequency Tuning Word Selection—Real Inputs

Rev. 0 | Page 37 of 64

AD9684

Data Sheet

NCO FREQUENCY TUNING WORD (FTW) SELECTION

12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096

QUADRATURE MIXER

ADC

SAMPLING

AT f_S

I

+

I

–

I

Q

QUADRATURE ANALOG MIXER +

Q

2 ADCs + QUADRATURE DIGITAL

MIXER + NCO

12-BIT

NCO

REAL

90°

PHASE

90°

0°

COMPLEX

Q

COMPLEX INPUT—SAMPLED AT f_S

I

+

ADC

SAMPLING

AT f_S

Q

+

BANDWIDTH OF

INTEREST

IMAGE DUE TO

ANALOG I/Q

MISMATCH

–

f_S/32

f_S/16

–

f_S/2

–f_S/3

–

f_S/4

–

f_S/8

–

f_S/16

f_S/8

f_S/4

f_S/3

f_S/2

DC

12-BIT NCO FTW =

ROUND ((f_S/3)/f_S× 4096) = +1365 (0x555)

POSITIVE FTW VALUES

–f_S/32

f_S/32

DC

Figure 61. DDC NCO Frequency Tuning Word Selection—Complex Inputs

Setting Up the NCO FTW and POW

DDC NCO PLUS MIXER LOSS AND SFDR

The NCO frequency value is given by the 12-bit, twos

complement number entered in the NCO FT W. Frequencies

between f_S/2 (+f_S/2 excluded) are represented using the

following frequency words:

When mixing a real input signal down to baseband, 6 dB of loss

is introduced in the signal due to filtering of the negative image.

The NCO introduces an additional 0.05 dB of loss. The total

loss of a real input signal mixed down to baseband is 6.05 dB. For

this reason, it is recommended to compensate for this loss by

enabling the 6 dB of gain in the gain stage of the DDC to

recenter the dynamic range of the signal within the full scale of

the output bits.

•

0x800 represents a frequency of −f_S/2.

0x000 represents dc (frequency is 0 Hz).

0x7FF represents a frequency of +f_S/2 − f_S/2¹².

Calculate the NCO frequency tuning word using the following

equation:

When mixing a complex input signal down to baseband, the

maximum value that each I/Q sample can reach is 1.414 × full

scale after it passes through the complex mixer. To avoid an

overrange of the I/Q samples and to keep the data bit-widths

aligned with real mixing, introduce 3.06 dB of loss (0.707 × full-

scale) in the mixer for complex signals. The NCO introduces an

additional 0.05 dB of loss. The total loss of a complex input

signal mixed down to baseband is −3.11 dB.









mod

(

f_C, f_S

f_S

)

12



NCO_ FTW = round 2





where:

NCO_FTW is a 12-bit, twos complement number representing

the NC O F T W.

f_Cis the desired carrier frequency in Hz.

f_Sis the AD9684 sampling frequency (clock rate) in Hz.

mod( ) is a remainder function. For example, mod(110,100) =

10, and for negative numbers, mod(−32, +10) = −2.

round( ) is a rounding function. For example, round(3.6) = 4,

and for negative numbers, round(−3.4) = −3.

The worst case spurious signal from the NCO is greater than

102 dBc SFDR for all output frequencies.

NUMERICALLY CONTROLLED OSCILLATOR

The AD9684 has a 12-bit NCO for each DDC that enables the

frequency translation process. The NCO allows the input

spectrum to be tuned to dc, where it can be effectively filtered

by the subsequent filter blocks to prevent aliasing. The NCO

can be set up by providing a frequency tuning word (FTW) and

a phase offset word (POW).

Note that this equation applies to the aliasing of signals in the

digital domain (that is, aliasing introduced when digitizing

analog signals).

Rev. 0 | Page 38 of 64

Data Sheet

AD9684

For example, if the ADC sampling frequency (f_S) is 1250 MSPS

and the carrier frequency (f_C) is 416.667 MHz,

Use the following two methods to synchronize multiple PAWs

within the chip:

•

Using the SPI. Use the DDC NCO soft reset bit in the DDC

synchronization control register (Register 0x300, Bit 4) to

reset all the PAWs in the chip. This is accomplished by

toggling the DDC NCO soft reset bit. Note that this

method synchronizes DDC channels within the same

AD9684 chip only.

mod

(

416.667,1250

1250

)









NCO _ FTW = round 2¹²

=1365 MHz





This, in turn, converts to 0x555 in the 12-bit, twos complement

representation for NCO_FTW. Calculate the actual carrier

frequency based on the following equation:

•

Using the SYNC pins. When the SYNC pins are enabled

in the SYNC control registers (Register 0x120 and

Register 0x121), and the DDC synchronization is enabled

in Bits[1:0] in the DDC synchronization control register

(Register 0x300), any subsequent SYNC event resets all

the PAWs in the chip. Note that this method synchronizes

DDC channels within the same AD9684 chip or DDC

channels within separate AD9684 chips.

NCO _ FTW × f_S

f_C

=

= 416.56 MHz

_ ACTUAL

2¹²

A 12-bit POW is available for each NCO to create a known

phase relationship between multiple AD9684 chips or

individual DDC channels inside one AD9684 chip.

The following procedure must be followed to update the FTW

and/or POW registers to ensure proper operation of the NCO:

1. Write to the FTW registers for all the DDCs.

2. Write to the POW registers for all the DDCs.

3. Synchronize the NCOs either through the DDC soft reset bit,

accessible through the SPI, or through the assertion of the

SYNC pins.

Mixer

The NCO is accompanied by a mixer, which operates similarly

to an analog quadrature mixer. It performs the downconversion

of input signals (real or complex) by using the NCO frequency

as a local oscillator. For real input signals, this mixer performs a

real mixer operation with two multipliers. For complex input

signals, the mixer performs a complex mixer operation with

four multipliers and two adders. The mixer adjusts its operation

based on the input signal (real or complex) provided to each

individual channel. The selection of real or complex inputs can be

controlled individually for each DDC block using Bit 7 of the DDC

control registers (Register 0x310, Register 0x330, Register 0x350,

and Register 0x370).

Note that the NCOs must be synchronized either through the

SPI or through the SYNC pins after all writes to the FTW or

POW registers are complete. This synchronization is necessary

to ensure the proper operation of the NCO.

NCO Synchronization

Each NCO contains a separate phase accumulator word (PAW)

that determines the instantaneous phase of the NCO. The initial

reset value of each PAW is determined by the POW, described

in the Setting Up the NCO FTW and POW section. The phase

increment value of each PAW is determined by the FTW.

Rev. 0 | Page 39 of 64

AD9684

Data Sheet

FIR FILTERS

Table 16 shows the different bandwidth options by including

different half-band filters. In all cases, the DDC filtering stage of

the AD9684 provides less than −0.001 dB of pass-band ripple

and greater than 100 dB of stop band alias rejection.

GENERAL DESCRIPTION

There are four sets of decimate by 2, low-pass, half-band, FIR

filters (labeled HB1 FIR, HB2 FIR, HB3 FIR, and HB4 FIR in

Figure 58) following the frequency translation stage. After the

carrier of interest is tuned down to dc (carrier frequency =

0 Hz), these filters efficiently lower the sample rate while

providing sufficient alias rejection from unwanted adjacent

carriers around the bandwidth of interest.

Table 17 shows the amount of stop band alias rejection for

multiple pass-band ripple/cutoff points. The decimation ratio of

the filtering stage of each DDC can be controlled individually

through Bits[1:0] of the DDC control registers (Register 0x310,

Register 0x330, Register 0x350, and Register 0x370).

HB1 FIR is always enabled and cannot be bypassed. The HB2,

HB3, and HB4 FIR filters are optional and can be bypassed for

higher output sample rates.

Table 16. DDC Filter Characteristics

Real Output Complex (I/Q)

Sample Rate Output Sample

Alias Protected Ideal SNR

Pass-Band Alias

Improvement¹Ripple

Rejection

(dB)

>100

ADC Sample

Rate (MSPS)

DDC Decimation

Ratio

Bandwidth

(MHz)

385.0

192.5

96.3

(MSPS)

1000

500

Rate (MSPS)

(dB)

1

(dB)

1000

2 (HB1)

4 (HB1 + HB2)

500 (I) + 500 (Q)

250 (I) + 250 (Q)

125 (I) + 125 (Q)

<−0.001

4

7

8 (HB1 + HB2 + HB3) 250

16 (HB1 + HB2 +

HB3 + HB4)

125

62.5 (I) + 62.5 (Q) 48.1

10

¹The ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(f_S/2)).

Table 17. DDC Filter Alias Rejection

Alias Protected Bandwidth for

Real (I) Outputs¹

Alias Protected Bandwidth for

Complex (I/Q) Outputs¹

Alias Rejection (dB)

Pass-Band Ripple/Cutoff Point (dB)

>100

90

85

63.3

25

19.3

10.7

<−0.001

<−0.006

−0.5

<38.5% × f_OUT

<38.7% × f_OUT

<38.9% × f_OUT

<40% × f_OUT

44.4% × f_OUT

45.6% × f_OUT

48% × f_OUT

<77% × f_OUT

<77.4% × f_OUT

<77.8% × f_OUT

<80% × f_OUT

88.8% × f_OUT

91.2% × f_OUT

96% × f_OUT

−1.0

−3.0

¹f_OUT= ADC input sample rate/DDC decimation ratio.

Rev. 0 | Page 40 of 64

Data Sheet

AD9684

0

–20

HALF-BAND FILTERS

The AD9684 offers four half-band filters to enable digital signal

processing of the ADC converted data. These half-band filters

are bypassable and can be individually selected.

–40

HB4 Filter

–60

The first decimate by 2, half-band, low-pass FIR filter (HB4)

uses an 15-bit, symmetrical, fixed coefficient filter

–80

implementation that is optimized for low power consumption.

The HB4 filter is used only when complex outputs (decimate by

16) or real outputs (decimate by 8) are enabled; otherwise, the

filter is bypassed. Table 18 and Figure 62 show the coefficients

and response of the HB4 filter.

–100

–120

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

NORMALIZED FREQUENCY (× π RAD/SAMPLE)

Table 18. HB4 Filter Coefficients

Figure 63. HB3 Filter Response

HB4 Coefficient Number

Decimal Coefficient (15-Bit)

HB2 Filter

C1, C11

C2, C10

C3, C9

C4, C8

C5, C7

C6

99

0

−808

0

4805

8192

The third decimate by 2, half-band, low-pass FIR filter (HB2)

uses a 19-bit, symmetrical, fixed coefficient filter implementation

that is optimized for low power consumption. The HB2 filter is

only used when complex outputs (decimate by 4, 8, or 16) or

real outputs (decimate by 2, 4, or 8) are enabled; otherwise, the

filter is bypassed.

0

–20

Table 20 and Figure 64 show the coefficients and response of

the HB2 filter.

Table 20. HB2 Filter Coefficients

–40

HB± Coefficient Number

Decimal Coefficient (19-Bit)

C1, C19

C2, C18

161

0

–60

C3, C17

C4, C16

−1328

0

–80

C5, C15

C6, C14

C7, C13

C8, C12

5814

0

−19272

0

–100

–120

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

NORMALIZED FREQUENCY (× π RAD/SAMPLE)

C9, C11

C10

80,160

131,072

Figure 62. HB4 Filter Response

HB3 Filter

0

–20

The second decimate by 2, half-band, low-pass, FIR filter (HB3)

uses an 18-bit, symmetrical, fixed coefficient filter implementation

that is optimized for low power consumption. The HB3 filter is

only used when complex outputs (decimate by 8 or 16) or real

outputs (decimate by 4 or 8) are enabled; otherwise, the filter is

bypassed. Table 19 and Figure 63 show the coefficients and

response of the HB3 filter.

–40

–60

–80

Table 19. HB3 Filter Coefficients

–100

–120

HB3 Coefficient Number

Decimal Coefficient (18-Bit)

C1, C11

C2, C10

C3, C9

C4, C8

C5, C7

C6

859

0

−6661

0

38570

65536

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

NORMALIZED FREQUENCY (× π RAD/SAMPLE)

Figure 64. HB2 Filter Response

Rev. 0 | Page 41 of 64

AD9684

Data Sheet

HB1 Filter

0

–20

The fourth and final decimate by 2, half-band, low-pass FIR

filter (HB1) uses a 21-bit, symmetrical, fixed coefficient filter

implementation that is optimized for low power consumption.

The HB1 filter is always enabled and cannot be bypassed. Table 21

and Figure 65 show the coefficients and response of the HB1

filter.

–40

–60

–80

Table 21. HB1 Filter Coefficients

HB1 Coefficient Number

Decimal Coefficient (±1-Bit)

–100

–120

C1, C55

C2, C54

−24

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

C3, C53

C4, C52

C5, C51

102

0

−302

NORMALIZED FREQUENCY (× π RAD/SAMPLE)

Figure 65. HB1 Filter Response

C6, C50

C7, C49

0

730

DDC GAIN STAGE

Each DDC contains an independently controlled gain stage.

The gain is selectable as either 0 dB or 6 dB. When mixing a real

input signal down to baseband, it is recommended to enable the

6 dB gain to recenter the dynamic range of the signal within the

full scale of the output bits.

C8, C48

C9, C47

0

−1544

0

2964

0

−5284

0

8903

0

−14,383

0

22,640

0

−35,476

0

57,468

0

−105,442

0

331,792

524,288

C10, C46

C11, C45

C12, C44

C13, C43

C14, C42

C15, C41

C16, C40

C17, C39

C18, C38

C19, C37

C20, C36

C21, C35

C22, C34

C23, C33

C24, C32

C25, C31

C26, C30

C27, C29

C28

When mixing a complex input signal down to baseband, the

mixer has already recentered the dynamic range of the signal

within the full scale of the output bits and no additional gain is

necessary. However, the optional 6 dB gain compensates for low

signal strengths. The downsample by 2 portion of the HB1 FIR

filter is bypassed when using the complex to real conversion

stage (see Figure 66).

DDC COMPLEX TO REAL CONVERSION BLOCK

Each DDC contains an independently controlled complex to

real conversion block. The complex to real conversion block

reuses the last filter (HB1 FIR) in the filtering stage, along with

an f_S/4 complex mixer to upconvert the signal.

After upconverting the signal, the Q portion of the complex

mixer is no longer needed and is dropped.

Figure 66 shows a simplified block diagram of the complex to

real conversion.

Rev. 0 | Page 42 of 64

Data Sheet

AD9684

HB1 FIR

GAIN STAGE

COMPLEX TO

REAL ENABLE

LOW-PASS

FILTER

I

0dB

OR

I

0

2

I/REAL

6dB

1

COMPLEX TO REAL CONVERSION

0dB

OR

6dB

cos(wt)

+

90°

REAL

f_S/4

0°

–

sin(wt)

0dB

OR

6dB

Q

LOW-PASS

FILTER

Q

0dB

OR

6dB

Q

2

HB1 FIR

Figure 66. Complex to Real Conversion Block

DDC EXAMPLE CONFIGURATIONS

Table 22 describes the register settings for multiple DDC example configurations.

Table 22. DDC Example Configurations

Chip

Application

Layer

Chip

Decimation

Ratio

DDC

Number of Virtual

Converters

Required (M)

DDC Input Output

Bandwidth

Per DDC¹

Type

Register Settings^±

One DDC

2

Complex

77% × f_S

2

Register 0x200 = 0x01 (one DDC, I/Q

selected)

Register 0x201 = 0x01 (chip decimate

by 2)

Register 0x310 = 0x83 (complex mixer,

0 dB gain, variable IF, complex outputs,

HB1 filter)

Register 0x311 = 0x04 (DDC I input =

ADC Channel A, DDC Q input = ADC

Channel B)

Register 0x314, Register 0x315,

Register 0x320, Register 0x321 = FTW

and POW set as required by application

for DDC 0

Two DDCs

4

Complex

38.5% × f_S

4

Register 0x200 = 0x02 (two DDCs, I/Q

selected)

Register 0x201 = 0x02 (chip decimate

by 4)

Register 0x310, Register 0x330 = 0x80

(complex mixer, 0 dB gain, variable IF,

complex outputs, HB2 + HB1 filters)

Register 0x311, Register 0x331 = 0x04

(DDC I input = ADC Channel A, DDC Q

input = ADC Channel B)

Rev. 0 | Page 43 of 64

AD9684

Data Sheet

Chip

Application

Layer

Chip

Decimation

Ratio

DDC

Number of Virtual

Converters

Required (M)

DDC Input Output

Bandwidth

Per DDC¹

Type

Register Settings^±

Register 0x314, Register 0x315,

Register 0x320, Register 0x321 = FTW

and POW set as required by application

for DDC 0

Register 0x334, Register 0x335,

Register 0x340, Register 0x341 = FTW

and POW set as required by application

for DDC 1

Two DDCs

4

Complex

Real

19.25% × f_S

2

Register 0x200 = 0x22 (two DDCs, Q

ignore selected)

Register 0x201 = 0x02 (chip decimate

by 4)

Register 0x310, Register 0x330 = 0x89

(complex mixer, 0 dB gain, variable IF,

real output, HB3 + HB2 + HB1 filters)

Register 0x311, Register 0x331 = 0x04

(DDC I input = ADC Channel A, DDC Q

input = ADC Channel B)

Register 0x314, Register 0x315,

Register 0x320, Register 0x321 = FTW

and POW set as required by application

for DDC 0

Register 0x334, Register 0x335,

Register 0x340, Register 0x341 = FTW

and POW set as required by application

for DDC 1

Two DDCs

4

Real

19.25% × f_S

2

Register 0x200 = 0x22 (two DDCs, Q

ignore selected)

Register 0x201 = 0x02 (chip decimate

by 4)

Register 0x310, Register 0x330 = 0x49

(real mixer, 6 dB gain, variable IF, real

output, HB3 + HB2 + HB1 filters)

Register 0x311 = 0x00 (DDC 0 I input =

ADC Channel A, DDC 0 Q input = ADC

Channel A)

Register 0x331 = 0x05 (DDC 1 I input =

ADC Channel B, DDC 1 Q input = ADC

Channel B)

Register 0x314, Register 0x315,

Register 0x320, Register 0x321 = FTW

and POW set as required by application

for DDC 0

Register 0x334, Register 0x335,

Register 0x340, Register 0x341 = FTW

and POW set as required by application

for DDC 1

Two DDCs

4

Real

Complex

38.5% × f_S

4

Register 0x200 = 0x02 (two DDCs, I/Q

selected)

Register 0x201 = 0x02 (chip decimate

by 4)

Register 0x310, Register 0x330 = 0x40

(real mixer, 6 dB gain, variable IF,

complex output, HB2 + HB1 filters)

Register 0x311 = 0x00 (DDC 0 I input =

ADC Channel A, DDC 0 Q input = ADC

Channel A)

Register 0x331 = 0x05 (DDC 1 I input =

ADC Channel B, DDC 1 Q input = ADC

Channel B)

Rev. 0 | Page 44 of 64

Data Sheet

AD9684

Chip

Application

Layer

Chip

Decimation

Ratio

DDC

Number of Virtual

Converters

Required (M)

DDC Input Output

Bandwidth

Per DDC¹

Type

Register Settings^±

Register 0x314, Register 0x315,

Register 0x320, Register 0x321 = FTW

and POW set as required by application

for DDC 0

Register 0x334, Register 0x335,

Register 0x340, Register 0x341 = FTW

and POW set as required by application

for DDC 1

Four DDCs

8

Real

Complex

19.25% × f_S

8

Register 0x200 = 0x03 (four DDCs, I/Q

selected)

Register 0x201 = 0x03 (chip decimate

by 8)

Register 0x310, Register 0x330,

Register 0x350, Register 0x370 = 0x41

(real mixer, 6 dB gain, variable IF,

complex output, HB3 + HB2 + HB1

filters)

Register 0x311 = 0x00 (DDC 0 I input =

ADC Channel A, DDC 0 Q input = ADC

Channel A)

Register 0x331 = 0x00 (DDC 1 I input =

ADC Channel A, DDC 1 Q input = ADC

Channel A)

Register 0x351 = 0x05 (DDC 2 I input =

ADC Channel B, DDC 2 Q input = ADC

Channel B)

Register 0x371 = 0x05 (DDC 3 I input =

ADC Channel B, DDC 3 Q input = ADC

Channel B)

Register 0x314, Register 0x315,

Register 0x320, Register 0x321 = FTW

and POW set as required by application

for DDC 0

Register 0x334, Register 0x335,

Register 0x340, Register 0x341 = FTW

and POW set as required by application

for DDC 1

Register 0x354, Register 0x355,

Register 0x360, Register 0x361 = FTW

and POW set as required by application

for DDC 2

Register 0x374, Register 0x375,

Register 0x380, Register 0x381 = FTW

and POW set as required by application

for DDC 3

Four DDCs

16

Real

Complex

9.625% × f_S

8

Register 0x200 = 0x03 (four DDCs, I/Q

selected)

Register 0x201 = 0x04 (chip decimate

by 16)

Register 0x310, Register 0x330,

Register 0x350, Register 0x370 = 0x42

(real mixer, 6 dB gain, variable IF,

complex output, HB4 + HB3 + HB2 +

HB1 filters)

Register 0x311 = 0x00 (DDC 0 I input =

ADC Channel A, DDC 0 Q input = ADC

Channel A)

Register 0x331 = 0x00 (DDC 1 I input =

ADC Channel A, DDC 1 Q input = ADC

Channel A)

Rev. 0 | Page 45 of 64

AD9684

Data Sheet

Chip

Application

Layer

Chip

Decimation

Ratio

DDC

Number of Virtual

Converters

Required (M)

DDC Input Output

Bandwidth

Per DDC¹

Type

Register Settings^±

Register 0x351 = 0x05 (DDC 2 I input =

ADC Channel B, DDC 2 Q input = ADC

Channel B)

Register 0x371 = 0x05 (DDC 3 I input =

ADC Channel B, DDC 3 Q input = ADC

Channel B)

Register 0x314, 0x315, 0x320, 0x321 =

FTW and POW set as required by

application for DDC 0

Register 0x334, Register 0x335,

Register 0x340, Register 0x341 = FTW

and POW set as required by application

for DDC 1

Register 0x354, Register 0x355,

Register 0x360, Register 0x361 = FTW

and POW set as required by application

for DDC 2

Register 0x374, Register 0x375,

Register 0x380, Register 0x381 = FTW

and POW set as required by application

for DDC 3

¹f_Sis the ADC sample rate. Bandwidths listed are <−0.001 dB of pass-band ripple and >100 dB of stop band alias rejection.

²The NCOs must be synchronized either through the SPI or through the SYNC pins after all writes to the FTW or POW registers are complete. This ensures the proper

operation of the NCO. See the NCO Synchronization section for more information.

Rev. 0 | Page 46 of 64

Data Sheet

AD9684

DIGITAL OUTPUTS

Minimize the length of the output data lines and the corresponding

loads to reduce transients within the AD9684. These transients

can degrade converter dynamic performance.

DIGITAL OUTPUTS

The AD9684 output drivers are for standard ANSI LVDS, but

optionally the drive current can be reduced using Register 0x56A.

The reduced drive current for the LVDS outputs potentially

reduces the digitally induced noise.

The lowest typical conversion rate of the AD9684 is 250 MSPS.

At clock rates below 250 MSPS, dynamic performance may

degrade.

As detailed in the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI

control.

Data Clock Output

The AD9684 also provides a data clock output (DCO) intended

for capturing the data in an external register. The DCO relative

to the data output can be adjusted using Register 0x569.

The AD9684 has a flexible three-state ability for the digital

output pins. The three-state mode is enabled when the device is

set for power-down mode.

ADC OVERRANGE

The ADC overrange (OR) indicator is asserted when an overrange

is detected on the input of the ADC. The overrange condition is

determined at the output of the ADC pipeline and, therefore, is

subject to a latency of 28 ADC clocks. An overrange at the input is

indicated by the OR bit 28 clock cycles after it occurs.

As shown in Table 24, the function of the output pins changes

based upon the selection of either parallel or byte output mode

in Register 0x568.

Timing

The AD9684 provides latched data with a pipeline delay of

33 input sample clock cycles. Data outputs are available one

propagation delay (t_PD) after the rising edge of the clock signal.

Table 23. LVDS Output Configurations

Number of Virtual

Converters Supported

Virtual Converter

Resolution (Max)

Parallel Output Mode

LVDS Byte Mode Outputs Required

Parallel Interleaved, Two

Converters (0x1)

2

14-bit

DCO + STATUS + D[13:0]

Parallel Channel Multiplexed, Two

Converters (0x3)

2

14-bit

DCO + STATUS + D[13:7] =

Channel AD[6:0] = Channel B

Byte Mode, Two Converters (0x5)

Byte Mode, Four Converters (0x6)

Byte Mode, Eight Converters (0x7)

2

4

8

16-bit

1 DCO + 1 STATUS + 8 DATA[7:0]

Table 24. Pin Mapping Between LVDS Parallel/Byte Modes

Pin Name

DCO−, DCO+

STATUS−, STATUS+

D13−, D13+

D12−, D12+

D11−, D11+

D10−, D10+

D9−, D9+

D8−, D8+

D7−, D7+

D6−, D6+

D5−, D5+

LVDS Parallel Mode Output

DCO−, DCO+

OVR−, OVR+

D13−, D13+

D12−, D12+

D11−, D11+

D10−, D10+

D9−, D9+

D8−, D8+

D7−, D7+

D6−, D6+

D5−, D5+

LVDS Byte Mode Output

DCO−, DCO+

FCO−, FCO+

STATUS−, STATUS+

DATA7−, DATA7+

DATA6−, DATA6+

DATA5−, DATA5+

DATA4−, DATA4+

DATA3−, DATA3+

DATA2−, DATA2+

DATA1−, DATA1+

DATA0−, DATA0+

Not applicable

D4−, D4+

D3−, D3+

D2−, D2+

D1−, D1+

D4−, D4+

D3−, D3+

D2−, D2+

D1−, D1+

D0−, D0+

Rev. 0 | Page 47 of 64

AD9684

Data Sheet

MULTICHIP SYNCHRONIZATION

The AD9684 supports several features that aid users in meeting

the requirements for capturing SYNC signals. The SYNC

sample event can be defined as either a synchronous low to high

transition or a synchronous high to low transition. Additionally,

the AD9684 allows the SYNC signal to be sampled using

either the rising edge or the falling edge of the CLK input. The

AD9684 can also to ignore a programmable number (up to 16)

of SYNC events. The SYNC control options can be selected

using Register 0x120 and Register 0x121.

The AD9684 has a SYNC input that allows the user flexible

options for synchronizing the internal blocks. The SYNC

input is a source synchronous system reference signal that

enables multichip synchronization. The input clock divider,

DDCs, and signal monitor block LVDS output link can be

synchronized using the SYNC input. For the highest level of

timing accuracy, SYNC must meet the setup and hold

requirements relative to the CLK input.

The flowchart in Figure 67 shows the internal mechanism by

which multichip synchronization can be achieved in the AD9684.

START

INCREMENT

SYNC± IGNORE

COUNTER

NO

SYNC±

IGNORE

COUNTER

EXPIRED?

REG (0x121)

UPDATE

SETUP/HOLD

DETECTOR STATUS

REG (0x128)

RESET

SYNC± IGNORE

COUNTER

SYNC±

ENABLED?

REG (0x120)

NO

YES

SYNC±

ASSERTED?

YES

CLOCK

DIVIDER

AUTO ADJUST

ENABLED?

REG (0x10D)

INPUT

CLOCK

INCREMENT

SYNC±

COUNTER

REG (0x12A)

CLOCK

DIVIDER

> 1?

ALIGN CLOCK

DIVIDER

PHASE TO

SYNC±

YES

DIVIDER

ALIGNMENT

REQUIRED?

REG (0x10B)

NO

ALIGN PHASE OF ALL

INTERNAL CLOCKS

TO SYNC±

CLOCK

ALIGNMENT

REQUIRED?

YES

NO

SIGNAL

MONITOR

SYNC

ENABLED?

REG (0x26F)

DDC NCO

ALIGN DDC

ALIGN SIGNAL

MONITOR

COUNTERS

YES

ALIGNMENT

ENABLED?

REG (0x300)

NCO PHASE

BACK TO START

ACCUMULATOR

NO

Figure 67. Multichip Synchronization

Rev. 0 | Page 48 of 64

Data Sheet

AD9684

Figure 68 and Figure 69 show the setup and hold status values for

different phases of SYNC .

SYNC± SETUP AND HOLD WINDOW MONITOR

To assist in ensuring a valid SYNC capture, the AD9684 has a

SYNC setup and hold window monitor. This feature allows the

system designer to determine the location of the SYNC signals

relative to the CLK signals by reading back the amount of setup

and hold margin on the interface through the memory map.

The setup detector returns the status of the SYNC signal before

the CLK edge and the hold detector returns the status of the

SYNC signal after the CLK edge. Register 0x128 stores the

status of SYNC and alerts the user if the SYNC signal is

captured by the ADC.

–1

–2

–3

–4

–5

–6

–7

REG 0x128[3:0]

–8

7

6

5

4

3

2

1

0

CLK±

INPUT

SYNC±

INPUT

VALID

FLIP FLOP

HOLD (MIN)

FLIP FLOP

SETUP (MIN)

FLIP FLOP

HOLD (MIN)

Figure 68. SYNC Setup Detector

–1

–2

–3

–4

–5

–6

–7

–8

7

REG 0x128[7:4]

6

5

4

3

2

1

0

CLK±

INPUT

SYNC±

INPUT

VALID

FLIP FLOP

SETUP (MIN)

FLIP FLOP

HOLD (MIN)

FLIP FLOP

HOLD (MIN)

Figure 69. SYNC Hold Detector

Rev. 0 | Page 49 of 64

AD9684

Data Sheet

Table 25 describes the contents of Register 0x128 and how to interpret those contents.

Table 25. SYNC Setup and Hold Monitor Register 0x128

Register 0x1±8, Bits[7:4],

Hold Status

Register 0x1±8, Bits[3:0],

Setup Status

Description

0x0

0x0 to 0x8

0x8

0x0 to 0x7

0x8

0x9 to 0xF

0x0

Possible setup error; the smaller this number, the smaller the setup margin

No setup or hold error (best hold margin)

No setup or hold error (best setup and hold margin)

No setup or hold error (best setup margin)

0x8

0x9 to 0xF

0x0

Possible hold error; the larger this number, the smaller the hold margin

Possible setup or hold error

Rev. 0 | Page 50 of 64

Data Sheet

AD9684

TEST MODES

and some are not. The pseudorandom number (PN) generators

from the PN sequence tests can be reset by setting Bit 4 or Bit 5

of Register 0x550. These tests can be performed with or without

an analog signal (if present, the analog signal is ignored);

however, they do require an encode clock. For more information,

see the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI.

ADC TEST MODES

The AD9684 has various test options that aid in the system level

implementation. The AD9684 has ADC test modes that are

available in Register 0x550. These test modes are described in

Table 26. When an output test mode is enabled, the analog

section of the ADC is disconnected from the digital back-end

blocks and the test pattern is run through the output formatting

block. Some of the test patterns are subject to output formatting,

Table 26. ADC Test Modes

Output Test Mode

Bit Sequence

Default/Seed

Value

Pattern Name

Off (default)

Midscale short

+Full-scale short

−Full-scale short

Checkerboard

PN sequence

long

PN sequence

short

Expression

Sample (N, N + 1, N + ±, …)

0000

0001

0010

0011

0100

0101

Not applicable

0x3AFF

Not applicable

0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555

0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6

00 0000 0000 0000

01 1111 1111 1111

10 0000 0000 0000

10 1010 1010 1010

x²³+ x¹⁸+ 1

0110

0111

1000

x⁹+ x⁵+ 1

0x0092

0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697

0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000

One-/zero-word

toggle

User input

11 1111 1111 1111

Not applicable

Register 0x551 to

Register 0x558

For repeat mode: User Pattern 1[15:2], User Pattern 2[15:2],

User Pattern 3[15:2], User Pattern 4[15:2], User Pattern 1[15:2]…

For single mode: User Pattern 1[15:2], User Pattern 2[15:2],

User Pattern 3[15:2], User Pattern 4[15:2], 0x0000…

(x) % 2¹⁴, (x + 1) % 2¹⁴, (x + 2) % 2¹⁴, (x + 3) % 2¹⁴

1111

Ramp output

(x) % 2¹⁴

Not applicable

Rev. 0 | Page 51 of 64

AD9684

Data Sheet

SERIAL PORT INTERFACE (SPI)

The AD9684 SPI allows the user to configure the converter for

specific functions or operations through a structured register

space provided inside the ADC. The SPI gives the user added

flexibility and customization, depending on the application.

Addresses are accessed via the serial port and can be written to

or read from via the serial port. Memory is organized into bytes

that can be further divided into fields. These fields are

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to program the chip and to read the contents of

the on-chip memory. If the instruction is a readback operation,

performing a readback causes the SDIO pin to change direction

from an input to an output at the appropriate point in the serial

frame.

documented in the Memory Map section. For detailed operational

information, see the Serial Control Interface Standard (Rev. 0).

Data can be sent in MSB first mode or in LSB first mode. MSB

first is the default configuration on power-up and can be

changed via the SPI port configuration register. For more

information about this and other features, see the Serial Control

Interface Standard (Rev. 0).

CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK pin, the SDIO

pin, and the CSB pin (see Table 27). The SCLK (serial clock) pin

synchronizes the read and write data presented from/to the

ADC. The SDIO (serial data input/output) pin is a dual-purpose

pin that allows data to be sent to and read from the internal ADC

memory map registers. The CSB (chip select bar) pin is an active

low control that enables or disables the read and write cycles.

HARDWARE INTERFACE

The pins described in Table 27 compose the physical interface

between the user programming device and the serial port of the

AD9684. The SCLK pin and the CSB pin function as inputs

when using the SPI. The SDIO pin is bidirectional, functioning

as an input during write phases and as an output during

readback.

Table 27. Serial Port Interface Pins

Function

The SPI is flexible enough to be controlled by either field

programmable gate arrays (FPGAs) or microcontrollers. One

method for SPI configuration is described in detail in the AN-

812 Application Note, Microcontroller-Based Serial Port

Interface (SPI) Boot Circuit.

SCLK Serial clock. The serial shift clock input, which synchronizes

the serial interface reads and writes.

SDIO Serial data input/output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

Do not activate the SPI port during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is used

for other devices, it may be necessary to provide buffers between

this bus and the AD9684 to prevent these signals from

transitioning at the converter inputs during critical sampling

periods.

CSB

Chip select bar. An active low control that gates the read

and write cycles.

The falling edge of CSB, in conjunction with the rising edge of

SCLK, determines the start of the framing. See Figure 3 and

Table 5 for an example of the serial timing and its definitions.

Other modes involving the CSB pin are available. The CSB pin

can be held low indefinitely, which permanently enables the

device; this is called streaming. The CSB pin can stall high

between bytes to allow additional external timing. When CSB is

tied high, SPI functions are placed in a high impedance mode.

This mode turns on any secondary functions of the SPI pins.

SPI ACCESSIBLE FEATURES

Table 28 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the Serial Control Interface Standard (Rev. 0). The AD9684

device specific features are described in the Memory Map

section.

All data is composed of 8-bit words. The first bit of each

individual byte of serial data indicates whether a read or write

command is issued. This bit allows the SDIO pin to change

direction from an input to an output.

Table 28. Features Accessible Using the SPI

Feature Name

Description

Mode

Clock

Allows the user to set either power-down mode or standby mode

Allows the user to access the clock divider via the SPI

DDC

Test Input/Output

Output Mode

Allows the user to set up the decimation filters for different applications

Allows the user to set the test modes to have known data on the output bits

Allows the user to set up outputs

Rev. 0 | Page 52 of 64

Data Sheet

AD9684

MEMORY MAP

Logic Levels

READING THE MEMORY MAP REGISTER TABLE

An explanation of logic level terminology follows:

Each row in the memory map register table has eight bit

locations. The memory map is divided into four sections: the

Analog Devices, Inc., SPI registers (Register 0x000 to

Register 0x00D), the ADC function registers (Register 0x015 to

Register 0x278), The DDC function registers (Register 0x300 to

Register 0x387), and the digital outputs and test modes registers

(Register 0x550 to Register 0x05B).

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

“X” denotes a “don’t care” bit.

Channel-Specific Registers

Table 29 documents the default hexadecimal value for each

hexadecimal address shown. The column with the heading Bit 7

(MSB) is the start of the default hexadecimal value given. For

example, Address 0x561, the output mode register, has a

hexadecimal default value of 0x01. This means that Bit 0 = 1,

and the remaining bits are 0s. This setting is the default output

format value, which is twos complement. For more information

on this function and others, see the Table 29.

Some channel setup functions, such as the input termination

(Register 0x016), can be programmed to a different value for

each channel. In these cases, channel address locations are

internally duplicated for each channel. These registers and bits

are designated in Table 29 as local. These local registers and bits

can be accessed by setting the appropriate Channel A or

Channel B bits in Register 0x008. If both bits are set, the

subsequent write affects the registers of both channels. In a read

cycle, set only Channel A or Channel B to read one of the two

registers. If both bits are set during an SPI read cycle, the device

returns the value for Channel A. Registers and bits designated

as global in Table 29 affect the entire device and the channel

features for which independent settings are not allowed

between channels. The settings in Register 0x005 do not affect

the global registers and bits.

Unassigned and Reserved Locations

All address and bit locations that are not included in Table 29

are not currently supported for this device. Write unused bits of

a valid address location with 0s unless the default value is set

otherwise. Writing to these locations is required only when part

of an address location is unassigned (for example, Address 0x561).

If the entire address location is open (for example, Address 0x013),

do not write to this address location.

SPI Soft Reset

Default Values

After issuing a soft reset by programming 0x81 to Register 0x000,

the AD9684 requires 5 ms to recover. Therefore, when program-

ming the AD9684 for application setup, ensure that an adequate

delay is programmed into the firmware after asserting the soft

reset and before starting the device setup.

After the AD9684 is reset, critical registers are loaded with

default values. The default values for the registers are given in

Table 29.

Rev. 0 | Page 53 of 64

AD9684

Data Sheet

MEMORY MAP REGISTER TABLE

All address locations that are not included in Table 29 are not currently supported for this device and must not be written.

Table 29. Memory Map Registers

Reg.

Addr. Register

(Hex) Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit ±

Bit 1

Bit 0 (LSB) Default Notes

Analog Devices SPI Registers

0x000 INTERFACE_ Soft reset

LSB first

0 = MSB

1 = LSB

Address

ascension

0

Address

ascension

LSB first

0 = MSB

1 = LSB

Soft reset

(self

clearing)

0x00

CONFIG_A

(self

clearing)

0x001 INTERFACE_ Single

0

Datapath

soft reset

(self

0

CONFIG_B

instruction

clearing)

0x002 DEVICE_

CONFIG

0

00 = normal operation 0x00

10 = standby

(local)

11 = power-down

0x003 CHIP_TYPE

011 = high speed ADC

0x03

0xD3

Read only

0x004 CHIP_ID

(low byte)

1

0

1

0

1

0x005 CHIP_ID

(high byte)

0

0x00

0x5X

Read only

0x006 CHIP_

GRADE

Chip speed grade

0101 = 500 MSPS

0

1

0

X

0x008 Device

index

0

Channel B Channel A 0x03

0x00A Scratch

pad

0

0x00

0x00B SPI revision

0

1

0

1

0

1

0

1

0

0x01

0x56

0x00C Vendor ID

(low byte)

Read only

0x00D Vendor ID

(high byte)

0

1

0

0x04

0x00

ADC Function Registers

0x015 Analog

input

0

Input

disable

(local)

0 = normal

operation

1 = input

disabled

0x016 Input

Analog input differential termination

0000 = 400 Ω (default)

0001 = 200 Ω

1

0

1

0

0x0C

0x20

termination

(local)

0010 = 100 Ω

0110 = 50 Ω

0x018 Input

buffer

0000 = 1.0× buffer current (default)

0001 = 1.5× buffer current

0010 = 2.0× buffer current

0011 = 2.5× buffer current

0100 = 3.0× buffer current

0101 = 3.5× buffer current

…

0

current

control

(local)

1111 = 8.5× buffer current

0x024 V_1P0

control

0

1.0 V refer- 0x00

ence select

0 = internal

1 =

external

0x025 Input full-

scale range

(local)

0

Full-scale adjust

0000 = 1.94 V

1000 = 1.46 V

1001 = 1.58 V

1010 = 1.70 V

1011 = 1.82 V

0x0C

V p-p

differ-

ential; use

in con-

junction

with Reg.

0x030

1100 = 2.06 V (default)

Rev. 0 | Page 54 of 64

Data Sheet

AD9684

Reg.

Addr. Register

Bit 7

(MSB)

(Hex)

Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit ±

Bit 1

Bit 0 (LSB) Default Notes

0

Diode

selection

0 = no

diode

0x00

Used in

0x028 Tempera-

ture diode

conjunc-

tion with

Reg. 0x040

(local)

selected

1 =

tempera-

ture diode

selected

0x030 Input full-

scale

0

Full-scale control

See Table 9 for

0

0x04

Input full-

scale

control

(local)

recommended settings for

different frequency bands

Default values:

control

(local)

Full scale range ≥ 1.82 V =

001

Full scale range < 1.82 V =

110

0x03F PDWN/

STBY pin

0 =

PDWN/

STBY

enabled

1 =

0

0x00

0x3F

Used in

conjunc-

tion with

Reg. 0x040

control

(local)

disabled

0x040 Chip pin

control

PDWN/STBY function

00 = power down

01 = standby

Fast Detect B (FD_B)

000 = Fast Detect B output

001 = reserved

Fast Detect A (FD_A)

000 = Fast Detect A output

001 = reserved

10 = disabled

010 = reserved

111 = disabled

010 = reserved

011 = temperature diode

111 = disabled

0x10B Clock

divider

0

000 = divide by 1

001 = divide by 2

011 = divide by 4

111 = divide by 8

0x00

0x10C Clock

divider

Independently controls Channel A and Channel B

clock divider phase offset

phase

(local)

0000 = 0 input clock cycles delayed

0001 = ½ input clock cycles delayed

0010 = 1 input clock cycles delayed

0011 = 1½ input clock cycles delayed

0100 = 2 input clock cycles delayed

0101 = 2½ input clock cycles delayed

…

1111 = 7½ input clock cycles delayed

Clock

divider and divider

Clock

divider

must be

>1

0x10D Clock

0

Clock divider negative

skew window

00 = no negative skew

01 = 1 device clock of

negative skew

Clock divider positive 0x00

skew window

00 = no positive skew

01 = 1 device clock of

positive skew

SYNC

control

automatic

phase

adjustment

0 =

disabled

1 =

10 = 2 device clocks of

negative skew

11 = 3 device clocks of

negative skew

10 = 2 device clocks of

positive skew

11 = 3 device clocks of

positive skew

enabled

0x117 Clock delay

control

0

Clock fine

delay

adjust

enable

0 =

0x00

Enabling

the clock

fine delay

adjustment

causes a

disabled

1 =

datapath

soft reset

enabled

Rev. 0 | Page 55 of 64

AD9684

Data Sheet

Reg.

Addr. Register

Bit 7

(MSB)

(Hex)

Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit ±

Bit 1

Bit 0 (LSB) Default Notes

0x118 Clock fine

delay

Clock fine delay adjust, Bits[7:0]

Twos complement coded control to adjust the fine sample clock skew in ~1.7 ps steps

0x00

Used in

con-

(local)

≤−88 = −151.7 ps skew

−87 = −150 ps skew

…

junction

with Reg.

0x0117

0 = 0 ps skew

…

≥+87 = +150 ps skew

0x11C Clock

status

0

0 = no

0x00

Read only

input clock

detected

1 = input

clock det-

ected

SYNC flag

reset

0 = normal

operation

1 = flags

SYNC

transition

select

0 = low to

high

CLK edge

select

0 = rising

SYNC mode select

00 = disabled

01 = continuous

0

0x120 SYNC

Control 1

1 = falling

10 = N shot

held in reset

1 = high to

low

0x121 SYNC

Control 2

0

SYNC N shot ignore counter select

0000 = next SYNC only

0001 = ignore the first SYNC transitions

0010 = ignore the first two SYNC transitions

…

0x00

Mode

select

(Reg.

0x120,

Bits[2:1])

must be

N shot

1111 = ignore the first 16 SYNC transitions

0x123 SYNC

timestamp

delay

SYNC timestamp delay, Bits[6:0]

Ignored

when Reg.

0x01FF =

0x00

0x00 = no delay

0x01 = 1 clock delay

…

control

0x7F = 127 clocks delay

0x128 SYNC

Status 1

SYNC hold status, Register 0x128, Bits [7:4]

SYNC setup status, Register 0x128, Bits [3:0]

Read

only

0x129 SYNC and

0

Clock divider phase when SYNC was captured

0000 = in-phase

Read

only

clock

divider

status

0001 = SYNC is ½ cycle delayed from clock

0010 = SYNC is 1 cycle delayed from clock

0011 = 1½ input clock cycles delayed

0100 = 2 input clock cycles delayed

0101 = 2½ input clock cycles delayed

…

1111 = 7½ input clock cycles delayed

0x12A SYNC

counter

SYNC counter, Bits[7:0] increments when a SYNC signal is captured

Read

only

0x1FF Chip sync

mode

Synchronization mode 0x00

00 = normal

01 = timestamp

0x200 Chip

application

mode

0

Chip Q

ignore

0 = normal

(I/Q)

1 = ignore

(I only)

0

Chip operating mode 0x00

00 = full bandwidth

mode

01 = DDC 0 on

10 = DDC 0 and DDC 1

0x201 Chip

decimation

ratio

0

Chip decimation ratio select

0x00

000 = decimate by 1

001 = decimate by 2

010 = decimate by 4

011 = decimate by 8

100 = decimate by 16

0x228 Customer

offset

Offset adjust in LSBs from +127 to −128 (twos complement format)

Rev. 0 | Page 56 of 64

Data Sheet

AD9684

Reg.

Addr. Register

Bit 7

(MSB)

(Hex)

Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit ±

Bit 1

Bit 0 (LSB) Default Notes

0x245 Fast detect

0

Force FD_A/ Force value

0

Enable fast 0x00

detect

output

(FD)

control

(local)

FD_B pins

0 = normal

function

of FD_A/

FD_B pins if

force pins is

1 = force to true, this

value

value is

output on

FD_x pins

0x247 FD upper

threshold

LSB

Fast detect upper threshold, Bits[7:0]

0x00

(local)

0x248 FD upper

threshold

MSB

0

Fast detect upper threshold, Bits[12:8]

(local)

0x249 FD lower

threshold

LSB

Fast detect lower threshold, Bits[7:0]

(local)

0x24A FD lower

threshold

MSB

Fast detect lower threshold, Bits[12:8]

(local)

0x24B FD dwell

time LSB

Fast detect dwell time, Bits[7:0]

0x00

(local)

0x24C FD dwell

time MSB

Fast detect dwell time, Bits[15:8]

(local)

0x26F Signal

monitor

0

Synchronization mode 0x00

00 = disabled

synchroni-

zation

control

01 = continuous

11 = one-shot

0x270 Signal

monitor

Peak

0

0x00

detector

control

0 =

(local)

disabled

1 =

enabled

0x271 Signal

Monitor

Signal monitor period, Bits[7:0]

Signal monitor period, Bits[15:8]

0x80

0x00

0x01

In

decimated

output

clock cycles

Period

Register 0

(local)

0x272 Signal

Monitor

In

decimated

output

clock cycles

Period

Register 1

(local)

0x273 Signal

Monitor

Signal monitor period, Bits[23:16]

In

decimated

output

clock cycles

Period

Register 2

(local)

0

Result

0

Result

selection

0 =

reserved

1 = peak

detector

0x274 Signal

monitor

result

update

1 = update

results (self

clear)

control

(local)

Rev. 0 | Page 57 of 64

AD9684

Data Sheet

Reg.

Addr. Register

Bit 7

(MSB)

(Hex)

Name

Bit 6

Bit 5

Bit 4

Signal monitor result, Bits[7:0]

When Register 0x0274, Bit 0 = 1, result Bits[19:7] = peak detector absolute value, Bits [12:0]; result Bits[6:0] = 0 only

Bit 3

Bit ±

Bit 1

Bit 0 (LSB) Default Notes

0x275 Signal

Monitor

Read

Updated

based on

Reg. 0x274,

Bit 4

Result

Register 0

(local)

0x276 Signal

Monitor

Signal monitor result, Bits[15:8]

Read

only

Updated

based on

Reg.

Result

Register 1

0x274, Bit 4

(local)

0x277 Signal

Monitor

0

Signal monitor result, Bits[19:16]

Read

only

Updated

based on

Reg.

Result

Register 1

0x274, Bit 4

(local)

0x278 Signal

monitor

period

Period count result, Bits[7:0]

Read

only

Updated

based on

Reg.

counter

result

0x274, Bit 4

(local)

Digital Downconverter (DDC) Function Registers—See the Digital Downconverters (DDCs) Section

0x300 DDC syn-

chronization

control

0

DDC NCO

soft reset

0 = normal

operation

1 = reset

0

Synchronization mode

(triggered by SYNC

00 = disabled

)

01 = continuous

11 = one-shot

0x310 DDC 0

control

Mixer

select

0 = real

mixer

1 =

Gain select

0 = 0 dB

gain

1 = 6 dB

gain

IF mode

Complex to

real enable

0 = disabled

1 = enabled

0

Decimation rate select 0x00

(complex to real

00 = variable IF mode

(mixers and NCO

enabled)

01 = 0 Hz IF mode (mixer

bypassed, NCO disabled)

10 = f_S/4 Hz IF mode (f_S/4

downmixing mode)

disabled)

11 = decimate by 2

00 = decimate by 4

01 = decimate by 8

10 = decimate by 16

(complex to real

complex

mixer

11 = test mode (mixer

inputs forced to +FS,

NCO enabled)

enabled)

11 = decimate by 1

00 = decimate by 2

01 = decimate by 4

10 = decimate by 8

0x311 DDC 0

input

0

Q input

select

0

I input

select

0x00

selection

0 = Ch. A

1 = Ch. B

0 = Ch. A

1 = Ch. B

0x314 DDC 0

frequency

LSB

DDC 0 NCO FTW, Bits[7:0], twos complement

0x00

0x315 DDC 0

frequency

MSB

X

DDC 0 NCO FTW, Bits[11:8], twos complement

0x320 DDC 0

phase LSB

DDC 0 NCO POW, Bits[7:0], twos complement

0x00

0x321 DDC 0

phase MSB

X

0

X

0

X

0

DDC 0 NCO POW, Bits[11:8], twos complement

0x327 DDC 0

output test

mode

0

Q output

test mode

enable

0

I output

test mode

enable

0 =

selection

0 =

disabled

1 = enabled

from Ch. B

disabled

1 =

enabled

from Ch. A

Rev. 0 | Page 58 of 64

Data Sheet

AD9684

Reg.

Addr. Register

Bit 7

(MSB)

(Hex)

Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit ±

Bit 1

Bit 0 (LSB) Default Notes

0x330 DDC 1

control

Mixer

select

0 = real

mixer

1 =

Gain select

0 = 0 dB

gain

1 = 6 dB

gain

IF mode

00 = variable IF mode

(mixers and NCO

Complex to

real enable

0 = disabled

1 = enabled

0

Decimation rate select 0x00

(complex to real

disabled)

11 = decimate by 2

(complex to real

enabled)

01 = 0 Hz IF mode (mixer

bypassed, NCO disabled)

10 = f_S/4 Hz IF mode (f_S/4

downmixing mode)

11 = test mode (mixer

inputs forced to +FS,

NCO enabled)

complex

mixer

11 = decimate by 1

0x331 DDC 1

input

0

Q input

select

0

I input

select

0x00

selection

0 = Ch. A

1 = Ch. B

0 = Ch. A

1 = Ch. B

0x334 DDC 1

frequency

LSB

DDC 1 NCO FTW, Bits[7:0], twos complement

0x00

0x335 DDC 1

frequency

MSB

X

DDC 1 NCO FTW, Bits[11:8], twos complement

0x340 DDC 1

phase LSB

DDC 1 NCO POW, Bits[7:0], twos complement

0x00

0x341 DDC 1

phase MSB

X

0

X

0

X

0

X

0

DDC 1 NCO POW, Bits[11:8], twos complement

0x347 DDC 1

output test

mode

0

Q output

test mode

enable

0

I output

test mode

enable

0 =

disabled

1 =

selection

0 = disabled

1 = enabled

from

Ch. B

enabled

from Ch. A

0x350 DDC 2

control

Mixer

select

0 = real

mixer

1 =

Gain select

0 = 0 dB

gain

1 = 6 dB

gain

IF mode

00 = variable IF mode

(mixers and NCO

enabled)

01 = 0Hz IF mode (mixer

bypassed, NCO disabled)

10 = f_S/4 Hz IF mode (f_S/4

downmixing mode)

11 = test mode (mixer

inputs forced to +FS, NCO

enabled)

Complex to

real enable

0 = disabled

1 = enabled

0

Decimation rate select 0x00

(complex to real

disabled)

11 = decimate by 2

00 = decimate by 4

01 = decimate by 8

10 = decimate by 16

(complex to real

complex

mixer

enabled)

11 = decimate by 1

00 = decimate by 2

01 = decimate by 4

10 = decimate by 8

0x351 DDC 2

input

0

Q input

select

0

I input

select

0x00

selection

0 = Ch. A

1 = Ch. B

0 = Ch. A

1 = Ch. B

0x354 DDC 2

frequency

LSB

DDC 2 NCO FTW, Bits[7:0], twos complement

0x00

0x355 DDC 2

frequency

MSB

X

DDC 2 NCO FTW, Bits[11:8], twos complement

0x360 DDC 2

phase LSB

DDC 2 NCOPOW, Bits[7:0], twos complement

DDC 2 NCO POW, Bits[11:8], twos complement

0x00

0x361 DDC 2

phase MSB

X

Rev. 0 | Page 59 of 64

AD9684

Data Sheet

Reg.

Addr. Register

Bit 7

(MSB)

(Hex)

0x367 DDC 2

output test

Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit ±

Bit 1

Bit 0 (LSB) Default Notes

0

Q output

test mode

enable

0 = disabled

1 = enabled

from Ch. B

0

I output

test mode

enable

0 =

disabled

1 =

0x00

mode

selection

enabled

from Ch. A

0x370 DDC 3

Mixer

select

0 = real

mixer

1 =

Gain select

0 = 0 dB

gain

1 = 6 dB

gain

IF mode

00 = variable IF mode

(mixers and NCO

Complex to

real enable

0 = disabled

1 = enabled

0

Decimation rate select 0x00

(complex to real

control

disabled)

enabled)

11 = decimate by 2

00 = decimate by 4

01 = decimate by 8

10 = decimate by 16

(complex to real

01 = 0 Hz IF mode (mixer

bypassed, NCO disabled)

10 = f_S/4 Hz IF mode (f_S/4

downmixing mode)

11 = test mode (mixer

inputs forced to +FS, NCO

enabled)

complex

mixer

enabled)

11 = decimate by 1

00 = decimate by 2

01 = decimate by 4

10 = decimate by 8

0x371 DDC 3

input

0

Q input

select

0

I input

select

0x05

selection

0 = Ch. A

1 = Ch. B

0 = Ch. A

1 = Ch. B

0x374 DDC 3

frequency

LSB

DDC 3 NCO FTW, Bits[7:0] twos complement

0x00

0x375 DDC 3

frequency

MSB

X

DDC 3 NCO FTW, Bits[11:8] twos complement

0x380 DDC 3

phase LSB

DDC 3 NCO POW, Bits[7:0] twos complement

0x00

0x381 DDC 3

phase MSB

X

0

X

0

X

0

X

0

DDC 3 NCO POW, Bits[11:8] twos complement

0x387 DDC 3

output test

mode

0

Q output

test mode

0

I output

test mode

enable

0 =

disabled

1 =

enable

selection

0 = disabled

1 = enabled

from Ch. B

enabled

from Ch. A

Digital Outputs and Test Modes

0x550 ADC test

modes

User

0

Reset PN

long gen

0 = long

PN enable enable

1 = long

PN reset

Reset PN

short gen

0 = short PN

Test mode selection

0000 = off (normal operation)

0001 = midscale short

0010 = positive full scale

0011 = negative full scale

0x00

pattern

selection

0 =

continuous

repeat

(local)

1 = short PN

reset

0100 = alternating checker board

1 = single

pattern

0101 = PN sequence, long

0110 = PN sequence, short

0111 = one/zero word toggle

1000 = the user pattern test mode (used with

Register 0x550, Bit 7 and User Pattern 1 to User

Pattern 4 registers)

1111 = ramp output

0x551 User

Pattern 1

LSB

0

0x00

Used with

Reg. 0x550

and

Reg. 0x573

0x552 User

Pattern 1

MSB

0

Used with

Reg. 0x550

and

Reg. 0x573

Rev. 0 | Page 60 of 64

Data Sheet

AD9684

Reg.

Addr. Register

Bit 7

(MSB)

(Hex)

0x553 User

Pattern 2

Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit ±

Bit 1

Bit 0 (LSB) Default Notes

0

0x00

Used with

Reg. 0x550

and

LSB

Reg. 0x573

0x554 User

0

Used with

Reg. 0x550

and

Pattern 2

MSB

Reg. 0x573

0x555 User

Used with

Reg. 0x550

and

Pattern 3

LSB

Reg. 0x573

0x556 User

Used with

Reg. 0x550

and

Pattern 3

MSB

Reg. 0x573

0x557 User

Used with

Reg. 0x550

and

Pattern 4

LSB

Reg. 0x573

0x558 User

Used with

Reg. 0x550

and

Pattern 4

MSB

Reg. 0x573

0x559 Output

Mode

Status bit selection

000 = tie low (1’b0)

Control 1

001 = overrange bit

010 = signal monitor bit

011 = fast detect (FD) bit

100 = not applicable

101 = system reference

0x561 Output

mode

0

Sample

invert

0 = normal

1 = sample

invert

Data format select

00 = offset binary

01 = twos

complement

0x01

0x00

0x562 Output

overrange

Virtual

Con-

verter 7 OR OR

0 = OR bit 0 = OR bit

enabled

Virtual

Converter 6

Virtual

Converter 5 verter 4 OR

OR

0 = OR bit

enabled

1 = OR bit

cleared

Virtual Con-

verter 3 OR

0 = OR bit

enabled

1 = OR bit

cleared

Virtual Con-

verter 2 OR

0 = OR bit

enabled

1 = OR bit

cleared

Virtual

Con-

verter 1

Convert-

er 0 OR

(OR) clear

0 = OR bit

enabled

1 = OR bit

cleared

OR

0 = OR bit

enabled

1 = OR bit

cleared

enabled

0 = OR

bit

enabled

1 = OR

bit

1 = OR bit 1 = OR bit

cleared

0x563 Output OR Virtual

Virtual Con-

verter 6 OR

verter 7 OR 0 = no OR

0 = no OR 1 = OR

Virtual

Converter 3

OR

0 = no OR

1 = OR

Virtual Con-

verter 2 OR

0 = no OR

1 = OR

Virtual

0x00

Read only

status

Con-

Converter 5 Converter 4

OR

0 = no OR

1 = OR

occurred

Converter Converter 0

1 OR OR

0 = no OR 0 = no OR

1 = OR 1 = OR

occurred occurred

OR

0 = no OR

1 = OR

occurred

1 = OR

occurred

0x564 Output

channel

0

Converter

channel

swap

select

0 = normal

channel

ordering

1 =

channel

swap

enabled

Rev. 0 | Page 61 of 64

AD9684

Data Sheet

Reg.

Addr. Register

Bit 7

(MSB)

(Hex)

Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit ±

Bit 1

Bit 0 (LSB) Default Notes

0x568 LVDS

output

0

Frame clock mode (only

used when in output data

mode is in byte mode)

00 = frame clock always

off

0

Output data mode

0x00

000 = parallel mode (one converter)

001 = parallel interleaved mode (two

converters)

mode

010 = parallel channel multiplexed

(even/odd) mode (one converter)

011 = parallel channel multiplexed

(even/odd) mode (two converters)

100 = byte mode (one converter)

101 = byte mode (two converters)

110 = byte mode (four converters)

Others = reserved

01 = frame clock always

on

10 = reserved

11 = frame clock

conditionally on based

on PN23 sequence

0x569 Digital

clock

0

1

0

DCO phase adjustment 0x01

0x0: 0°

0x1: 90°

0x2: 180°

0x3: 270°

output

adjust

0x56A Output

Parallel

0

LVDS output drive current adjust

000 = 2 mA

0

0x4C

Driver

Adjust 1

001 = 2.25 mA

010 = 2.5 mA

011 = 2.75 mA

100 = 3.0 mA

101 = 3.25 mA

110 = 3.5 mA (default)

111 = 3.75 mA

0x05B Output

Parallel

0

Output slew rate

control of LVDS driver

Interface

0x00

Driver

Adjust 2

00 = 80 ps

01 = 150 ps

10 = 200 ps

11 = 250 ps

Rev. 0 | Page 62 of 64

Data Sheet

AD9684

APPLICATIONS INFORMATION

It is not necessary to split all of these power domains in all

POWER SUPPLY RECOMMENDATIONS

cases. The recommended solution shown in Figure 70 provides

the lowest noise, highest efficiency power delivery system for

the AD9684. If only one 1.25 V supply is available, route to

AVDD1 first and then tap it off and isolate it with a ferrite bead

or a filter choke, preceded by decoupling capacitors for

SPIVDD, DVDD, and DRVDD, in that order. The user can

employ several different decoupling capacitors to cover both

high and low frequencies. These capacitors must be located

close to the point of entry at the PCB level and close to the

devices, with minimal trace lengths.

The AD9684 must be powered by the following six supplies:

AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD =

1.25 V, DRVDD = 1.25 V, and SPIVDD = 1.8 V. For applications

requiring an optimal high power efficiency and low noise

performance, it is recommended that the ADP2164 and ADP2370

switching regulators be used to convert the 3.3 V, 5.0 V, or 12 V

input rails to an intermediate rail (1.8 V and 3.8 V). These

intermediate rails are then postregulated by very low noise, low

dropout (LDO) regulators (ADP1741, ADP1740, and ADP125).

Figure 70 shows the recommended power supply scheme for

the AD9684.

3.3V

INPUT

ADP1741

LDO

2.5V: AVDD2

1.8V: SPIVDD

1.25V: AVDD1

1.25V: DVDD

1.25V: DRVDD

ADP125

LDO

ADP2164

1.8V

ADP1741

LDO

BUCK

REGULATOR

ADP1741

LDO

ADP1740

LDO

ADP2370

3.8V

5V/12V

INPUT

ADP125

LDO

3.3V: AVDD3

BUCK

REGULATOR

Figure 70. High Efficiency, Low Noise Power Solution for the AD9684

Rev. 0 | Page 63 of 64

AD9684

Data Sheet

OUTLINE DIMENSIONS

12.10

12.00 SQ

11.90

A1 BALL

PAD CORNER

A1 BALL

PAD CORNER

14 13 12 11 10 9

8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

8.20 SQ

10.40 REF

SQ

K

L

0.80

11.20 SQ

M

N

P

TOP VIEW

BOTTOM VIEW

0.80 REF

DETAIL A

1.49

1.38

1.27

1.15

1.05

0.95

DETAIL A

0.75

REF

0.38

0.33

0.28

0.30 REF

0.50

0.45

0.40

SEATING

PLANE

COPLANARITY

0.12

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.

Figure 71. 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]

(BP-196-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

AD9684BBPZ-500

AD9684BBPZRL7-500

AD9684-500EBZ

−40°C to +85°C

196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]

Evaluation Board for AD9684-500

BP-196-3

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D13015-0-5/15(0)

Rev. 0 | Page 64 of 64


型号：	AD9684BBPZ-500
厂家：	ADI
描述：	Dual Analog-to-Digital Converter
文件：	总65页 (文件大小：1276K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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