AD8426ACPZ-R7 [ADI]
Wide Supply Range, Rail-to-Rail; 宽电源电压范围，轨到轨
| 型号： | AD8426ACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | Wide Supply Range, Rail-to-Rail |
| 文件： | 总28页 (文件大小：805K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wide Supply Range, Rail-to-Rail
Output Instrumentation Amplifier
AD8426
CONNECTION DIAGRAM
FEATURES
2 channels in a small, 4 mm × 4 mm LFCSP
LFCSP package has no metal pad
More routing room
No current leakage to pad
Gain set with 1 external resistor
Gain range: 1 to 1000
Input voltage goes below ground
Inputs protected beyond supplies
Very wide power supply range
Single supply: 2.2 V to 36 V
16 15 14 13
AD8426
12 –IN2
–IN1
RG1
RG1
+IN1
1
2
3
4
RG2
RG2
+IN2
11
10
9
5
6
7
8
Dual supply: 1.35 V to 18 V
Bandwidth (G = 1): 1 MHz
Figure 1.
CMRR (G = 1): 80 dB minimum
Input noise: 24 nV/√Hz
Typical supply current (per amplifier): 350 μA
Specified temperature range: −40°C to +125°C
Table 1. Instrumentation Amplifiers by Category1
General-
Purpose
Zero
Drift
Military
Grade
Low
Power
High Speed
PGA
AD8220
AD8221
AD8222
AD8224
AD8228
AD8295
AD8231
AD8290
AD8293
AD8553
AD8556
AD8557
AD620
AD621
AD524
AD526
AD624
AD627
AD623
AD8250
AD8251
AD8253
APPLICATIONS
Industrial process controls
Bridge amplifiers
Medical instrumentation
Portable data acquisition
Multichannel systems
AD8235
AD8236
AD8426
AD8226
AD8227
1 See www.analog.com for the latest instrumentation amplifiers.
GENERAL DESCRIPTION
The AD8426 is a dual-channel, low cost, wide supply range
instrumentation amplifier that requires only one external
resistor to set any gain from 1 to 1000.
The AD8426 is designed to make PCB routing easy and efficient.
The two amplifiers are arranged in a logical way so that typical
application circuits have short routes and few vias. Unlike most
chip scale packages, the AD8426 does not have an exposed metal
pad on the bottom of the part, which frees additional space for
routing and vias. The AD8426 offers two in-amps in the equivalent
board space of a typical MSOP package.
The AD8426 is designed to work with a variety of signal
voltages. A wide input range and rail-to-rail output allow the
signal to make full use of the supply rails. Because the input
range can also go below the negative supply, small signals near
ground can be amplified without requiring dual supplies. The
AD8426 operates on supplies ranging from 1.35 V to 18 V
for dual supplies and 2.2 V to 36 V for a single supply.
The AD8426 is ideal for multichannel, space-constrained industrial
applications. Unlike other low cost, low power instrumentation
amplifiers, the AD8426 is designed with a minimum gain of 1 and
can easily handle 10 V signals. With its space-saving LFCSP
package and 125°C temperature rating, the AD8426 thrives in
tightly packed, zero airflow designs.
The robust AD8426 inputs are designed to connect to real-
world sensors. In addition to its wide operating range, the
AD8426 can handle voltages beyond the rails. For example,
with a 5 V supply, the part is guaranteed to withstand 35 V
at the input with no damage. Minimum and maximum input
bias currents are specified to facilitate open-wire detection.
The AD8226 is the single-channel version of the AD8426.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
AD8426
TABLE OF CONTENTS
Features .............................................................................................. 1
Gain Selection............................................................................. 21
Reference Terminal .................................................................... 22
Input Voltage Range................................................................... 22
Layout .......................................................................................... 23
Input Bias Current Return Path ............................................... 24
Input Protection ......................................................................... 24
Radio Frequency Interference (RFI)........................................ 24
Applications Information.............................................................. 25
Precision Strain Gage................................................................. 25
Differential Drive ....................................................................... 25
Driving a Cable........................................................................... 26
Driving an ADC ......................................................................... 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
Connection Diagram ....................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual-Supply Operation ............................................................... 3
Single-Supply Operation ............................................................. 6
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 21
Architecture................................................................................. 21
REVISION HISTORY
7/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD8426
SPECIFICATIONS
DUAL-SUPPLY OPERATION
+VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 2.
A Grade
Typ
B Grade
Typ
Test Conditions/
Comments
Parameter
Min
Max
Min
Max
Unit
COMMON-MODE REJECTION
RATIO (CMRR)
VCM = −10 V to +10 V
CMRR, DC to 60 Hz
G = 1
G = 10
80
90
dB
dB
dB
dB
100
105
105
105
110
110
G = 100
G = 1000
CMRR at 5 kHz
G = 1
G = 10
G = 100
80
90
90
100
80
90
90
100
dB
dB
dB
dB
G = 1000
NOISE
Total noise:
eN = √(eNI2 + (eNO/G)2)
Voltage Noise
Input Voltage Noise, eNI
Output Voltage Noise, eNO
RTI Noise
f = 1 kHz
24
120
27
125
24
120
27
125
nV/√Hz
nV/√Hz
f = 0.1 Hz to 10 Hz
G = 1
G = 10
G = 100 to 1000
Current Noise
2
2
μV p-p
μV p-p
μV p-p
fA/√Hz
pA p-p
0.5
0.4
100
3
0.5
0.4
100
3
f = 1 kHz
f = 0.1 Hz to 10 Hz
VOLTAGE OFFSET
Input Offset, VOSI
Average Temperature
Coefficient
Output Offset, VOSO
Total offset voltage:
V
OS = VOSI + (VOSO/G)
VS = 5 V to 15 V
TA = −40°C to +125°C
200
2
100
1
μV
μV/°C
0.5
2
0.5
1
VS = 5 V to 15 V
TA = −40°C to +125°C
1000
10
500
5
μV
μV/°C
Average Temperature
Coefficient
Offset RTI vs. Supply (PSR)
G = 1
G = 10
G = 100
G = 1000
VS = 5 V to 15 V
80
90
dB
dB
dB
dB
100
105
105
105
110
110
INPUT CURRENT
Input Bias Current1
TA = +25°C
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
5
5
5
20
15
30
70
27
25
35
5
5
5
20
15
30
70
27
25
35
nA
nA
nA
pA/°C
Average Temperature
Coefficient
Input Offset Current
TA = +25°C
TA = +125°C
TA = −40°C
1.5
1.5
2
0.5
0.5
0.5
nA
nA
nA
Average Temperature
Coefficient
TA = −40°C to +125°C
5
5
pA/°C
Rev. 0 | Page 3 of 28
AD8426
A Grade
Typ
B Grade
Typ
Test Conditions/
Comments
Parameter
REFERENCE INPUT
RIN
Min
−VS
1
Max
+VS
Min
−VS
1
Max
+VS
Unit
100
7
100
7
kΩ
μA
V
V/V
%
IIN
Voltage Range
Reference Gain to Output
Reference Gain Error
GAIN
Gain Range
Gain Error
1
0.01
1
0.01
G = 1 + (49.4 kΩ/RG)
VOUT 10 V
1000
1000
V/V
G = 1
0.04
0.3
0.01
0.1
%
%
G = 5 to 1000
Gain Nonlinearity
G = 1 to 10
G = 100
G = 1000
Gain vs. Temperature2
VOUT = −10 V to +10 V
RL ≥ 2 kΩ
RL ≥ 2 kΩ
20
75
750
20
75
750
ppm
ppm
ppm
RL ≥ 2 kΩ
G = 1
TA = −40°C to +85°C
TA = +85°C to +125°C
TA = −40°C to +125°C
VS = 1.35 V to +36 V
5
5
1
2
ppm/°C
ppm/°C
ppm/°C
G > 1
−100
−100
INPUT
Input Impedance
Differential
Common Mode
Input Operating Voltage
Range3
0.8||2
0.4||2
0.8||2
0.4||2
GΩ||pF
GΩ||pF
V
TA = +25°C
−VS − 0.1
+VS − 0.8
−VS − 0.1
+VS − 0.8
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
−VS − 0.05
−VS − 0.15
+VS − 40
+VS − 0.6
+VS − 0.9
−VS + 40
−VS − 0.05
−VS − 0.15
+VS − 40
+VS − 0.6
+VS − 0.9
−VS + 40
V
V
V
Input Overvoltage Range
OUTPUT
Output Swing
RL = 2 kΩ to Ground
TA = +25°C
TA = +125°C
TA = −40°C
TA = +25°C
TA = +125°C
TA = −40°C
−VS + 0.4
−VS + 0.4
−VS + 1.2
−VS + 0.2
−VS + 0.3
−VS + 0.2
−VS + 0.1
+VS − 0.7
+VS − 1.0
+VS − 1.1
+VS − 0.2
+VS − 0.3
+VS − 0.2
+VS − 0.1
−VS + 0.4
−VS + 0.4
−VS + 1.2
−VS + 0.2
−VS + 0.3
−VS + 0.2
−VS + 0.1
+VS − 0.7
+VS − 1.0
+VS − 1.1
+VS − 0.2
+VS − 0.3
+VS − 0.2
+VS − 0.1
V
V
V
V
V
V
V
mA
RL = 10 kΩ to Ground
RL = 100 kΩ to Ground
Short-Circuit Current
POWER SUPPLY
TA = −40°C to +125°C
13
13
Operating Range
Quiescent Current
(Per Amplifier)
Dual-supply operation
TA = +25°C
1.35
18
425
1.35
18
425
V
μA
350
350
TA = −40°C
TA = +85°C
TA = +125°C
250
450
525
325
525
600
+125
250
450
525
325
525
600
+125
μA
μA
μA
°C
TEMPERATURE RANGE
−40
−40
1 The input stage uses PNP transistors; therefore, input bias current always flows into the part.
2 The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3 Input voltage range of the AD8426 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the Input Voltage Range section for more information.
Rev. 0 | Page 4 of 28
AD8426
Dynamic Performance Specifications
+VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 3. Single-Ended Output Configuration (Both Amplifiers)
A Grade
Typ
B Grade
Typ
Test Conditions/
Comments
Parameter
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1
Min
Max
Min
Max
Unit
1000
160
20
1000
160
20
kHz
kHz
kHz
kHz
G = 10
G = 100
G = 1000
2
2
Settling Time 0.01%
G = 1
G = 10
G = 100
G = 1000
10 V step
25
15
40
750
25
15
40
750
μs
μs
μs
μs
Slew Rate
G = 1
G = 5 to 100
0.4
0.6
0.4
0.6
V/μs
V/μs
Table 4. Differential Output Configuration
Test Conditions/
Comments
A Grade
Typ
B Grade
Typ
Parameter
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1
Min
Max
Min
Max
Unit
850
300
30
850
300
30
kHz
kHz
kHz
kHz
G = 10
G = 100
G = 1000
2
2
Settling Time 0.01%
G = 1
G = 10
G = 100
G = 1000
10 V step
25
15
80
300
25
15
80
300
μs
μs
μs
μs
Slew Rate
G = 1
G = 5 to 100
0.4
0.6
0.4
0.6
V/μs
V/μs
Rev. 0 | Page 5 of 28
AD8426
SINGLE-SUPPLY OPERATION
+VS = 2.7 V, −VS = 0 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 5.
A Grade
Typ
B Grade
Typ
Test Conditions/
Comments
Parameter
Min
Max
Min
Max
Unit
COMMON-MODE REJECTION
RATIO (CMRR)
VCM = 0 V to 1.7 V
CMRR, DC to 60 Hz
G = 1
G = 10
80
90
dB
dB
dB
dB
100
105
105
105
110
110
G = 100
G = 1000
CMRR at 5 kHz
G = 1
G = 10
G = 100
80
90
90
100
80
90
90
100
dB
dB
dB
dB
G = 1000
NOISE
Total noise:
eN = √(eNI2 + (eNO/G)2)
Voltage Noise
Input Voltage Noise, eNI
Output Voltage Noise, eNO
RTI Noise
f = 1 kHz
24
120
27
125
24
120
27
125
nV/√Hz
nV/√Hz
f = 0.1 Hz to 10 Hz
G = 1
G = 10
G = 100 to 1000
Current Noise
2
2
μV p-p
μV p-p
μV p-p
fA/√Hz
pA p-p
0.5
0.4
100
3
0.5
0.4
100
3
f = 1 kHz
f = 0.1 Hz to 10 Hz
VOLTAGE OFFSET
Input Offset, VOSI
Average Temperature
Coefficient
Output Offset, VOSO
Average Temperature
Coefficient
Offset RTI vs. Supply (PSR)
G = 1
G = 10
G = 100
Total offset voltage:
VOS = VOSI + (VOSO/G)
300
3
150
1.5
μV
μV/°C
TA = −40°C to +125°C
0.5
2
0.5
1
1000
12
500
8
μV
μV/°C
TA = −40°C to +125°C
VS = 2.7 V to 36 V
80
90
dB
dB
dB
dB
100
105
105
105
110
110
G = 1000
INPUT CURRENT
Input Bias Current1
TA = +25°C
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
5
5
5
20
15
30
70
30
28
38
5
5
5
20
15
30
70
30
28
38
nA
nA
nA
pA/°C
Average Temperature
Coefficient
Input Offset Current
TA = +25°C
TA = +125°C
TA = −40°C
2
2
3
1
1
1
nA
nA
nA
Average Temperature
Coefficient
TA = −40°C to +125°C
5
5
pA/°C
Rev. 0 | Page 6 of 28
AD8426
A Grade
Typ
B Grade
Typ
Test Conditions/
Comments
Parameter
REFERENCE INPUT
RIN
Min
−VS
1
Max
+VS
Min
−VS
1
Max
+VS
Unit
100
7
100
7
kΩ
μA
V
V/V
%
IIN
Voltage Range
Reference Gain to Output
Reference Gain Error
GAIN
Gain Range
Gain Error
1
0.01
1
0.01
G = 1 + (49.4 kΩ/RG)
1000
1000
V/V
G = 1
VOUT = 0.8 V to 1.8 V
VOUT = 0.2 V to 2.5 V
0.05
0.3
0.05
0.1
%
%
G = 5 to 1000
Gain vs. Temperature2
G = 1
TA = −40°C to +85°C
TA = +85°C to +125°C
TA = −40°C to +125°C
5
5
1
2
ppm/°C
ppm/°C
ppm/°C
G > 1
−100
−100
INPUT
−VS = 0 V, +VS = 2.7 V
to 36 V
Input Impedance
Differential
Common Mode
0.8||2
0.4||2
0.8||2
0.4||2
GΩ||pF
GΩ||pF
Input Operating Voltage
Range3
TA = +25°C
−0.1
+VS − 0.7
−0.1
+VS − 0.7
V
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
−0.05
−0.15
+VS − 40
+VS − 0.6
+VS − 0.9
−VS + 40
−0.05
−0.15
+VS − 40
+VS − 0.6
+VS − 0.9
−VS + 40
V
V
V
Input Overvoltage Range
OUTPUT
Output Swing
RL = 10 kΩ to 1.35 V
Short-Circuit Current
POWER SUPPLY
Operating Range
Quiescent Current
(Per Amplifier)
TA = −40°C to +125°C
0.1
+VS − 0.1
36
0.1
2.2
+VS − 0.1
36
V
mA
13
13
Single-supply operation 2.2
−VS = 0 V, +VS = 2.7 V
V
TA = +25°C
TA = −40°C
TA = +85°C
TA = +125°C
−40
325
250
425
475
400
325
500
550
+125
325
250
425
475
400
325
500
550
+125
μA
μA
μA
μA
°C
TEMPERATURE RANGE
−40
1 The input stage uses PNP transistors; therefore, input bias current always flows into the part.
2 The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3 Input voltage range of the AD8426 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the Input Voltage Range section for more information.
Rev. 0 | Page 7 of 28
AD8426
Dynamic Performance Specifications
+VS = 2.7 V, −VS = 0 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 6. Single-Ended Output Configuration (Both Amplifiers)
A Grade
Typ
B Grade
Typ
Test Conditions/
Comments
Parameter
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1
Min
Max
Min
Max
Unit
1000
160
20
1000
160
20
kHz
kHz
kHz
kHz
G = 10
G = 100
G = 1000
2
2
Settling Time 0.01%
G = 1
G = 10
G = 100
G = 1000
2 V step
6
6
35
750
6
6
35
750
μs
μs
μs
μs
Slew Rate
G = 1
G = 5 to 100
0.4
0.6
0.4
0.6
V/μs
V/μs
Table 7. Differential Output Configuration
Test Conditions/
Comments
A Grade
Typ
B Grade
Typ
Parameter
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1
Min
Max
Min
Max
Unit
850
300
30
850
300
30
kHz
kHz
kHz
kHz
G = 10
G = 100
G = 1000
2
2
Settling Time 0.01%
G = 1
G = 10
G = 100
G = 1000
2 V step
25
15
80
300
25
15
80
300
μs
μs
μs
μs
Slew Rate
G = 1
G = 5 to 100
0.4
0.6
0.4
0.6
V/μs
V/μs
Rev. 0 | Page 8 of 28
AD8426
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 8.
The θJA value in Table 9 assumes a 4-layer JEDEC standard
board with zero airflow.
Parameter
Rating
Supply Voltage
18 V
Output Short-Circuit Current
Maximum Voltage at −INx or +INx
Minimum Voltage at −INx or +INx
REFx Voltage
Indefinite
−VS + 40 V
+VS − 40 V
VS
Table 9.
Package
θJA
Unit
16-Lead LFCSP (CP-16-19)
86
°C/W
Storage Temperature Range
Specified Temperature Range
Maximum Junction Temperature
ESD
−65°C to +150°C
−40°C to +125°C
130°C
ESD CAUTION
Human Body Model
Charged Device Model
Machine Model
1.5 kV
1.5 kV
100 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 9 of 28
AD8426
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16 15 14 13
AD8426
12 –IN2
–IN1
RG1
RG1
+IN1
1
2
3
4
RG2
RG2
+IN2
11
10
9
5
6
7
8
Figure 2. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
−IN1
RG1
RG1
+IN1
+VS
Description
1
2
3
4
Negative Input, In-Amp 1
Gain-Setting Resistor Terminal, In-Amp 1
Gain-Setting Resistor Terminal, In-Amp 1
Positive Input, In-Amp 1
Positive Supply
5
6
7
8
REF1
REF2
−VS
Reference Adjust, In-Amp 1
Reference Adjust, In-Amp 2
Negative Supply
9
+IN2
RG2
RG2
−IN2
−VS
OUT2
OUT1
+VS
Positive Input, In-Amp 2
Gain-Setting Resistor Terminal, In-Amp 2
Gain-Setting Resistor Terminal, In-Amp 2
Negative Input, In-Amp 2
Negative Supply
Output, In-Amp 2
Output, In-Amp 1
Positive Supply
10
11
12
13
14
15
16
Rev. 0 | Page 10 of 28
AD8426
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 15 V, RL = 10 kꢀ, unless otherwise noted.
IN-AMP 1
IN-AMP 1
IN-AMP 2
60
50
40
30
20
10
0
IN-AMP 2
40
30
20
10
0
–100
–50
0
50
100
–21
–20
–19
I (nA)
BIAS
–18
–17
CMRR (µV/V)
Figure 3. Typical Distribution for CMRR (G = 1)
Figure 6. Typical Distribution of Input Bias Current, Inverting Input
50
40
30
20
10
0
IN-AMP 1
IN-AMP 2
IN-AMP 1
IN-AMP 2
50
40
30
20
10
0
–21
–20
–19
(nA)
–18
–17
–100
–50
0
50
100
I
BIAS
V
(µV)
OSI
Figure 4. Typical Distribution of Input Offset Voltage
Figure 7. Typical Distribution of Input Bias Current, Noninverting Input
60
50
40
30
20
10
0
IN-AMP 1
IN-AMP 2
IN-AMP 1
IN-AMP 2
70
60
50
40
30
20
10
0
–600
–400
–200
0
200
400
600
–0.010
–0.005
0
0.005
0.010
GAIN ERROR (%)
V
(µV)
OSO
Figure 5. Typical Distribution of Output Offset Voltage
Figure 8. Typical Distribution of Gain Error (G = 1)
Rev. 0 | Page 11 of 28
AD8426
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
+0.01V, +1.90V
V
= +1.35V
REF
+0.01V, +1.90V
V
= +1.35V
REF
+1.35V, +1.95V
+1.35V, +1.94V
+2.61V, +1.13V
+2.60V, +1.11V
+0.01V, +1.28V
+0.01V, +1.19V
+2.17V, +0.90V
V
= 0V
V
= 0V
REF
+2.46V, +0.72V
REF
+2.61V, +0.37V
+0.01V, +0.31V
+0.01V, +0.05V
+2.61V, +0.08V
–0.5
–0.5
–1.0
+1.35V, –0.41V
0.00V, –0.45V
+0.01V, –0.40V
+1.35V, –0.55V
–1.0
–0.5
2.0
0
0.5
1.0
1.5
2.5
3.0
2.0
–0.5
0
0.5
1.0
1.5
2.5
3.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 9. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = 2.7 V, G = 1
Figure 12. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = 2.7 V, G = 100
5
5
V
= +2.50V
+0.02V, +4.25V
REF
+2.50V, +4.25V
+2.49V, +4.25V
+0.02V, +4.20V
V
= +2.5V
REF
4
3
4
3
+4.90V, +3.02V
+4.90V, +3.03V
+0.02V, +2.95V
+0.02V, +2.89V
V
= 0V
REF
+4.64V, +2.03V
2
2
V
= 0V
REF
+4.77V, +1.71V
+0.01V, +0.87V
1
1
+0.01V, +0.69V
+4.90V, +0.82V
+4.90V, +0.54V
0
0
+2.49V, –0.30V
+2.50V, –0.40V
+0.01V, –0.30V
+0.01V, –0.40V
–1
–0.5
–1
–0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT VOLTAGE (V)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT VOLTAGE (V)
Figure 10. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = 5 V, G = 1
Figure 13. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = 5 V, G = 100
6
6
0V, +4.25V
0V, +4.24V
4
4
2
2
+4.87V, +1.79V
+4.90V, +1.76V
–4.93V, +1.77V
–4.93V, +1.74V
0
–2
–4
–6
0
–2
–4
–6
+4.90V, –2.84V
+4.90V, –3.18V
–4.93V, –2.83V
–4.93V, –3.15V
0V, –5.30V
–0.01V, –5.30V
4
–6
–4
–2
0
2
4
6
–6
–4
–2
0
2
6
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 11. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = 5 V, G = 1
Figure 14. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = 5 V, G = 100
Rev. 0 | Page 12 of 28
AD8426
20
15
20
15
V
= ±15V
V = ±15V
S
S
0V, +14.2V
0V, +11.2V
0V, +14.1V
0V, +11.2V
+14.8V, +6.64V
10
10
–14.9V, +6.61V
–14.9V, +6.7V
+14.8V, +6.8V
5
5
–11.9V, +5.2V
–11.9V, –6.0V
–11.9V, +5.22V
–11.9V, –6.71V
+11.9V, +5.3V
+11.8V, –6.5V
+11.8V, +5.25V
V
= ±12V
V = ±12V
S
S
0
0
–5
–5
+11.8V, –6.63V
0V, –12.3V
–0.01V, –12.3V
–10
–15
–20
–10
–15
–20
–14.9V, –7.6V
+14.8V, –7.9V
+14.8V, –8.18V
–14.9V, –8.09V
0V, –15.3V
0
–0.01V, –15.3V
0
–20
–15
–10
–5
5
10
15
20
–20
–15
–10
–5
5
10
15
20
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 15. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = 15 V and VS = 12 V, G = 1
Figure 18. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = 15 V and VS = 12 V, G = 100
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0.6
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0.6
V
= 2.7V
V = 2.7V
S
G = 100
S
0.5
0.5
G = 1
–V = 0V
–V = 0V
IN
IN
0.4
0.4
V
V
OUT
OUT
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
I
IN
I
IN
–0.25
–0.25
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 16. Input Overvoltage Performance,
Single Supply, VS = 2.7 V, G = 1
Figure 19. Input Overvoltage Performance,
Single Supply, VS = 2.7 V, G = 100
16
14
12
10
8
16
14
12
10
8
0.8
0.8
V
G = 1
–V = 0V
= ±15V
V = ±15V
S
G = 100
S
0.7
0.7
0.6
0.6
–V = 0V
IN
IN
V
V
OUT
OUT
0.5
0.5
0.4
0.4
6
6
0.3
0.3
4
4
0.2
0.2
2
2
0.1
0.1
I
IN
0
0
0
0
–2
–4
–6
–8
–10
–12
–14
–16
–2
–4
–6
–8
–10
–12
–14
–16
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
I
IN
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 17. Input Overvoltage Performance,
Dual Supply, VS = 15 V, G = 1
Figure 20. Input Overvoltage Performance,
Dual Supply, VS = 15 V, G = 100
Rev. 0 | Page 13 of 28
AD8426
30
28
26
24
22
20
18
50
45
40
35
30
25
20
15
10
5
–15.1V
–0.12V
+4.22V
+14.1V
0
16
–5
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–16
–12
–8
–4
0
4
8
12
16
COMMON-MODE VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
Figure 21. Input Bias Current vs. Common-Mode Voltage,
Single Supply, VS = 5 V
Figure 24. Input Bias Current vs. Common-Mode Voltage,
Dual Supply, VS = 15 V
160
140
120
100
160
140
120
100
GAIN = 1000
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
GAIN = 100
GAIN = 10
GAIN = 1
80
60
40
20
0
80
60
40
20
0
0.1
1
10
100
1k
10k
100k
1M
0.1
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 22. Positive PSRR vs. Frequency, RTI
Figure 25. Negative PSRR vs. Frequency
70
60
70
60
50
40
30
20
10
0
V
= ±15V
S
GAIN = 1000
GAIN = 100
GAIN = 1000
50
40
GAIN = 100
GAIN = 10
30
GAIN = 10
GAIN = 1
20
10
0
GAIN = 1
–10
–20
–30
–10
–20
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23. Gain vs. Frequency, Dual Supply, VS = 15 V
Figure 26. Gain vs. Frequency, Single Supply, VS = 2.7 V
Rev. 0 | Page 14 of 28
AD8426
30
25
20
15
10
5
250
200
150
100
50
160
GAIN = 1000
GAIN = 100
140
120
100
80
BANDWIDTH
LIMITED
GAIN = 10
GAIN = 1
±I
B
I
OS
60
40
20
0
0
0
–45
–50
115 135
–25
–5
15
35
55
75
95
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 27. CMRR vs. Frequency, RTI
Figure 30. Input Bias Current and Input Offset Current vs. Temperature
120
100
80
40
20
GAIN = 100
GAIN = 1000
GAIN = 1
BANDWIDTH
LIMITED
GAIN = 10
0
–20
–40
–60
60
40
20
0
NORMALIZED AT 25°C
–80
0.1
1
10
100
FREQUENCY (Hz)
1k
10k
100k
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
Figure 31. Gain Error vs. Temperature, G = 1
Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance
6
5
4
3
2
1
0
10
5
0
–5
–1
–10
–15
–20
–2
–3
–4
–5
–6
REPRESENTATIVE DATA
NORMALIZED AT 25°C
0
10 20 30 40 50 60 70 80 90 100 110 120
WARM-UP TIME (Seconds)
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
Figure 29. Change in Input Offset Voltage vs. Warm-Up Time
Figure 32. CMRR vs. Temperature, G = 1
Rev. 0 | Page 15 of 28
AD8426
+V
15
10
5
S
–40°C
+25°C
+85°C
+105°C
+125°C
–0.2
–0.4
–0.6
–0.8
–40°C
+25°C
+85°C
+105°C
+125°C
0
–V
S
–5
–10
–15
–0.2
–0.4
–0.6
–0.8
100
1k
10k
100k
2
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (±V )
LOAD RESISTANCE (Ω)
S
Figure 36. Output Voltage Swing vs. Load Resistance
Figure 33. Input Voltage Limit vs. Supply Voltage
+V
+V
S
S
–0.2
–0.4
–0.6
–0.8
–0.1
–0.2
–0.3
–0.4
–40°C
+25°C
+85°C
+105°C
+125°C
–40°C
+25°C
+85°C
+105°C
+125°C
+0.4
+0.3
+0.2
+0.1
+0.8
+0.6
+0.4
+0.2
–V
–V
S
0.01
S
0.1
1
10
2
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (±V )
OUTPUT CURRENT (µA)
S
Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ
Figure 37. Output Voltage Swing vs. Output Current, G = 1
+V
S
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–40°C
+25°C
+85°C
+105°C
+125°C
+1.2
+1.0
+0.8
+0.6
+0.4
+0.2
–V
S
OUTPUT VOLTAGE (V)
2
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (±V )
S
Figure 38. Gain Nonlinearity, RL ≥ 10 kΩ, G = 1
Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ
Rev. 0 | Page 16 of 28
AD8426
1k
100
10
GAIN = 1
GAIN = 100
GAIN = 10
GAIN = 1000
1k
OUTPUT VOLTAGE (V)
1
10
100
10k
100k
FREQUENCY (Hz)
Figure 39. Gain Nonlinearity, RL ≥ 10 kΩ, G = 10
Figure 42. Voltage Noise Spectral Density vs. Frequency
GAIN = 1000, 200nV/DIV
GAIN = 1, 1µV/DIV
1s/DIV
OUTPUT VOLTAGE (V)
Figure 40. Gain Nonlinearity, RL ≥ 10 kΩ, G = 100
Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000
1k
100
10
OUTPUT VOLTAGE (V)
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 44. Current Noise Spectral Density vs. Frequency
Figure 41. Gain Nonlinearity, RL ≥ 10 kΩ, G = 1000
Rev. 0 | Page 17 of 28
AD8426
5V/DIV
17µs TO 0.01%
23µs TO 0.001%
0.002%/DIV
1.5pA/DIV
1s/DIV
50µs/DIV
Figure 45. 0.1 Hz to 10 Hz Current Noise
Figure 48. Large Signal Pulse Response and Settling Time,
10 V Step, Dual Supply, VS = 15 V, G = 10
30
V
= ±15V
27
24
21
18
15
12
9
S
5V/DIV
42µs TO 0.01%
60µs TO 0.001%
0.002%/DIV
6
V
= +5V
S
3
100µs/DIV
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 46. Large Signal Frequency Response
Figure 49. Large Signal Pulse Response and Settling Time,
10 V Step, Dual Supply, VS = 15 V, G = 100
5V/DIV
5V/DIV
580µs TO 0.01%
780µs TO 0.001%
26µs TO 0.01%
27µs TO 0.001%
0.002%/DIV
0.002%/DIV
50µs/DIV
500µs/DIV
Figure 47. Large Signal Pulse Response and Settling Time,
10 V Step, Dual Supply, VS = 15 V, G = 1
Figure 50. Large Signal Pulse Response and Settling Time,
10 V Step, Dual Supply, VS = 15 V, G = 1000
Rev. 0 | Page 18 of 28
AD8426
20mV/DIV
4µs/DIV
20mV/DIV
100µs/DIV
Figure 51. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF, G = 1
Figure 54. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF, G = 1000
NO LOAD
47pF
100pF
147pF
20mV/DIV
4µs/DIV
20mV/DIV
4µs/DIV
Figure 52. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF, G = 10
Figure 55. Small Signal Pulse Response with Various Capacitive Loads,
G = 1, RL = Infinity
60
50
40
SETTLED TO 0.001%
30
SETTLED TO 0.01%
20
10
0
20mV/DIV
20µs/DIV
2
4
6
8
10
12
14
16
18
20
STEP SIZE (V)
Figure 53. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF, G = 100
Figure 56. Settling Time vs. Step Size, Dual Supply, VS = 15 V
Rev. 0 | Page 19 of 28
AD8426
760
740
720
700
680
660
640
70
60
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
50
40
30
20
10
0
–10
–20
100
620
0
1k
10k
100k
1M
2
4
6
8
10
12
14
16
18
FREQUENCY (Hz)
SUPPLY VOLTAGE (±V )
S
Figure 57. Supply Current vs. Supply Voltage (Both Amplifiers)
Figure 59. Gain vs. Frequency, Differential Output Configuration
200
100
90
180
GAIN = 1000
160
80
140
70
LIMITED BY
MEASUREMENT
120 GAIN = 1
60
50
40
30
20
10
0
SYSTEM
100
80
60
40
20
0
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 58. Channel Separation vs. Frequency, RL = 2 kΩ,
Source Channel at G = 1 and G = 1000
Figure 60. Output Balance vs. Frequency, Differential Output Configuration
Rev. 0 | Page 20 of 28
AD8426
THEORY OF OPERATION
+V
–V
+V
–V
S
S
R
G
NODE 3
NODE 4
R3
50kꢀ
S
S
R1
24.7kꢀ
R2
24.7kꢀ
+V
–V
S
R4
50kꢀ
NODE 2
V
A3
OUT
+V
–V
NODE 1
R5
50kꢀ
S
R6
50kꢀ
S
ESD AND
OVERVOLTAGE
PROTECTION
ESD AND
OVERVOLTAGE
PROTECTION
REF
Q1
Q2
+IN
–IN
A1
A2
S
V
R
R
BIAS
B
B
–V
DIFFERENCE
AMPLIFIER STAGE
S
GAIN STAGE
Figure 61. Simplified Schematic
ARCHITECTURE
GAIN SELECTION
The AD8426 is based on the classic 3-op-amp topology. This
topology has two stages: a gain stage (preamplifier) to provide
differential amplification, followed by a difference amplifier stage
to remove the common-mode voltage. Figure 61 shows a simplified
schematic of one of the instrumentation amplifiers in the AD8426.
Placing a resistor across the RG terminals sets the gain of the
AD8426. The gain can be calculated by referring to Table 11
or by using the following gain equation:
49.4 kΩ
RG =
G −1
The first stage works as follows. To maintain a constant voltage
across the bias resistor, RB, A1 must keep Node 3 at a constant
diode drop above the positive input voltage. Similarly, A2 keeps
Node 4 at a constant diode drop above the negative input voltage.
Therefore, a replica of the differential input voltage is placed
across the gain setting resistor, RG. The current that flows across
this resistance must also flow through the R1 and R2 resistors,
creating a gained differential signal between the A2 and A1 out-
puts. Note that, in addition to a gained differential signal, the
original common-mode signal, shifted up by a diode drop, is
also still present.
Table 11. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG
Calculated Gain
49.9 kΩ
12.4 kΩ
5.49 kΩ
2.61 kΩ
1.00 kΩ
499 Ω
1.990
4.984
9.998
19.93
50.40
100.0
249 Ω
199.4
100 Ω
495.0
49.9 Ω
991.0
The second stage is a difference amplifier, composed of A3 and
four 50 kꢀ resistors. The purpose of this stage is to remove the
common-mode signal from the amplified differential signal.
The AD8426 defaults to G = 1 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the AD8426 specifications to determine the total gain accu-
racy of the system. When the gain resistor is not used, gain
error and gain drift are minimal.
The transfer function of the AD8426 is
V
OUT = G × (VIN+ − VIN−) + VREF
where:
49.4 kΩ
G =1 +
RG
Rev. 0 | Page 21 of 28
AD8426
Equation 1 to Equation 3 can be used to understand the inter-
action of the gain (G), common-mode input voltage (VCM),
differential input voltage (VDIFF), and reference voltage (VREF).
REFERENCE TERMINAL
The output voltage of the AD8426 is developed with respect
to the potential on the reference terminal. This is useful when
the output signal needs to be offset to a precise midsupply level.
For example, a voltage source can be tied to the REF pin to level-
shift the output so that the AD8426 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
The values for the constants (V−LIMIT, V+LIMIT, and VREF_LIMIT
)
at different temperatures are shown in Table 12. These three
equations, along with the input and output voltage range speci-
fications in Table 2 and Table 5, set the operating boundaries
of the part.
V
DIFF × G
For the best performance, source impedance to the REF
terminal should be kept below 2 ꢀ. As shown in Figure 62,
the reference terminal, REF, is at one end of a 50 kΩ resistor.
Additional impedance at the REF terminal adds to this 50 kΩ
resistor and results in amplification of the signal connected to
the positive input. The amplification from the additional RREF
VCM
VCM
−
+
> −VS + V−LIMIT
(1)
(2)
2
V
DIFF × G
< +VS − V+LIMIT
2
V
DIFF ×G
⎛
⎜
⎞
+ VCM +VREF
⎟
⎟
⎟
can be computed by 2 × (50 kΩ + RREF)/100 kΩ + RREF
.
2
⎜
⎜
< +VS − VREF_LIMIT
(3)
Only the positive signal path is amplified; the negative path is
unaffected. This uneven amplification degrades the CMRR of
the amplifier.
2
⎜
⎝
⎟
⎠
Table 12. Input Voltage Range Constants for Various
Temperatures
INCORRECT
CORRECT
CORRECT
Temperature
V−LIMIT (V)
V+LIMIT (V)
VREF_LIMIT (V)
−40°C
−0.55
+0.8
+1.3
AD8426
AD8426
AD8426
+25°C
−0.35
+0.7
+1.15
REF
REF
REF
V
V
REF
REF
+85°C
+125°C
−0.15
−0.05
+0.65
+0.6
+1.05
+0.9
V
REF
+
+
OP1177
–
AD8426
–
The common-mode input voltage range shifts upward with temp-
erature. At cold temperatures, the part requires extra headroom
from the positive supply, whereas operation near the negative
supply has more margin. Conversely, at hot temperatures, the part
requires less headroom from the positive supply but is subject
to the worst-case conditions for input voltages near the negative
supply.
Figure 62. Driving the Reference Pin
INPUT VOLTAGE RANGE
The 3-op-amp architecture of the AD8426 applies gain in
the first stage before removing common-mode voltage in the
difference amplifier stage. In addition, the input transistors in
the first stage shift the common-mode voltage up one diode
drop. Therefore, internal nodes between the first and second
stages (Node 1 and Node 2 in Figure 61) experience a combina-
tion of gained signal, common-mode signal, and a diode drop.
This combined signal can be limited by the voltage supplies even
when the individual input and output signals are not limited.
Figure 9 to Figure 15 and Figure 18 show the allowable common-
mode input voltage ranges for various output voltages and
supply voltages.
A typical part functions up to the boundaries described in this
section. However, for best performance, designing with a few
hundred millivolts of extra margin is recommended. As signals
approach the boundary, internal transistors begin to saturate,
which can affect frequency and linearity performance.
Rev. 0 | Page 22 of 28
AD8426
Common-Mode Rejection Ratio over Frequency
LAYOUT
Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp. Such
conversions occur when one input path has a frequency response
that is different from the other. To keep CMRR over frequency
high, the input source impedance and capacitance of each path
should be closely matched. Additional source resistance in the
input paths (for example, for input protection) should be placed
close to the in-amp inputs to minimize the interaction of the
inputs with parasitic capacitance from the PCB traces.
To ensure optimum performance of the AD8426 at the PCB
level, care must be taken in the design of the board layout.
The AD8426 pins are arranged in a logical manner to aid in
this task.
16 15 14 13
AD8426
12 –IN2
–IN1
RG1
RG1
+IN1
1
2
3
4
RG2
RG2
+IN2
11
10
9
Parasitic capacitance at the gain setting pins can also affect CMRR
over frequency. If the board design has a component at the gain
setting pins (for example, a switch or jumper), the component
should be chosen so that the parasitic capacitance is as small as
possible.
5
6
7
8
Power Supplies
Figure 63. Pinout Diagram
A stable dc voltage should be used to power the instrumenta-
tion amplifier. Noise on the supply pins can adversely affect
performance. See the PSRR performance curves in Figure 22
and Figure 25 for more information.
Package Considerations
The AD8426 is available in a 16-lead, 4 mm × 4 mm LFCSP with
no exposed paddle. The footprint from another 4 mm × 4 mm
LFCSP part should not be copied because it may not have the
correct lead pitch and lead width dimensions. Refer to the
Outline Dimensions section to verify that the corresponding
dimensional symbol has the correct dimensions.
A 0.1 μF capacitor should be placed as close as possible to each
supply pin. As shown in Figure 65, a 10 μF capacitor can be used
farther away from the part. In most cases, it can be shared by
other precision integrated circuits.
+V
S
Hidden Paddle Package
The AD8426 is available in an LFCSP package with a hidden
paddle. Unlike chip scale packages where the pad limits routing
capability, this package allows routes and vias directly beneath
the chip. In this way, the full space savings of the small LFCSP
can be realized. Although the package has no metal in the center
of the part, the manufacturing process leaves a very small section
of exposed metal at each of the package corners, as shown in
Figure 64 and in Figure 73 in the Outline Dimensions section.
This metal is connected to −VS through the part. Because of the
possibility of a short, vias should not be placed beneath these
exposed metal tabs.
0.1µF
10µF
+IN
–IN
OUT
LOAD
R
G
AD8426
REF
0.1µF
10µF
–V
S
Figure 65. Supply Decoupling, REF, and Output Referred to Local Ground
HIDDEN
PADDLE
References
The output voltage of the AD8426 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie the REFx pins to the appropriate local ground. This should
also help minimize crosstalk between the two channels.
EXPOSED METAL
TABS
BOTTOM VIEW
NOTES
1. EXPOSED METAL TABS AT THE FOUR
CORNERS OF THE PACKAGE ARE
INTERNALLY CONNECTED TO –V .
S
Figure 64. Hidden Paddle Package, Bottom View
Rev. 0 | Page 23 of 28
AD8426
The other AD8426 terminals should be kept within the supplies.
All terminals of the AD8426 are protected against ESD.
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8426 must have a return path
to ground. When the source, such as a thermocouple, cannot
provide a current return path, one should be created, as shown
in Figure 66.
For applications where the AD8426 encounters voltages beyond
the allowed limits, external current limiting resistors and low
leakage diode clamps such as the BAV199L, the FJH1100, or the
SP720 should be used.
INCORRECT
+V
CORRECT
+V
RADIO FREQUENCY INTERFERENCE (RFI)
S
S
RF interference is often a problem when amplifiers are used in
applications where there are strong RF signals. The precision
circuits in the AD8426 can rectify the RF signals so that they
appear as a dc offset voltage error. To avoid this rectification,
place a low-pass RC filter at the input of the instrumentation
amplifier (see Figure 67). The filter limits both the differential
and common-mode bandwidth, as shown in the following
equations:
AD8426
AD8426
REF
REF
REF
REF
–V
–V
S
S
TRANSFORMER
TRANSFORMER
1
+V
S
+V
S
FilterFrequencyDIFF
FilterFrequencyCM
=
2πR(2CD +CC )
1
=
2πRCC
AD8426
AD8426
REF
where CD ≥ 10 CC.
+V
10Mꢀ
S
–V
–V
S
S
0.1µF
+IN
10µF
THERMOCOUPLE
THERMOCOUPLE
C
1nF
C
+V
+V
S
S
R
4.02kꢀ
C
C
C
OUT
C
10nF
D
R
G
AD8426
R
R
1
R
REF
fHIGH-PASS
=
AD8426
2πRC
AD8426
–IN
4.02kꢀ
C
REF
C
C
1nF
0.1µF
10µF
–V
–V
S
S
–V
S
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
Figure 67. RFI Suppression
Figure 66. Creating an Input Bias Current Return Path
CD affects the differential signal, and CC affects the common-
mode signal. Values of R and CC should be chosen to minimize
RFI. Any mismatch between the R × CC at the positive input
and the R × CC at the negative input degrades the CMRR of the
AD8426. By using a value of CD one order of magnitude larger
than CC, the effect of the mismatch is reduced, and performance
is improved.
INPUT PROTECTION
The AD8426 has very robust inputs and typically does not
need additional input protection. Input voltages can be up to
40 V from the opposite supply rail. For example, with a +5 V
positive supply and a −8 V negative supply, the part can safely
withstand voltages from −35 V to +32 V. Unlike some other
instrumentation amplifiers, the part can handle large differen-
tial input voltages even when the part is in high gain. Figure 16,
Figure 17, Figure 19, and Figure 20 show the behavior of the
part under overvoltage conditions.
Rev. 0 | Page 24 of 28
AD8426
APPLICATIONS INFORMATION
A common application sets the common-mode output voltage
to the midscale of a differential ADC. In this case, the ADC
reference voltage is sent to the +IN2 terminal, and ground is
connected to the REF2 terminal. This produces a common-
mode output voltage of half the ADC reference voltage.
PRECISION STRAIN GAGE
The low offset and high CMRR over frequency of the AD8426
make it an excellent candidate for bridge measurements. The
bridge can be connected directly to the inputs of the amplifier
(see Figure 68).
2-Channel Differential Output Using a Dual Op Amp
5V
10µF
0.1µF
Another differential output topology is shown in Figure 70.
Instead of a second in-amp, one-half of a dual op amp creates
the inverted output. The recommended dual op amps (the
AD8642 and the AD822) are packaged in an MSOP. This
configuration allows the creation of a dual-channel, precision
differential output in-amp with little board area.
350ꢀ
350ꢀ
350ꢀ
350ꢀ
+IN
–IN
+
R
AD8426
G
–
2.5V
Figure 70 shows how to configure the AD8426 for differential
output.
Figure 68. Precision Strain Gage
DIFFERENTIAL DRIVE
+IN
The differential output configuration of the AD8426 has the
same excellent dc precision specifications as the single-ended
output configuration.
V
AD8426
OUT+
–IN
R
R
REF
V
BIAS
Differential Output Using Both AD8426 Amplifiers
–
+
The circuit configuration is shown in Figure 69. The differential
output specifications in Table 2, Table 4, Table 5, and Table 7
refer to this configuration only. The circuit includes an RC filter
that maintains the stability of the loop.
OP AMP
V
OUT–
RECOMMENDED OP AMPS: AD8642, AD822.
RECOMMENDED R VALUES: 5kꢀ TO 20kꢀ.
+IN1
R
+
V
OUT+
G
AD8426
–
Figure 70. Differential Output Using an Op Amp
–IN1
10kꢀ
The differential output voltage is set by the following equation:
–
100pF
V
DIFF_OUT = VOUT+ − VOUT− = G × (VIN+ − VIN−)
AD8426
where:
+INx
+
REF2
49.4 kΩ
G = 1+
V
OUT–
RG
Figure 69. Differential Circuit Schematic
The common-mode output voltage is set by the following
equation:
The differential output voltage is set by the following equation:
V
DIFF_OUT = VOUT+ − VOUT− = G × (VIN+ − VIN−)
V
CM_OUT = (VOUT+ − VOUT−)/2 = VBIAS
where:
The advantage of this circuit is that the dc differential accuracy
depends on the AD8426 and not on the op amp or the resistors.
This circuit takes advantage of the precise control of the AD8426
over its output voltage relative to the reference voltage. Op amp
dc performance and resistor matching do affect the dc common-
mode output accuracy. However, because common-mode errors
are likely to be rejected by the next device in the signal chain, these
errors typically have little effect on overall system accuracy.
49.4 kΩ
G = 1+
RG
The common-mode output voltage is set by the average of +IN2
and REF2. The transfer function is
V
CM_OUT = (VOUT+ + VOUT−)/2 = (V+IN2 + VREF2)/2
For best ac performance, an op amp with gain bandwidth of at
least 2 MHz and a slew rate of at least 1 V/μs is recommended.
Good choices for op amps are the AD8642 and the AD822.
Rev. 0 | Page 25 of 28
AD8426
Tips for Best Differential Output Performance
DRIVING A CABLE
Keep trace lengths from resistors to the inverting terminal of
the op amp as short as possible. Excessive capacitance at this
node can cause the circuit to be unstable. If capacitance cannot
be avoided, use lower value resistors.
All cables have a certain capacitance per unit length, which varies
widely with cable type. The capacitive load from the cable may
cause peaking in the output response of the AD8426. To reduce
the peaking, use a resistor between the AD8426 outputs and the
cable (see Figure 71). Because cable capacitance and desired output
response vary widely, this resistor is best determined empirically.
A good starting point is 50 Ω.
For best linearity and ac performance, a minimum positive supply
voltage (+VS) is required. Table 13 shows the minimum supply
voltage required for optimum performance, where VCM_MAX
indicates the maximum common-mode voltage expected at the
input of the AD8426.
AD8426
Table 13. Minimum Positive Supply Voltage
Temperature
Equation
DIFFERENTIAL OUTPUT
Less than −10°C
−10°C to +25°C
More than +25°C
+VS > (VCM_MAX + VBIAS)/2 + 1.4 V
+VS > (VCM_MAX + VBIAS)/2 + 1.25 V
+VS > (VCM_MAX + VBIAS)/2 + 1.1 V
AD8426
SINGLE OUTPUT
Figure 71. Driving a Cable
The AD8426 operates at such a relatively low frequency that
transmission line effects are rarely an issue; therefore, the resistor
need not match the characteristic impedance of the cable.
Rev. 0 | Page 26 of 28
AD8426
Option 2 shows a circuit for driving higher frequency signals.
It uses a precision op amp (AD8616) with relatively high band-
width and output drive. This amplifier can drive a resistor and
capacitor with a much higher time constant and is, therefore,
suited for higher frequency applications.
DRIVING AN ADC
Figure 72 shows several different methods of driving an ADC.
The ADC in the ADuC7026 microcontroller was chosen for
this example because it has an unbuffered, charge sampling
architecture that is typical of most modern ADCs. This type of
architecture typically requires an RC buffer stage between the
ADC and the amplifier to work correctly.
Option 3 is useful for applications where the AD8426 must
operate from a large voltage supply but drives a single-supply
ADC. In normal operation, the AD8426 output signal stays
within the ADC range, and the AD8616 simply buffers the signal.
However, in a fault condition, the output of the AD8426 may
go outside the supply range of both the AD8616 and the ADC.
This is not a problem in this circuit, because the 10 kΩ resistor
between the two amplifiers limits the current into the AD8616
to a safe level.
Option 1 shows the minimum configuration required to drive
a charge sampling ADC. The capacitor provides charge to the
ADC sampling capacitor, and the resistor shields the AD8426
from the capacitance. To keep the AD8426 stable, the RC time
constant of the resistor and capacitor needs to stay above 5 μs.
This circuit is mainly useful for lower frequency signals.
OPTION 1: DRIVING LOW FREQUENCY SIGNALS
3.3V
3.3V
AV
DD
ADC0
100ꢀ
AD8426
REF
100nF
ADuC7026
OPTION 2: DRIVING HIGH FREQUENCY SIGNALS
3.3V
3.3V
AD8426
10ꢀ
REF
ADC1
AD8616
10nF
OPTION 3: PROTECTING ADC FROM LARGE VOLTAGES
+15V
AD8426
–15V
3.3V
10kꢀ
10ꢀ
REF
AD8616
ADC2
AGND
10nF
Figure 72. Driving an ADC
Rev. 0 | Page 27 of 28
AD8426
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
13
12
16
1
4
0.65
BSC
PIN 1
INDICATOR
3.75
BCS SQ
1.95 REF
SQ
9
8
5
0.75
0.60
0.50
TOP VIEW
BOTTOM VIEW
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.35
0.30
0.25
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-263-VBBC
Figure 73. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad, with Hidden Paddle
(CP-16-19)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD8426ACPZ-R7
AD8426ACPZ-WP
AD8426BCPZ-R7
AD8426BCPZ-WP
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
CP-16-19
CP-16-19
CP-16-19
CP-16-19
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
1 Z = RoHS Compliant Part.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09490-0-7/11(0)
Rev. 0 | Page 28 of 28
相关型号：
©2020 ICPDF网 联系我们和版权申明