AD8364-EVAL-2140_技术文档

LF to 2.7 GHz

Dual 60 dB TruPwr™ Detector

AD8364

FUNCTIONAL BLOCK DIAGRAM

FEATURES

RMS measurement of high crest-factor signals

Dual-channel and channel difference outputs ports

Integrated accurately scaled temperature sensor

Wide dynamic range 1 dB over 60 dB

0.5 dB temperature-stable linear-in-dB response

Low log conformance ripple

24

23

22

21

20

19

18

17

TEMP

VGA

CONTROL

25

26

27

28

29

30

16

15

14

13

12

11

VPSA

INHA

VSTA

OUTA

FBKA

OUTP

OUTN

FBKB

2

I

SIG

CHANNEL A

TruPwr™

+5 V operation at 70 mA, –40°C to +85°C

Small footprint, 5 mm x 5 mm, LFCSP

2

I

TGT

INLA

PWDN

COMR

INLB

OUTA

OUTB

APPLICATIONS

Wireless infrastructure power amplifier linearization/control

Antenna VSWR monitor

Gain and power control and measurement

Transmitter signal strength indication (TSSI)

Dual-channel wireless infrastructure radios

2

I

SIG

CHANNEL B

TruPwr™

31

32

10

9

INHB

OUTB

VSTB

2

I

TGT

VPSB

VGA

CONTROL

BIAS

1

2

3

4

5

6

7

8

Figure 1. Functional Block Diagram

GENERAL DESCRIPTION

The AD8364 is a true rms, responding, dual-channel RF power

measurement subsystem for the precise measurement and control

of signal power. The flexibility of the AD8364 allows communi-

cations systems, such as RF power amplifiers and radio transceiver

AGC circuits, to be monitored and controlled with ease. Operating

on a single 5 V supply, each channel is fully specified for operation

up to 2.7 GHz over a dynamic range of 60 dB. The AD8364

provides accurately scaled, independent, rms outputs of both RF

measurement channels. Difference output ports, which measure

the difference between the two channels, are also available. The

on-chip channel matching makes the rms channel difference

outputs extremely stable with temperature and process variations.

The device also includes a useful temperature sensor with an

accurately scaled voltage proportional to temperature, specified

over the device operating temperature range. The AD8364 can

be used with input signals having rms values from −55 dBm to

+5 dBm referred to 50 Ω and large crest factors with no

accuracy degradation.

Integrated in the AD8364 are two matched AD8362 channels

(see the AD8362 data sheet for more information) with improved

temperature performance and reduced log conformance ripple.

Enhancements include improved temperature performance and

reduced log-conformance ripple compared to the AD8362. On-

chip wide bandwidth output op amps are connected to accom-

modate flexible configurations that support many system

solutions.

The device can easily be configured to provide four rms

measurements simultaneously. Linear-in-dB rms measurements

are supplied at OUTA and OUTB, with conveniently scaled

slopes of 50 mV/dB. The rms difference between OUTA and

OUTB is available as differential or single-ended signals at

OUTP and OUTN. An optional voltage applied to VLVL

provides a common mode reference level to offset OUTP and

OUTN above ground.

The AD8364 is supplied in a 32-lead, 5 mm × 5 mm LFCSP, for

the operating temperature of –40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD8364

TABLE OF CONTENTS

Specifications..................................................................................... 3

Gain-Stable Transmitter/Receiver............................................ 29

Temperature Compensation Adjustment................................ 31

Device Calibration and Error Calculation.............................. 31

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

General Description and Theory.................................................. 18

Square Law Detector and Amplitude Target .......................... 19

RF Input Interface ...................................................................... 19

Offset Compensation................................................................. 19

Temperature Sensor Interface................................................... 20

VREF Interface ........................................................................... 20

Power-Down Interface............................................................... 20

VST[A, B] Interface.................................................................... 20

OUT[A, B, P, N] Outputs .......................................................... 21

Selecting Calibration Points to Improve Accuracy

over a Reduced Range................................................................ 32

Altering the Slope....................................................................... 34

Channel Isolation ....................................................................... 35

Choosing the Right Value for CHP[A, B] and CLP[A, B].... 36

RF Burst Response Time ........................................................... 36

Single-Ended Input Operation ................................................. 36

Printed Circuit Board Considerations..................................... 37

Package Considerations............................................................. 37

Description of Characterization............................................... 38

Basis for Error Calculations...................................................... 38

Evaluation and Characterization Circuit Board Layouts...... 40

Evaluation Boards........................................................................... 44

Assembly Drawings.................................................................... 46

Outline Dimensions....................................................................... 47

Ordering Guide .......................................................................... 47

Measurement Channel Difference Output

Using OUT[P, N]........................................................................ 22

Controller Mode......................................................................... 22

RF Measurement Mode Basic Connections............................ 23

Controller Mode Basic Connections ....................................... 24

Constant Output Power Operation.......................................... 27

REVISION HISTORY

4/05—Revision 0: Initial Version

Rev. 0 | Page 2 of 48

AD8364

SPECIFICATIONS

V_S= VPSA = VPSB = VPSR = 5 V, T_A= 25°C, Channel A frequency = Channel B frequency, VLVL = VREF, VST[A, B] = OUT[A, B],

OUT[P, N] = FBK[A, B], differential input via Balun, CW input f ≤ 2.7 GHz, unless otherwise noted.

Table 1.

Parameter

Conditions

Min

Typ

Max

Unit

OVERALL FUNCTION

Signal Input Interface

Specified Frequency Range

DC Common-Mode Voltage

Signal Output Interface

Wideband Noise

Channel A and Channel B, CW sine wave input

INH[A, B] (Pins 26, 31) INL[A, B] (Pins 27, 30)

LF

2.7

GHz

V

2.5

40

OUT[A, B] (Pins 15, 10)

CLP[A, B] = 0.1µF, f_SPOT= 100 kHz,

RF input = 2140 MHz, ≥−40 dBm

nV/√Hz

MEASUREMENT MODE,

450 MHz OPERATION

ADJA = ADJB = 0 V, error referred to best fit line using

linear regression @ P_{INH[A, B]}= −40 dBm and −20 dBm,

T_A= 25°C, balun = M/A-Com ETK4-2T

1 dB Dynamic Range¹

0.5 dB Dynamic Range¹

Pins OUT[A, B]

−40°C < T_A< +85°C

Pins OUT[A, B], (Channel A/Channel B)

−40°C < T_A< +85°C, (Channel A/Channel B)

1 dB error

69

65

dB

dBm

mV/dB

dBm

V

62/59

50/52

12

−58

51.6

−59

2.53

0.99

Maximum Input Level

Minimum Input Level

Slope

1 dB error

Intercept

Output Voltage—High Power In Pins OUT[A, B] @ P_{INH[A, B]}= −10 dBm

Output Voltage—Low Power In

Temperature Sensitivity

Pins OUT[A, B] @ P_{INH[A, B]}= −40 dBm

Deviation from OUT[A, B] @ 25°C

V

−40°C < T_A< 85°C; P_{INH[A, B]}= −10 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −25 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −40 dBm

Deviation from OUTP to OUTN @ 25°C

−40°C < T_A< 85°C; P_{INH[A, B]}= −10 dBm, −25 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −25 dBm, −25 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −40 dBm, −25 dBm

Baluns = Macom ETC1.6-4-2-3 (both channels)

Freq separation = 1 kHz

−0.1, +0.2

−0.2, +0.3

−0.3, +0.4

dB

0.25

0.2

dB

Input A to Input B Isolation

Input A to OUTB Isolation

Input B to OUTA Isolation²

71

P_INHB= −50 dBm, OUTB = OUTB_PINHB1 dB

P_INHA= −50 dBm, OUTA = OUTA_PINHA1 dB

54

dB

Input Impedance

Input Return Loss

INHA/INLA, INHB/INLB differential drive

With recommended balun

210||0.1

−12

Ω||pF

dB

MEASUREMENT MODE,

880 MHz OPERATION

ADJA = ADJB = 0 V, error referred to best fit line using

linear regression @ P_{INH[A, B]}= −40 dBm and −20 dBm,

T_A= 25°C, balun = Mini-Circuits® JTX-4-10T

1 dB Dynamic Range¹

0.5 dB Dynamic Range¹

Pins OUT[A, B], (Channel A/Channel B)

−40°C < T_A< +85°C

Pins OUT[A, B], (Channel A/Channel B)

−40°C < T_A< +85°C

1 dB error, (Channel A/Channel B)

66/57

58/40

62/54

20/20

8/0

−58/−57

51.6

−59.2

2.54

dB

dBm

mV/dB

dBm

V

Maximum Input Level

Minimum Input Level

Slope

Intercept

Output Voltage—High Power In Pins OUT[A, B] @ P_{INH[A, B]}= −10 dBm

Output Voltage—Low Power In Pins OUT[A, B] @ P_{INH[A, B]}= −40 dBm

0.99

V

Rev. 0 | Page 3 of 48

AD8364

Parameter

Conditions

Min

Typ

Max

Unit

Temperature Sensitivity

Deviation from OUT[A, B] @ 25°C

−40°C < T_A< 85°C; P_{INH[A, B]}= −10 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −25 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −40 dBm

Deviation from OUTP to OUTN @ 25°C

−40°C < T_A< 85°C; P_{INH[A, B]}= −10 dBm, −25 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −25 dBm, −25 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −40 dBm, −25 dBm

Baluns = Macom ETC1.6-4-2-3 (both channels)

P_INHB= −50 dBm, OUTB = OUTB_PINHB1 dB

P_INHA= −50 dBm, OUTA = OUTA_PINHA1 dB

+0.5

dB

+0.1, −0.2

64

35

dB

Input A to Input B Isolation

Input A to OUTB Isolation

Input B to OUTA Isolation²

Input Impedance

Input Return Loss

INHA/INLA, INHB/INLB differential drive

With recommended balun

200||0.3

−9

Ω||pF

dB

MEASUREMENT MODE,

1880 MHz OPERATION

ADJA = ADJB = 0.75 V, error referred to best fit line using

linear regression @ P_{INH[A, B]}= −40 dBm and −20 dBm,

T_A= 25°C, balun = Murata LDB181G8820C-110

1 dB Dynamic Range¹

0.5 dB Dynamic Range¹

Pins OUT[A, B], (Channel A/Channel B)

−40°C < T_A< +85°C

Pins OUT[A, B], (Channel A/Channel B)

−40°C < T_A< +85°C

1 dB error, (Channel A/Channel B)

1 dB error

69/61

60/50

62/51

58/51

11/3

−58

50

−62

2.49

dB

dBm

mV/dB

dBm

V

Maximum Input Level

Minimum Input Level

Slope

Intercept

Output Voltage—High Power In Pins OUT[A, B] @ P_INH[A,B]= −10 dBm

Output Voltage—Low Power In

Temperature Sensitivity

Pins OUT[A, B] @ P_INH[A,B]= −40 dBm

Deviation from OUT[A, B] @ 25°C

0.98

V

−40°C < T_A< 85°C; P_{INH[A, B]}= −10 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −25 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −40 dBm

Deviation from OUTP to OUTN @ 25°C

−40°C < T_A< 85°C; P_{INH[A, B]}= −10 dBm, −25 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −25 dBm, −25 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −40 dBm, −25 dBm

Baluns = Macom ETC1.6-4-2-3 (both channels)

P_INHB= −50 dBm, OUTB = OUTB_PINHB1 dB

P_INHA= −50 dBm, OUTA = OUTA_PINHA1 dB

+0.5, −0.2

dB

0.3

61

33

dB

Input A to Input B Isolation

Input A to OUTB Isolation

Input B to OUTA Isolation²

Input Impedance

Input Return Loss

INHA/INLA, INHB/INLB differential drive

With recommended balun

167||0.14

−8

Ω||pF

dB

MEASUREMENT MODE,

2.14 GHz OPERATION

ADJA = ADJB = 1.02 V, error referred to best fit line using

linear regression @ P_{INH[A, B]}= −40 dBm and −20 dBm,

T_A= 25°C, balun = Murata LDB212G1020C-001

1 dB Dynamic Range¹

0.5 dB Dynamic Range¹

Pins OUT[A, B], (Channel A/Channel B)

−40°C < T_A< +85°C

Pins OUT[A, B], (Channel A/Channel B)

−40°C < T_A< +85°C

66/57

58/40

62/54

30/30

dB

Maximum Input Level

Minimum Input Level

Slope

1 dB Error, (Channel A/Channel B)

Channel A/Channel B

−2/−4

dBm

mV/dB

dBm

V

−57−51

49.5/52.1

−58.3/−57.1

2.42

Intercept

Channel A/Channel B

Output Voltage—High Power In Pins OUT[A, B] @ P_{INH[A, B]}= −10 dBm

Rev. 0 | Page 4 of 48

AD8364

Parameter

Conditions

Min

Typ

Max

Unit

Output Voltage—Low Power In

Temperature Sensitivity

Pins OUT[A, B] @ P_{INH[A, B]}= −40 dBm

Deviation from OUT[A, B] @ 25°C

0.90

V

−40°C < T_A< 85°C; P_{INH[A, B]}= −10 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −25 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −40 dBm

Deviation from OUTP to OUTN @ 25°C

−40°C < T_A< 85°C; P_{INH[A, B]}= −10 dBm, −25 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −25 dBm, −25 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −40 dBm, −25 dBm

5.5 dB peak-to-rms ratio (WCDMA one channel)

12 dB peak-to-rms ratio (WCDMA three channels)

18 dB peak-to-rms ratio (WCDMA four channels)

Baluns = Macom ETC1.6-4-2-3 (both channels)

P_INHB= −50 dBm, OUTB = OUTB_PINHB1 dB

P_INHA= −50 dBm, OUTA = OUTA_PINHA1 dB

INHA/INLA, INHB/INLB differential drive

With recommended balun

+0.1, −0.4

dB

+0.1, −0.4

+0.2, −0.2

+0.1, −0.2

0.2

0.3

58

33

150||1.9

−10

dB

Ω||pF

dB

Deviation from CW Response

Input A to Input B Isolation

Input A to OUTB Isolation

Input B to OUTA Isolation²

Input Impedance

Input Return Loss

MEASUREMENT MODE,

2.5 GHz OPERATION

ADJA = ADJB = 1.14 V, error referred to best fit line using

linear regression @ P_{INH[A, B]}= −40 dBm and −20 dBm,

T_A= 25°C, balun = Murata LDB182G4520C-110

1 dB Dynamic Range¹

0.5 dB Dynamic Range¹

Pins OUT[A, B], (Channel A/Channel B)

−40°C < T_A< +85°C

Pins OUT[A, B], (Channel A/Channel B)

−40°C < T_A< +85°C

69/63

58

55/50

25

dB

Maximum Input Level

Minimum Input Level

Slope

1 dB error, (Channel A/Channel B)

1 dB error

17/11

−52

50

−52.7

2.14

0.65

dBm

mV/dB

dBm

V

Intercept

Output Voltage—High Power In Pins OUT[A, B] @ P_{INH[A, B]}= −10 dBm

Output Voltage—Low Power In

Temperature Sensitivity

Pins OUT[A, B] @ P_{INH[A, B]}= −40 dBm

Deviation from OUT[A, B] @ 25°C

V

−40°C < T_A< 85°C; P_{INH[A, B]}= −10 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −25 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −40 dBm

Deviation from OUTP to OUTN @ 25°C

−40°C < T_A< 85°C; P_{INH[A, B]}= −10 dBm, −25 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −25 dBm, −25 dBm

−40°C < T_A< 85°C; P_{INH[A, B]}= −40 dBm, −25 dBm

Baluns = Macom ETC1.6-4-2-3 (both channels)

P_INHB= −50 dBm, OUTB = OUTB_PINHB1 dB

P_INHA= −50 dBm, OUTA = OUTA_PINHA1 dB

INHA/INLA, INHB/INLB differential drive

With recommended balun

0.5

dB

0.3

54

31

150||1.7

−11.5

dB

Input A to Input B Isolation

Input A to OUTB Isolation

Input B to OUTA Isolation²

Input Impedance

Ω||pF

dB

Input Return Loss

OUTPUT INTERFACE

Voltage Range Min

Pin OUTA and OUTB

R_L≥ 200 Ω to ground

0.09

V

Voltage Range Max

Source/Sink Current

R_L≥ 200 Ω to ground

OUTA and OUTB held at V_S/2, to 1% change

V_S− 0.15

70

V

mA

Rev. 0 | Page 5 of 48

AD8364

Parameter

Conditions

Min

Typ

Max

Unit

SETPOINT INPUT

Voltage Range

Pin VSTA and VSTB

Law conformance error ≤1 dB

0.5

3.75

V

Input Resistance

68

kΩ

Logarithmic Scale Factor

Logarithmic Intercept

CHANNEL DIFFERENCE OUTPUT

Voltage Range Min

Voltage Range Max

Source/Sink Current

DIFFERENCE LEVEL ADJUST

Voltage Range³

f = 450 MHz, −40°C ≤ T_A≤ +85°C

f = 450 MHz, −40°C ≤ T_A≤ +85°C, referred to 50 Ω

Pin OUTP and OUTN

R_L≥ 200 Ω to ground

OUTP and OUTN held at V_S/2, to 1% change

Pin VLVL

OUT[P, N] = FBK[A, B]

50

−55

mV/dB

dBm

0.1

V_S− 0.15

70

V

mA

0

5

V_S−

0.15

V

OUT[P,N] Voltage Range

OUT[P, N] = FBK[A, B]

Input Resistance

1

kΩ

TEMPERATURE COMPENSATION

Input Voltage Range

Input Resistance

Pin ADJA and ADJB

0

2.5

V

MΩ

>1

VOLTAGE REFERENCE

Output Voltage

Temperature Sensitivity

Current Limit Source/Sink

TEMPERATURE REFERENCE

Output Voltage

Temperature Coefficient

Current Source/Sink

POWER-DOWN INTERFACE

Logic Level to Enable

Logic Level to Disable

Input Current

Pin VREF

RF in = −55 dBm

−40°C ≤ T_A≤ +85°C

1% change

2.5

0.4

10/3

V

mV/°C

mA

Pin TEMP

T_A= 25°C, R_L≥ 10 kΩ

−40°C ≤ T_A≤ +85°C, R_L≥ 10 kΩ

T_A= 25°C to 1% change

Pin PWDN

Logic LO enables

Logic HI disables

Logic HI PWDN = 5 V

Logic LO PWDN = 0 V

PWDN LO to OUTA/OUTB at 100% final value,

C_LPA/B= Open, C_HPA/B= 10 nF, RF in = 0 dBm

PWDN HI to OUTA/OUTB at 10% final value,

C_LPA/B= Open, C_HPA/B= 10nF, RF in = 0 dBm

0.62

2

1.6/2

V

mV/°C

mA

1

V

µA

µs

3

95

<100

2

Enable Time

Disable Time

1.6

µs

POWER INTERFACE

Supply Voltage

Quiescent Current

Pin VPS[A, B], VPSR

4.5

5.5

90

V

RF in = −55 dBm, V_S= 5 V

−40°C ≤ T_A≤ +85°C

PWDN enabled, V_S= 5 V

−40°C ≤ T_A≤ +85°C

70

mA

µA

Supply Current

500

900

¹Best fit line, linear regression.

²See Figure 75 for a plot of isolation vs. frequency for a 1 dB error.

³VLVL + OUTA/2 should not exceed VPSA − 1.31 V. Likewise, VLVL + OUTB/2 should not exceed VPSB − 1.31 V.

Rev. 0 | Page 6 of 48

AD8364

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter

Supply Voltage VPSA, VPSB, VPSR

PWDN, VSTA, VSTB, ADJA, ADJB,

FBKA, FBKB

Input Power (Referred to 50 Ω)

Internal Power Dissipation

θ_JA

θ_JC

Stresses above those listed under Absolute Maximum Ratings

Rating

5.5 V

0 V, 5.5 V

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

23 dBm

600 mW

39.8°C/W^{1, 2}

3.9°C/W²

θ_JB

Ψ_JT

22.8°C/W²

0.4°C/W^{1, 2}

125°C

−40°C to +85°C

−65°C to +150°C

Maximum Junction Temperature

Operating Temperature Range

Storage Temperature Range

¹Still air.

²All values are modeled using a standard 4-layer JEDEC test board with the

pad soldered to the board and thermal vias in the board.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. 0 | Page 7 of 48

AD8364

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VPSA 25

INHA 26

INLA 27

PWDN 28

COMR 29

INLB 30

INHB 31

VPSB 32

16 VSTA

15 OUTA

14 FBKA

13 OUTP

12 OUTN

11 FBKB

10 OUTB

AD8364

TOP VIEW

PIN 1

INDICATOR

9

VSTB

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

Equiv. Circuit

Figure 52

1

CHPB

Connect to common via a capacitor to determine 3 dB point of Channel B input signal high-

pass filter.

Decoupling Terminals for INHA/INLA and INHB/INLB. Connect to common via a large

capacitance to complete input circuit.

2, 23

DECB, DECA

3, 22, 29

4, 5

COMB, COMA, COMR

ADJB, ADJA

Input System Common Connection. Connect via low impedance to system common.

Temperature Compensation for Channel B and Channel A. An external voltage is connected

to these pins to improve temperature drift. This voltage can be derived from VREF, that is,

connect a resistor from VREF to ADJ[A, B] and another resistor from ADJ[A, B] to ground. The

value of these resistors change as the frequency changes.

Figure 68

6

7

VREF

VLVL

General-Purpose Reference Voltage Output of 2.5 V.

Figure 54

Figure 58

Reference Level Input for OUTP and OUTN. (Usually connected to VREF through a voltage

divider or left open).

8, 17

CLPB, CLPA

Channel B and Channel A Connection for Loop Filter Integration (Averaging) Capacitor.

Connect a ground-referenced capacitor to this pin. A resistor can be connected in series with

this capacitor to improve loop stability and response time.

9

VSTB

The voltage applied to this pin sets the decibel value of the required RF input voltage to

Channel B that results in zero current flow in the loop integrating capacitor pin, CLPB.

Channel B Output of Error Amplifier. In measurement mode, normally connected directly to

VSTB.

Figure 56

Figure 57

10

OUTB

11

12

FBKB

OUTN

Feedback Through 1 kΩ to the Negative Terminal of the Integrated Op Amp Driving OUTN.

Channel Differencing Op Amp Output. In measurement mode, normally connected directly to

FBKB and follows the equation OUTN = OUTA − OUTB + VLVL.

Channel Differencing Op Amp Output. In measurement mode, normally connected directly to

FBKA and follows the equation OUTP = OUTA − OUTB + VLVL.

Figure 58

13

OUTP

14

15

FBKA

OUTA

Feedback Through 1kΩ to the Negative Terminal of the Integrated Op Amp Driving OUTP.

Channel A Output of Error Amplifier. In measurement mode, normally connected directly to

VSTA.

The voltage applied to this pin sets the decibel value of the required RF input voltage to

Channel A that results in zero current flow in the loop integrating capacitor pin, CLPA.

Figure 57

Figure 56

16

VSTA

18, 20

ACOM

Analog Common for Channels A and B. Connect via low impedance to common.

21, 25, 32

VPSR, VPSA, VPSB

Supply for the Input System of Channels A and B. Supply for the internal references. Connect

to +5 V power supply.

19

24

TEMP

CHPA

Temperature Sensor Output.

Figure 53

Connect to common via a capacitor to determine 3 dB point of Channel A input signal high-

pass filter.

26, 27

28

INHA, INLA

PWDN

Channel A High and Low RF Signal Input Terminal.

Figure 52

Figure 55

Figure 52

Disable/Enable Control Input. Apply logic high voltage to shut down the AD8364.

Channel B Low and High RF Signal Input Terminal.

30, 31

INLB, INHB

Exposed Paddle

Under

Package

The exposed paddle on the under side of the package should be soldered to a ground plane

with low thermal and electrical characteristics.

Rev. 0 | Page 8 of 48

AD8364

TYPICAL PERFORMANCE CHARACTERISTICS

V_P= 5 V; T_A= +25°C, –40°C, +85°C; CLPA/B = OPEN. Colors: +25°C black, –40°C blue, +85°C red.

5

4

3

2

1

0

2.5

5

4

3

2

1

0

2.5

2.0

1.5

1.0

0.5

0

2.0

1.5

A

OUTN

OUTP

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–0.5

–1.0

–1.5

–2.0

B

–2.5

20

–60

–50

–40

–30

–20

–10

0

10

20

–60

–50

–40

–30

–20

–10

0

10

INPUT AMPLITUDE (dBm)

Figure 3. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at

450 MHz, Typical Device, ADJ[A, B] = 0 V, Sine Wave, Differential Drive,

Balun = Macom ETK4-2T

Figure 6. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at

450 MHz, with B Input Held at −25 dBm and A Input Swept, Typical Device,

ADJ[A, B] = 0 V, Sine Wave, Differential Drive, Balun = Macom ETK4-2T

(Note that the OUTP and OUTN Error Curves Overlap)

5

4

3

2

1

0

2.5

5

2.5

2.0

4

2.0

1.5

3

2

1.0

0.5

1

0

–0.5

–1.0

–1.5

–2.0

–2.5

–0.5

–1.0

–1.5

–2.0

–2.5

–1

–2

–3

–4

–5

–60

–50

–40

–30

–20

–10

0

10

20

–60

–50

–40

–30

–20

–10

0

10

20

INPUT AMPLITUDE (dBm)

Figure 4. Distribution of OUT[A, B] Voltage and Error over Temperature After

Ambient Normalization vs. Input Amplitude for at Least 30 Devices from

Multiple Lots, Frequency = 450 MHz, ADJ[A, B] = 0 V, Sine Wave, Differential

Drive, Balun = Macom ETK4-2T

Figure 7. Distribution of [OUTP − OUTN] Voltage and Error over Temperature

After Ambient Normalization vs. Input Amplitude for at Least 30 Devices

from Multiple Lots, Frequency = 450 MHz, ADJ[A, B] = 0 V, Sine Wave,

Differential Drive, P_INCh. B = −25 dBm, Channel A Swept

0.20

0.15

0.10

0.05

0

4

+2DB

+1DB

2

+15DEG

0

+10DEG

–2

REF

–15DEG

–10DEG

–4

–6

–0.05

–0.10

–0.15

–0.20

–1DB

SERIES NAME INDICATES THE

POLARITY AND MAGNITUDE OF THE

DEVIATION APPLIED TO THE INHA

INPUT, RELATIVE TO THE INLA INPUT,

AS REFERENCED TO THE REF SIGNAL.

–8

–2DB

–5

–10

–40 –35 –30 –25 –20 –15 –10

0

5

10

–60

–50

–40

–30

–20

–10

0

10

20

RF INPUT AT INLA (dBm)

INPUT AMPLITUDE (dBm)

Figure 8. Log Conformance vs. Input Amplitude at various Amplitude and

Phase Balance points, 450 MHz, Typical Device, ADJ[A, B] = 0 V, Sine Wave,

Differential Drive

Figure 5. Distribution of [OUTA – OUTB] Voltage vs. Input Amplitude over

Temperature for at Least 30 Devices from Multiple Lots, Frequency = 450 MHz,

ADJ[A, B] = 0 V, Sine Wave, Differential Drive, Balun = Macom ETK4-2T

Rev. 0 | Page 9 of 48

AD8364

5

4

3

2

1

2.5

5

4

3

2

1

0

2.5

2.0

1.5

B

OUTN

OUTP

1.0

A

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–0.5

–1.0

–1.5

–2.0

–2.5

0

–60

–50

–40

–30

–20

–10

0

10

20

–60

–50

–40

–30

–20

–10

0

10

20

INPUT AMPLITUDE (dBm)

Figure 9. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at

880 MHz, Typical Device, ADJ[A, B] = 0.5 V, Sine Wave, Differential Drive,

Balun = Mini-Circuits JTX-4-10T

Figure 12. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at

880 MHz, with B Input Held at −25 dBm and A Input Swept, Typical Device,

ADJ[A, B] = 0.5 V, Sine Wave, Differential Drive, Balun = JTX-4-10T

(Note that the OUTP and OUTN Error Curves Overlap)

5

4

3

2

1

0

2.5

5

2.0

1.5

4

3

1.5

B

1.0

0.5

2

1

0

A

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–0.5

–1

–2

–3

–1.0

–1.5

–2.0

–2.5

–4

–5

–60

–50

–40

–30

–20

–10

0

10

20

–60

–50

–40

–30

–20

–10

0

10

20

INPUT AMPLITUDE (dBm)

Figure 10. Distribution of OUT[A, B] Voltage and Error over Temperature After

Ambient Normalization vs. Input Amplitude for at Least 15 Devices from

Multiple Lots, Frequency = 880 MHz, ADJ[A, B] = 0.5 V, Sine Wave, Differential

Drive, Balun =JTX-4-10T

Figure 13. Distribution of [OUTP − OUTN] Voltage and Error over

Temperature After Ambient Normalization vs. Input Amplitude for at Least

15 Devices from Multiple Lots, Frequency = 880 MHz, ADJ[A, B] =0.5 V, Sine

Wave, Differential Drive, P_INCh. B = −25 dBm, Channel A Swept

0.20

0.15

0.10

0.05

0

4

+20DEG

+30DEG

2

0

–2

-15DEG

REF

+1dB

+10DEG

–4

–6

–8

–10

+2dB

–0.05

–0.10

–0.15

–0.20

–12

–14

SERIES NAME INDICATES THE POLARITY

-2dB

–16

–18

–20

AND MAGNITUDE OF THE DEVIATION

APPLIED TO THE INHA INPUT, RELATIVE

TO THE INLA INPUT, AS REFERENCED TO

THE REF SIGNAL.

-1dB

-10DEG

–60

–50

–40

–30

–20

–10

0

10

20

–40 –35 –30 –25 –20 –15 –10

–5

0

5

10

INPUT AMPLITUDE (dBm)

RF INPUT AT INLA (dBm)

Figure 14. Log Conformance vs. Input Amplitude at Various Amplitude and

Phase Balance points, 880 MHz, Typical Device, ADJ[A, B] = 0.5 V, Sine Wave,

Differential Drive

Figure 11. Distribution of [OUTA – OUTB] Voltage vs. Input Amplitude over

Temperature for at Least 15 Devices from Multiple Lots, Frequency =

880 MHz, ADJ[A, B] = 0.5 V, Sine Wave, Differential Drive, Balun =JTX-4-10T

Rev. 0 | Page 10 of 48

AD8364

5

4

3

2

1

0

2.5

5

4

3

2

1

0

2.5

2.0

1.5

1.0

0.5

0

2.0

1.5

OUTN

OUTP

A

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–0.5

–1.0

–1.5

–2.0

B

–2.5

20

–60

–50

–40

–30

–20

–10

0

10

20

–60

–50

–40

–30

–20

–10

0

10

INPUT AMPLITUDE (dBm)

Figure 15. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at

1.88 GHz, Typical Device, TADJ[A, B]= 0.65 V, Sine Wave, Differential Drive,

Balun = Murata LDB181G8820C-110

Figure 18. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at

1.88 GHz, with B Input Held at −25 dBm and A Input Swept, Typical Device,

ADJ[A, B] = 0.65 V, Sine Wave, Differential Drive, Balun = Murata

LDB181G8820C-110 (Note that the OUTP and OUTN Error Curves Overlap)

2.5

5

4

2.5

5

2.0

1.5

4

3

2

1

3

2

1.0

0.5

1

0

–0.5

–1.0

–1.5

–2.0

–2.5

–1

–2

–3

–1.0

–1.5

–2.0

–2.5

–4

–5

0

–60

–50

–40

–30

–20

–10

0

10

20

–50

–40

–30

–20

–10

0

10

20

INPUT AMPLITUDE (dBm)

Figure 16. Distribution of OUT[A, B] Voltage and Error over Temperature After

Ambient Normalization vs. Input Amplitude for at Least 20 Devices from

Multiple Lots, Frequency = 1.88 GHz, ADJ[A, B] = 0.65 V, Sine Wave,

Differential Drive, Balun = Murata LDB181G8820C-110

Figure 19. Distribution of [OUTP − OUTN] Voltage and Error over

Temperature After Ambient Normalization vs. Input Amplitude for at Least

20 Devices from Multiple Lots, Frequency = 1.88 GHz, ADJ[A, B] =0.65 V,

Sine Wave, Differential Drive, P_INCh. B = −25 dBm, Channel A Swept

0.20

0.15

0.10

0.05

0

2

–2dB

+20DEG

0

–2

REF

+30deg

+2dB

–1dB

–4

+10deg

–10deg

–6

–8

–30deg

–20deg

–10

–12

–14

–16

–18

–0.05

–0.10

–0.15

–0.20

+1dB

SERIES NAME INDICATES THE POLARITY

AND MAGNITUDE OF THE DEVIATION

APPLIED TO THE INHA INPUT, RELATIVE

TO THE INLA INPUT, AS REFERENCED TO

THE REF SIGNAL.

–60

–50

–40

–30

–20

–10

0

10

20

–40 –35 –30 –25 –20 –15 –10

–5

0

5

10

INPUT AMPLITUDE (dBm)

RF INPUT AT INLA (dBm)

Figure 17. Distribution of [OUTA – OUTB] Voltage vs. Input Amplitude over

Temperature for at Least 20 Devices from Multiple Lots, Frequency =

1.88 GHz, ADJ[A, B] = 0.65 V, Sine Wave, Differential Drive, Balun = Murata

LDB181G8820C-110

Figure 20. Log Conformance vs. Input Amplitude at Various Amplitude and

Phase Balance Points, 1.880 GHz, Typical Device, ADJ[A, B] = 0.65 V,

Sine Wave, Differential Drive

Rev. 0 | Page 11 of 48

AD8364

5

4

3

2

1

2.5

5

4

3

2

1

0

2.5

2.0

1.5

B

OUTN

OUTP

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–0.5

–1.0

–1.5

–2.0

–2.5

A

0

–60

–50

–40

–30

–20

–10

0

10

20

–60

–50

–40

–30

–20

–10

0

10

20

INPUT AMPLITUDE (dBm)

Figure 21. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at

2.14 GHz, Typical Device, ADJ[A, B] = 0.85 V, Sine Wave, Differential Drive,

Balun = Murata LDB212G1020C-001

Figure 24. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at

2.14 GHz, with B Input Held at −25 dBm and A Input Swept, Typical Device,

ADJ[A, B] = 0.85 V, Sine Wave, Differential Drive, Balun = Murata

LDB212G1020C-001 (Note that the OUTP and OUTN Error Curves Overlap)

5

4

3

2

1

0

2.5

5

4

2.5

2.0

1.5

3

2

B

1.0

0.5

1

0

–0.5

–1.0

–1.5

–2.0

–2.5

–0.5

–1.0

–1.5

–2.0

–2.5

–1

–2

–3

A

–4

–5

–60

–50

–40

–30

–20

–10

0

10

20

–60

–50

–40

–30

–20

–10

0

10

20

INPUT AMPLITUDE (dBm)

Figure 22. Distribution of OUT[A, B] Voltage and Error over Temperature After

Ambient Normalization vs. Input Amplitude for at Least 3 Devices from

Multiple Lots, Frequency = 2.14 GHz, ADJ[A, B] = 0.85 V, Sine Wave,

Differential Drive, Balun = Murata LDB212G1020C-001

Figure 25. Distribution of [OUTP − OUTN] Voltage and Error over

Temperature After Ambient Normalization vs. Input Amplitude for at Least

3 Devices from Multiple Lots, Frequency = 2.14 GHz, ADJ[A, B] = 0.85 V,

Sine Wave, Differential Drive, P_INCh. B = −25 dBm, Channel A Swept

0.20

0.15

0.10

0.05

0

4

+30DEG

–2dB

2

0

–2

+2dB

–1dB

–4

REF

+1dB

–6

–8

–10DEG

–10

–12

–14

–16

–18

–20

–22

–24

+20DEG

+10DEG

SERIES NAME INDICATES THE POLARITY

AND MAGNITUDE OF THE DEVIATION

APPLIED TO THE INHA INPUT, RELATIVE

TO THE INLA INPUT, AS REFERENCED TO

THE REF SIGNAL.

–0.05

–0.10

–0.15

–0.20

–20DEG

–30DEG

–40 –35 –30 –25 –20 –15 –10

–5

0

5

10

–60

–50

–40

–30

–20

–10

0

10

20

RF INPUT AT INLA (dBm)

INPUT AMPLITUDE (dBm)

Figure 26. Log Conformance vs. Input Amplitude at Various Amplitude and

Phase Balance Points, 2.140 GHz, Typical Device, ADJ[A, B] = 0.85 V, Sine

Wave, Differential Drive

Figure 23. Distribution of [OUTA – OUTB] Voltage vs. Input Amplitude over

Temperature for 3 Devices from Multiple Lots, Frequency = 2.14 GHz,

ADJ[A, B] = 0.85 V, Sine Wave, Differential Drive, Balun = Murata

LDB212G1020C-001

Rev. 0 | Page 12 of 48

AD8364

5

4

3

2

1

0

2.5

2.0

1.5

1.0

0.5

0

5

4

3

2

1

0

2.5

2.0

OUTP

1.5

OUTN

1.0

0.5

A

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

–2.5

B

–2.5

20

–60

–50

–40

–30

–20

–10

0

10

–60

–50

–40

–30

–20

–10

0

10

20

INPUT AMPLITUDE (dBm)

Figure 30. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at

2.5 GHz, with B Input Held at −25 dBm and A Input Swept, Typical Device,

ADJ[A, B] = 1.1 V, Sine Wave, Differential Drive, Balun = Murata

Figure 27. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at

2.5 GHz, Typical Device, ADJ[A, B] = 1.1 V, Sine Wave, Differential Drive, Balun

= Murata LDB182G4520C-110

LDB182G4520C-110 (Note that the OUTP and OUTN Error Curves Overlap)

5

4

2.5

5

4

3

2

1

0

2.5

2.0

1.5

3

2

1.0

0.5

1

0

–0.5

–1.0

–1.5

–2.0

–2.5

–0.5

–1.0

–1.5

–2.0

–2.5

–1

–2

–3

–4

–5

–60

–50

–40

–30

–20

–10

0

10

20

–60

–50

–40

–30

–20

–10

0

10

20

INPUT AMPLITUDE (dBm)

Figure 31. Distribution of [OUTP − OUTN] Voltage and Error over

Temperature After Ambient Normalization vs. Input Amplitude for at Least

15 Devices from Multiple Lots, Frequency = 2.5 GHz, ADJ[A, B] =1.1 V, Sine

Wave, Differential Drive, P_INCh. B = −25 dBm, Channel A Swept

Figure 28. Distribution of OUT[A, B] Voltage and Error over Temperature After

Ambient Normalization vs. Input Amplitude for at Least 15 Devices from

Multiple Lots, Frequency = 2.5 GHz, ADJ[A, B] = 1.1 V, Sine Wave, Differential

Drive, Balun = Murata LDB182G4520C-110

0.20

0.15

0.10

0.05

0

4

–2dB

2

–1dB

0

–2

–4

REF

+20DEG

–6

–8

+30DEG

–10DEG

+1dB

–10

–12

–14

–16

–18

–20

–22

–24

+10DEG

+2dB

–0.05

–0.10

–0.15

–0.20

–20DEG

–30DEG

SERIES NAME INDICATES THE POLARITY AND

MAGNITUDE OF THE DEVIATION APPLIED TO

THE INHA INPUT, RELATIVE TO THE INLA INPUT,

AS REFERENCED TO THE REF SIGNAL.

–60

–50

–40

–30

–20

–10

0

10

20

–40 –35 –30 –25 –20 –15 –10

–5

0

5

10

INPUT AMPLITUDE (dBm)

RF INPUT AT INLA (dBm)

Figure 32. Log Conformance vs. Input Amplitude at Various Amplitude and

Phase Balance Points, 2.500 GHz, Typical Device, ADJ[A, B] = 1.1 V, Sine Wave,

Differential Drive

Figure 29. Distribution of [OUTA – OUTB] Voltage vs. Input Amplitude over

Temperature for at Least 15 Devices from Multiple Lots, Frequency = 2.5 GHz,

ADJ[A, B] = 1.1 V, Sine Wave, Differential Drive, Balun = Murata

LDB182G4520C-110

Rev. 0 | Page 13 of 48

AD8364

2.0

1.5

ERROR CW

ERROR QPSK 4dB CF

1.0

0.5

1.0

ERROR 256 QAM 8dB CF

0.5

0

ERROR CW

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

ERROR 16C CDMA2K

9CH SR1 14dB CF

ERROR 3 CARRIER

CDMA2K SR1

ERROR 4 CARRIER

WCDMA TM 1-64

ERROR 1C TM1-32 DPCH

13dB CF

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5

0

5

10 15 20

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5

0

5

10 15 20

P

MEAS (dBm)

P

IN

MEAS (dBm)

IN

Figure 33. Output Error from CW Linear Reference vs. Input Amplitude with

Different Waveforms, CW, QPSK, 256QAM, WCDMA 1-Carrier Test Model 1

with 32 DPCH, CDMA2000, 16-Carrier, 9-Channel SR1 Frequency 2.140 GHz,

CLP[A, B] = 1 µF, Balun = Murata LDB212G1020C-001

Figure 35. Output Voltage and Error from CW Linear Reference vs. Input

Amplitude with Different Waveforms, CW, 3-Carrier CDMA2000 SR1,

4-Carrier WCDMA, Test Model 1 with 64 DPCH, Frequency 2.140 GHz,

Balun = Murata LDB212G1020C-001

2

2.0

ERROR FWD 1 CARRIER

CDMA2K PILOTSR1

1.5

1.0

ERROR 2

CARRIER TM1-64

1.0

ERROR CW

ERROR 4

CARRIER TM1-64

ERROR FWD 4

CARRIER CDMA2K

CDMA2K 9CH SR1

9CH SR1

0.5

ERROR CW

ERROR FWD 1 CARRIER

0.5

0

–0.5

ERROR 3

CARRIER TM1-64

ERROR FWD 16

CARRIER CDMA2K

–1.0

–1.5

–1.0

ERROR FWD 4

CARRIER CDMA2K

9CH SR1

ERROR 1

CARRIER TM1-64

–1.5

–2.0

ERROR FWD 3

CARRIER CDMA2K

9CH SR1

–2.0

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5

0

5

10 15 20

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5

0

5

10 15 20

P

MEAS (dBm)

P

MEAS (dBm)

IN

Figure 34. Error from CW Linear Reference vs. Input Amplitude with Different

Waveforms, CW, WCDMA1, 2-, 3-, and 4-Carrier, Test Model 1 with 64 DPCH,

Frequency 2.14 GHz, Balun = Murata LDB212G1020C-001

Figure 36. Error from CW Linear Reference vs. Input Amplitude with Different

Waveforms, CW, 1-Carrier CDMA2000 Pilot CH SR1, 1-Carrier CDMA2000

9CH SR1, 3-Carrier CDMA2000 9CH SR1, 4-Carrier CDMA2000 9CH SR1

Frequency 16-Carrier CDMA2000 9CH SR1, Frequency 2.140 GHz, Balun =

Murata LDB212G1020C-001

Rev. 0 | Page 14 of 48

AD8364

90

60

120

20

15

150

30

10

180

0

5

0

–5

210

330

–10

–15

–20

240

300

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

TEMPERATURE (°C)

270

Figure 37. Differential Input Impedance (S11) vs. Frequency; Z_O= 50 Ω

Figure 40. Change in VREF vs. Temperature for 11 Devices

14

TOTAL = 40 DEVICES

10000

1000

100

RF INPUT = –60dBm

450MHz, 0dB

450MHz, –40dB

450MHz, –20dB

12

10

8

2140MHz, –20dB

2140MHz, –40dB

2140MHz, 0dB

6

4

2

450MHz, RF OFF

10k

0

2.486 2.488 2.490 2.492 2.494 2.496 2.498 2.500 2.502 2.504 2.506

450MHz

10

100

V

(V)

REF

1k

100k

1M

10M

FREQUENCY (Hz)

Figure 38. Distribution of VREF for 40 Devices

Figure 41. Noise Spectral Density of OUT[A, B]; CLP[A, B] = Open

14

12

10

8

TOTAL = 40 DEVICES

RF INPUT = –60dBm

10000

0dB

1000

100

10

–20dB

–40dB

6

4

2

RF OFF

1M

0

0.617

0.619

0.621

V

0.623

(V)

0.625

0.627

REF

100

1k

10k

100k

10M

FREQUENCY (Hz)

Figure 39. Distribution of TEMP Voltage for 40 Devices

Figure 42. Noise Spectral Density of OUT[P, N]; CLP[A, B] = 0.1 µF,

Frequency = 2140 MHz

Rev. 0 | Page 15 of 48

AD8364

10000

PWDN

2

0dB

OUTA

1000

100

CARRIER FREQUENCY 450MHz,

CLPA = OPEN

–20dB

0dBm

V

= 5V

= 0V

DD

–40dB

A

B

–20dBm

–40dBm

B2

RF OFF

10k

FREQUENCY (Hz)

CH2 5.0V

CH4 1.0V

M4.0µs 625MS/s

A CH2 2.1V

1.6ns/pt

10

100

1k

100k

1M

10M

REF2 1.0V 4.0µs

Figure 46. Output Response Using Power-Down Mode for Various RF Input

Levels, Carrier Frequency 450 MHz, CLPA = Open

Figure 43. Noise Spectral Density of OUT[A, B]; CLP[A, B] = 0.1 µF,

Frequency = 2140 MHz

PWDN

RF BURST ENABLE

2

OUTA

CARRIER FREQUENCY 450MHz,

CLPA = OPEN

CLPA = 0.1µF

0dBm

V

= 5V

= 0V

DD

V

= 5V

= 0V

DD

–20dBm

–40dBm

–20dBm

A

B

A

B

–40dBm

B2

CH2 5.0V

CH4 1.0V

M2.0ms 1.25MS/s

800ns/pt

CH2 5.0V

CH4 1.0V

M2.0µs 1.25GS/s

A CH2 2.1V

800ps/pt

A CH2

1.7V

REF2 1.0V 2.0µs

Figure 47. Output Response Using Power-Down Mode for Various RF Input

Levels, Carrier Frequency 450 MHz, CLPA = 0.1 µF, CHPA = 10 nF

Figure 44. Output Response to RF Burst Input for Various RF Input Levels,

Carrier Frequency 450 MHz, CLPA = Open

RF BURST ENABLE

2

OUTA

CARRIER FREQUENCY 450MHz,

CLPA = 0.1µF

0dBm

V

= 5V

= 0V

DD

–20dBm

–40dBm

A

B

B2

CH2 5.0V

CH4 1.0V

M2.0µs 1.25MS/s

800ns/pt

A CH2

2.1V

REF2 1.0V 2.0ms

Figure 45. Output Response to RF Burst Input for Various RF Input Levels,

Carrier Frequency 450 MHz, CLPA = 0.1 µF

Rev. 0 | Page 16 of 48

AD8364

80

70

60

50

40

30

20

10

0

2.0

1.5

1.0

0.5

V

PWDN

INCREASING

V

0

PWDN

DECREASING

–0.5

–1.0

–1.5

–2.0

1.0

1.2

1.4

1.6

1.8

(V)

2.0

2.2

2.4

–60

–50

–40

–30

–20

–10

0

10

20

V

PWDN

RF INPUT (dBm)

Figure 48. Output Voltage Stability vs. VP (Supply Voltage) at 2.14 GHz,

When VP Varies by 10%,ADJ[A, B] =0.85 V, Sine Wave, Differential Drive,

Murata LDB212G1020C-001

Figure 49. Supply Current vs. V_PWDN

Rev. 0 | Page 17 of 48

AD8364

GENERAL DESCRIPTION AND THEORY

The AD8364 is a dual-channel, 2.7 GHz, true rms responding

detector with 60 dB measurement range. It incorporates two

AD8362 channels with shared reference circuitry (See the

AD8362 datasheet for more information). Multiple enhancements

have been made to the AD8362 cores to improve measurement

accuracy. Log-conformance peak-to-peak ripple has been reduced

to < 0.2 dB over the entire dynamic range. Temperature stability

of the rms output measurements provides < 0.5 dB error over

the specified temperature range of −40°C to 85°C through

proprietary techniques. The use of well-matched channels offers

extremely temperature-stable difference outputs, OUTP and

OUTN. Given well-matched channels through IC integration,

the rms measurement outputs, OUTA and OUTB, drift in the

same manner. With OUTP shorted to FBKA, the function at

OUTP is

24

23

22

21

20

19

18

17

TEMP

VGA

CONTROL

25

26

27

28

29

30

16

15

14

13

12

11

VPSA

INHA

VSTA

OUTA

FBKA

OUTP

OUTN

FBKB

2

I

SIG

CHANNEL A

TruPwr™

2

I

TGT

INLA

PWDN

COMR

INLB

OUTA

OUTB

2

I

SIG

CHANNEL B

TruPwr™

31

32

10

9

INHB

OUTB

VSTB

2

I

TGT

VPSB

VGA

CONTROL

BIAS

1

2

3

4

5

6

7

8

OUTP = OUTA – OUTB + VLVL

(1)

When OUTN is shorted to FBKB, the function at OUTN is

Figure 50. Block Diagram

OUTN = OUTB – OUTA + VLVL

(2)

OUTP and OUTN are insensitive to the common drift due to

the difference cancellation of OUTA and OUTB.

V

IN

INH[A, B]

INL[A, B]

VGA

x²

TEMPERATURE

COMPENSATION

V

ADJ[A, B]

OUT[A, B]

SIG

GSET

SETPOINT

The AD8364 is a fully calibrated rms-to-dc converter capable of

operating on signals of a few hertz to 2.7 GHz or more. Unlike

logarithmic amplifiers, the AD8364 response is waveform

independent. The device accurately measures waveforms that

have a high peak-to-rms ratio (crest factor). Figure 50 shows a

block diagram.

OFFSET

NULLING

V

× 0.03

REF

CHP[A, B]

VST[A, B]

OUTPUT

BUFFER

V

ST[A, B]

INTERFACE

C

F

CLP [A, B]

REF

C

LPF

EXTERNAL

BAND GAP

REFERENCE

V

REF

2.5V

A single channel of the AD8364 consists of a high performance

AGC loop. As shown in Figure 51, the AGC loop comprises

a wide bandwidth variable gain amplifier (VGA), square law

detectors, an amplitude target circuit, and an output driver. For

a more detailed description of the functional blocks, see the

AD8362 data sheet.

ACOM

Figure 51. Single-Channel Details

Rev. 0 | Page 18 of 48

AD8364

RF INPUT INTERFACE

SQUARE LAW DETECTOR AND AMPLITUDE TARGET

The AD8364’s RF inputs are connected as shown in Figure 52.

There are 100 Ω resistors connected between DEC[A, B] and

INH[A, B] and also between DEC[A, B] and INL[A, B]. The

DEC[A, B] pins have a dc level established as (7 × VPS[A, B] +

55 × V_BE)/30. With a 5 V supply, DEC[A, B] is approximately

2.5 V.

The output of the VGA, called V_SIG, is applied to a wideband

square law detector. The detector provides the true rms

response of the RF input signal, independent of waveform, up

to a crest factor of 6. The detector output, called I_SQU, is a

fluctuating current with positive mean value. The difference

between I_SQUand an internally generated current, I_{TGT[A, B]}, is

integrated by C_Fand a capacitor attached to CLP[A, B]. CF is

the on-chip 25 pF filter capacitor. CLP[A, B] can be used to

arbitrarily increase the averaging time while trading off

response time. When the AGC loop is at equilibrium,

Signal-coupling capacitors must be connected from the input

signal to the INH[A, B] and INL[A, B] pins. The high-pass

corner is

f

_high-pass= 1/(2 × π × 100 × C)

(8)

MEAN(I_SQU) = I_{TGT[A, B]}

(3)

A decoupling capacitor should be connected from DEC[A, B] to

ground to attenuate any signal at the midpoint. A 100 pF and

0.1 µF cap from DEC[A, B] to ground are recommended, with a

1 nF coupling capacitor such that signals greater than 1.6 MHz

can be measured. For coupling signals less than 1.6 MHz,

100 × C_couplingfor the DEC[A, B] capacitor generally can be used.

This equilibrium occurs only when

2

MEAN(V_SIG²) = V_{TGT[A, B]}

(4)

where V_TGTis an attenuated version of the VREF voltage.

Because the square law detectors are electrically identical and

well matched, process and temperature dependant variations

are effectively cancelled.

DEC[A, B]

VSP[A, B]

COM[A, B]

INH[A, B]

By forcing the above identity through varying the VGA

setpoint, it is apparent that

100Ω

V

VGA

IN

RMS(V_SIG) = √(MEAN(V_SIG²)) = √(V_TGT²) = V_TGT

Substituting the value of V_SIG, we have

(5)

(6)

INL[A, B]

VSP[A, B]

RMS(G0 × RF_INexp(−VST[A, B]/V_GNS)) = V_TGT

When connected as a measurement device VST[A, B] =

OUT[A, B]. Solving for OUT[A, B] as a function of RF_IN,

COM[A, B] COM[A, B]

Figure 52. AD8364 RF Inputs

OUT[A, B] = V_SLOPE× Log10(RMS(RF_IN)/V_Z)

(7)

OFFSET COMPENSATION

where V_SLOPEis laser trimmed to 1 V/decade (or 50 mV/dB) at

100 MHz. V_Zis the intercept voltage, since Log 10(1) = 0 when

RMS(RF_IN) = V_Z. If desired, the effective value of V_SLOPEmay be

altered by using a resistor divider from OUT[A, B] to drive

VST[A, B]. The intercept, V_Z, is also laser trimmed to 180 µV

(−62 dBm, referred to 50 Ω) with a CW signal at 100 MHz. This

value is extrapolated, because OUT[A, B] do not respond to input

of less than approximately −55 dBm with differential drive.

An offset-nulling loop is used to address small dc offsets in the

VGA. The high-pass corner frequency of this loop is internally

preset to about 1 MHz using an on-chip capacitor of 25 pF

(1/(2 × 5K × 25 pF)), which is sufficiently low for most HF

applications. The high-pass corner can be reduced by a

capacitor from CHP[A, B] to ground. The input offset voltage

varies depending on the actual gain at which the VGA is

operating and, thus, on the input signal amplitude. When an

excessively large value of CHP[A, B] is used, the offset

correction process may lag the more rapid changes in the VGA’s

gain, which may increase the time required for the loop to fully

settle for a given steady input amplitude.

In most applications, the AGC loop is closed through the

setpoint interface, VST[A, B]. In measurement mode, OUT[A, B]

are tied to VST[A, B], respectively. In controller mode, a control

voltage is applied to VST[A, B]. Pins OUT[A, B] drive the control

input of a system. The RF feedback signal to the input pins is

forced to have an rms value determined by VSTA or VSTB.

Rev. 0 | Page 19 of 48

AD8364

TEMPERATURE SENSOR INTERFACE

POWER-DOWN INTERFACE

The AD8364 provides a temperature sensor output capable of

driving about 1.6 mA. A 330 Ω-equivalent internal resistance is

connected from TEMP to COMR to provide current sink

capability. The temperature scaling factor of the output voltage is

approximately 2 mV/°C. The typical absolute voltage at 25°C is

about 620 mV.

The operating and stand-by currents for the AD8364 at 25°C are

approximately 70 mA and 500 µA, respectively. The PWDN pin

is connected to an internal resistor divider made with two 42 kΩ

resistors. The divider voltage is applied to the base of an NPN

transistor to force a power-down condition when the device is

active. Typically when PWDN is pulled greater than 2 V, the

device is powered down. Figure 46 and Figure 47 show typical

response times for various RF input levels. The output reaches

to within 0.1 dB of its steady-state value in about 1.6 µs; the

reference voltage is available to full accuracy in a much shorter

time. This wake-up response vary depending on the input

coupling means and the capacitances CDEC[A, B], CHP[A, B],

and CLP[A, B].

VPSR

INTERNAL

VPTAT

TEMP

4kΩ

350Ω

1kΩ

PWDN

POWER DOWN

SIGNAL

COMR

Figure 53. TEMP Interface Simplified Schematic

VREF INTERFACE

42kΩ

COMR

An internal voltage reference is provided to the user at Pin VREF.

The VREF voltage is a temperature stable 2.5 V reference that

can drive about 18 mA. An 830 Ω equivalent internal resistance

is connected from VREF to ACOM for 3 mA sink capability.

Figure 55. PWDN Interface Simplified Schematic

VST[A, B] INTERFACE

The VST[A, B] interface has a high input impedance of 72 kΩ.

The voltage at VST[A, B] is converted to an internal current

used to steer the VGA gain. The VGA attenuation control is

set to 20 dB/V.

VPSR

INTERNAL

VOLTAGE

V

REF

9kΩ

GAIN ADJUST

900Ω

1.35µA/dB

1.465kΩ

36kΩ

VST[A, B]

COMR

36kΩ

Figure 54. VREF Interface Simplified Schematic

18.5kΩ

ACOM

Figure 56. VST[A, B] Interface Simplified Schematic

Rev. 0 | Page 20 of 48

AD8364

VLVL VPSR

OUT[A, B, P, N] OUTPUTS

1kΩ

The output drivers used in the AD8364 are different than the

output stage on the AD8362. The AD8364 incorporates rail-to-

rail output drivers with pull-up and pull-down capabilities.

The output noise is approximately 40 nV/√Hz at 100 kHz.

OUT[A, B, P, N] can source and sink up to 70 mA. There is also an

internal load from both OUTA and OUTB to ACOM of 2.5 kΩ.

1kΩ

OUTA

OUTB

OUTP

1kΩ

FBKA COMR

VLVL VPSR

1kΩ

OUTB

OUTA

VPS[A, B]

OUTN

INTERNAL

VOLTAGE

1kΩ

OUT[A, B]

FBKB COMR

2kΩ

Figure 58. OUT[P, N] Interface Simplified Schematic

500Ω

COM[A, B]

ACOM

Figure 57. OUT[A, B] Interface Simplified Schematic

Rev. 0 | Page 21 of 48

AD8364

MEASUREMENT CHANNEL DIFFERENCE OUTPUT

USING OUT[P, N]

CONTROLLER MODE

The channel difference outputs can be used for controlling a

feedback loop to the AD8364’s RF inputs. A capacitor connected

between FBKA and OUTP forms an integrator, keeping in mind

that the on-chip 1 kΩ feedback resistor forms a zero. (The value

of the on-chip resistors can vary as much as 20% with manufac-

turing process variation.) If Channel A is driven and Channel B

has a feedback loop from OUTP through a PA, then OUTP

integrates to a voltage value such that

The AD8364 incorporates two operational amplifiers with rail-

to-rail output capability to provide a channel difference output.

As in the case of the output drivers for OUT[A, B], the output

stages have the capability of driving 70 mA. The output noise is

approximately 40 nV/√Hz at 100 kHz. OUTA and OUTB are

internally connected through 1 kΩ resistors to the inputs of each

op amp. The pin VLVL is connected to the positive terminal of

both op amps through 1 kΩ resistors to provide level shifting. The

negative feedback terminal is also made available through a 1 kΩ

resistor. The input impedance of VLVL is 1 kΩ and FBK[A, B]

is 2 kΩ. See Figure 59 for the connections of these pins.

OUTB = (OUTA + VLVL)/2

(11)

The output value from OUTN may or may not be useful. It is

given by

OUTN = 0 V

(12)

24

23

22

21

20

19

18

17

For VLVL < OUTA/3,

Otherwise,

TEMP

VGA

CONTROL

25

26

27

28

29

30

16

15

14

13

12

11

VPSA

INHA

VSTA

OUTA

FBKA

OUTP

OUTN

FBKB

2

I

SIG

OUTN = (3 × VLVL – OUTA)/2

(13)

CHANNEL A

TruPwr™

2

I

TGT

INLA

If VLVL is connected to OUTA, then OUTB is forced to equal

OUTA through the feedback loop. This flexibility provides the

user with the capability to measure one channel operating at a

given power level and frequency while forcing the other channel

to a desired power level at another frequency. ADJA and ADJB

should be set to different voltage levels to reduce the temperature

drift of the output measurement. The temperature drift will be

statistical sum of the drift from Channel A and Channel B. As

stated before, VLVL can be used to force the slaved channel to

operate at a different power than the other channel. If the two

channels are forced to operate at different power levels, then

some static offset occurs due to voltage drops across metal

wiring in the IC.

PWDN

COMR

INLB

OUTA

OUTB

2

I

SIG

CHANNEL B

TruPwr™

31

32

10

9

INHB

OUTB

VSTB

2

I

TGT

VPSB

VGA

CONTROL

BIAS

1

2

3

4

5

6

7

8

Figure 59. Op Amp Connections (All Resistors are 1 kΩ 20%)

If OUTP is connected to FBKA, then OUTP is given as

OUTP = OUTA – OUTB + VLVL

If an inversion is necessary in the feedback loop, OUTN can be

used as the integrator by placing a capacitor between OUTN

and OUTP. This changes the output equation for OUTB and

OUTP to

(9)

If OUTN is connected to FBKB, then OUTN is given as

OUTN = OUTB – OUTA + VLVL

(10)

OUTB = 2 × OUTA − VLVL

For VLVL < OUTA/2,

OUTN = 0 V

(14)

(15)

(16)

In this configuration, all four measurements, OUT[A, B, P, N],

are made available simultaneously. A differential output can be

taken from OUTP − OUTN, and VLVL can be used to adjust

the common-mode level for an ADC connection.

Otherwise,

OUTN = 2 × VLVL – OUTA

The previous equations are valid when Channel A is driven and

Channel B is slaved through a feedback loop. When Channel B

is driven and Channel A is slaved, the above equations can be

altered by changing OUTB to OUTA and OUTN to OUTP.

Rev. 0 | Page 22 of 48

AD8364

The device is placed in measurement mode by connecting OUTA

and/or OUTB to VSTA and/or VSTB, respectively. This closes the

AGC loop within the device with OUT[A, B] representing the

VGA control voltage, which is required to present the correct

rms voltage at the input of the internal square law detector.

RF MEASUREMENT MODE BASIC CONNECTIONS

The AD8364 requires a single supply of nominally 5 V. The

supply is connected to the three supply pins, VPSA, VPSB, and

VPSR. Each pin should be decoupled using the two capacitors

with values equal or similar to those shown in Figure 60. These

capacitors must provide a low impedance over the full

frequency range of the input, and they should be placed as close

as possible to the VPOS pins. Two different capacitors are used

in parallel to provide a broadband ac short to ground.

As the input signal to Channel A and Channel B are swept over

their nominal input dynamic range of +10 dBm to −50 dBm,

the output swings from 0 V to 3.5 V. The voltages OUTA and

OUTB are also internally applied to a difference amplifier with

a gain of two. So as the dB difference between INA and INB

ranges from approximately −30 dB to +30 dB, the difference

voltage on OUTP and OUTN swings from −3.5 V to +3.5 V.

Input differences larger than 30 dB can be measured as long as

the absolute input level at INA and INB are within their nominal

ranges of +10 dBm to −50 dBm. However, measurement of large

differences between INA and INB are affected by on-chip signal

leakage (see the Channel Isolation section). The common-mode

level of OUTP and OUTN is set by the voltage applied to VLVL.

These output can be easily biased up to a common-mode

voltage of 2.5 V by connecting VREF to VLVL. As the gain range

is swept, OUTP swings from approximately 1 V to 4.5 V and

OUTN swings from 4.5 V to 1 V.

The input signals are applied to the input differentially. The RF

inputs of the AD8364 have a differential input impedance of

200 Ω. When the AD8364 RF inputs are driven from a 50 Ω

source, a 4:1 balun transformer is recommended to provide the

necessary impedance transformation. The inputs can be driven

single-ended, however, this reduces the measurement range of

the rms detectors (see the Single-Ended Input Operation

section).

Table 4. Baluns Used to Characterize the AD8364

Frequency

Balun

450 MHz

MIA-COM ETK4-2T

880 MHz

Mini-Circuits JTX-4-10T

Murata LDB181G8820C-110

Murata LDB212G1020C-001

Murata LDB182G4520C-110

1880 MHz

2140 MHz

2500 MHz

Rev. 0 | Page 23 of 48

AD8364

VPOS

R24

0Ω

C23

100pF

C13

0.1µF

R5

0Ω

VPOS

C12

C8

100pF

0.1µF

C14

0.1µF

C11

0.1µF

C9

0.1µF

24

23

22

21

20

19

18

17

C10

100pF

CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA

25

26

16

15

VPSA

VSTA

C5

0.1µF

C7

0.1µF

T2

INPA

INHA

OUTA

1:4

27

28

29

30

14

13

12

11

INLA

FBKA

OUTP

OUTN

FBKB

C6

0.1µF

AD8364ACPZ

PWDN

COMR

INLB

OUTP

OUTN

C4

0.1µF

T1

1:4

31

32

10

9

INPB

INHB

OUTB

VSTB

OUTB

EXPOSED PADDLE

C3

0.1µF

C2

0.1µF

VPSB

CHPB DECB COMB ADJB ADJA VREF VLVL CLPB

1

2

3

4

5

6

7

8

C20

100pF

C22

0.1µF

C19

0.1µF

C16

0.1µF

1

R20 R18

C21

0.1µF

C1

0.1µF

C24

100pF

1

R19

R17

VPOS

1

SEE TEXT.

Figure 60. Basic Connections for Operation in Measurement Mode

recommended maximum input level for optimum linearity and

temperature stability at the frequency of operation.

CONTROLLER MODE BASIC CONNECTIONS

In addition to being a measurement device, the AD8364 can

also be configured to measure and control rms signal levels. The

AD8364 has two controller modes. Each of the two rms log

detectors can be separately configured to set and control the

output power level of a variable gain amplifier (VGA) or

variable voltage attenuator (VVA). Alternatively, the two rms

log detectors can be configured to measure and control the gain

of an amplifier or signal chain.

VSTA and OUTA are no longer shorted together. OUTA now

provides a bias or gain control voltage to the VGA. The gain

control sense of the VGA must be negative and monotonic, that

is, increasing voltage tends to decrease gain. However, the gain

control transfer function of the device does not need to be well

controlled or particularly linear. If the gain control sense of the

VGA is positive, an inverting op amp circuit with a dc offset

shift can be used between the AD8364 and the VGA to keep the

gain control voltage in the 0 V to 5 V range.

Automatic Power Control

Figure 61 shows how the device should be reconfigured to

control output power.

VSTA becomes the setpoint input to the system. This can be

driven by a DAC, as shown in Figure 61, if the output power is

expected to vary, or it can simply be driven by a stable reference

voltage if constant output power is required. This DAC should

have an output swing that covers the 0 V to 3.5 V range. The

AD7391 and AD7393 serial-input and parallel-input 10-bit

DACs provide adequate resolution (4 mV/bit) and an output

swing up to 4.5 V.

The RF input to the device is configured as before. A directional

coupler taps off some of the power being generated by the VGA

(typically a 10 dB to 20 dB coupler is used). A power splitter can

be used instead of a directional coupler if there are no concerns

about reflected energy from the next stage in the signal chain.

Some additional attenuation may be required to set the

maximum input signal at the AD8364 to be equal to the

Rev. 0 | Page 24 of 48

AD8364

When VSTA is set to a particular value, the AD8364 compares

this value to the equivalent input power present at the RF input.

If these two values do not match, OUTA increases or decreases

in an effort to balance the system. The dominant pole of the

error amplifier/integrator circuit that drives OUTA is set by the

capacitance on Pin CLPA; some experimentation may be

necessary to choose the right value for this capacitor. In general,

CLPA should be chosen to provide stable loop operation for the

complete output power control range. If the slope (in dB/V) of

the gain control transfer function of the VGA is not constant,

CLPA must be chosen to guarantee a stable loop when the gain

control slope is at its maximum. On the other hand, CLPA must

provide adequate averaging to the internal low range squaring

detector so that the rms computation is valid. Larger values of

CLPA tend to make the loop less responsive.

Automatic Gain Control

Figure 62 shows how the AD8364 can be connected to provide

automatic gain control to an amplifier or signal chain.

Additional pins are omitted for clarity. In this configuration,

both rms detectors are connected in measurement mode with

appropriate filtering being used on CLP[A, B] to effect a valid

rms computation on both channels. OUTA, however, is also

connected to the VLVL pin of the on-board difference amplifier.

Also, the OUTP output of the difference amplifier drives a

variable gain element (either VVA or VGA) and is connected

back to the FBKA input via a capacitor so that it is operating as

an integrator.

Assume that OUTA is much bigger than OUTB. Because OUTA

also drives VLVL, this voltage is also present on the noninverting

input of the op amp driving OUTP. This results in a net current

flow from OUTP through the integrating capacitor into the

FBKA input. This results in the voltage on OUTP increasing. If

the gain control transfer function of the VVA/VGA is positive,

this increases the gain, which in turn increases the input signal

to INHB. The output voltage on the integrator continues to

increase until the power on the two input channels is equal,

resulting in a signal chain gain of unity.

The relationship between VSTA and the RF input follows from

the measurement mode behavior of the device. For example,

from Figure 9, which shows the measurement mode transfer

function at 880 MHz, it can be seen that an input power of

−10 dBm yields an output voltage of 2.5 V. Therefore, in

controller mode, VSTA should be set to 2.5 V, which results in

an input power of −10 dBm to the AD8364.

If a gain other than 0 dB is required, an attenuator can be used

in one of the RF paths, as shown in Figure 62. Alternatively,

power splitters or directional couplers of different coupling

factors can be used. Another convenient option is to apply a

voltage on VLVL other than OUTA. Refer to Equation 11 and

the Controller Mode section for more detail.

VGA OR VVA

(OUTPUT POWER

P

OUT

IN

DECREASES AS

INCREASES)

V

APC

V

APC

ATTENUATOR

(0V TO 4.9V AVAILABLE SWING)

If the VGA/VVA has a negative gain control sense, the OUTN

output of the difference amplifier can be used with the

integrating capacitor tied back to FBKB.

C7

0.1µF

C5

0.1µF

OUTA

T2

INHA

1:4

AD8364

INLA

The choice of the integrating capacitor affects the response time

of the AGC loop. Small values give a faster response time but

can result in instability, whereas larger values reduce the response

time. Note that in this mode, the capacitors on CLPA and CLPB,

which perform the rms averaging function, must still be used

and also affect the loop response time.

C6

0.1µF

VSTA

INHA

SEE TEXT

DAC

0V TO 3.5V

Figure 61. Operation in Controller Mode for Automatic Power Control

Rev. 0 | Page 25 of 48

AD8364

DIRECTIONAL

OR

POWER SPLITTER

VGA/VVA

CLPF

I

ERR

VGA

C5

0.1µF

T1

1:4

C7

0.1µF

VSTA

CONTROL

2

I

OUTA

SIG

INHA

INLA

CHANNEL A

TruPwr™

1:4

C

INT

ATTENUATOR

2

I

FBKA

OUTP

TGT

C6

0.1µF

OUTA

OUTB

DIFF OUT +

AD8364

OUTN

T2

C4

1:4

0.1µF

FBKB

OUTB

INLB

INHB

2

I

CHANNEL B SIG

TruPwr™

1:4

2

I

TGT

C3

0.1µF

C2

0.1µF

VGA

CONTROL

VSTB

VLVL

CLPF

Figure 62. Operation in Controller Mode for Automatic Gain Control

Rev. 0 | Page 26 of 48

AD8364

fixed output power from the AD8367 even though its input

CONSTANT OUTPUT POWER OPERATION

power is changing. The input power can vary over a 36 dB

range, while the output power remains constant and the drift

over temperature is less than 0.2 dB

In controller mode, the AD8364 can be used to hold the output

power stable over a broad temperature/input power range. This

can be very useful in systems, such as a transmit module driving

a high power amplifier (HPA) in a basestation, that connect

multiple power sensitive modules together. In applications

where stable output power is needed, the RF output is

Figure 64 shows a constant output power circuit using the

AD8364 and the AD8367 VGA. The input power was swept

from +3 dBm to −35 dBm, the output power was measured at

multiple temperatures between −40°C and +85°C, and the

power changed less than 0.07 dB (Figure 63).

connected to Channel B using a coupler, VLVL is connected to

VREF, VSTB is used to set the power to a particular level and

can be controlled using a DAC or a dc voltage, OUTB is used to

drive the gain control of an amplifier that is capable of negative-

gain law conformance (such as the AD8367), and ADJB (set at

0 V in this example) is used to control the temperature drift.

Using this configuration, the RF input signal is down converted

to 80 MHz using the AD8343 and amplified using the AD8367.

The signal then splits and part of it is fed back to the AD8364

through Channel B, and a setpoint voltage is applied to VSTB.

This voltage corresponds to a particular power level, which is

determined by the slope of the AD8364. The power detected at

the input of the AD8364 is compared with this voltage, and the

voltage present at OUTB is adjusted up or down to match the

setpoint voltage, with the power detected on the input. The

OUTB voltage is connected to the gain control of the AD8367

VGA and increases or decreases the gain of the AD8367,

resulting in the output power being held constant, regardless of

variations in the input power. The AD8364 is able to maintain a

–15.0

–15.1

P

+25°C

OUT

P

+85°C

OUT

–15.2

–15.3

–15.4

–15.5

–15.6

–15.7

–15.8

–15.9

–16.0

–20°C

P

–40°C

OUT

–40

–35

–30

–25

–20

–15

(dBm)

–10

–5

0

5

P

IN

Figure 63. AD8364 Constant Power Performance

Rev. 0 | Page 27 of 48

AD8364

RFIN

1880MHz

IFOUT

80MHz

AD8343

0Ω 0Ω

107Ω

AD8367

90MHz

LPF

11dB

COUPLING

MODE SEL

0V TO 1.2V

VPOS

R24

0Ω

R23

0Ω

C23

100pF

C13

0.1µF

C14

0.1µF

R5

0Ω

C12

100pF

C11

0.1µF

C8

0.1µF

R6

0Ω

TEMP

SENSOR

J4

R4

0Ω

C9

0.1µF

C15

0.1µF

C10

100pF

24

23

22

21

20

19

18

17

CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA

VPSA

T2

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

VSTA

OUTA

FBKA

OUTP

OUTN

FBKB

OUTB

VSTB

LDB181G8820C-110

R9

C5

0.1µF

C7

0.1µF

0Ω

INPA

J3

INHA

INLA

R3

OPEN

R10

0Ω

1:4

C6

0.1µF

PWDN

J2

A

AD8364ACPZ

SW1

PWDN

COMR

INLB

R2

10kΩ

B

VPOS

C4

R11

0Ω

EXPOSED PADDLE

0.1µF

R1

OPEN

INPB

J1

1:4

INHB

VPSB

C3

C5

0.1µF

R12

0Ω

T1

ETK4-2T

R13

OPEN OPEN

R14

VSTB

0.4V TO

3.4V

CHPB DECB COMB ADJB ADJA VREF VLVL CLPB

C20

100pF

1

2

3

4

5

6

7

8

R21

0Ω

C19

0.1µF

C22

0.1µF

R20

0Ω

R18

0Ω

R15

0Ω

C16

0.1µF

C18

OPEN

C17

0.1µF

C21

0.1µF

0.705V

R16

OPEN

C1

0.1µF

C24

100pF

VPOS

TP1

COMM

TP2

VREF

Figure 64. Constant Output Power Circuit

Rev. 0 | Page 28 of 48

AD8364

Because the difference in the coupler values is 8.32 dB, a fixed

gain of −8.32 dB is expected. In practice, there is a gain of

−13 dB. This is caused by the intercept shift of the AD8364 due

to its frequency response, the insertion loss of the output

coupler, and the insertion loss differences of the baluns used on

the input of the AD8364. In this configuration, approximately

33 dB of control range with 0.5 dB drift over temperature is

obtained.

GAIN-STABLE TRANSMITTER/RECEIVER

There are many applications for a transmitter or receiver with a

highly accurate temperature-stable gain. For example, a

multicarrier basestation high power amplifier (HPA) using

digital predistortion has a power detector and an auxiliary

receiver. The power detector and all parts associated with it can

be removed if the auxiliary receiver has a highly accurate

temperature-stable gain. With a set gain receiver, the ADC on

the auxiliary receiver can not only determine the overall power

being transmitted but can also determine the power in each

carrier for a multicarrier HPA.

Figure 66 shows a gain-stable receiver amplifier circuit using

the AD8364 to control an ADL5330 VGA and the AD8343

mixer. The input power was swept from +3 dBm to −35 dBm,

the output power was measured, and the gain was calculated at

multiple temperatures between −40°C and +85°C. Note that the

gain changed less than 0.45 dB over this range (Figure 65).

Most of the gain change was caused by performance differences

at different frequencies.

In controller mode, the AD8364 can be used to hold the

receiver gain constant over a broad input power/temperature

range. In this application, the difference outputs are used to

hold the receiver gain constant.

The RF input is connected to INPA, using a 19.1 dB coupler,

and the down converted output from our signal chain is

connected to INPB, using a 10.78 dB coupler. A 0.1 µF capacitor

is connected between FBKA and OUTP, forming an integrator.

OUTA is connected to VLVL, forcing OUTP to adjust the VGA

so that OUTB is equal to OUTA. The circuit gain is set by the

difference in the coupling values of the input and output

couplers. As noted, OUTP is used to drive the gain control of

the ADL5330 by adjusting the gain up or down as needed to

force the power at the AD8364 inputs to be equal in amplitude.

Since operating at different frequencies, the appropriate voltages

on the ADJ[A, B] pins must be supplied. Because INPA is

operating at 1880 MHz, ADJA is set to 0.75 V. Likewise, because

INPB is operating at 80 MHz, ADJB is set to 0 V.

–11.0

–11.5

–12.0

–40°C

–12.5

+25°C

–13.0

+85°C

–13.5

–14.0

–40

–35

–30

–25

–20

–15

–10

–5

0

5

P

(dBm)

IN

Figure 65. Performance of Gain-Stable Receiver

Rev. 0 | Page 29 of 48

AD8364

RFIN

1880MHz

IFOUT

80MHz

AD8343

0Ω 0Ω

454Ω

0Ω 0Ω

107Ω

ADL5330

90MHz

LPF

19dB

COUPLING

11dB

COUPLING

MODE SEL

0V TO 1.2V

VPOS

R24

0Ω

R23

0Ω

C23

100pF

C13

0.1µF

C14

0.1µF

R5

0Ω

C12

100pF

C11

0.1µF

C8

0.1µF

R6

0Ω

TEMP

SENSOR

J4

R4

0Ω

C9

0.1µF

C15

0.1µF

C10

100pF

24

23

22

21

20

19

18

17

CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA

VPSA

T2

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

VSTA

OUTA

FBKA

OUTP

OUTN

FBKB

OUTB

VSTB

LDB181G8820C-110

R9

0Ω

C5

0.1µF

C7

0.1µF

INHA

INLA

INPA

J3

R3

OPEN

1:4

0.1µF

C6

0.1µF

PWDN

J2

A

AD8364

DIFF OUT +

SW1

PWDN

COMR

INLB

R2

10kΩ

B

VPOS

C4

R11

0Ω

0.1µF

R1

OPEN

INPB

J1

1:4

INHB

VPSB

C3

C5

0.1µF

R12

0Ω

T1

ETK4-2T

R13

R14

OPEN OPEN

CHPB DECB COMB ADJB ADJA VREF VLVL CLPB

C20

100pF

1

2

3

4

5

6

7

8

R21

0Ω

C19

0.1µF

C22

0.1µF

R20

0Ω

R18

0Ω

R15

0Ω

C16

0.1µF

C18

OPEN

C17

0.1µF

C21

0.1µF

0.75V

R16

OPEN

C1

0.1µF

C24

100pF

VPOS

TP1

COMM

TP2

VREF

Figure 66. Gain-Stable Receiver Circuit

Rev. 0 | Page 30 of 48

AD8364

Figure 68 shows a simplified schematic representation of the

ADJ[A, B] interface.

TEMPERATURE COMPENSATION ADJUSTMENT

The AD8364 has a highly stable measurement output with

respect to temperature. However, when the RF inputs exceed a

frequency of 600 MHz, the output temperature drift must be

compensated for using ADJ[A, B] for optimal performance.

Proprietary techniques are used to compensate for the temper-

ature drift. The absolute value of compensation varies with

frequency, balun choice, and circuit board material. Table 5

shows recommended voltages for ADJ[A, B] to maintain a

temperature drift error of typically 0.5 dB or better over the

entire rated temperature range with the recommended baluns.

VPSR

INTERNAL

CURRENT

ADJ[A, B]

VREF/2

COMR

IADJ[A, B]

Figure 68. ADJ[A, B] Interface Simplified Schematic

Table 5. Recommended Voltages for ADJ[A, B]

DEVICE CALIBRATION AND ERROR CALCULATION

450

880

1880

2140

2500

1.10

Frequency (MHz)

The measured transfer function of the AD8364 at 2.14 GHz is

shown in Figure 69. The figure shows plots of both output

voltage vs. input power and calculated error vs. input power. As

the input power varies from −50 dBm to 0 dBm, the output

voltage varies from 0.4 V to about 2.8 V.

0

0.5

0.65

0.85

ADJ[A, B] (V)

Compensating the device for temperature drift using ADJ[A, B]

allows for great flexibility. If the user requires minimum temper-

ature drift at a given input power or subset of the dynamic range,

the ADJ[A, B] voltage can be swept while monitoring OUT[A, B]

over temperature. Figure 67 shows the result of such an exercise

with a broadband balun, one that is not the recommended balun

at 1880 MHz. The value of ADJ[A, B] where the output has

minimum movement (approximately 0.77 V for the example in

Figure 67) is the recommended voltage for ADJ[A, B] to achieve

minimum temperature drift at a given power and frequency.

3.50

3.15

2.80

2.45

2.0

BLUE = –40°C

GREEN = +25°C

RED = +85°C

1.6

ERROR CW –40°C

1.2

0.8

ERROR CW +25°C

2.10

1.75

0.4

ERROR CW +85°C

0

1.70

V_OUT

2

1

1.40

–0.4

–0.8

–1.2

–1.6

–2.0

+85°C

1.65

1.05

0.70

+65°C

V_OUT

1.60

0.35

0

+45°C

1.55

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5

0

5

10

+25°C

P

MEAS (dBm)

IN

INTERCEPT

P_IN

1

P_IN2

+10°C

–20°C

1.50

1.45

1.40

Figure 69. Transfer Function at 2.14 GHz.

Because slope and intercept vary from device to device, board-

level calibration must be performed to achieve high accuracy.

The equation for output voltage can be written as

–40°C

0

0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50

ADJA (V)

V

_OUT= Slope × (P_IN− Intercept)

Figure 67. OUTA vs. ADJA over Temp. Pin = −30 dBm, 1.9 GHz

The ADJ[A, B] input has high input impedance. The input can

be conveniently driven from an attenuated value of VREF using

a resistor divider, if desired.

Where Slope is the change in output voltage divided by the

change in power (dB), and Intercept is the calculated power at

which the output voltage would be 0 V. (Note that Intercept is a

theoretical value; the output voltage can never achieve 0 V).

In general, the calibration is performed by applying two known

signal levels to the AD8364’s input and measuring the

corresponding output voltages. The calibration points are

generally chosen to be within the linear-in-dB operating range

of the device (see the Specifications section for more details).

Rev. 0 | Page 31 of 48

AD8364

Calculation of the slope and intercept is done using the

equations:

Calibration points should be chosen to suit the application at

hand. In general, though, do not choose calibration points in

the nonlinear portion of the log amp’s transfer function (above

0 dBm or below −50 dBm in this case).

Slope = (V_OUT1− V_OUT2)/(P_IN1− P_IN2

Intercept = P_IN1− (V_OUT1/Slope)

)

Figure 71 shows how calibration points can be adjusted to

increase dynamic range, but at the expense of linearity. In this

case, the calibration points for slope and intercept are set at

−1 dBm and −50 dBm. These points are at the end of the

device’s linear range. At 25°C, there is an error of 0 dB at the

calibration points. Note also that the range over which the

AD8364 maintains an error of < 0.4 dB is extended to 57 dB at

25°C. The disadvantage of this approach is that linearity suffers,

especially at the top end of the input range.

Once slope and intercept have been calculated, an equation can

be written that will allow calculation of the input power based

on the output voltage of the detector.

P

_IN(unknown) = (V_{OUT1(measured)}/Slope) + Intercept

The log conformance error of the calculated power is given by

Error (dB) = (V_{OUT(MEASURED)}− V_OUT(IDEAL))/Slope

Figure 69 includes a plot of the error at 25°C, the temperature at

which the log amp is calibrated. Note that the error is not zero.

This is because the log amp does not perfectly follow the ideal

V_OUTvs. P_INequation, even within its operating region. The

error at the calibration points (−43 dBm and −23 dBm in this

case) will, however, be equal to zero by definition.

Another way of presenting the error function of a log amp

detector is shown in Figure 72. In this case, the dB error at hot

and cold temperatures is calculated with respect to the output

voltage at ambient. This is a key difference in comparison to the

previous plots, in which all errors have been calculated with

respect to the ideal transfer function at ambient.

Figure 69 also includes error plots for the output voltage at

−40°C and +85 °C. These error plots are calculated using the

slope and intercept at 25°C. This is consistent with calibration

in a mass-production environment, where calibration at

temperature is not practical.

When the alternative technique, the error at ambient becomes

by definition equal to 0 (see Figure 72).

This would be valid if the device transfer function perfectly

followed the ideal V_OUT= Slope × (P_IN− Intercept) equation.

However, since an rms amp, in practice, never perfectly follows

this equation (especially outside of its linear operating range),

this plot tends to artificially improve linearity and extend the

dynamic range, unless enough calibration points were taken to

remove the error. This plot is a useful tool for estimating temper-

ature drift at a particular power level with respect to the (nonideal)

output voltage at ambient.

SELECTING CALIBRATION POINTS TO IMPROVE

ACCURACY OVER A REDUCED RANGE

In some applications, very high accuracy is required at one

power level or over a reduced input range. For example, in a

wireless transmitter, the accuracy of the high power amplifier

(HPA) is most critical at or close to full power.

Figure 70 shows the same measured data as Figure 69. Notice

that accuracy is very high from −10 dBm to −25 dBm. At

approximately −45 dBm, the error increases to about −0.3 dB

because the calibration points have been changed to −15 dBm

and −25 dBm.

Rev. 0 | Page 32 of 48

AD8364

3.50

3.15

2.80

2.0

3.50

3.15

2.80

2.45

2.10

1.75

1.40

1.05

0.70

0.35

0

2.0

BLUE = –40°C

GREEN = +25°C

RED = +85°C

1.6

ERROR CW –40°C

ERROR CW +25°C

ERROR CW –40°C

1.2

ERROR CW +25°C

ERROR CW +85°C

2.45

2.10

0.8

0.4

V

_OUT2

0.4

1.75

1.40

1.05

0.70

0.35

0

V_OUT

1

–0.4

–0.8

–1.2

–1.6

–2.0

–0.4

–0.8

–1.2

–1.6

ERROR CW +85°C

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5

INTERCEPT

0

5

10

–2.0

10

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5

0

5

P

MEAS (dBm)

IN

P

MEAS (dBm)

IN

P_IN

1

P_IN2

Figure 72. Error vs. Temperature with Respect to Output Voltage at 25 °C,

2.14 GHz (Does Not Account for Transfer Function Nonlinearities at 25°C)

Figure 70. Output Voltage and Error vs. P_INwith 2-Point Calibration at

−15 dBm and −25 dBm, 2.14 GHz

P

1

P 2

IN

3.50

3.15

2.80

2.45

2.10

1.75

1.40

1.05

0.70

0.35

0

2.0

1.6

1.2

ERROR CW –40°C

V

2

OUT

0.8

ERROR CW +25°C

0.4

0

ERROR CW +85°C

–0.4

–0.8

–1.2

–1.6

–2.0

V

1

OUT

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5

0

5

10

P

MEAS (dBm)

IN

57dB DYNAMIC RANGE

Figure 71. Dynamic Range Extension by Choosing Calibration Points that are

Close to the End of the Linear Range, 2.14 GHz

Rev. 0 | Page 33 of 48

AD8364

ALTERING THE SLOPE

24

23

22

21

20

19

18

17

None of the changes to operating conditions discussed so far

affect the logarithmic slope, V_SLOPE, in Equation 7. The slope can

readily be altered by controlling the fraction of OUT[A, B] that

is fed back to the setpoint interface at the VST[A, B] pin. When

the full signal from OUT[A, B] is applied to VST[A, B], the

slope assumes its nominal value of 50 mV/dB. It can be

increased by including a voltage divider between these pins, as

shown in Figure 73. Moderately low resistance values should be

used to minimize scaling errors due to the approximately 70 kΩ

input resistance at the VST[A, B] pin. Keep in mind that this

resistor string also loads the output, and it eventually reduces

the load-driving capabilities if very low values are used.

Equation 17 can be used to calculate the resistor values.

TEMP

VGA

CONTROL

25

26

27

28

29

30

16

15

14

13

12

11

VPSA

INHA

VSTA

OUTA

FBKA

OUTP

OUTN

FBKB

2

I

SIG

CHANNEL A

TruPwr™

2

I

TGT

INLA

PWDN

COMR

INLB

OUTA

OUTB

2

I

SIG

CHANNEL B

TruPwr™

V

OUT

31

32

10

9

INHB

I

OUTB

VSTB

TGT

R1

R2

VPSB

VGA

CONTROL

BIAS

1

2

3

4

5

6

7

8

R1 = R2' (S_D/50 − 1)

where:

S_Dis the desired slope, expressed in mV/dB.

R2' is the value of R2 in parallel with 70 kΩ.

(17)

Figure 73. External Network to Raise Slope

For example, using R1 = 1.65 kΩ and R2 = 1.69 kΩ (R2' =

1.649 kΩ), the nominal slope is increased to 100 mV/dB. This

choice of scaling is useful when the output is applied to a digital

voltmeter because the displayed number directly reads as a

decibel quantity with only a decimal point shift.

24

23

22

21

20

19

18

17

TEMP

VGA

CONTROL

25

26

27

28

29

30

16

15

14

13

12

11

VPSA

INHA

VSTA

OUTA

FBKA

OUTP

OUTN

2

I

SIG

CHANNEL A

TruPwr™

Operating at a high slope is useful when it is desired to measure

a particular section of the input range in greater detail. A

measurement range of 60 dB would correspond to a 6 V change

in VOUT at this slope, exceeding the capacity of the AD8364’s

output stage when operating on a 5 V supply. This requires that

the intercept is repositioned to place the desired input range

section within a window corresponding to an output range of

0.1 V ≤ VOUT ≤ 4.8 V, a 47 dB range.

2

I

TGT

INLA

PWDN

COMR

INLB

OUTA

OUTB

FBKB

OUTB

2

I

SIG

CHANNEL B

TruPwr™

V

OUT

31

32

10

9

INHB

2

I

TGT

R1

4.02kΩ

VSTB

VPSB

VGA

CONTROL

R2

Using the arrangement shown in Figure 74, an output of 0.4 V

corresponds to the lower end of the desired range, and an

output of 3.5 V corresponds to the upper limit with 3 dB of

margin at each end of the range, nominally −32 dBm to −1 dBm

with the intercept at −35.6 dBm. Note that R2 is connected to

VREF rather than ground. R3 is needed to ensure that the

AD8364’s reference buffer is correctly loaded.

BIAS

4.32kΩ

1

2

3

4

5

6

7

8

R3

2kΩ

Figure 74. Scheme Providing 100 mV/dB Slope for Operation over a 3 mV to

300 mV Input Range

When the slope is raised by some factor, the loop capacitor,

CLP[A, B], should be raised by the same factor to ensure

stability and to preserve a chosen averaging time. The slope can

be lowered by placing a voltage divider after the output pin,

following standard practice.

Rev. 0 | Page 34 of 48

AD8364

–40

–45

–50

–55

–60

–65

–70

–75

–80

–85

–90

CHANNEL ISOLATION

Isolation must be considered when using both channels of the

AD8364 at the same time. The two isolation requirements that

should be considered are the isolation from one RF channel

input to the other RF channel input and the isolation from one

RF channel input to the other channel output. When using both

channels of the AD8364, care should be taken in the layout to

isolate the RF inputs from each other. Coupling on the PC

board affects both types of isolation.

B->A

A->B

1,000

In most applications, the designer has the ability to adjust the

power going into the AD8364 through the use of different

valued temperature-stable couplers and accurate temperature-

stable attenuators. When isolation is a concern, it is useful to

adjust the input power so the lowest expected detectable power

is not far from the lowest detectable power of the AD8364 at the

frequency of operation. The AD8364’s lowest detectable power

point has little variation from part to part and is not affected by

the balun. This equalizes the signals on both channels at their

lowest possible power level, which reduces the overall isolation

requirements and possibly adds attenuators to the RF inputs of

the device, reducing the RF channel input isolation requirements.

10

100

10,000

FREQUENCY (MHz)

Figure 75. RF Channel Input-to-Input Isolation

16

14

12

10

8

PEAK INTERFERENCE (IN dB) TO A –45dBm INPUT SIGNAL

DUE TO AN INTERFERING SIGNAL ON THE OTHER

CHANNEL. A->B = A INTERFERING WITH B, X-AXIS IS

CHANNEL A INPUT B->A = B INTERFERING WITH A, X-AXIS

IS CHANNEL B INPUT FREQUENCY SEPARATION OF THE

TWO CHANNELS = 1kHz. SEE CHARACTERIZATION

DESCRIPTION SECTION FOR MORE INFORMATION.

A–>B 880MHz

B–>A 1880MHz

B–>A 880MHz

Measuring the RF channel input to the other RF channel input

isolation is straight forward, and the result of such an exercise is

shown in Figure 75. Note that adding an attenuator in series

with the RF signal increases the channel input-to-input

isolation by the value of the attenuator.

A–>B 1880MHz

B–>A 2140MHz

6

B–>A

450 MHz

B–>A 2500 MHz

A–>B 2140MHz

4

A–>B

450 MHz

A–>B

2

2500MHZ

The isolation between one RF channel input and the other

channel output is a little more complicated. Do not assume that

worst-case isolation happens when one RF channel has high

power and the other RF channel is set at its lowest detectable

power. Worst-case isolation happens when the low power channel

is at a nominally low power level, as chosen in Figure 76. If the

inputs to both RF channels are at the same frequency, the isola-

tion also depends on the phase shift between the RF signals put

into the AD8364. This can be seen by placing a high power

signal on one RF channel input and another signal (low power)

slightly offset in frequency to the other RF channel. If the output

of the low power channel is observed with an oscilloscope, it

would have a ripple that would look similar to a full-wave

rectified sine wave with a frequency equal to the frequency

difference between the two channels, that is, a beat tone. The

magnitude of the ripple reflects the isolation at a specific phase

offset (note that two signals of slightly different frequencies act

like two signals with a constantly changing phase), and the

frequency of that ripple is directly related to the frequency offset.

The data taken in Figure 76 assumes worst-case amplitude and

phase offset. If the RF signals on Channel A and Channel B are at

significantly different frequencies, the input-to-output isolation

increase, depending on the capacitors placed on CLP[A, B] and

CHP[A, B] and the frequency offset of the two signals (Figure 77),

due to the response roll-off within AD8364.

0

–20

–15

–10

–5

0

5

10

15

INTERFERING CHANNEL AMPLITUDE (dBm)

Figure 76. Apparent Measurement Error Due to Overall Channel-to-Channel

Cross-Coupling

7

PEAK INTERFERENCE (IN dB) TO A -45dBm INPUT

SIGNAL DUE TO AN INTERFERING SIGNAL ON THE

OTHER CHANNEL.

6

5

4

3

2

1

0

A->B = A INTERFERING WITH B, X-AXIS IS CHANNEL A

INPUT Freq chA = 2500 MHz Freq CHB = 1880MHz

B->A = B INTERFERING WITH A, X-AXIS IS

CHANNEL B INPUT Freq CHB = 2500 MHz

Freq CHA = 1880 MHz

FREQUENCY SEPARATION OF THE

TWO CHANNELS = 620 MHz.

SEE CHARCTERIZATION DESCRIPTION

SECTION FOR MORE INFORMATION

B->A

A->B

–20

–15

–10

–5

0

5

10

15

INTERFERING CHANNEL AMPLITUDE (dBm)

Figure 77. Improved Measurement Error with Increased Frequency

Separation

Rev. 0 | Page 35 of 48

AD8364

Once the response time is set so that the AD8364 is just able to

follow the RF burst requirements (within the tolerance of the

capacitors), the output of the AD8364 should be evaluated with

an oscilloscope. If there is ripple on the output (due to the

modulated signal), averaging may need to be performed on

the DSP to achieve a true rms response. Figure 44 and Figure 45

may help in determining the proper CLP[A, B] values to use.

CHOOSING THE RIGHT VALUE

FOR CHP[A, B] AND CLP[A, B]

The AD8364’s VGA includes an offset cancellation loop, which

introduces a high-pass filter effect in its transfer function. The

corner frequency, f_HP, of this filter must be below that of the lowest

input signal in the desired measurement bandwidth frequency

to properly measure the amplitude of the input signal. The

required value of the external capacitor is given by

SINGLE-ENDED INPUT OPERATION

For optimum operation, the RF inputs to the AD8364 should be

driven differentially. However, the AD8364 RF inputs can also

be driven in a single-ended configuration with reduced

dynamic range. Figure 78 shows a recommended input

configuration for a single channel.

CHP[A, B] = 200 µF/(2 × π × f_HP)(f_HPin Hz)

(18)

Thus, for operation at frequencies down to 100 kHz, CHP[A, B]

should be 318 pF.

In the standard connections for the measurement mode, the

VST[A, B] pin is tied to OUT[A, B]. For small changes in input

amplitude (a few decibels), the time-domain response of this

loop is essentially linear with a 3 dB low-pass corner frequency

of nominally f_LP= 1/(2 × π × CLP[A, B] × 1.1 kΩ). Internal time

delays around this local loop set the minimum recommended

value of this capacitor to about 300 pF, making f_LP= 482 kHz.

Figure 79 shows the performance obtained with the

configuration shown in Figure 78. The user should note that the

dynamic range performance suffers in single-ended

configuration due to the inherent amplitude and phase

imbalance at the RF inputs. However, at low frequency the

dynamic range is quite good and users trying to detect low

frequency or baseband signals may want to consider this as an

option. At frequencies greater than 450 MHz, the dynamic

range decreases to about 20 dB, reducing the AD8364’s

usefulness for many applications. Performance in single-ended

configuration is subject to circuit board layout (see the Printed

Circuit Board Considerations section).

For operation at lower signal frequencies, or whenever the

averaging time needs to be longer, use

CLP[A, B] = 900 µF/2 × π × f_LP(f_LPin Hz)

(19)

When the input signal exhibits large crest factors, such as a

WCDMA signal, CLP[A, B] must be much larger than might at

first seem necessary. This is due to the presence of significant low

frequency components in the complex, pseudo random modu-

lation, which generates fluctuations in the output of the AD8364.

INHx

100Ω

INLx

100Ω

RF BURST RESPONSE TIME

Figure 78. Recommended Input Configuration for Single-Ended Input Drive

RF burst response time is important for modulated signals that

have large steps in power, such as a single carrier EVDO that

has the potential for a greater than 20 dB burst of power (for

approximately 200 µs out of every 800 µs).

5.0

50MHz

4.5

4.0

3.5

Accurate power detection for signals with RF bursts is achieved

when the AD8364 is able to respond quickly to the change in RF

power; however, the response time is limited by the capacitors

placed on Pins CLP[A, B], CHP[A, B], and DEC[A, B].

50MHz Error

450MHz ERROR

3.0

100MHz

2.5

2.0

45 MHz

Capacitors placed on the DEC[A, B] pins affect the response time

the least and should be chosen as stated in the RF Input Interface

section. Capacitors placed on CHP[A, B] and CLP[A, B] should

be chosen according to the equations in the Choosing the Right

Value for CHP[A, B] and CLP[A, B] section and the response time

for the AD8364 should be evaluated. If the response time is not

fast enough to follow the burst response, the values for CLP[A, B]

should be decreased. The capacitor values placed on the CLP[A,

B] have the largest effect on the rise and fall times. The capacitor

values placed on CHP[A, B] affect the rising and falling corner

of the response (overshoot or under-shoot); however, the falling

corner is most likely swamped out by the effect of CLP[A, B].

1.5

1.0

0.5

100MHz ERROR

0

–60

–50

–40

–30

–20

–10

0

10

20

RF INPUT (dBm)

Figure 79. Single-Ended Performance for

the Configuration Shown in Figure 78

Rev. 0 | Page 36 of 48

AD8364

The accurate measurement range (that is, the dynamic range) of

AD8364’s detectors is sensitive to amplitude and phase matching

of the signals presented at the differential inputs. Care should be

taken to ensure matching of these parameters and to minimize

parasitic capacitance on the RF inputs when laying out the PC

board. It is also suggested that the two traces associated with

each differential input be mirror images, or duplicates, of one

another where possible. A high quality balun with known

output magnitude and phase characteristics is recommended to

perform single-ended to balanced conversions. It is possible to

improve the dynamic range by skewing the amplitude and

phase matching at the input. See the Typical Performance

Characteristics section for more details.

PRINTED CIRCUIT BOARD CONSIDERATIONS

Each RF input pin of the AD8364 presents 100 Ω impedance

relative to their respective ac grounds. To ensure that signal

integrity is not seriously impaired by the printed circuit board

(PCB), the relevant connection traces should provide

appropriate characteristic impedance to the ground plane. This

can be achieved through proper layout. When laying out an RF

trace with controlled impedance, consider the following:

•

When calculating the RF line impedance, take into account

the spacing between the RF trace and the ground on the

same layer.

•

Ensure that the width of the microstrip line is constant and

that there are as few discontinuities, such as component

pads, as possible along the length of the line. Width

variations cause impedance discontinuities in the line and

may result in unwanted reflections.

Stable, low ESR capacitors are mandatory in the RF circuitry of

the AD8364. This corresponds to capacitors connected to

Pins INH[A, B], INL[A, B], DEC[A, B], and CHP[A, B]. High

ESR capacitors may result in amplitude and phase mismatch at

the differential inputs, which in turn results in low dynamic

range. Capacitors with poor aging characteristics under

temperature cycling have been shown to accentuate the

temperature drift during operation of the AD8364. Use of

Samsung CL10 series multilayer ceramic capacitors (or similar)

in the RF area are recommended.

•

Do not use silkscreen over the signal line because it can

alter the line impedance.

Keep the length of the RF input traces as short as possible.

Figure 80 shows the cross section of a PC board, and Table 6

shows two possible sets of dimensions that provide a 100 Ω line

impedance for FR-4 board material with ε_r= 4.6 and Rodgers 4003

board material with ε_r= 3.38.

High transient and noise levels on the power supply, ground,

and inputs should be avoided. This reinforces the need for

proper supply bypassing and decoupling. See the Evaluation

Boards for suggestions.

Table 6. Possible Trace Dimensions for Z_O= 100 Ω

Dimension

FR-4 (mil)

Rodgers 4003 (mil)

A solder appropriate for either the lead-free or leaded version of

the AD8364 should be chosen. After the circuit board has been

soldered, it is important to thoroughly clean all excess solder

flux and residues from the board. Any residual material may act

as stray parasitic capacitance, which could result in degraded

performance.

W

H

T

22

53

2

6

11

0.7

3W

W

3W

T

PACKAGE CONSIDERATIONS

E

H

R

The AD8364 uses a compact 32-lead LFCSP. A large exposed

paddle on the bottom of the device provides both a thermal

benefit and a low inductance path to ground for the circuit. To

make proper use of this packaging feature, the PCB RF/dc

common ground reference needs to make contact directly

under the device with as many vias as possible to lower the

inductance and thermal impedance.

Figure 80. Cross-Section View of a PC Board

It is possible to approximate a 100 Ω trace on a board designed

with the 50 Ω dimensions above by removing the ground plane

within three line widths of the area directly below the trace.

However, more predictable performance may be obtained with

precise ground plane spacing. It is possible to design a circuit

board with two ground planes, one plane for areas with 50 Ω

characteristic impedance and another for areas with 100 Ω

characteristic impedance. If the 100 Ω plane is placed below the

50 Ω plane, then an opening can be made in the 50 Ω plane to

allow the 100 Ω traces to work against the 100 Ω ground plane.

The two ground planes should be connected together with as

many vias as possible.

Rev. 0 | Page 37 of 48

AD8364

BASIS FOR ERROR CALCULATIONS

DESCRIPTION OF CHARACTERIZATION

The slope and intercept are derived using the coefficients of a

linear regression performed on data collected in its central

operating range. Error is stated in two forms: (1) error from

linear response to CW waveform and (2) output delta from

25°C performance.

The general hardware configuration used for most of the

AD8362 characterization is shown in Figure 81. The signal

sources used in this example are the Rohde & Schwarz SMIQ03B

and Agilent E4438C. Input-matching baluns are used to transform

the single-ended RF signal to its differential form. Due to the

differential inputs’ sensitivity to amplitude and phase mismatch,

specific baluns were used for each characterization frequency to

achieve the best performance.

The error from linear response to CW waveform is the decibel

difference in output from the ideal output defined by the

conversions gain and output reference. This is a measure of the

linearity of the device response to both CW and modulated

waveforms. The error in dB is calculated by

Other selected configurations are shown in Figure 82 and

Figure 83 as well.

V_OUT− Slope ×

(

P_IN− P_Z

)

OUTA

OUTB

OUTP

OUTN

VREF

TEMP

SIGNAL

SOURCE

INA

–3dB

Error (dB) =

AGILENT

34970A

METER/

AD8364

Slope

CHARACTERIZATION

BOARD

INB

SWITCHING

SIGNAL

SOURCE

–3dB

where P_Zis the x-axis intercept expressed in dBm. This is

analogous to the input amplitude that would produce an output

of 0 V, if such an output was possible.

Error from the linear response to the CW waveform is not a

measure of absolute accuracy, since it is calculated using the

slope and intercept of each device. However, it verifies the

linearity and the effect of modulation on the device’s response.

Similarly, error from 25°C performance uses the 25°C

performance of a given device and waveform type as the

reference from which all other performance parameters shown

alongside it are compared. It is predominantly (and most often)

used as a measurement of output variation with temperature.

COMPUTER

CONTROLLER

Figure 81. General Characterization Configuration

MINI-CIRCUITS

ZHL–42W

AD8340 OR

–6dB SPLITTER

AD8341 VECTOR

INHA/B

INLA/B

MODULATOR

–8dB

–6dB

AGILENT 8648

RF SOURCE

50Ω

–9dB

–8dB

–6dB

Figure 82. Configuration for Amplitude and Phase Mismatch

Characterization

Rev. 0 | Page 38 of 48

AD8364

VPOS

R24

0Ω

VPOS

C23

100pF

C13

0.1µF

R5

0Ω

C12

100pF

C11

0.1µF

C8

0.1µF

TEKTDS510

SCOPE

R4

0Ω

C15

CLPA

C9

0.1µF

C10

24

23

22

21

20

19

18

17

100pF

CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA

25

16

VPSA

VSTA

26

27

15

14

INHA

INLA

OUTA

FBKA

SMIQ06B

SIGNAL

GENERATOR

3dB

BALUN

AD8364ACPZ

28

29

30

31

32

13

12

11

10

9

PWDN

COMR

INLB

OUTP

OUTN

FBKB

OUTB

VSTB

LECROY9213

PULSE

GENERATOR

BALUN

INHB

VPSB

CHPB DECB COMB ADJB ADJA VREF VLVL CLPB

C20

100pF

1

2

3

4

5

6

7

8

R21

0Ω

C22

0.1µF

C16

CLPB

HP6236B

POWER

SUPPLY

C21

0.1µF

C1

0.1µF

C24

100pF

VPOS

Figure 83. Configuration for RF Burst Measurement

Rev. 0 | Page 39 of 48

AD8364

designated frequency range. The RF area layout of the circuit

board used for characterization work at 880 MHz is included in

this section, showing the footprint of the recommended balun

(Mini-Circuits JTX-4-10T) and trace lengths used. The user

may obtain different performance than shown in this data sheet

if their layout dimensions and style differ.

EVALUATION AND CHARACTERIZATION

CIRCUIT BOARD LAYOUTS

There are two evaluation boards for the AD8364, one

appropriate for low frequency work (AD8364-EVAL-500) and

another one designed for use at 2140 MHz (AD8364-EVAL-

2140). Each board has a balun specific to operation in the

Figure 84. AD8364-EVAL-500 Evaluation Board RF Area Layout

Rev. 0 | Page 40 of 48

AD8364

Figure 85. AD8364_EVAL-2140 Evaluation Board RF Area Layout

Figure 86. 880 MHz Characterization Board RF Area Layout

Rev. 0 | Page 41 of 48

AD8364

Table 7. AD8364-EVAL-500 Evaluation Board Configuration Options (10 MHz to 650 MHz)

Component

Function/Notes

Part Number

Default Value

T1, T2

The dynamic range of the AD8364 is directly related to the

magnitude and phase balance of the balun feeding the RF

signal to the part. The evaluation board includes M/A-COM

ETK4-2T soldered to the board and two unsoldered M/A-COM

ETC1.6-4-2-3. The ETK4-2T has good magnitude and phase

balance between 10 MHz and 650 MHz, but slowly degrades

above 650 MHz due to the balun. The M/A-COM ETC1.6-4-2-3

broadband baluns allow limited dynamic range performance

between 500 MHz and 2500 MHz. Better dynamic range can be

achieved by using narrow band baluns with better magnitude

and phase performance.

M/A-COM ETK4-2T

C11, C13, C21

C10, C12, C20

C19

C18

C15, C17

C14, C16

Supply filtering/decoupling capacitors.

VREF filtering/decoupling capacitor.

Optional VLVL filtering/decoupling capacitor.

Output low-pass filter capacitors (CLPA/B).

0.1 µF

100 pF

0.1 µF

OPEN

0.1 µF

Output low-pass filter capacitors, which can be activated by

removing jumpers R6 and R15.

C23, C24

C1, C8

C2, C3, C4, C5, C6, C7

Input bias-point decoupling capacitors (DECA/B).

Samsung CL10B101KONC

Samsung CL10B104KONC

100 pF

0.1 µF

Stable, low ESR capacitors are mandatory in the RF input area

of the AD8364. This corresponds to capacitors connected to

Pins INH[A, B], INL[A, B], DEC[A, B], and CHP[A, B]. Poor quality

capacitors may result in amplitude and phase mismatch at the

differential inputs, which in turn results in low dynamic range.

Capacitors with poor aging characteristics under temperature

cycling have been shown to accentuate the temperature drift

during operation of the AD8364. Using Samsung CL10 series

multilayer ceramic capacitors (or similar) in the RF area is

suggested.

C9, C22

Input high-pass filter capacitor (CHPA/B).

Samsung CL10B104KONC

0.1 µF

R17, R18, R19, R20

R17/R19 are usually jumpers and R18/R20 are usually left open.

The pads for R17/R18 or R19/R20 can be used to make voltage

dividers to set the ADJA/B voltages for temperature

compensation at different frequencies.

R17/R19 = 0 Ω

R18/R20 =

OPEN

R12, R13

DUT

R4, R5, R6, R9, R15, R21,

R24, R23

R12 is usually a jumper and R13 is usually open, but the pads

can also be used to make a voltage divider to adjust the slope of

Channel B.

AD8364.

Jumpers.

R12 = 0 Ω

R13 = OPEN

AD8364ACPZ

0 Ω

R10, R11

R2, R16

R1, R3

Capacitors can be installed for controller mode.

Optional pull-down resistors.

100 Ω resistor to be added when input coupling from a single-

ended source (not installed).

0 Ω

10 kΩ/OPEN

OPEN/100 Ω

R14

To be added for use in slope adjustment (not installed).

OPEN

SW1

Power-down/enable or external power-down selector, open is

enable (Position A, unloaded).

SW2, SW3

Measurement mode (Position A)/controller mode (Position B)

selector.

SW4

SW5

SW6

VLVL VREF (Position A)/external control (Position B) selector.

ADJA VREF (Position A)/external control (Position B) selector.

ADJB VREF (Position B)/external control (Position A) selector.

Rev. 0 | Page 42 of 48

AD8364

Table 7. AD8364-EVAL-2140 Evaluation Board Configuration Options (2140 MHz)

Component

Function/Notes

Part Number

Default Value

T1, T2

The dynamic range of the AD8364 is directly related to the

magnitude and phase balance of the balun feeding the RF

signal to the part. At 2140 MHz, we have found it necessary to

use a narrow band balun and have used the Murata

LDB212G1020C-001.

Murata LDB212G1020C-00

C11, C13, C21

C10, C12, C20

C19

C18

C15, C17

C14, C16

Supply filtering/decoupling capacitors.

VREF filtering/decoupling capacitor.

Optional VLVL filtering/decoupling capacitor.

Output low-pass filter capacitors (CLPA/B).

0.1 µF

100 pF

0.1 µF

OPEN

0.1 µF

Output low-pass filter capacitors, which can be activated by

removing jumpers R6 and R15.

C23, C24

C1, C8

C2, C3, C4, C5, C6, C7

Input bias-point decoupling capacitors (DECA/B).

Samsung CL10B101KONC

Samsung CL10B104KONC

100 pF

0.1 µF

Stable, low ESR capacitors are mandatory in the RF input area

of the AD8364. This corresponds to capacitors connected to

Pins INH[A, B], INL[A, B], DEC[A, B], and CHP[A, B]. Poor quality

capacitors may result in amplitude and phase mismatch at the

differential inputs, which in turn results in low dynamic range.

Capacitors with poor aging characteristics under temperature

cycling have been shown to accentuate the temperature drift

during operation of the AD8364. Using Samsung CL10 series

multilayer ceramic capacitors (or similar) in the RF area is

suggested.

C9, C22

R17, R18, R19, R20

Input high-pass filter capacitor (CHPA/B).

Samsung CL10B104KONC

AD8364ACPZ

0.1 µF

R17/R19 = 0 Ω

R18/R20 =

OPEN

R17/R19 are usually jumpers and R18/R20 are usually left open.

The pads for R17/R18 or R19/R20 can be used to make voltage

dividers to set the ADJA/B voltages for temperature

compensation at different frequencies.

AD8364.

Jumpers.

DUT

R4, R5, R6, R9, R12, R15,

R21

0 Ω

R10, R11

R24

R2, R16

R14, R27

SW1

Capacitors can be installed for controller mode.

Optional loading resistor for TEMP.

Optional pull-down resistors.

To be added for use in slope adjustment (not installed).

Power-down/enable or external power-down selector, open is

enable (Position A, unloaded).

0 Ω

1 kΩ

OPEN

SW2, SW3

Measurement mode (Position A)/controller mode (Position B)

selector.

SW4

SW5

SW6

VLVL VREF (Position A)/external control (Position B) selector.

ADJA VREF (Position A)/external control (Position B)l selector.

ADJB VREF (Position B)/external control (Position A) selector.

Rev. 0 | Page 43 of 48

AD8364

EVALUATION BOARDS

VPOS

R24

0Ω

R23

0Ω

C23

100pF

C13

0.1µF

C14

0.1µF

R5

0Ω

C12

100pF

C11

0.1µF

C8

0.1µF

R6

0Ω

TEMP

SENSOR

J4

R4

0Ω

C9

0.1µF

C15

0.1µF

C10

100pF

SETPOINT

VOLTAGE A

J5

24

23

22

21

20

19

18

17

CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA

VPSA

B

A

SW2

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

VSTA

OUTA

FBKA

OUTP

OUTN

FBKB

OUTB

VSTB

T2

ETK4-2T

R9

0Ω

C5

C7

0.1µF

OUTPUT

VOLTAGE A

J6

INPA

J3

INHA

INLA

R3

OPEN

R10

0Ω

1:4

A

C6

0.1µF

PWDN

J2

AD8364ACPZ

SW1

DIFF OUT +

J7

PWDN

COMR

INLB

R2

10kΩ

B

VPOS

DIFF OUT +

J8

R11

0Ω

C4

0.1µF

EXPOSED PADDLE

R1

OPEN

1:4

OUTPUT

VOLTAGE B

J9

INPB

J1

INHB

C3

0.1µF

C2

0.1µF

R12

A

B

T1

ETK4-2T

0Ω

VPSB

R13

OPEN OPEN

R14

SW3

SETPOINT

VOLTAGE B

J10

CHPB DECB COMB ADJB ADJA VREF VLVL CLPB

C20

1

2

3

4

5

6

7

8

R21

0Ω

100pF

C19

C22

R20

R18

0.1µF

OPEN OPEN

R15

0Ω

C16

C18

C17

0.1µF

C21

0.1µF

OPEN

R19

0Ω

R17

0Ω

R16

C1

0.1µF

C24

OPEN

100pF

VPOS

TP1

SW6

A

SW5

B

A

SW4

A

COMM

TP2

B

VREF

ADJB ADJA

J13 J12

REF LEVEL

VOLTAGE

J11

Figure 87. AD8364-EVA-500 Evaluation Board

Rev. 0 | Page 44 of 48

AD8364

VPOS

C23

100pF

C13

0.1µF

C14

0.1µF

R5

0Ω

C12

100pF

C11

0.1µF

C8

0.1µF

R6

0Ω

TEMP

SENSOR

J4

R4

0Ω

R24

1kΩ

VREF

C9

0.1µF

C15

0.1µF

C10

100pF

SETPOINT

VOLTAGE A

J5

R27

OPEN

24

23

22

21

20

19

18

17

CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA

VPSA

B

A

SW2

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

VSTA

OUTA

FBKA

OUTP

OUTN

FBKB

OUTB

VSTB

T2

LDB212G1020C C7

R9

0Ω

C5

0.1µF

OUTPUT

VOLTAGE A

J6

INPA

J3

INHA

INLA

R3

OPEN

R10

1:4

A

0Ω

C6

PWDN

J2

0.1µF

AD8364ACPZ

SW1

DIFF OUT +

J7

PWDN

COMR

INLB

B

VPOS

DIFF OUT –

J8

R11

0Ω

C4

0.1µF

EXPOSED PADDLE

1:4

OUTPUT

VOLTAGE B

J9

INPB

J1

INHB

C3

C2

R12

0Ω

A

B

0.1µF

T1

LDB212G1020C

VPSB

R14

OPEN

SW3

SETPOINT

VOLTAGE B

J10

CHPB DECB COMB ADJB ADJA VREF VLVL CLPB

C20

1

2

3

4

5

6

7

8

R21

100pF

VREF

C19

0.1µF

0Ω

C22

0.1µF

R20

R18

OPEN OPEN

R15

0Ω

C16

C18

OPEN

C17

0.1µF

C21

0.1µF

R19

R17

R16

OPEN

C1

0.1µF

C24

0Ω

100pF

VPOS

TP1

SW6

B

SW5

A

B

A

SW4

A

COMM

TP2

B

VREF

ADJB ADJA

J13 J12

REF LEVEL

VOLTAGE

J11

Figure 88. AD8364-EVAL-2140 Evaluation Board

Rev. 0 | Page 45 of 48

AD8364

ASSEMBLY DRAWINGS

Figure 89. AD8364-EVAL-500 Assembly Drawing

Figure 90. AD8364-EVAL-2140 Assembly Drawing

Rev. 0 | Page 46 of 48

AD8364

OUTLINE DIMENSIONS

5.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

EXPOSED

PAD

(BOTTOM VIEW)

3.45

3.30 SQ

3.15

TOP

VIEW

4.75

BSC SQ

0.50

0.40

0.30

17

16

8

9

0.25 MIN

3.50 REF

0.80 MAX

0.65 TYP

12° MAX

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 91. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-3)

Dimensions shown in millimeters

ORDERING GUIDE

Ordering

Model

Temperature Range Package Description

Package Option

CP-32-3

Quantity

AD8364ACPZ-WP^{1, 2}

−40°C to +85°C

32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Evaluation Board, Low Frequency to 500 MHz

Evaluation Board, 2140 MHz only

36 Units

AD8364ACPZ-REEL7¹−40°C to +85°C

1,500 Units

250 Units

1,500 Units

AD8364ACPZ-RL2¹

AD8364ACP-REEL7

AD8364-EVAL-500

AD8364-EVAL-2140

−40°C to +85°C

¹Z = Pb-free part.

²WP = Waffle Pack

Rev. 0 | Page 47 of 48

AD8364

NOTES

©

registered trademarks are the property of their respective owners.

D05334–0–4/05(0)

Rev. 0 | Page 48 of 48


型号：	AD8364-EVAL-2140
厂家：	ADI
描述：	LF to 2.7 GHz Dual 60 dB TruPwr Detector LF至2.7 GHz双60分贝TruPwr检测器
文件：	总48页 (文件大小：3267K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD8364-EVAL-2140 [ADI]

相关型号：

AD8364-EVAL-500

AD8364-EVALZ

AD8364ACP-REEL7

AD8364ACPZ-R2

AD8364ACPZ-REEL7

AD8364ACPZ-RL2

AD8364ACPZ-RL21

AD8364ACPZ-WP

AD8364XCP

AD8364_16

AD8366

AD8366-EVALZ