AD834JRZ-REEL [ADI]
暂无描述;
ADI 
a
500 MHz Four-Quadrant Multiplier
AD834
FUNCTIONAL BLOCK DIAGRAM
FEATURES
DC to >500 MHz Operation
Differential ؎1 V Full-Scale Inputs
Differential ؎4 mA Full-Scale Output Current
Low Distortion (≤0.05% for 0 dBm Input)
Supply Voltages from ؎4 V to ؎9 V
Low Power (280 mW typical at VS = ؎5 V)
APPLICATIONS
High Speed Real Time Computation
Wideband Modulation and Gain Control
Signal Correlation and RF Power Measurement
Voltage Controlled Filters and Oscillators
Linear Keyers for High Resolution Television
Wideband True RMS
(W)
PRODUCT DESCRIPTION
The AD834 is a monolithic laser-trimmed four-quadrant analog
multiplier intended for use in high frequency applications, hav-
ing a transconductance bandwidth (RL = 50 Ω) in excess of
500 MHz from either of the differential voltage inputs. In multi-
plier modes, the typical total full-scale error is 0.5%, dependent
on the application mode and the external circuitry. Performance
is relatively insensitive to temperature and supply variations, due
to the use of stable biasing based on a bandgap reference genera-
tor and other design features.
Two application notes featuring the AD834 (AN-212 and
AN-216) can now be obtained by calling 1-800-ANALOG-D.
For additional applications circuits consult the AD811 data sheet.
PRODUCT HIGHLIGHTS
l. The AD834 combines high static accuracy (low input and
output offsets and accurate scale factor) with very high band-
width. As a four-quadrant multiplier or squarer, the response
extends from dc to an upper frequency limited mainly by
packaging and external board layout considerations. A large
signal bandwidth of over 500 MHz is attainable under opti-
mum conditions.
To preserve the full bandwidth potential of the high speed
bipolar process used to fabricate the AD834, the outputs appear
as a differential pair of currents at open collectors. To provide a
single ended ground referenced voltage output, some form of ex-
ternal current to voltage conversion is needed. This may take the
form of a wideband transformer, balun, or active circuitry such
as an op amp. In some applications (such as power measure-
ment) the subsequent signal processing may not need to have
high bandwidth.
2. The AD834 can be used in many high speed nonlinear
operations, such as square rooting, analog division, vector
addition and rms-to-dc conversion. In these modes, the
bandwidth is limited by the external active components.
3. Special design techniques result in low distortion levels (better
than –60 dB on either input) at high frequencies and low signal
feedthrough (typically –65 dB up to 20 MHz).
The transfer function is accurately trimmed such that when
X = Y = 1 V, the differential output is 4 mA. This absolute
calibration allows the outputs of two or more AD834s to be
summed with precisely equal weighting, independent of the
accuracy of the load circuit.
4. The AD834 exhibits low differential phase error over the input
range—typically 0.08° at 5 MHz and 0.8° at 50 MHz. The
large signal transient response is free from overshoot, and has
an intrinsic rise time of 500 ps, typically settling to within 1%
in under 5 ns.
The AD834J is specified for use over the commercial tempera-
ture range of 0°C to +70°C and is available in an 8-lead DIP
package and an 8-lead plastic SOIC package. AD834A is avail-
able in cerdip and 8-lead plastic SOIC packages for operation
over the industrial temperature range of –40°C to +85°C. The
AD834S/883B is specified for operation over the military tem-
perature range of –55°C to +125°C and is available in the 8-lead
cerdip package. S-Grade chips are also available.
5. The nonloading, high impedance, differential inputs simplify
the application of the AD834.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(T = +25؇C and ؎V = ؎5 V, unless otherwise noted; dBm assumes 50 ⍀ load.)
AD834–SPECIFICATIONS
A
S
AD834J
Typ
AD834A, S
Typ
Model
Conditions
Min
Max
Min
Max
Units
MULTIPLIER PERFORMANCE
XY
(1V )2
XY
(1V )2
0.5
1.5
0.1
W =
× 4 mA
W =
× 4 mA
Transfer Function
Total Error1 (Figure 6)
vs. Temperature
vs. Supplies2
–1 V ≤ X, Y < +1 V
TMIN to TMAX
4 V to 6 V
0.5
؎2
؎2
؎3
0.3
؎1
% FS
% FS
% FS/V
% FS
MHz
0.1
0.5
0.3
؎1
Linearity3
0.5
Bandwidth4
See Figure 5
500
500
Feedthrough, X
Feedthrough, Y
AC Feedthrough, X5
X = 1 V, Y = Nulled
X = Nulled, Y = 1 V
X = 0 dBm, Y = Nulled
f = 10 MHz
f = 100 MHz
X = Nulled, Y = 0 dBm
f = 10 MHz
0.2
0.1
0.3
0.2
0.2
0.1
0.3
0.2
% FS
% FS
–65
–50
–65
–50
dB
dB
AC Feedthrough, Y5
–70
–50
–70
–50
dB
dB
f = 100 MHz
INPUTS (X1, X2, Y1, Y2)
Full-Scale Range
Clipping Level
Input Resistance
Offset Voltage
Differential
Differential
Differential
1
1.3
25
0.5
10
1
1.3
25
0.5
10
V
V
kΩ
؎1.1
؎1.1
3
3
mV
µV/°C
mV
µV/V
µA
dB
% FS
% FS
vs. Temperature
TMIN to TMAX
4 V to 6 V
4
300
4
300
vs. Supplies2
Bias Current
Common-Mode Rejection
Nonlinearity, X
Nonlinearity, Y
Distortion, X
100
45
70
0.2
0.1
100
45
70
0.2
0.1
f ≤ 100 kHz; 1 V p-p
Y = 1 V; X = 1 V
X = 1 V; Y = 1 V
X = 0 dBm, Y = 1 V
f = 10 MHz
0.5
0.3
0.5
0.3
–60
–44
–60
–44
dB
dB
f = 100 MHz
Distortion, Y
X = 1 V, Y = 0 dBm
f = 10 MHz
–65
–50
–65
–50
dB
dB
f = 100 MHz
OUTPUTS (W1, W2)
Zero Signal Current
Differential Offset
vs. Temperature
Each Output
X = 0, Y = 0
TMIN to TMAX
8.5
20
40
8.5
20
40
mA
µA
nA/°C
µA
mA
؎60
؎60
؎60
4.04
9
Scaling Current
Output Compliance
Noise Spectral Density
Differential
3.96
4.75
4
4.04
9
3.96
4.75
4
V
f = 10 Hz to 1 MHz
Outputs into 50 Ω Load
16
16
nV/√Hz
POWER SUPPLIES
Operating Range
Quiescent Current6
+VS
4
9
4
9
V
TMIN to TMAX
11
28
14
35
11
28
14
35
mA
mA
–VS
TEMPERATURE RANGE
Operating, Rated Performance
Commercial (0°C to +70°C)
Military (–55°C to +125°C)
Industrial (–40°C to +85°C)
AD834J
AD834S
AD834A
PACKAGE OPTIONS
8-Pin SOIC (R)
8-Pin Cerdip (Q)
AD834JR, REEL, REEL7
AD834JN
AD834AR
AD834AQ, SQ/883B
8-Pin Plastic DIP (N)
NOTES
1Error is defined as the maximum deviation from the ideal output, and expressed as a percentage of the full-scale output.
2Both supplies taken simultaneously; sinusoidal input at f ≤ 10 kHz.
3Linearity is defined as residual error after compensating for input offset voltage, output offset current and scaling current errors.
4Bandwidth is guaranteed when configured in squarer mode. See Figure 5.
5Sine input; relative to full-scale output; zero input port nulled; represents feedthrough of the fundamental.
6Negative supply current is equal to the sum of positive supply current, the signal currents into each output, W1 and W2, and the input bias currents.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels.
Specifications subject to change without notice.
–2–
REV. C
AD834
ABSOLUTE MAXIMUM RATINGS*
CONNECTION DIAGRAM
Supply Voltage (+VS to –VS) . . . . . . . . . . . . . . . . . . . . . . 18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 500 mW
Input Voltages (X1, X2, Y1, Y2) . . . . . . . . . . . . . . . . . . . . +VS
Operating Temperature Range
Small Outline (R) Package
Plastic DIP (N) Package
Cerdip (Q) Package
AD834J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD834A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD834S/883B . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range (Q) . . . . . . . . . –65°C to +150°C
Storage Temperature Range (R, N) . . . . . . . –65°C to +125°C
Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . .+300°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the devices. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
METALIZATION PHOTOGRAPH
CHIP DIMENSIONS AND BONDING DIAGRAM
Dimensions shown in inches and (mm).
THERMAL CHARACTERISTICS
Contact factory for latest dimensions.
JC
JA
8-Pin Cerdip Package (Q)
8-Pin Plastic SOIC (R)
8-Pin Plastic Mini-DIP (N)
30°C/W
45°C/W
50°C/W
110°C/W
165°C/W
99°C/W
ORDERING GUIDE
Temperature
Range
Package
Option*
Model
AD834JN
AD834JR
AD834JR-REEL
AD834JR-REEL7
AD834AR
AD834AQ
AD834SQ/883B
AD834S CHIPS
0°C to +70°C
N-8
0°C to +70°C
SO-8
SO-8
SO-8
SO-8
Q-8
Q-8
DIE
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
*N = Plastic DIP; Q = Cerdip; SO = Small Outline IC (SOIC) Package.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Small Outline (SO-8) Package
Cerdip (Q) Package
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
BSC
؋
45؇ 0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
8؇
0؇
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
REV. C
–3–
AD834–Typical Characteristics
Figure 1. Mean-Square Output
vs. Frequency
Figure 3. Total Harmonic Distortion
vs. Frequency
Figure 2. AC Feedthrough
vs. Frequency
Figure 1. Figure 1 is a plot of the mean-square output versus
frequency for the test circuit of Figure 5. Note that the rising
response is due to package resonances.
By placing capacitors C3/C5 and C4/C6 across load resistors R1
and R2, a simple low-pass filter is formed, and the mean-square
value is extracted. The mean-square response can be measured
using a DVM connected across R1 and R2.
Figure 2. For frequencies above 1 MHz, ac feedthrough is
dominated by static nonlinearities in the transfer function and
the finite offset voltages. The offset voltages cause a small frac-
tion of the fundamental to appear at the output, and can be
nulled out.
Figure 3. THD data represented in Figure 3 is dominated by
the second harmonic, and is generated with 0 dBm input on the
ac input and +1 V on the dc input. For a given amplitude on the
ac input, THD is relatively insensitive to changes in the
dc input amplitude. Varying the ac input amplitude while
maintaining a constant dc input amplitude will affect THD
performance.
Figure 5. Bandwidth Test Circuit
Figure 4. Test Configuration for Measuring AC
Feedthrough and Total Harmonic Distortion
Figure 5. The squarer configuration shown in Figure 5 is used
to determine wideband performance because it eliminates the
need for (and the response uncertainties of) a wideband mea-
surement device at the output. The wideband output of a
squarer configuration is a fluctuating current at twice the input
frequency with a mean value proportional to the square of the
input amplitude.
Figure 6. Low Frequency Test Circuit
–4–
REV. C
AD834
BASIC OPERATION
Figure 7 is a functional equivalent of the AD834. There are
three differential signal interfaces: the voltage inputs X =
X1–X2 and Y = Y1–Y2, and the current output, W (see Figure
7) which flows in the direction shown when X and Y are posi-
tive. The outputs W1 and W2 each have a standing current of
typically 8.5 mA.
Figure 8. Basic Connections for Wideband Operation
impedance is quite high (about 25 kΩ), the input bias current of
typically 45 µA can generate significant offset voltages if not
compensated. For example, with a source and termination
resistance of 50 Ω (net source of 25 Ω) the offset would be
25 Ω × 45 µA = 1.125 mV. This can be almost fully cancelled by
including (in this example) another 25 Ω resistor in series with
the “unused” input (in Figure 8, either X1 or Y2). In order to
minimize crosstalk the input pins closest to the output (X1 and
Y2) should be grounded; the effect is merely to reverse the
phase of the X input and thus alter the polarity of the output.
Figure 7. AD834 Functional Block Diagram
The input voltages are first converted to differential currents
which drive the translinear core. The equivalent resistance of
the voltage-to-current (V-I) converters is about 285 Ω. This low
value results in low input related noise and drift. However, the
low full-scale input voltage results in relatively high nonlinearity
in the V-I converters. This is significantly reduced by the use of
distortion cancellation circuits which operate by Kelvin sensing
the voltages generated in the core—an important feature of the
AD834.
TRANSFER FUNCTION
The output current W is the linear product of input voltages
X and Y divided by (1 V)2 and multiplied by the “scaling
current” of 4 mA:
The current mode output of the core is amplified by a special
cascode stage which provides a current gain of nominally × 1.6,
trimmed during manufacture to set up the full-scale output cur-
rent of 4 mA. This output appears at a pair of open
collectors which must be supplied with a voltage slightly
above the voltage on Pin 6. As shown in Figure 8, this can be
arranged by inserting a resistor in series with the supply to this
pin and taking the load resistors to the full supply. With R3 =
60 Ω, the voltage drop across it is about 600 mV. Using two
50 Ω load resistors, the full-scale differential output voltage is
400 mV.
XY
W =
4mA
2
1V
(
)
Provided that it is understood that the inputs are specified in
volts, a simplified expression can be used:
W =(XY )4mA
Alternatively, the full transfer function can be written:
XY
1V 250 Ω
1
W =
×
The full bandwidth potential of the AD834 can only be realized
when very careful attention is paid to grounding and decou-
pling. The device must be mounted close to a high quality
ground plane and all lead lengths must be extremely short, in
keeping with UHF circuit layout practice. In fact, the AD834
shows useful response to well beyond 1 GHz, and the actual up-
per frequency in a typical application will usually be determined
by the care with which the layout is effected. Note that R4 (in
series with the –VS supply) carries about 30 mA and thus intro-
duces a voltage drop of about 150 mV. It is made large enough
to reduce the Q of the resonant circuit formed by the supply
lead and the decoupling capacitor. Slightly larger values can be
used, particularly when using higher supply voltages. Alterna-
tively, lossy RF chokes or ferrite beads on the supply leads may
be used.
When both inputs are driven to their clipping level of about
1.3 V, the peak output current is roughly doubled, to 8 mA,
but distortion levels will then be very high.
TRANSFORMER COUPLING
In many high frequency applications where baseband operation
is not required at either inputs or output, transformer coupling
can be used. Figure 9 shows the use of a center-tapped output
transformer, which provides the necessary dc load condition at
the outputs W1 and W2, and is designed to match into the de-
sired load impedance by appropriate choice of turns ratio. The
specific choice of the transformer design will depend entirely on
the application. Transformers may also be used at the inputs.
Center-tapped transformers can reduce high frequency distor-
tion and lower HF feedthrough by driving the inputs with
balanced signals.
Figure 8 shows the use of optional termination resistors at the
inputs. Note that although the resistive component of the input
REV. C
–5–
AD834
WIDEBAND MULTIPLIER CONNECTIONS
Where operation down to dc and a ground based output are
necessary, the configuration shown in Figure 11 can be used.
The element values were chosen in this example to result in a
full-scale output of 1 V at the load, so the overall multiplier
transfer function is
W = (X1–X2) (Y1–Y2)
where it is understood that the inputs and output are in volts. The
polarity of the output can be reversed simply by reversing either
the X or Y input.
Figure 9. Transformer—Coupled Output
A particularly effective type of transformer is the balun1 which is
a short length of transmission line wound on to a toroidal ferrite
core. Figure 10 shows this arrangement used to convert the
bal(anced) output to an un(balanced) one (hence the use of the
term). Although the symbol used is identical to that for a trans-
former, the mode of operation is quite different. In the first
place, the load should now be equal to the characteristic imped-
ance of the line (although this will usually not be critical for
short line lengths). The collector load resistors RC may also be
chosen to reverse terminate the line, but again this will only be
necessary when an electrically long line is used. In most cases,
RC will be made as large as the dc conditions allow, to minimize
power loss to the load. The line may be a miniature coaxial
cable or a twisted pair.
Figure 11. Sideband DC-Coupled Multiplier
The op amp should be chosen to support the desired output
bandwidth. The AD5539 is shown here, providing an overall
system bandwidth of 100 MHz. Many other choices are possible
where lower post multiplication bandwidths are acceptable. The
level shifting network places the input nodes of the op amp to
within a few hundred millivolts of ground using the recom-
mended balanced supplies. The output offset may be nulled by
including a 100 Ω trim pot between each of the lower pair of re-
sistors (3.74 kΩ) and the negative supply.
The pulse response for this circuit shown in Figure 12; the X in-
put was a pulse of 0 V to +1 V and the Y input was +1 V dc.
The transition times at the output are about 4 ns.
Figure 10. Using a Balun at the Output
It is important to note that the upper bandwidth limit of the
balun is determined only by the quality of the transmission line;
hence, it will usually exceed that of the multiplier. This is unlike
a conventional transformer where the signal is conveyed as a
flux in a magnetic core and is limited by core losses and leakage
inductance. The lower limit on bandwidth is determined by the
series inductance of the line, taken as a whole, and the load resis-
tance (if the blocking capacitors C are sufficiently large). In
practice, a balun can provide excellent differential-to-single-sided
conversion over much wider bandwidths than a transformer.
1For a good treatment of baluns, see “Transmission Line Transformers” by Jerry
Sevick; American Radio Relay League publication.
Figure 12. Pulse Response for the Circuit of Figure 11
–6–
REV. C
AD834
POWER MEASUREMENT (MEAN SQUARE AND RMS)
The AD834 is well suited to measurement of average power in
high frequency applications, connected either as a multiplier for
the determination of the V × I product, or as a squarer for use
with a single input. In these applications, the multiplier is fol-
lowed by a low-pass filter to extract the long term average value.
Where the bandwidth extends to several hundred megahertz, the
first pole of this filter should be formed by grounded capacitors
placed directly at the output pins W1 and W2. This pole can be
at a few kilohertz. The effective multiplication or squaring band-
width is then limited solely by the AD834, since the following
active circuitry is required to process only low frequency signals.
path to the second AD834. This increases the maximum input
capability to +15 dBm and improves the response flatness by
damping some of the resonances. The overall gain is unity; that
is, the output voltage is exactly equal to the rms value of the
input signal. The offset potentiometer at the AD834 outputs ex-
tends the dynamic range, and is adjusted for a dc output of
125.7 mV when a 1 MHz sinusoidal input at –5 dBm is applied.
Additional filtering is provided; the time constants were chosen
to allow operation down to frequencies as low as 1 kHz and to
provide a critically damped envelope response, which settles
typically within 10 ms for a full-scale input (and proportionally
slower for smaller inputs). The 5 µF and 0.1 µF capacitors may
be scaled down to reduce response time if accurate rms opera-
tion at low frequencies is not required. The output op amp must
be specified to accept a common-mode input near its supply.
Note that the output polarity may be inverted by replacing the
NPN transistor with a PNP type.
(Refer to Figure 5 test configuration.) Using the device as a
squarer the wideband output in response to a sinusoidal stimu-
lus is a raised cosine:
sin2 ωt = (1 – cos 2 ωt) /2
Recall here that the full-scale output current (when full-scale
input voltages of 1 V are applied to both X and Y) is 4 mA. In a
50 Ω system, a sinusoid power of +10 dBm has a peak value of
1 V. Thus, at this drive level the peak output voltage across the
differential 50 Ω load in the absence of the filter capacitors
would be 400 mV (that is, 4 mA × 50 Ω × 2), whereas the
average value of the raised cosine is only 200 mV. The averaging
configuration is useful in evaluating the bandwidth of the
AD834, since a dc voltage is easier to measure than a wideband,
differential output. In fact, the squaring mode is an even more
critical test than the direct measurement of the bandwidth of
either channel taken independently (with a dc input on the
nonsignal channel), because the phase relationship between the
two channels also affects the average output. For example, a
time delay difference of only 250 ps between the X and Y chan-
nels would result in zero output when the input frequency is
1 GHz, at which frequency the phase angle is 90 degrees and
the intrinsic product is now between a sine and cosine function,
which has zero average value.
Figure 13. Connections for Wideband RMS Measurement
FREQUENCY DOUBLER
Figure 14 shows another squaring application. In this case, the
output filter has been removed and the wideband differential
output is converted to a single sided signal using a “balun,”
which consists of a length of 50 Ω coax cable fed through a fer-
rite core (Fair-Rite type 2677006301). No attempt is made to
reverse terminate the output. Higher load power could be
achieved by replacing the 50 Ω load resistors by ferrite bead
inductors. The same precautions should be observed with re-
gard to PC board layout as recommended above. The output
spectrum shown in Figure 15 is for an input power of +10 dBm
at a frequency of 200 MHz. The second harmonic component
at 400 MHz has an output power of –15 dBm. Some feed-
through of the fundamental occurs: it is 15 dBs below the main
output. It is believed that improvements in the design of the
balun would reduce this feedthrough. A spurious output at
600 MHz is also present, but it is 30 dBs below the main out-
put. At an input frequency of 100 MHz, the measured power
level at 200 MHz is –16 dBm, while the fundamental feed-
through is reduced to 25 dBs below the main output; at an
output of 600 MHz the power is –11 dBm and the third
harmonic at 900 MHz is 32 dBs below the main output.
The physical construction of the circuitry around the IC is criti-
cal to realizing the bandwidth potential of the device. The input is
supplied from an HP8656A signal generator (100 kHz to
990 MHz) via an SMA connector and terminated by an HP436A
power meter using an HP8482A sensor head connected via a
second SMA connector. Since neither the generator nor the
sensor provide a dc path to ground, a lossy 1 µH inductor L1,
formed by a 22-gauge wire passing through a ferrite bead (Fair-
Rite type 2743001112) is included. This provides adequate
impedance down to about 30 MHz. The IC socket is mounted
on a ground plane, with a clear area in the rectangle formed by
the pins. This is important, since significant transformer action
can arise if the pins pass through individual holes in the board;
this has been seen to cause an oscillation at 1.3 GHz in improp-
erly constructed test jigs. The filter capacitors must be
connected
directly to the same point on the ground plane via the shortest
possible leads. Parallel combinations of large and small capaci-
tors are used to minimize the impedance over the full frequency
range. (Refer to Figure 1 for mean-square response for the
AD834 in cerdip package, using the configuration of Figure 5.)
To provide a square-root response and thus generate the rms
value at the output, a second AD834, also connected as a
squarer, can be used, as shown in Figure 13. Note that an at-
tenuator is inserted both in the signal input and in the feedback
REV. C
–7–
AD834
Figure 14. Frequency Doubler Connections
Figure 15. Output Spectrum for Configuration of Figure 14
WIDEBAND THREE SIGNAL MULTIPLIER/DIVIDER
Two AD834s and a wideband op amp can be connected to
make a versatile multiplier/divider having the transfer function
(X1– X2)(Y1–Y2)
W =
+ Z
(U1–U2)
with a denominator range of about 100:1. The denominator in-
put U = U1–U2 must be positive and in the range 100 mV to
10 V; X, Y and Z inputs may have either polarity. Figure 16
shows a general configuration which may be simplified to suit a
particular application. This circuit accepts full-scale input volt-
ages of 10 V, and delivers a full-scale output voltage of 10 V.
The optional offset trim at the output of the AD834 improves
the accuracy for small denominator values. It is adjusted by
nulling the output voltage when the X and Y inputs are zero and
U = +100 mV.
Figure 16. Wideband Three Signal Multiplier/Divider
can be connected to ground through a single resistor, equal to
the parallel sum of the resistors in the attenuator section. The
full-scale input levels on X, Y and U can be adapted to any full-
scale voltage down to 1 V by altering the attenuator ratios.
Note, however, that precautions must be taken if the attenuator
ratio from the output of A3 back to the second AD834 (A2) is
lowered. First, the HF compensation limit of the AD840 may be
exceeded if the negative feedback factor is too high. Second, if
the attenuated output at the AD834 exceeds its clipping level of
1.3 V, feedback control will be lost and the output will sud-
denly jump to the supply rails. However, with these limitations
understood, it will be possible to adapt the circuit to smaller
full-scale inputs and/or outputs, and for use with lower supply
voltages.
The AD840 is internally compensated to be stable without the
use of any additional HF compensation. As the input U is re-
duced, the bandwidth falls because the feedback around the op
amp is proportional to the input U.
This circuit may be modified in several ways. For example, if
the differential input feature is not needed, the unused input
–8–
REV. C
相关型号：
AD834JRZ-REEL7
IC ANALOG MULTIPLIER OR DIVIDER, 500 MHz BAND WIDTH, PDSO8, SOIC-8, Analog Computational Function
ADI
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