AD8345AREZ-REEL7 [ADI]
140MHz - 1000MHz RF/MICROWAVE QUADRAPHASE MODULATOR, MO-153ABT, TSSOP-16;
| 型号： | AD8345AREZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 140MHz - 1000MHz RF/MICROWAVE QUADRAPHASE MODULATOR, MO-153ABT, TSSOP-16 射频 微波 |
| 文件： | 总20页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
140 MHz to 1000 MHz
Quadrature Modulator
AD8345
FEATURES
FUNCTIONAL BLOCK DIAGRAM
140 MHz to 1000 MHz operating frequency
+2.5 dBm P1dB @ 800 MHz
−155 dBm/Hz noise floor
0.5 degree RMS phase error (IS95)
0.2 dB amplitude balance
Single 2.7 V to 5.5 V supply
AD8345
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QBBP
QBBN
COM3
COM3
VPS2
IBBP
IBBN
COM3
COM1
LOIN
LOIP
+
Pin-compatible with AD8346 and AD8349
16-lead TSSOP_EP package
PHASE
SPLITTER
VOUT
COM2
COM3
APPLICATIONS
VPS1
ENBL
Cellular communication systems
W-CDMA/CDMA/GSM/PCS/ISM transceivers
Fixed broadband access systems LMDS/MMDS
Wireless LAN
BIAS
Figure 1.
Wireless local loop
Digital TV/CATV modulators
Single sideband upconverter
PRODUCT DESCRIPTION
APPLICATIONS
The AD8345 is a silicon RFIC quadrature modulator, designed
for use from 140 MHz to 1000 MHz. Its excellent phase
accuracy and amplitude balance enable the high performance
direct modulation of an IF carrier.
The AD8345 modulator can be used as the IF transmit
modulator in digital communication systems such as GSM and
PCS transceivers. It can also directly modulate an LO signal to
produce QPSK and various QAM formats for 900 MHz
communication systems as well as digital TV and CATV
systems.
The AD8345 accurately splits the external LO signal into two
quadrature components through the polyphase phase splitter
network. The I and Q LO components are mixed with the
baseband I and Q differential input signals. Finally, the outputs
of the two mixers are combined in the output stage to provide a
single-ended 50 Ω drive at VOUT.
Additionally, this quadrature modulator can be used with direct
digital synthesizers in hybrid phase-locked loops to generate
signals over a wide frequency range with millihertz resolution.
The AD8345 modulator is supplied in a 16-lead TSSOP_EP
package. Its performance is specified over a −40°C to +85°C
temperature range. This device is fabricated on Analog Devices’
advanced silicon bipolar process.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD8345
TABLE OF CONTENTS
Features .............................................................................................. 1
Basic Connections.......................................................................... 12
LO Drive...................................................................................... 12
LO Frequency Range ................................................................. 12
Baseband I and Q Channel Drive ............................................ 13
Reduction of LO Leakage.......................................................... 13
Single-Ended I and Q Drive...................................................... 13
RF Output.................................................................................... 14
Application with TxDAC®......................................................... 14
Soldering Information ............................................................... 15
Evaluation Board........................................................................ 15
Characterization Setups................................................................. 17
SSB Setup..................................................................................... 17
Modulated Waveform Setup ..................................................... 18
CDMA IS95................................................................................. 18
WCDMA 3GPP .......................................................................... 18
GSM ............................................................................................. 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Description......................................................................... 1
Applications....................................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Equivalent Circuits......................................................................... 10
Circuit Description......................................................................... 11
Overview...................................................................................... 11
LO Interface................................................................................. 11
Differential Voltage-to-Current Converter............................. 11
Mixers .......................................................................................... 11
Differential-to-Single-Ended Converter ................................. 11
Bias ............................................................................................... 11
REVISION HISTORY
12/05—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Ordering Guide .......................................................... 19
4/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Change to Part Name.........................................................Universal
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 19
7/01—Revision 0: Initial Version
Rev. B | Page 2 of 20
AD8345
SPECIFICATIONS
VS = 5 V; LO = −2 dBm @ 800 MHz; 50 Ω source and load impedances; I and Q inputs 0.7 V 0.3 V on each side for a 1.2 V p-p
differential input, I and Q inputs driven in quadrature @ 1 MHz baseband frequency. TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Min Typ
Max
Unit
Test Conditions/Comments
RF OUTPUT
Operating Frequency1
Output Power
140
0.5
0.5
1000 MHz
dBm
140 MHz
220 MHz
800 MHz
dBm
−3
−1
2.5
−155
0.5
0.2
+2
dBm
dBm
dBm/Hz
Degree rms
dB
Output P1dB
Noise Floor
20 MHz offset from LO, all BB inputs at 0.7 V
CDMA IS95 setup (see Figure 38)
CDMA IS95 setup (see Figure 38)
Quadrature Error
I/Q Amplitude Balance
LO Leakage
−41
−40
−42
−33
−48
−42
−52
−60
25
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBm
dBm
dB
140 MHz
220 MHz
800 MHz
140 MHz
220 MHz
800 MHz
−33
Sideband Rejection
−40
−34
Third Order Distortion
Second Order Distortion
Equivalent Output IP3
Equivalent Output IP2
Output Return Loss (S22)
RESPONSE TO CDMA IS95
BASEBAND SIGNALS
ACPR
59
−20
See Figure 38
−72
1.3
dBc
%
EVM
Rho
0.9995
LO INPUT
LO Drive level
LOIP Input Return Loss (S11)2
−10
−2
0
dBm
−5
−9
dB
dB
No termination on LOIP, LOIN at ac ground
50 Ω terminating resistor, differential drive via balun
BASEBAND INPUTS
Input Bias Current
Input Capacitance
DC Common Level
Bandwidth (3 dB)
ENABLE
10
2
0.7
80
μA
pF
V
0.6
0.8
MHz
Full power (0.7 V 0.3 V on each input, see Figure 4)
Turn-On
Turn-Off
ENBL High Threshold (Logic 1)
ENBL Low Threshold (Logic 0)
POWER SUPPLIES
Voltage
2.5
1.5
+VS/2
+VS/2
μs
μs
V
Enable high to output within 0.5 dB of final value
Enable low to supply current dropping below 2 mA
V
2.7
50
5.5
78
V
mA
μA
Current Active
Current Standby
65
70
1 For information on operation below 140 MHz, see Figure 29.
2 See the LO Interface section for more details on input matching.
Rev. B | Page 3 of 20
AD8345
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage VPS1, VPS2
Input Power LOIP, LOIN (re 50 Ω)
IBBP, IBBN, QBBP, QBBN
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
5.5 V
10 dBm
0 V, 2.5 V
500 mW
30°C/W
95°C/W
150°C
−40°C to +85°C
−65°C to +150°C
300°C
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)
θJA (Exposed Paddle not Soldered Down)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering 60 sec)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada-
tion or loss of functionality.
Rev. B | Page 4 of 20
AD8345
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IBBP
IBBN
COM3
COM1
LOIN
LOIP
QBBP
QBBN
COM3
COM3
VPS2
AD8345
TOP VIEW
(Not to Scale)
VOUT
COM2
COM3
VPS1
ENBL
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
Equivalent Circuit
1, 2
IBBP, IBBN
I Channel Baseband Differential Input Pins. These high impedance inputs should be
dc-biased to approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p on each
pin (0.4 V to 1 V). This gives a differential drive of 1.2 V p-p. Inputs are not self-biasing, so
external biasing circuitry must be used in ac-coupled applications.
Circuit A
3, 9, 13, 14 COM3
Ground Pin for Input V-to-I Converters and Mixer Core.
Ground Pin for the LO Phase Splitter and LO Buffers.
4
COM1
5, 6
LOIN, LOIP
Differential LO Drive Pins. Internal dc bias (approximately 1.8 V @ VS = 5 V) is supplied.
Pins must be ac-coupled. Single-ended or differential drive is permissible.
Circuit B
7
VPS1
Power Supply Pin for the Bias Cell and LO Buffers. This pin should be decoupled using
local 1000 pF and 0.01 μF capacitors.
8
ENBL
COM2
VOUT
VPS2
Enable Pin. A high level enables the device; a low level puts the device in sleep mode.
Ground Pin for the Output Stage of Output Amplifier.
50 Ω DC-Coupled RF Output. Pin should be ac-coupled.
Power Supply Pin for Baseband Input Voltage to Current Converters and Mixer Core.
This pin should be decoupled using local 1000 pF and 0.01 μF capacitors.
Circuit C
Circuit D
10
11
12
15, 16
QBBN, QBBP Q Channel Baseband Differential Input Pins. Inputs should be dc-biased to approxi-
mately 0.7 V. Nominal characterized ac swing is 0.6 V p-p on each pin (0.4 V to 1 V). This
gives a differential drive level of 1.2 V p-p. Inputs are not self-biasing, so external biasing
circuitry must be used in ac-coupled applications.
Circuit A
Rev. B | Page 5 of 20
AD8345
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–2
T
= –40°C
–2
A
V
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
S
–4
–6
–4
–6
–8
T
= +25°C
A
–10
–12
–14
–16
–18
–20
–8
–10
–12
–14
–16
T
= +85°C
A
V
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
S
250 300 350 400 450 500 550 600 650 700 750 800 850 900 9501000
250 300 350 400 450 500 550 600 650 700 750 800 850 900 9501000
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 3. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (FLO
(I and Q Inputs Driven in Quadrature at Baseband Frequency (FBB) = 1 MHz;
TA = 25°C)
)
Figure 6. SSB Output 1 dB Compression Point (OP1dB) vs. FLO
(VS = 2.7 V, LO Level = −2 dBm,
I and Q Inputs Driven in Quadrature, FBB = 1 MHz)
4.0
1.0
0.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
–0.5
0.0
T
= +85°C
A
–0.5
V
= 2.7V, 5V DIFFERENTIAL INPUT = 200mV p-p
S
T
= +25°C
A
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
T
A
= –40°C
V
= 5V DIFFERENTIAL INPUT = 1.2V p-p
S
250 300 350 400 450 500 550 600 650 700 750 800 850 900 9501000
LO FREQUENCY (MHz)
0.1
1
10
100
BASEBAND FREQUENCY (MHz)
Figure 7. SSB Output 1 dB Compression Point (OP1dB) vs. FLO
(VS = 5 V, LO Level = −2 dBm,
Figure 4. I and Q Input Bandwidth
(TA = 25°C, FLO = 800 MHz, LO Level = −2 dBm,
I and Q Inputs Driven in Quadrature)
I and Q Inputs Driven in Quadrature, FBB = 1 MHz)
0
–2
–40
V
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
–41
–42
–43
–44
–45
–46
–47
–48
–49
–50
S
–4
V
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
S
–6
–8
–10
–12
–14
–16
–18
–20
–22
–24
–26
V
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
S
V
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
S
–40
–20
0
20
40
60
80
250 300 350 400 450 500 550 600 650 700 750 800 850 900 9501000
LO FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 5. SSB POUT vs. Temperature
(FLO = 800 MHz, LO Level = −2 dBm, FBB = 1 MHz,
I and Q Inputs Driven in Quadrature)
Figure 8. Carrier Feedthrough vs. FLO
(LO Level = −2 dBm, TA = 25°C)
Rev. B | Page 6 of 20
AD8345
–30
–32
–34
–36
–38
–40
–42
–44
–46
–48
–50
–26
–28
–30
–32
–34
–36
–38
–40
–42
–44
V
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
S
V
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
S
V
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
S
V
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
S
–40
–20
0
20
40
60
80
0
5
10
15
20
25
30
35
40
45
50
TEMPERATURE (°C)
BASEBAND FREQUENCY (MHz)
Figure 9. Carrier Feedthrough vs. Temperature
(FLO = 800 MHz, LO Level = −2 dBm)
Figure 12. Sideband Suppression vs. FBB
(TA = 25°C, FLO = 800 MHz, LO Level = −2 dBm,
I and Q Inputs Driven in Quadrature)
30
28
26
24
22
20
18
16
14
12
10
8
–35
–36
–37
–38
–39
–40
–41
–42
–43
–44
–45
T = +85
T = –40
V
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
S
V
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
S
6
4
2
0
–86
–82
–78
–74
–70
–66
–62
–58
–54
–50
–40
–20
0
20
40
60
80
CARRIER FEEDTHROUGH (dBm)
TEMPERATURE (°C)
Figure 10. Carrier Feedthrough Distribution at Temperature Extremes After
Feedthrough Nulled to <−65 dBm at TA = 25°C
Figure 13. Sideband Suppression vs. Temperature
(FLO = 800 MHz, LO Level = −2 dBm, FBB = 1 MHz,
I and Q Inputs Driven in Quadrature)
(FLO = 800 MHz, LO Level = −2 dBm)
–30
–32
–34
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
V
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
S
V
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
S
–36
–38
–40
–42
–44
–46
–48
–50
V
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
S
V
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
S
250 300 350 400 450 500 550 600 650 700 750 800 850 900 9501000
LO FREQUENCY (MHz)
0
5
101
52
02
53
03
54
04
55
0
BASEBAND FREQUENCY (MHz)
Figure 11. Sideband Suppression vs. FLO
(TA = 25°C, LO Level = −2 dBm, FBB = 1 MHz,
I and Q Inputs Driven in Quadrature)
Figure 14. Third Order Distortion vs. FBB
(TA = 25°C, FLO = 800 MHz, LO Level = −2 dBm,
I and Q Inputs Driven in Quadrature)
Rev. B | Page 7 of 20
AD8345
80
75
70
65
60
55
50
45
40
–45
–50
–55
–60
–65
–70
–75
–80
V
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
S
V
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
S
V
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
S
V
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
S
–40
–20
0
20
40
C)
60
80
–40
–20
0
20
40
C)
60
80
TEMPERATURE (
°
TEMPERATURE (
°
Figure 18. Power Supply Current vs. Temperature
Figure 15. Third Order Distortion vs. Temperature
(FLO = 800 MHz, LO Level = −2 dBm, FBB = 1 MHz,
I and Q Inputs Driven in Quadrature)
1GHz
SMITH CHART
–2
NORMALIZED
TO 50Ω
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–4
WITH 50Ω
–6
–8
SSB P
OUT
–10
–12
–14
–16
–18
–20
–22
–24
–26
250MHz
THIRD ORDER DISTORTION
LOIN NO BALUN
OR TERMINATION
0.0
0.5
1.0
1.5
2.0
2.5
3.0
WITH 100Ω
1GHz
BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)
Figure 16. Third Order Distortion and SSB POUT vs. Baseband Differential Input
Voltage (TA = 25°C, FLO = 800 MHz, LO Level = −2 dBm, FBB = 1 MHz, VS = 2.7 V)
Figure 19. Smith Chart of LOIN Port S11 (LOIP Pin AC-Coupled to Ground);
Curves with Balun and External Termination Resistors Also Shown
(VS = 5 V, TA = 25°C)
4
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
0
2
0
–5
–2
SSB P
OUT
–4
–6
–10
–15
–20
–8
–10
–12
–14
–16
–18
–20
–22
THIRD ORDER DISTORTION
V
S
= 2.7V
–25
–30
V
S
= 5V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
250 300 350 400 450 500 550 600 650 700 750 800 850 900 9501000
BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)
FREQUENCY (MHz)
Figure 17. Third Order Distortion and SSB POUT vs. Baseband Differential Input
Voltage (TA = 25°C, FLO = 800 MHz, LO Level = −2 dBm, FBB = 1 MHz, VS = 5 V)
Figure 20. Return Loss (S22) of VOUT Output (TA = 25°C)
Rev. B | Page 8 of 20
AD8345
–150
–151
–152
–153
–154
–155
–156
–157
–158
–159
–160
–36
–38
–40
–42
–44
–46
–48
–50
V
= 5V
S
V
= 5.5V
S
–10 –9 –8 –7 –6 –5 –4 –3 –2 –1
0
1
2
–10 –9 –8 –7 –6 –5 –4 –3 –2 –1
0
1
2
LO LEVEL (dBm)
LO LEVEL (dBm)
Figure 21. Noise Floor vs. LO Input Power
(TA = 25°C, FLO = 800 MHz, VS = 5 V, All I and Q Inputs Are DC-Biased to 0.7 V)
Noise Measured at 20 MHz Offset from Carrier
Figure 22. LO Feedthrough vs. LO Input Power
(TA = 25°C, LO = 800 MHz, VS = 5.5 V)
Rev. B | Page 9 of 20
AD8345
EQUIVALENT CIRCUITS
VPS2
VPS2
BUFFER
TO MIXER
CORE
100kΩ
100kΩ
100kΩ
ENBL
INPUT
TO BIAS FOR
STARTUP/
SHUTDOWN
CURRENT
MIRROR
Figure 25. Circuit C
Figure 23. Circuit A
VPS2
VPS1
40Ω
LOIN
LOIP
PHASE
SPLITTER
CONTINUES
VOUT
40Ω
Figure 24. Circuit B
Figure 26. Circuit D
Rev. B | Page 10 of 20
AD8345
CIRCUIT DESCRIPTION
OVERVIEW
DIFFERENTIAL VOLTAGE-TO-CURRENT
CONVERTER
The AD8345 can be divided into the following sections: local
oscillator (LO) interface, mixer, differential voltage-to-current
(V-to-I) converter, differential-to-single-ended (D-to-S)
converter, and bias. A block diagram of the part is shown in
Figure 27.
In this circuit, each baseband input pin is connected to an op amp
driving a transistor connected as an emitter follower. A resistor
between the two emitters maintains a varying current proportional
to the differential input voltage through the transistor. These
currents are fed to the two mixers in differential form.
LOIP
LOIN
PHASE
SPLITTER
MIXERS
There are two double-balanced mixers, one for the in-phase
channel (I channel) and one for the quadrature channel
(Q channel). Each mixer uses the Gilbert-cell design with four
cross-connected transistors. The bases of the transistors are
driven by the LO signal of the corresponding channel. The
output currents from the two mixers are summed together in
two load resistors. The signal developed across the load resistors
is sent to the differential-to-single-ended converter.
IBBP
IBBN
Σ
OUT
QBBP
QBBN
Figure 27. AD8345 Block Diagram
The LO interface generates two LO signals at 90° of phase
difference with each other, to drive two mixers in quadrature.
Baseband signals are converted into current form in the
differential V-to-I converters, feeding into the two mixers. The
outputs of the mixers are combined to feed the differential-to-
single-ended converter, which provides a 50 Ω output interface.
Bias currents to each section are controlled by the enable
(ENBL) signal. A detailed description of each section follows.
DIFFERENTIAL-TO-SINGLE-ENDED CONVERTER
The differential-to-single-ended converter consists of two
emitter followers driving a totem-pole output stage whose
output impedance is established by the emitter resistors in the
output transistors. The output of this stage is connected to the
output pin (VOUT).
BIAS
LO INTERFACE
A band gap reference circuit based on the Δ-VBE principle
generates the proportional-to-absolute temperature (PTAT) as
well as temperature-stable currents used by the different
sections as references. When the band gap reference is disabled
by pulling down the voltage at the ENBL pin, all other sections
are shut off accordingly.
The LO interface consists of interleaved stages of polyphase
phase splitters and buffer amplifiers. The polyphase phase
splitter contains resistors and capacitors connected in a circular
manner to split the LO signal into I and Q paths in precise
quadrature with each other. The signal on each path goes
through a buffer amplifier to make up for the loss and high
frequency roll-off. The two signals then go through another
polyphase network to enhance the quadrature accuracy. The
broad operating frequency range (140 MHz to 1000 MHz) is
achieved by staggering the RC time constants of each stage of
the phase splitters. The outputs of the second phase splitter are
fed into the driver amplifiers for the mixers’ LO inputs.
Rev. B | Page 11 of 20
AD8345
BASIC CONNECTIONS
IP
AD8345
1
2
3
4
5
6
7
8
QP
QN
16
QBBP
IBBP
IBBN
COM3
COM1
LOIN
LOIP
QBBN 15
IN
14
13
12
11
10
9
COM3
COM3
VPS2
C6
1000pF
5
1
2
3
+V
LO
S
C1
1000pF
C2
0.01μF
T1
R1
50Ω
C7
1000pF
ETC1-1-13
VOUT
COM2
COM3
VOUT
4
C5
1000pF
VPS1
ENBL
+V
S
C4
C3
0.01μF
1000pF
Figure 28. Basic Connections
The basic connections for operating the AD8345 are shown in
Figure 28. A single power supply of between 2.7 V and 5.5 V is
applied to the VPS1 pin and the VPS2 pin. A pair of ESD
protection diodes is connected internally between the VPS1 pin
and the VPS2 pin so these must be tied to the same potential.
Both pins should be individually decoupled using 1000 pF and
0.01 μF capacitors, located as close as possible to the device. For
normal operation, the enable pin (ENBL) must be pulled high.
The turn-on threshold for ENBL is VS/2. COM1 to COM3
should all be tied to the same low impedance ground plane.
LO FREQUENCY RANGE
The frequency range on the LO input is limited by the internal
quadrature phase splitter. The phase splitter generates drive
signals for the internal mixers which are 90° out of phase
relative to one another.
Outside of the specified LO frequency range of 140 MHz to 1 GHz,
this quadrature accuracy degrades, resulting in decreased sideband
suppression. See Figure 11 for a plot of sideband suppression vs.
LO frequency from 250 MHz to 1 GHz. Figure 29 shows the
sideband suppression of a typical device from 70 MHz to 300 MHz.
LO DRIVE
0
In Figure 28, a 50 Ω resistor to ground combines with the
device’s high input impedance to provide an overall input
impedance of approximately 50 Ω (see Figure 19 for a plot of
LO port input impedance). For maximum LO suppression at
the output, a differential LO drive is recommended. In
Figure 28, this is achieved using a balun (M/A-COM part
number ETC1-1-13).
–5
V
= 5V, DIFFERENTIAL INPUT = 1.2V
S
–10
–15
–20
–25
–30
–35
–40
–45
–50
The outputs of the balun are ac-coupled to the LO inputs, which
have a bias level of approximately 1.8 V dc. An LO drive level of
−2 dBm is recommended for lowest output noise. Higher levels
degrade linearity while lower levels tend to increase the noise
floor slightly. For example, reducing the LO power from −2 dBm
to −10 dBm increases the noise floor by approximately 0.3 dB
(see Figure 21).
40 60 80 100 120 140 160 180 200 220 240 260 280 300
LO FREQUENCY (MHz)
Figure 29. Typical Lower Frequency Sideband Suppression Performance
The LO input pins can be driven single-ended at the expense of
slightly higher LO leakage. LOIN is ac-coupled to ground using
a capacitor and LOIP is driven through a coupling capacitor
from a (single-ended) 50 Ω source. (This scheme could also be
reversed with the drive signal being applied to LOIN.)
Rev. B | Page 12 of 20
AD8345
The procedure for reducing the LO feedthrough is simple. In
BASEBAND I AND Q CHANNEL DRIVE
order to isolate the LO in the output spectrum, a single
sideband configuration is recommended (set I and Q signals to
sine and cosine waves at, for example, 100 kHz; set LO to
The I channel and Q channel baseband inputs should be driven
differentially. This is convenient as most modern high-speed
DACs have differential outputs. For optimal performance at
VS = 5 V, the drive signal should be a 1.2 V p-p differential
signal with a bias level of 0.7 V; that is, each input should swing
from 0.4 V to 1 V. If the AD8345 is being run on a lower supply
voltage, then the peak-to-peak voltage on the I and Q channel
inputs must be reduced to avoid input clipping. For example, at
a supply voltage of 2.7 V, a 200 mV p-p differential drive is
recommended. This results in a corresponding reduction in
output power (see Figure 3). The I and Q inputs have a large
input bandwidth of approximately 80 MHz. At lower baseband
input levels, the input bandwidth increases (see Figure 4).
F
RF − 100 kHz). An offset voltage is applied from the I DAC
until the LO leakage reaches a trough. With this offset level
held, an offset voltage is applied to the Q DAC until a (lower)
trough is reached.
LO leakage compensation holds up well over temperature.
Figure 10 shows the effect of temperature on LO leakage after
compensation at ambient.
Compensated LO leakage degrades somewhat as the frequency
is moved away from the frequency at which the compensation
was performed. This is due to the effects of LO to RF output
leakage, which is not a result of offsets on the I and Q inputs.
If the baseband signal has a high peak-to-average ratio (such as
CDMA or WCDMA), then the rms signal strength must be
backed off from this peak level in order to prevent clipping of
the signal peaks.
SINGLE-ENDED I AND Q DRIVE
Where only single-ended I and Q signals are available, a
differential amplifier such as the AD8132 or AD8138 can be
used to generate the required differential drive signal for the
AD8345.
Clipping of signal peaks tends to increase signal leakage into
adjacent channels. Backing off the I and Q signal strength, in
the manner recommended, reduces the output power by a
corresponding amount. This also applies to multicarrier
applications where the per-carrier output power is lower by
3 dB for each doubling of the number of output carriers.
Although most DACs have differential outputs, using a single-
ended, low-pass filter between the dual DAC and the I and Q
inputs can be more desirable from the perspective of
component count and cost. As a result, the output signal from
the filter must be converted back to differential mode and
possibly be rebiased to 0.7 V common mode.
The I and Q inputs have high input impedances because they
connect directly to the bases of PNP transistors. If a dc-coupled
filter is being used between a DAC and the modulator inputs,
then the filter must be terminated with the appropriate
resistance. If the filter is differential, then the termination
resistor should be connected across the I and Q differential
inputs.
Figure 30 shows a circuit that converts a ground-referenced,
single-ended signal to a differential signal and adds the required
0.7 V bias voltage. Two AD8132 differential op amps configured
for unity gain are used. With a 50 Ω input impedance, this
circuit is configured to accept a signal from a 50 Ω source (for
example, a low-pass filter). The input impedance can be easily
changed by replacing the 49.9 Ω shunt resistor (and the
corresponding 24.9 Ω resistor on the inverting input) with the
appropriate value. The required dc-bias level is conveniently
added to the signal by applying 0.7 V to the VOCM pins of the
differential amplifiers.
REDUCTION OF LO LEAKAGE
Because the I and Q signals are being effectively multiplied with
the LO, any internal offset voltages on these inputs result in
leakage of the LO. The nominal LO leakage of −42 dBm, which
results from these internal offset voltages, can be reduced further
by applying offset compensation voltages on the I and Q inputs.
(Note that LO feedthrough is reduced by varying the differential
offset voltages on the I and Q inputs, not by varying the nominal
bias level of 0.7 V.) The reduction is easily accomplished by
programming (and then storing) the appropriate DAC offset
code. This does, however, require dc coupling the path from the
DAC to the I and Q inputs. (DC coupling is also advantageous
from the perspective of I and Q input biasing if the DAC is
capable of delivering a bias level of 0.7 V.)
Differential amplifiers, such as the AD8132 and AD8138, can
also be used to implement active filters. For more information
on this topic, refer to the data sheets of these devices.
Rev. B | Page 13 of 20
AD8345
+5V
10kΩ
+
0.1μF
10μF
0.01μF
1000pF
1000pF
0.01μF
1.5kΩ
348Ω
348Ω
I
8
2
3
IN
5
49.9Ω
VPS1 VPS2
AD8132
IBBP
0.1μF
4
348Ω
24.9Ω
1
6
VOUT
IBBN
Σ
348Ω
0.1μF
LOIP
LOIN
10μF
–5V
+5V
+
PHASE
SPLITTER
QBBP
QBBN
+
AD8345
0.1μF
10μF
348Ω
COM1 COM2 COM3
348Ω
3
8
2
Q
IN
5
49.9Ω
AD8132
0.1μF
4
348Ω
24.9Ω
1
6
+
348Ω
10μF
0.1μF
–5V
Figure 30. Single-Ended 1Q Drive Circuit
Note that this circuit assumes that the single-ended I and Q
signals are ground-referenced. Any differential dc-offsets result
in increased LO leakage at the output of the AD8345.
APPLICATION WITH TxDAC®
Figure 31 shows the AD8345 driven by the AD9761 TxDAC.
(Any of the devices in the Analog Devices’ TxDAC family can
also be used in this application.)
It is possible to drive the baseband inputs with a single-ended
signal biased to 0.7 V, with the unused inputs being biased to a
dc level of 0.7 V. However, this mode of operation is not recom-
mended because any dc level difference between the bias level
of the drive signal and the dc level on the unused input
(including the effect of temperature drift) results in increased
LO leakage. In addition, the maximum output power is reduced
by 6 dB.
The I and Q DACs generate differential output currents of 0 mA
to 10 mA and 10 mA to 0 mA, respectively. The combination of
140 Ω resistors shunted to ground off each DAC output, along
with 210 Ω resistors shunted between each differential DAC
pair, produces a baseband signal into the AD8345 I and Q
inputs that has a differential peak-to-peak swing of 1.2 V with a
dc common-mode bias of 700 mV.
RF OUTPUT
The RF output is designed to drive a 50 Ω load but should be ac
coupled as shown in Figure 28. If the I and Q inputs are driven
in quadrature by 1.2 V p-p signals, then the resulting output
power is approximately −1 dBm (see Figure 3). The RF output
impedance is very close to 50 Ω. As a result, no additional
matching circuitry is required if the output is driving a 50 Ω
load.
Rev. B | Page 14 of 20
AD8345
DVDD
DCOM
AVDD
VPS1
VPS2
IOUTA
IOUTB
IBBP
IBBN
"I"
DAC
LATCH
"I"
2⋅
210Ω
VOUT
Σ
140Ω
140Ω
DAC
DATA
INPUTS
AD9761
2⋅
LOIP
LOIN
PHASE
SPLITTER
QOUTA
QOUTB
QBBP
QBBN
LATCH
"Q"
"Q"
DAC
210Ω
SELECT
WRITE
MUX
CONTROL
140Ω
140Ω
AD8345
CLOCK
SLEEP
FS ADJ
REFIO
R
2kΩ
SET
0.1μF
Figure 31. AD8345/TxDAC Interface
The board is powered by a single supply (VS) in the range 2.7 V
to 5.5 V. The power supply is decoupled by 0.01 μF and 1000 pF
capacitors. The circuit closely follows the basic connection
schematic with SW1 in Position B. If SW1 is in Position A, the
enable pin (ENBL) is pulled to ground by a 10 kΩ resistor, and
the device is in its power-down mode.
SOLDERING INFORMATION
The AD8345 is packaged in a 16-lead TSSOP_EP package. For
optimum thermal conductivity, the exposed pad can be
soldered to the exposed metal of a ground plane. This results in
a junction-to-air thermal impedance (θJA) of 30°C/W. However,
soldering is not necessary for safe operation. If the exposed pad
is not soldered down, then the θJA is equal to 95°C/W.
All connectors are SMA-type. The I and Q inputs are dc-coupled to
allow a direct connection to a dual DAC with differential outputs.
Resistor pads are provided in case termination at the I and Q inputs
is required. The local oscillator input (LO) is terminated to approxi-
mately 50 Ω with an external 50 Ω resistor to ground. A 1:1 wide-
band transformer (ETC1-1-13) provides a differential drive to the
AD8345’s differential LO input.
EVALUATION BOARD
Figure 32 shows the schematic of the AD8345 evaluation board.
Note that uninstalled components are marked as open. This is a
4-layer board, with the two center layers used as ground plane,
and top and bottom layers used as signal and power planes.
R1
(OPEN)
R9
(OPEN)
AD8345
QBBP 16
1
2
3
4
5
6
7
8
IP
IN
QP
QN
IBBP
IBBN
COM3
COM1
LOIN
LOIP
15
14
13
12
11
10
9
QBBN
COM3
COM3
VPS2
R2
(OPEN)
R10
(OPEN)
R11
0Ω
C1
1000pF
VPOS
VOUT
C6
0.01μF
C5
1000pF
5
4
1
LO
R6
50Ω
C2
1000pF
T1
R12
0Ω
2
3
ETC1-1-13
VOUT
COM2
COM3
R14
R15
(OPEN)
C7
1000pF
(OPEN)
VPOS
VPS1
ENBL
C3
R7
0Ω
C4
1000pF
0.01μF
A
ENBL
R8
10kΩ
B
SW1
VPOS
Figure 32. Evaluation Board Schematic
Rev. B | Page 15 of 20
AD8345
Figure 33. Evaluation Board Silkscreen
Figure 34. Layout of Evaluation Board, Top Layer
Figure 35. Layout of Evaluation Board, Bottom Layer
Rev. B | Page 16 of 20
AD8345
CHARACTERIZATION SETUPS
SSB SETUP
Essentially, two primary setups are used to characterize the
AD8345. These setups are shown in Figure 37 and Figure 38.
Figure 37 shows the setup used to evaluate the product as a
single sideband modulator. The interface board converts the
single-ended I and Q inputs from the arbitrary function
generator to differential inputs with a dc bias of approximately
0.7 V. The interface board also provides connections for power
supply routing. The HP34970A and its associated plug-in 34901
are used to monitor power supply currents and voltages being
supplied to the AD8345 characterization board. Two HP34907
plug-ins are used to provide additional miscellaneous dc and
control signals to the interface board. The LO inputs are driven
directly by an RF signal generator, and the output is measured
directly with a spectrum analyzer. With the I channel driven
with a sine wave and the Q channel driven with a cosine wave,
the lower sideband is the single sideband output. The typical
SSB output spectrum is shown in Figure 36.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CENTER = 900MHz
SPAN = 1MHz
Figure 36. Typical SSB Output Spectrum
IEEE
D1
HP34970A
D2
D3
34901
D1
34907
D2
34907
D3
TEKAFG2020
+15V MAX
COM
VPS1
I_IN
OUTPUT_1
OUTPUT_2
INTERFACE
BOARD
IEEE
IEEE
+25V MAX
–25V MAX
Q_IN
VN
GND
VP
ARB FUNCTION GEN
HP3631
P1 IN IP QP QN
IP
QP
QN
IN
AD8345
HP8648C
CHARACTERIZATION
BOARD
HP8593E
LO
IEEE
RFOUT
SWEEP OUT
VOUT
RF I/P
ENBL
28V
P1
SPECTRUM
ANALYZER
IEEE
IEEE
PC CONTROLLER
Figure 37. Characterization Board SSB Test Setup
Rev. B | Page 17 of 20
AD8345
MODULATED WAVEFORM SETUP
WCDMA 3GPP
To evaluate the AD8345 with modulated waveforms, the setup
shown in Figure 38 is used. A Rohde & Schwarz AMIQ signal
generator with differential outputs is used to generate the
baseband signals. For all measurements, the input level on each
baseband input pin is 0.7 V 0.3 V peak. The output is
measured with a Rohde & Schwarz FSIQ spectrum/vector
analyzer.
To evaluate the AD8345 for WCDMA, the 3GPP standard is
used with a chip rate of 3.84 MHz. The plot in Figure 40 is an
ACPR plot of the AD8345 using Test Model 1 from the 3GPP
specification with 64 channels active.
–10
CH PWR = –10.95dBm
–20
–30
–40
–50
–60
–70
–80
–90
ACP UP = –52.51dB
ACP LOW = –52.41dB
PC CONTROL
AMIQ
IN
IP
QP
QN
IEEE
PC CONTROLLER
IP
QP
QN
CHARACTERIZATION
AD8345
IN
HP8648C
FSIQ
RFOUT
IEEE
LO
BOARD
–100
–110
ENBL
RF I/P
VOUT
IEEE
P1
CENTER = 380MHz
SPAN = 14.7MHz
SPECTRUM
ANALYZER
Figure 40. Typical AD8345 WCDMA 3GPP Output Spectrum
+15V MAX
COM
GSM
IEEE
+25V MAX
–25V MAX
To compare the AD8345 output to the GSM transmit mask, I
and Q signals are generated using MSK modulation, GSM
differential coding, a Gaussian filter, and a symbol rate of
270.833 kHz. The transmit mask is manually generated on the
FSIQ using the GSM BTS specification for reference. The plot in
Figure 41 shows that the AD8345 meets the GSM transmit
mask requirements.
HP3631
Figure 38. Test Setup for Evaluating AD8345 with Modulated Waveforms
CDMA IS95
To measure ACPR, the I and Q input signals used are generated
with Pilot channel (Walsh Code 00), Sync channel (WC 32), Paging
channel (WC 01), and six Traffic (WC 08, 09, 10, 11, 12, 13)
channels active. Figure 39 shows the typical output spectrum for
this configuration.
0
–10
–20
–30
–40
–50
–60
–70
–80
To perform EVM, Rho, phase, and amplitude balance
measurements, the I and Q input signals used are generated
with only the Pilot channel (Walsh Code 00) active.
–10
CH PWR = –12.41dBm
ACP UP = –72.9dB
ACP LOW = –72.9dB
–20
–30
–40
–50
–60
–70
–80
–90
–90
–100
CENTER = 900MHz
SPAN = 1MHz
Figure 41. Typical AD8345 GSM Output Spectrum
–100
–110
CENTER = 880MHz
SPAN = 7.5MHz
Figure 39. Typical IS95 Output Spectrum
Rev. B | Page 18 of 20
AD8345
OUTLINE DIMENSIONS
5.10
5.00
4.90
BOTTOM
VIEW
16
9
8
4.50
4.40
4.30
EXPOSED
PAD
(Pins Up)
TOP
VIEW
6.40
BSC
3.00
SQ
1
1.05
1.00
0.80
1.20 MAX
0.20
0.09
8°
0°
0.15
0.00
0.30
0.19
0.65
BSC
0.75
0.60
0.45
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-ABT
Figure 42. 16-Lead Thin Shrink Small Outline with Exposed Pad (TSSOP_EP)
(RE-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8345ARE
AD8345ARE-REEL7
AD8345AREZ1
AD8345AREZ-RL71
AD8345-EVAL
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
16-Lead TSSOP with Exposed Pad, Tube
16-Lead TSSOP with Exposed Pad, 7" Tape and Reel
16-Lead TSSOP with Exposed Pad, Tube
16-Lead TSSOP with Exposed Pad, 7" Tape and Reel
Evaluation Board
RE-16-2
RE-16-2
RE-16-2
RE-16-2
1 Z = Pb-free part.
Rev. B | Page 19 of 20
AD8345
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00932-0-12/05(B)
Rev. B | Page 20 of 20
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