AD8275ARMZ-RL [ADI]
G = 0.2, Level Translation, 16-Bit ADC Driver; G = 0.2 ，电平转换， 16位ADC驱动器
| 型号： | AD8275ARMZ-RL |
| 厂家： | 
ADI |
| 描述： | G = 0.2, Level Translation, 16-Bit ADC Driver |
| 文件： | 总16页 (文件大小：567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
G = 0.2, Level Translation,
16-Bit ADC Driver
AD8275
FEATURES
PIN CONFIGURATION
Translates 10 V to +4 V
Drives 16-bit SAR ADCs
Small MSOP package
Input overvoltage: +40 V to −35 V (VS = 5 V)
Fast settling time: 450 ns to 0.001%
Rail-to-rail output
Wide supply operation: +3.3 V to +15 V
High CMRR: 80 dB
REF1
–IN
1
2
3
4
8
7
6
5
REF2
AD8275
+V
S
TOP VIEW
+IN
OUT
(Not to Scale)
–V
SENSE
S
Figure 1.
TYPICAL APPLICATION
+5V
0.1µF
0.1µF
Low gain drift: 1 ppm/°C
Low offset drift: 2.5 μV/°C
7
+4.048V
+2.048V
+0.048V
+V
S
+10V
50kΩ
–IN
10kΩ
2
5
APPLICATIONS
SENSE
33Ω
VDD
AD7685
IN+
IN–
OUT
Level translator
ADC driver
6
2.7nF
REF
GND
50kΩ
+IN
20kΩ
20kΩ
Instrumentation amplifier building block
Automated test equipment
3
8
1
VIN
–10V
REF2
REF1
VREF
4.096V
10µF
AD8275 –V
S
4
Figure 2. Translating 10 V to 4.096 V ADC Full Scale
GENERAL DESCRIPTION
The AD8275 is a G = 0.2 difference amplifier that can be used
to translate ±±0 V signals to a +4 V level. It solves the problem
typically encountered in industrial and instrumentation applic-
ations where ±±0 V signals must be interfaced to a single-supply
4 V or 5 V ADC. The AD8275 interfaces the two signal levels,
simplifying design.
The AD8275 can be used as an analog front end, or it can follow
buffers to level translate high voltages to a voltage range accepted
by the ADC. In addition, the AD8275 can be configured for diff-
erential outputs if used with a differential ADC.
The AD8275 is available in a space-saving, 8-lead MSOP
and is specified for performance over the −40°C to +85°C
temperature range.
The AD8275 has fast settling time of 450 ns and low distortion,
making it suitable for driving medium speed successive approx-
imation (SAR) ADCs. Its wide input voltage range and rail-to-
rail outputs make it an easy to use building block. Single-supply
operation reduces the power consumption of the amplifier and
helps to protect the ADC from overdrive conditions.
Table 1. Difference Amplifiers by Category
Single-Supply
Current Sense
Low Distortion
AD8270
High Voltage
AD628
AD8202
AD8273
AD629
AD8203
Internal, matched, precision laser-trimmed resistors ensure
low gain error, low gain drift of ± ppm/°C (maximum), and
high common-mode rejection of 80 dB. Low offset and low
offset drift, combined with its fast settling time, make the
AD8275 suitable for a variety of data acquisition applications
where accurate and quick capture is required.
AD8274
AD8205
AD8275
AD8206
AMP03
AD8216
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD8275
TABLE OF CONTENTS
Features .............................................................................................. ±
Reference ..................................................................................... ±2
Common-Mode Input Voltage Range..................................... ±2
Input Protection ......................................................................... ±2
Configurations............................................................................ ±3
Applications Information.............................................................. ±4
Driving a Single-Ended ADC................................................... ±4
Differential Outputs................................................................... ±4
Increasing Input Impedance ..................................................... ±5
AC Coupling ............................................................................... ±5
Applications....................................................................................... ±
Pin Configuration............................................................................. ±
Typical Application........................................................................... ±
General Description......................................................................... ±
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Maximum Power Dissipation ..................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... ±±
Basic Connection........................................................................ ±±
Power Supplies ............................................................................ ±2
Using the AD8275 as a Level Translator in a Data Acquisition
System .......................................................................................... ±5
Outline Dimensions....................................................................... ±6
Ordering Guide .......................................................................... ±6
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD8275
SPECIFICATIONS
VS = 5 V, G = 0.2, REF± connected to GND and REF2 connected to 5 V, RL = 2 kΩ connected to VS/2, TA = 25°C, unless otherwise noted.
Specifications referred to output unless otherwise noted.
Table 2.
A Grade
Typ
B Grade
Typ
Parameter
Test Conditions/Comments
Min
Max
Min
Max
Unit
DYNAMIC PERFORMANCE
Small Signal Bandwidth
Slew Rate
Settling Time to 0.01%
Settling Time to 0.001%
Overload Recovery Time
NOISE/DISTORTION1
THD + N
−3 dB
4 V step
4 V step on output, CL = 100 pF
4 V step on output, CL = 100 pF
50% overdrive
10
20
15
25
350
450
300
10
20
15
25
350
450
300
MHz
V/μs
ns
ns
ns
450
550
f = 1 kHz, VOUT = 4 V p-p, 22 kHz band
pass filter
106
106
dB
Voltage Noise
Spectral Noise Density
GAIN
f = 0.1 Hz to 10 Hz, referred to output
f = 1 kHz, referred to output
1
40
0.2
4
1
40
0.2
4
μV p-p
nV/√Hz
V/V
VREF2 = 4.096 V, REF1 and RL connected
to GND, (VIN+) − (VIN−) = −10 V to +10 V
Gain Error
Gain Drift
Gain Nonlinearity
OFFSET AND CMRR
Offset2
0.024
3
0.024
1
3
%
−40°C to +85°C
VOUT = 4 V p-p, RL = 600 Ω, 2 kΩ, 10 kΩ
1
2.5
0.3
2.5
ppm/°C
ppm
Referred to output, VS = 2.5 V,
reference and input pins grounded
−40°C to +85°C
VS = 3.3 V to 5 V
300
2.5
700
150
2.5
500
7
μV
vs. Temperature
vs. Power Supply
Reference Divider Accuracy
Common-Mode Rejection
Ratio3
μV/°C
dB
%
90
80
100
86
0.024
+12
0.024
VCM
=
10 V, referred to output
96
dB
INPUT CHARACTERISTICS
Input Voltage Range4
Impedance5
−12.3
−12.3
+12
V
Differential
Common Mode
VCM = VS/2
108||2
27.5||2
108||2
27.5||2
kΩ||pF
kΩ||pF
OUTPUT CHARACTERISTICS
Output Swing
VREF2 = 4.096 V, REF1 and RL connected
to GND, RL = 2 kΩ
−VS +
0.048
+VS −
0.1
−VS +
0.048
+VS −
0.1
V
Capacitive Load6
Short-Circuit Current Limit
POWER SUPPLY
100
30
100
30
pF
mA
Specified Voltage Range
Operating Voltage Range
Supply Current
5
5
V
V
mA
3.3
15
2.3
3.3
15
2.3
IO = 0 mA, VS = 2.5 V, reference and
input pins grounded
IO = 0 mA, VS = 2.5 V, reference and
input pins grounded, −40°C to +85°C
1.9
2.1
1.9
2.1
Over Temperature
2.7
2.7
mA
°C
TEMPERATURE RANGE
Specified Performance
−40
+85
−40
+85
1 Includes amplifier voltage and current noise, as well as noise of internal resistors.
2 Includes input bias and offset current errors.
3 See Figure 7 for CMRR vs. temperature.
4 The input voltage range is a function of the voltage supplies, reference voltage, and ESD diodes. When operating on other supply voltages, see the Absolute Maximum
Ratings section, Figure 11, and Table 5 for more information.
5 Internal resistors are trimmed to be ratio matched but have 20% absolute accuracy.
6 See Figure 25 to Figure 28 in the Typical Performance Characteristics section for more information.
Rev. 0 | Page 3 of 16
AD8275
ABSOLUTE MAXIMUM RATINGS
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some of which is dissipated in the
load (VOUT × IOUT).
Table 3.
Parameter
Rating
Supply Voltage
18 V
The difference between the total drive power and the load
power is the drive power dissipated in the package.
Output Short-Circuit Current
See derating curve
(Figure 3)
Voltage at +IN, −IN Pins
Voltage at REFx, +VS, − VS, SENSE,
and OUT Pins
Current into REFx, +IN, −IN, SENSE,
and OUT Pins
Storage Temperature Range
Specified Temperature Range
Thermal Resistance (θJA)
−VS + 40 V, +VS − 40 V
−VS − 0.5 V, +VS + 0.5 V
PD = Quiescent Power + (Total Drive Power − Load Power)
2
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VS VOUT
VOUT
RL
PD =
(
VS × IS
)
+
×
–
2
RL
3 mA
In single-supply operation with RL referenced to –VS, the worst
case is VOUT = VS/2.
−65°C to +130°C
−40°C to +85°C
135°C/W
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces θJA.
Package Glass Transition Temperature
(TG)
ESD Human Body Model
140°C
2 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature on a 4-layer JEDEC
standard board.
2.00
1.75
1.50
MAXIMUM POWER DISSIPATION
1.25
1.00
0.75
0.50
0.25
0
The maximum safe power dissipation in the AD8275 package is
limited by the associated rise in junction temperature (TJ) on
the die. The plastic encapsulating the die locally reaches the
junction temperature. At approximately ±40°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8275. Exceeding
a junction temperature of ±40°C for an extended period can
result in changes in silicon devices, potentially causing failure.
–40
–20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
The still air thermal properties of the package and PCB (θJA),
the ambient temperature (TA), and the total power dissipated in
the package (PD) determine the junction temperature of the die.
The junction temperature is calculated as follows:
TJ = TA + (PD × θJA)
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
Rev. 0 | Page 4 of 16
AD8275
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REF1
–IN
1
2
3
4
8
7
6
5
REF2
+V
AD8275
S
TOP VIEW
+IN
OUT
(Not to Scale)
–V
SENSE
S
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
5
6
7
8
REF1
−IN
+IN
Reference Pin. Sets the output voltage level (see the Reference section).
Negative Input Pin.
Positive Input Pin.
Negative Supply Pin.
Sense Output Pin. Tie this pin to the OUT pin.
Output Pin (Force Output).
−VS
SENSE
OUT
+VS
Positive Supply Pin.
Reference Pin. Sets the output voltage level (see the Reference section).
REF2
Rev. 0 | Page 5 of 16
AD8275
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, G = 0.2, REF± connected to GND and REF2 connected to 5 V, RL = 2 kΩ connected to VS/2, TA = 25°C, unless otherwise noted.
300
250
14
200
12
150
100
10
50
8
6
4
2
0
0
–50
–100
–150
–200
–250
–300
NORMALIZED AT 25°C, REPRESENTATIVE SAMPLES
–40 –20 20 40 60 80 100
TEMPERATURE (°C)
–600
–400
–200
0
200
400
600
0
120
OFFSET VOLTAGE (µV)
Figure 5. Typical Distribution of System Offset Voltage, Referred to Output
Figure 8. Offset Voltage vs. Temperature, Normalized at 25°C,
Referred to Output
50
40
70
60
50
40
30
20
10
0
30
20
10
0
–10
–20
–30
–40
GAIN ERROR NORMALIZED AT 25°C
–50
–45 –30 –15
0
15 30 45 60 75 90 105 120
–60
–40
–20
0
20
40
60
TEMPERATURE (°C)
CMRR (µV/V)
Figure 6. Typical Distribution of CMRR, Referred to Output
Figure 9. Gain Error vs. Temperature, Normalized at 25°C
60
5
4
3
2
1
40
20
0
5V
–20
–40
–60
3.3V
–40
–20
0
20
40
60
80
100
120
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. CMRR vs. Temperature, Normalized at 25°C
Figure 10. Quiescent Current vs. Temperature
Rev. 0 | Page 6 of 16
AD8275
35
30
120
100
80
25
20
15
10
60
5
40
0
–5
20
–10
–15
–20
–25
0
–20
100
1k
10k
100k
1M
–0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 11. Input Common-Mode Voltage vs. Output Voltage, No Load
Figure 14. Power Supply Rejection vs. Frequency, Referred to Output
0
–5
6
5
4
3
2
1
0
–10
–15
–20
–25
–30
–35
–40
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 12. Gain vs. Frequency
Figure 15. Maximum Output Voltage vs. Frequency
100
90
80
70
60
50
40
20
15
10
5
0
–5
–10
–15
–20
0
1
2
3
4
100
1k
10k
100k
1M
10M
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 16. Gain Nonlinearity, RL = 600 Ω, 2 kΩ, 10 kΩ
Figure 13. Common-Mode Rejection vs. Frequency, Referred to Input
Rev. 0 | Page 7 of 16
AD8275
+V
60
50
S
–40°C
+V – 0.4
S
+125°C
+85°C
40
5V SOURCE
+25°C
+V – 0.8
S
30
+V – 1.2
3.3V SOURCE
S
20
+V – 1.6
S
10
+V – 2.0
S
0
–10
–20
–30
–40
–50
–60
–V + 2.0
S
–V + 1.6
S
3.3V SINK
5V SINK
–V + 1.2
S
–V + 0.8
S
+85°C +125°C
+25°C
8
–V + 0.4
S
–40°C
12 14
–70
–50
–V
S
–25
0
25
50
75
100
125
0
2
4
6
10
OUTPUT CURRENT (mA)
TEMPERATURE (°C)
Figure 17. Short-Circuit Current vs. Temperature, VS = 3.3 V, 5 V
Figure 20. Output Voltage Swing vs. Output Current, VS = 5 V
1k
+V
S
–40°C
+V – 0.2
S
+25°C
+V – 0.4
S
+85°C
+125°C
+V – 0.6
S
+V – 0.8
S
+V – 1.0
S
100
–V + 1.0
S
–V + 0.8
S
+125°C
+85°C
+25°C
–V + 0.6
S
–V + 0.4
S
–V + 0.2
S
–40°C
100
10
–V
S
1
10
100
1k
10k
100k
1k
10k
100k
R
(Ω)
LOAD
FREQUENCY (Hz)
Figure 18. Output Voltage Swing vs. RLOAD, VS = 5 V
Figure 21. Voltage Noise Density vs. Frequency, Referred to Output
+V
S
–40°C
+25°C
+V – 0.4
S
+125°C
+85°C
+V – 0.8
S
+V – 1.2
S
+V – 1.6
S
+V – 2.0
S
–V + 2.0
S
–V + 1.6
S
–V + 1.2
S
–V + 0.8
S
+125°C
12
+85°C
10
+25°C
8
–V + 0.4
S
–40°C
–V
S
0
2
4
6
14
TIME (1s/DIV)
OUTPUT CURRENT (mA)
Figure 19. Output Voltage Swing vs. Output Current, VS = 3.3 V
Figure 22. 0.1 Hz to 10 Hz Voltage Noise, Referred to Output
Rev. 0 | Page 8 of 16
AD8275
40
35
30
25
20
15
10
5
60
50
40
30
20
10
0
+SR
–SR
3.3V
5V
0
–40
–20
0
20
40
60
80
100
120
0
20
40
60
80
100
120
140
160
160
160
TEMPERATURE (°C)
CAPACITANCE (pF)
Figure 26. Small Signal Overshoot vs. Capacitive Load,
No Resistive Load
Figure 23. Slew Rate vs. Temperature
60
50
40
30
20
10
C
= 47pF
LOAD
2kΩ
NO LOAD
600Ω
3.3V
5V
10kΩ
0
0
20
40
60
80
100
120
140
1µs/DIV
CAPACITANCE (pF)
Figure 27. Small Signal Overshoot vs. Capacitive Load,
600 Ω in Parallel with Capacitive Load
Figure 24. Small Signal Step Response for Various Resistive Loads
(Step Responses Staggered for Clarity)
60
NO RESISTIVE LOAD
100pF
20pF
50
40
30
20
10
0
NO CAP
3.3V
5V
47pF
0
20
40
60
80
100
120
140
1µs/DIV
CAPACITANCE (pF)
Figure 28. Small Signal Overshoot vs. Capacitive Load,
2 kΩ in Parallel with Capacitive Load
Figure 25. Small Signal Pulse Response for Various Capacitive Loads
(Step Responses Staggered for Clarity)
Rev. 0 | Page 9 of 16
AD8275
1.0
0.1
V
= 4V p-p
OUT
10V/DIV
0.01
R
= 600ꢀ
= 10kꢀ
L
10mV/DIV
0.001
0.0001
R
= 2kꢀ
L
R
L
2µs/DIV
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 29. Large Signal Pulse Response and Settling Time, RL = 2 kΩ
Figure 30. THD + N vs. Frequency, VOUT = 4 V p-p
Rev. 0 | Page 10 of 16
AD8275
THEORY OF OPERATION
The AD8275 level translates ±±0 V signals at its inputs to 4 V
at its output. It does this by attenuating the input signal by 5.
A subtractor network performs the attenuation, the level shifting,
and the differential-to-single-ended conversion. One benefit of
the subtractor topology is that it can accept input signals
beyond its supply voltage. The subtractor is composed of tightly
matched resistors. By integrating the resistors and trimming the
resistor ratios, the AD8275 achieves 80 dB CMRR and 0.024%
gain error.
The AD8275 employs a balanced, high gain, linear output stage
that adaptively generates current as required, eliminating the
dynamic errors found in other amplifiers. This is useful when
driving SAR ADCs, which can deliver kickback current into the
output of the amplifier. The result is a design that achieves low
distortion, consistent bandwidth, and high slew rate.
BASIC CONNECTION
The basic configurations for the AD8275 are shown in
Figure 33 and Figure 34. In Figure 33, REF± and REF2 are
tied together. A voltage, VREF, applied to the tied REF± and
REF2 pins, sets the output voltage level to VREF. For example,
in Figure 33, if VREF = 2 V and the inputs are tied to ground,
the output remains at 2 V.
+V
S
50kꢀ
10kꢀ
INPUT
ESD
–IN
SENSE
+V
S
–V
+V
S
–V
+V
S
S
S
S
7kꢀ
7kꢀ
+5V
OUT
0.1µF
–V
S
2.5V
7
–V
+V
S
+V
S
–V
S
–V
S
+V
S
50kꢀ
–IN
10kꢀ
V
5
6
2
INN
20kꢀ
REF2
REF1
SENSE
OUT
–V
S
V
OUT
+V
S
20kꢀ
INPUT
ESD
V
+IN
REF
50kꢀ
+IN
20kꢀ
20kꢀ
50kꢀ
3
8
1
V
INP
REF2
REF1
–V
S
Figure 31. AD8275 Simplified Schematic
AD8275 –V
S
4
To achieve a wider input voltage range, the AD8275 uses an
internal 2.5 V voltage bias tied to –VS and two 7 kꢀ resistors, as
shown in Figure 3±. The resistors help to set the common mode
of the internal amplifier. The benefit of this circuit is that it
extends the input range without causing crossover distortion
typical of amplifiers that have rail-to-rail complementary
transistor inputs. The input range of the internal op amp is
+VS − 0.9 V to −VS + ±.35 V.
(V ) – (V
INP
)
INN
V
=
+ V
REF
OUT
5
Figure 33. Basic Configuration 1: Shared Reference
In contrast, Figure 34 shows REF± tied to ground and REF2
tied to VREF. In this example, the two 20 kꢀ resistors serve as a
resistor divider, and VREF is divided by 2. For example, if both
inputs of the AD8275 are grounded and VREF = 5 V, the output
is 2.5 V.
600
400
200
+5V
0.1µF
7
+V
S
0
50kꢀ
–IN
10kꢀ
V
5
6
2
INN
SENSE
OUT
–200
–400
–600
V
OUT
V
REF
50kꢀ
+IN
20kꢀ
20kꢀ
3
8
1
V
INP
REF2
REF1
–10
–8
–6
–4
–2
0
2
4
6
8
10
COMMON-MODE VOLTAGE (V)
AD8275 –V
S
4
Figure 32. AD8275 Does Not Have Crossover Distortion Typical of Rail-to-Rail
Input Amplifiers
(V ) – (V
INP
)
V
+ 0V
2
INN
REF
V
=
+
OUT
5
Figure 34. Basic Configuration 2: Split Reference
Rev. 0 | Page 11 of 16
AD8275
POWER SUPPLIES
COMMON-MODE INPUT VOLTAGE RANGE
Use a stable dc voltage to power the AD8275. Noise on the
supply pins can adversely affect performance. Place a bypass
capacitor of 0.± μF between each supply pin and ground, as
close to each pin as possible. A tantalum capacitor of ±0 μF
should also be used between each supply and ground. It can
be farther away from the AD8275 and typically can be shared
by other precision integrated circuits.
The common-mode voltage range is a function of the input
voltage range of the internal op amp, the supply voltage, and
the reference voltage.
Equation ± expresses the maximum positive common-mode
voltage range.
VCM_POS ≤ ±3.±4(+VS) – 7.±4(–VS) – 5((REF1 + REF2)/2) – 29.69 (±)
Equation 2 expresses the minimum common-mode voltage
range.
REFERENCE
The reference terminals are used to provide a bias level for the
output. For example, in a single-supply 5 V operation, the
reference terminals can be set so that the output is biased at
2.5 V. This ensures that the output can swing positive or
negative around a 2.5 V level.
V
CM_NEG ≥ 6(–VS) – 5((REF1 + REF2)/2) – 0.±±
(2)
The voltage range of the internal op amp varies depending on
temperature. The equations reflect a typical input voltage range
of +VS − 0.9 V and −VS + ±.35 V over temperature. Table 5 lists
expected common-mode ranges for typical configurations.
Figure 33 and Figure 34 illustrate two different ways to set the
reference voltage. See the Basic Connection section for the
differences between the two settings.
Table 5. Expected Common-Mode Voltage Range for Typical
Configurations
+VS (V)1 VREF1 (V)
VREF2 (V)
VCM+ (V)
23.5
29.8
25.8
5.4
VCM− (V)
−12.6
−6.4
−10.4
−8.4
The allowable reference voltage range is a function of the
common-mode input and supply voltages. The REF± and REF2
pins should not exceed either +VS or −VS by more than 0.5 V.
5
5
0
0
0
0
0
5
5
5
3.3
3.3
5
2.5
4.096
3.3
2.5
5
The REFx terminals should be driven by low source impedance
because parasitic resistance in series with REF± and REF2 can
adversely affect CMRR and gain accuracy.
7.4
−6.4
11.0
15.5
21.0
23.5
25.8
29.8
36.0
−25.1
−20.6
−15.1
−12.6
−10.4
−6.4
CORRECT
INCORRECT
5
5
4.096
3
4.096
3
2.5
2.048
1.25
0
+V
7
+V
7
S
S
5
5
5
5
2.5
2.048
1.25
0
SENSE
SENSE
50kꢀ
–IN
10kꢀ
50kꢀ
–IN
10kꢀ
2
3
5
2
3
5
OUT
OUT
6
6
V
REF
−0.1
V
1 –VS = 0 V.
REF
REF2
REF1
REF2
REF1
50kꢀ
+IN
50kꢀ
+IN
20kꢀ
20kꢀ
20kꢀ
20kꢀ
8
1
8
1
INPUT PROTECTION
–V
S
4
–V
S
The inputs of the AD8275, +IN and −IN, are protected by ESD
diodes that clamp 40 V above −VS and 40 V below +VS. When
operating on a single +5 V supply, the ESD diode conducts at
input voltages less than −35 V and greater than +40 V.
AD8275
AD8275
4
+V
7
+V
7
S
S
If the input voltage is expected to exceed the maximum ratings
of the AD8275, use external transorbs. Adding series resistors to
the inputs of the AD8275 is not recommended because the
internal resistor ratios are matched to provide optimal CMRR
and gain accuracy. Adding external series resistors to the input
degrades the performance of the AD8275.
SENSE
SENSE
50kꢀ
–IN
10kꢀ
50kꢀ
–IN
10kꢀ
2
3
5
2
3
5
OUT
OUT
6
6
V
REF
V
REF
REF2
REF1
REF2
REF1
50kꢀ
+IN
50kꢀ
+IN
20kꢀ
20kꢀ
20kꢀ
20kꢀ
8
1
8
1
All other pins are protected by ESD diodes that clamp 0.5 V
beyond either supply rail. For example, the voltage range of the
REF± and REF2 pins on a 5 V supply is −0.5 V to +5.5 V.
–V
4
–V
S
S
AD8275
AD8275
4
Figure 35. REF1 and REF2 Pin Guidelines
Rev. 0 | Page 12 of 16
AD8275
CONFIGURATIONS
Figure 36 and Figure 37, along with Table 6 and Table 7, provide
examples of the possible input and output ranges for various
supplies and reference voltages.
Note that Table 6 and Table 7 list the typical voltage range of the
AD8275; these values do not reflect variation over process or
temperature.
+5V
+5V
0.1µF
0.1µF
USEFUL V
OUT
USEFUL V
OUT
HI
HI
7
7
LINEAR V
RANGE
LINEAR V
RANGE
+SWING
–SWING
+SWING
–SWING
IN
IN
+V
+V
S
S
HI
HI
50kꢀ
–IN
10kꢀ
50kꢀ
–IN
10kꢀ
LO
LO
2
5
6
2
5
6
V
V
INN
INN
SENSE
OUT
SENSE
OUT
MID
LO
MID
LO
V
V
OUT
OUT
V
V
REF
REF
50kꢀ
+IN
20kꢀ
20kꢀ
50kꢀ
+IN
20kꢀ
20kꢀ
3
8
1
3
8
1
V
V
INP
INP
REF2
REF1
REF2
REF1
AD8275 –V
AD8275 –V
S
S
4
4
Figure 36. Split Reference
Figure 37. Shared Reference
Table 6. Input and Output Relationships for Split Reference
Configuration in Figure 36
Table 7. Input and Output Relationships for Shared
Reference Configuration in Figure 37
Linear
Linear
V
OUT for
Differential
VIN Range
Useful VOUT
Ranges
V
OUT for
Differential
VIN Range
Useful VOUT
Ranges
1
1
+VS
VREF
VIN = 0 V
+VS
VREF
VIN = 0 V
5 V
5 V
2.5 V
High: +12 V
Mid: 0 V
High: +4.95 V
Swing: +2.45 V,
5 V
5 V
5 V
High: −0.1 V
Mid: 0 V
High: +4.98 V
Swing: −4.94 V
Low: −12.3 V −2.455 V
Low: +0.045 V
High: +18.3 V High: +4.95 V
Low: −24.7 V Low: +0.06 V
5 V
5 V
5 V
5 V
5 V
0 V
4.096 V 4.096 V
High: +4.4 V
Mid: 0 V
High: +4.98 V
Swing: +0.884 V
5 V
5 V
2.5 V
1.25 V
Mid: 0 V
Low: −6 V
Swing: +3.7 V,
−1.205 V
Low: −20.2 V to −4.03 V
Low: +0.06 V
Low: +0.045 V
High: +14.3 V High: +4.95 V
3 V
3 V
High: +9.5 V
Mid: 0 V
High: +4.95 V
Swing: +1.9 V,
4.096 V 2.048 V
Mid: 0 V
Low: −10 V
Swing: +2.902 V,
−2.003 V
Low: −14.8 V −2.955 V
Low: +0.045 V
Low: +0.045 V
2.5 V
2.5 V
High: +12 V
Mid: 0 V
High: +4.95 V
Swing: +2.45 V,
3.3 V 3.3 V
3.3 V 2.5 V
1.65 V
1.25 V
High: +8 V
Mid: 0 V
Low: −8 V
High: +3.24 V
Swing: +1.59 V,
−1.605 V
Low: −12.3 V −2.455 V
Low: +0.045 V
High: +14.3 V High: +4.95 V
Low: +0.045 V
2.048 V 2.048 V
High: +10 V
Mid: 0 V
Low: −6 V
High: +3.24 V
Swing: +1.99 V,
−1.205 V
Mid: 0 V
Low: −10 V
Swing: +2.902 V,
−2.003 V
Low: +0.045 V
Low: +0.045 V
1.25 V
0 V
1.25 V
0 V
+18.3 V to
−6 V
High: +4.95 V
Swing: +3.7 V,
−1.205 V
1 −VS = 0 V.
Low: +0.045 V
24.5 V to 0.2 V High: 4.95 V
Swing: 4.95 V
Low: 0.045 V
1 −VS = 0 V.
Rev. 0 | Page 13 of 16
AD8275
APPLICATIONS INFORMATION
10
0
–10
DRIVING A SINGLE-ENDED ADC
The AD8275 provides the common-mode rejection that SAR
ADCs often lack. In addition, it enables designers to use cost-
effective, precision, ±6-bit ADCs such as the AD7685, yet still
condition ±±0 V signals.
–20
–30
–40
–50
–60
–70
–80
–90
One important factor in selecting an ADC driver is its ability to
settle within the acquisition window of the ADC. The AD8275
is able to drive medium speed SAR ADCs.
–100
–110
–120
–130
–140
–150
–160
–170
In Figure 38, the 2.7 nF capacitor serves to store and deliver
necessary charge to the switched capacitor input of the ADC.
The 33 ꢀ series resistor reduces the burden of the 2.7 nF load
from the amplifier and isolates it from the kickback current
injected from the switched capacitor input of the AD7685. The
output impedance of the amplifier can affect the THD of the
ADC. In this case, the combined impedance of the 33 ꢀ resistor
and the output impedance of the AD8275 provides extremely
low THD of −±±2 dB. Figure 39 shows the ac response of the
AD8275 driving the AD7685.
0
1
4
7
10
2
5
8
3
6
9
FREQUENCY (kHz)
Figure 39. FFT of AD8275 Directly Driving the AD7685 Using the 5 V
Reference of the Evaluation Board (Input = 20 V p-p, 1 kHz, THD = −112 dB)
The AD8275 can condition signals for higher resolution ADCs
such as ±8-bit SAR converters, provided that a narrower
bandwidth is sampled to limit noise.
+5V
DIFFERENTIAL OUTPUTS
0.1µF
0.1µF
In certain applications, it is necessary to create a differential signal.
For example, high resolution ADCs often require a differential
input. In other cases, transmission over a long distance can require
differential signals for better immunity to interference.
7
+V
S
50kꢀ
–IN
10kꢀ
2
5
SENSE
33ꢀ
VDD
AD7685
IN+
Figure 40 shows how to configure the AD8275 to output a
differential signal. The AD8655 op amp is used in an inverting
topology to create a differential voltage. VREF sets the output
midpoint. Errors from the op amp are common to both outputs
and are thus common mode. Likewise, errors from using
mismatched resistors cause a common-mode dc offset error.
Such errors are rejected in differential signal processing by
differential input ADCs or by instrumentation amplifiers.
OUT
6
2.7nF
IN–
REF
GND
50kꢀ
+IN
20kꢀ
20kꢀ
3
8
1
VIN
REF2
REF1
VREF
(ADR444,
ADR445)
10µF
AD8275 –V
S
4
Figure 38. Driving a Single-Ended ADC
When using this circuit to drive a differential ADC, VREF can be
set using a resistor divider from the ADC reference to make the
output ratiometric with the ADC.
+5V
0.1µF
7
+V
S
50kꢀ
–IN
10kꢀ
2
5
6
SENSE
OUT
+4.5V
+V
OUT
+2.5V
+0.5V
AD8655
2kꢀ
2kꢀ
V
= 2.5V
REF
+10V
–10V
50kꢀ
+IN
20kꢀ
20kꢀ
3
8
1
REF2
REF1
8.2µF
+5V
0.1µF
AD8275
+4.5V
–V
4
S
+2.5V
+0.5V
–V
OUT
Figure 40. AD8275 Configured for Differential Output (for Driving a Differential ADC)
Rev. 0 | Page 14 of 16
AD8275
INCREASING INPUT IMPEDANCE
USING THE AD8275 AS A LEVEL TRANSLATOR IN
A DATA ACQUISITION SYSTEM
In applications where a high input impedance is needed, low
input bias current op amps can be used to buffer the AD8275.
In Figure 4±, an AD8620 is used to provide high input imped-
ance. Input bias current is limited to ±0 pA.
+5V
Signal size varies dramatically in some data acquisition applica-
tions. Instrumentation amplifiers, such as the AD8253, AD8228,
or AD822±, are often used at the inputs to provide CMRR and
high input impedance. However, the instrumentation amplifiers
output ±±0 V signals and the ADC full scale is 5 V or 4.096 V.
In Figure 43, the AD8275 serves as a level translator between
the in-amp and the ADC. The AD8275, along with the AD8228
and the AD8253, have very low gain drift because all gain setting
resistors are internal and laser-trimmed.
0.1µF
+13V
8
INVERTING
INPUT
7
+V
0.1µF
1
S
3
2
50kꢀ
–IN
10kꢀ
SENSE
OUT
2
5
6
AD8620
1/2
+5V
V
OUT
0.1µF
0.1µF
V
REF
7
50kꢀ
+IN
20kꢀ
REF2
REF1
6
5
3
8
1
AD8620
2/2
+V
S
7
20kꢀ
50kꢀ
–IN
10kꢀ
2
5
NON-
INVERTING
INPUT
0.1µF
SENSE
AD8275 –V
VCC
ADC
S
4
33ꢀ
4
+IN
–IN
+15V
–13V
OUT
6
0.1µF
0.1µF
2.7nF
REF GND
Figure 41. Adding Op Amp Buffers for High Input Impedance
50kꢀ
+IN
20kꢀ
20kꢀ
3
8
1
IN-AMP
REF2
REF1
AC COUPLING
VREF
10µF
An integrator can be tied to the AD8275 in feedback to create a
high-pass filter as shown in Figure 42. This circuit can be used
to reject dc voltages and offsets. At low frequencies, the impedance
of the capacitor, C, is high. Thus, the gain of the integrator is
high. DC voltage at the output of the AD8275 is inverted and
gained by the integrator. The inverted signal is injected back
into the REFx pins, nulling the output. In contrast, at high fre-
quencies, the integrator has low gain because the impedance of
C is low. Voltage changes at high frequencies are inverted but at
a low gain. The signal is injected into the REFx pins but it is not
enough to null the output. High frequency signals are, therefore,
allowed to pass.
–15V
AD8275 –V
S
4
Figure 43. Level Translation in a Data Acquisition System
When a signal exceeds fHIGH-PASS, the AD8275 outputs the
conditioned input signal.
+5V
0.1µF
7
+V
S
50kꢀ
–IN
10kꢀ
1
2
5
6
f
=
HIGH-PASS
2πRC
SENSE
OUT
V
OUT
R
C
50kꢀ
+IN
20kꢀ
20kꢀ
3
8
1
REF2
REF1
OP
AMP
AD8275 –V
S
V
4
REF
0.1µF
+5V
Figure 42. AC-Coupled Level Translator
Rev. 0 | Page 15 of 16
AD8275
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 44. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
8-Lead MSOP
8-Lead MSOP, Tape and Reel
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP
Package Option
RM-8
RM-8
RM-8
RM-8
Branding
Y13
Y13
Y13
Y1V
AD8275ARMZ1
AD8275ARMZ-R71
AD8275ARMZ-RL1
AD8275BRMZ1
AD8275BRMZ-R71
AD8275BRMZ-RL1
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
8-Lead MSOP, Tape and Reel
8-Lead MSOP, 13" Tape and Reel
RM-8
RM-8
Y1V
Y1V
1 Z = RoHS Compliant Part.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07546-0-10/08(0)
Rev. 0 | Page 16 of 16
相关型号：
©2020 ICPDF网 联系我们和版权申明