AD8251ARMZ-RL_技术文档

10 MHz, 20 V/μs, G = 1, 2, 4, 8 iCMOS^®

Programmable Gain Instrumentation Amplifier

AD8251

FEATURES

FUNCTIONAL BLOCK DIAGRAM

DGND WR

A1

5

A0

4

Small package: 10-lead MSOP

Programmable gains: 1, 2, 4, 8

Digital or pin-programmable gain setting

Wide supply: 5 V to 15 V

2

6

LOGIC

1

–IN

Excellent dc performance

High CMRR: 98 dB (minimum), G = 8

Low gain drift: 10 ppm/°C (maximum)

Low offset drift: 1.8 μV/°C (maximum), G = 8

Excellent ac performance

7

OUT

10

+IN

Fast settling time: 785 ns to 0.001% (maximum)

High slew rate: 20 V/ꢀs (minimum)

Low distortion: −110 dB THD at 1 kHz,10 V swing

High CMRR over frequency: 80 dB to 50 kHz (minimum)

Low noise: 18 nV/√Hz, G = 10 (maximum)

Low power: 4 mA

AD8251

8

3

–V

9

+V

REF

S

Figure 1.

25

APPLICATIONS

20

15

10

5

G = 8

G = 4

Data acquisition

Biomedical analysis

Test and measurement

G = 2

G = 1

GENERAL DESCRIPTION

The AD8251 is an instrumentation amplifier with digitally

programmable gains that has GΩ input impedance, low output

noise, and low distortion, making it suitable for interfacing with

sensors and driving high sample rate analog-to-digital converters

(ADCs). It has high bandwidth of 10 MHz, low THD of −110 dB,

and fast settling time of 785 ns (maximum) to 0.001%. Offset

drift and gain drift are guaranteed to 1.8 μV/°C and 10 ppm/°C,

respectively, for G = 8. In addition to its wide input common

voltage range, it boasts a high common-mode rejection of 80 dB

at G = 1 from dc to 50 kHz. The combination of precision dc

performance coupled with high speed capabilities makes the

AD8251 an excellent candidate for data acquisition. Furthermore,

this monolithic solution simplifies design and manufacturing

and boosts performance of instrumentation by maintaining a

tight match of internal resistors and amplifiers.

0

–5

–10

1k

100M

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 2. Gain vs. Frequency

Table 1. Instrumentation and Difference Amplifiers

by Category

High

Low

High

Mil

Low

Digital

Gain

AD627¹AD8231¹

Performance Cost

Voltage Grade Power

AD8220¹

AD8221

AD8222

AD8224¹

AD623¹

AD8553¹

AD628

AD629

AD620

AD621

AD524

AD526

AD624

AD8250

AD8555¹

AD8556¹

AD8557¹

The AD8251 user interface consists of a parallel port that allows

users to set the gain in one of two different ways (see Figure 1

for the functional block diagram). A 2-bit word sent via a bus

¹Rail-to-rail output.

WR

can be latched using the

input. An alternative is to use

The AD8251 is available in a 10-lead MSOP package and is

specified over the −40°C to +85°C temperature range, making it

an excellent solution for applications where size and packing

density are important considerations.

transparent gain mode where the state of logic levels at the gain

port determines the gain.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD8251

TABLE OF CONTENTS

Features .............................................................................................. 1

Power Supply Regulation and Bypassing ................................ 18

Input Bias Current Return Path ............................................... 18

Input Protection ......................................................................... 18

Reference Terminal .................................................................... 19

Common-Mode Input Voltage Range..................................... 19

Layout .......................................................................................... 19

RF Interference ........................................................................... 19

Driving an Analog-to-Digital Converter ................................ 20

Applications..................................................................................... 21

Differential Output .................................................................... 21

Setting Gains with a Microcontroller ...................................... 21

Data Acquisition......................................................................... 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 23

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Diagram ........................................................................... 5

Absolute Maximum Ratings............................................................ 6

Maximum Power Dissipation ..................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 16

Gain Selection............................................................................. 16

REVISION HISTORY

5/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD8251

SPECIFICATIONS

+V_S= +15 V, −V_S= −15 V, V_REF= 0 V @ T_A= 25°C, G = 1, R_L= 2 kΩ, unless otherwise noted.

Table 2.

Parameter

Conditions

Min

Typ

Max

Unit

COMMON-MODE REJECTION RATIO (CMRR)

CMRR to 60 Hz with 1 kΩ Source Imbalance

+IN = −IN = −10 V to +10 V

G = 1

G = 2

G = 4

G = 8

80

86

92

98

94

dB

104

105

CMRR to 50 kHz

+IN = −IN = −10 V to +10 V

G = 1

G = 2

G = 4

G = 8

80

84

86

dB

NOISE

Voltage Noise, 1 kHz, RTI

G = 1

G = 2

G = 4

G = 8

40

27

22

18

nV/√Hz

0.1 Hz to 10 Hz, RTI

G = 1

G = 2

G = 4

G = 8

2.5

1.8

1.2

μV p-p

pA/√Hz

pA p-p

Current Noise, 1 kHz

Current Noise, 0.1 Hz to 10 Hz

VOLTAGE OFFSET

Offset RTI V_OS

5

60

G = 1, 2, 4, 8

200 + 600/G

μV

Over Temperature

Average TC

T = −40°C to +85°C

V_S= 5 V to 15 V

260 + 900/G

1.2 + 5/G

6 + 20/G

μV

μV/°C

μV/V

Offset Referred to the Input vs. Supply (PSR)

INPUT CURRENT

Input Bias Current

Over Temperature

Average TC

Input Offset Current

Over Temperature

Average TC

5

30

40

400

30

nA

pA/°C

nA

T = −40°C to +85°C

160

pA/°C

DYNAMIC RESPONSE

Small Signal −3 dB Bandwidth

G = 1

10

8

MHz

G = 2

G = 4

G = 8

2.5

Settling Time 0.01%

G = 1

G = 2

G = 4

G = 8

ΔOUT = 10 V step

615

460

625

ns

Rev. 0 | Page 3 of 24

AD8251

Parameter

Conditions

Min

Typ

Max

Unit

Settling Time 0.001%

ΔOUT = 10 V step

G = 1

G = 2

G = 4

G = 8

785

700

770

ns

Slew Rate

G = 1

G = 2

G = 4

G = 8

20

30

V/μs

dB

Total Harmonic Distortion + Noise

f = 1 kHz, R_L= 10 kΩ, 10V,

G = 1, 10 Hz to 22 kHz band-

pass filter

−110

GAIN

Gain Range

Gain Error

G = 1, 2, 4, 8

OUT = 10 V

1

8

V/V

G = 1

G = 2, 4, 8

0.03

0.04

%

Gain Nonlinearity

G = 1

G = 2

G = 4

G = 8

OUT = −10 V to +10 V

R_L= 10 kΩ, 2 kΩ, 600 Ω

All gains

9

ppm

12

15

10

Gain vs. Temperature

INPUT

3

ppm/°C

Input Impedance

Differential

1||2pF

GΩ||pF

Common Mode

Input Operating Voltage Range

Over Temperature

OUTPUT

GΩ||pF

V

V_S= 5 V to 15 V

T = −40°C to +85°C

−V_S+ 1.5

−V_S+ 1.6

+V_S− 1.5

+V_S− 1.7

Output Swing

Over Temperature

Short-Circuit Current

REFERENCE INPUT

R_IN

−13.5

+13.5

V

mA

T = −40°C to +85°C

+IN, −IN, REF = 0

37

20

kΩ

μA

V

I_IN

1

+V_S

Voltage Range

Gain to Output

DIGITAL LOGIC

Digital Ground Voltage, DGND

Digital Input Voltage Low

Digital Input Voltage High

Digital Input Current

Gain Switching Time¹

t_SU

−V_S

1

0

0.0001

V/V

Referred to GND

−V_S+ 4.25

DGND

2.8

+V_S− 2.7

2.1

+V_S

V

μA

ns

1

325

See Figure 3 timing diagram

20

10

20

40

t_HD

t _{WR -LOW}

t _{WR -HIGH}

Rev. 0 | Page 4 of 24

AD8251

Parameter

Conditions

Min

Typ

Max

Unit

POWER SUPPLY

Operating Range

Quiescent Current, +I_S

Quiescent Current, −I_S

Over Temperature

TEMPERATURE RANGE

Specified Performance

5

15

4.5

V

4.1

3.7

mA

T = −40°C to +85°C

−40

+85

°C

¹Add time for the output to slew and settle to calculate the total time for a gain change.

TIMING DIAGRAM

t_WR-HIGH

t_WR-LOW

WR

t_SU

t_HD

A0, A1

Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)

Rev. 0 | Page 5 of 24

AD8251

ABSOLUTE MAXIMUM RATINGS

package due to the load drive for all outputs. The quiescent

power is the voltage between the supply pins (V_S) times the

quiescent current (I_S). Assuming the load (R_L) is referenced to

midsupply, the total drive power is V_S/2 × I_OUT, some of which is

dissipated in the package and some in the load (V_OUT× I_OUT).

Table 3.

Parameter

Rating

17 V

Supply Voltage

Power Dissipation

See Figure 4

Indefinite¹

V_S

Output Short-Circuit Current

Common-Mode Input Voltage

Differential Input Voltage

Digital Logic Inputs

The difference between the total drive power and the load

power is the drive power dissipated in the package.

P_D= Quiescent Power + (Total Drive Power − Load Power)

Storage Temperature Range

Operating Temperature Range²

Lead Temperature (Soldering 10 sec)

Junction Temperature

–65°C to +125°C

–40°C to +85°C

300°C

2

⎛

⎜

⎝

⎞

⎟

⎠

V_SV_OUT

V_OUT

R_L

P_D

=

(

V_S× I_S

)

+

×

–

2

R_L

140°C

In single-supply operation with R_Lreferenced to −V_S, the worst

case is V_OUT= V_S/2.

θ_JA(4-Layer JEDEC Standard Board)

Package Glass Transition Temperature

112°C/W

140°C

Airflow increases heat dissipation, effectively reducing θ_JA. In

addition, more metal directly in contact with the package leads

from metal traces, through holes, ground, and power planes

reduces the θ_JA.

¹Assumes the load is referenced to midsupply.

²Temperature for specified performance is −40°C to +85°C. For performance

to +125°C, see the Typical Performance Characteristics section.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Figure 4 shows the maximum safe power dissipation in the

package vs. the ambient temperature on a 4-layer JEDEC

standard board.

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8251 package is

limited by the associated rise in junction temperature (T_J) on

the die. The plastic encapsulating the die locally reaches the

junction temperature. At approximately 140°C, which is the

glass transition temperature, the plastic changes its properties.

Even temporarily exceeding this temperature limit can change

the stresses that the package exerts on the die, permanently

shifting the parametric performance of the AD8251. Exceeding

a junction temperature of 140°C for an extended period can

result in changes in silicon devices, potentially causing failure.

–40

–20

0

20

40

60

80

100

120

AMBIENT TEMPERATURE (°C)

Figure 4. Maximum Power Dissipation vs. Ambient Temperature

ESD CAUTION

The still-air thermal properties of the package and PCB (θ_JA),

the ambient temperature (T_A), and the total power dissipated in

the package (P_D) determine the junction temperature of the die.

The junction temperature is calculated as

T_J= T_A

+

(

P_D× θ_JA

)

The power dissipated in the package (P_D) is the sum of the

quiescent power dissipation and the power dissipated in the

Rev. 0 | Page 6 of 24

AD8251

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

–IN

1

2

3

4

5

10

9

+IN

DGND

REF

AD8251

TOP VIEW

(Not to Scale)

–V

8

+V

S

A0

A1

7

OUT

WR

6

Figure 5. 10-Lead MSOP (RM-10) Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

3

4

−IN

DGND

−V_S

Inverting Input Terminal. True differential input.

Digital Ground.

Negative Supply Terminal.

Gain Setting Pin (LSB).

A0

5

A1

Gain Setting Pin (MSB).

6

WR

Write Enable.

7

8

9

10

OUT

+V_S

REF

Output Terminal.

Positive Supply Terminal.

Reference Voltage Terminal.

Noninverting Input Terminal. True differential input.

+IN

Rev. 0 | Page 7 of 24

AD8251

TYPICAL PERFORMANCE CHARACTERISTICS

T_A@ 25°C, +V_S= +15 V, −V_S= −15 V, R_L= 10 kꢀ, unless otherwise noted.

2700

2400

2100

1800

1500

1200

900

800

700

600

500

400

300

200

100

0

600

300

0

–30

–20

–10

0

10

20

30

–120

–90

–60

–30

0

30

60

90

120

INPUT OFFSET CURRENT (nA)

CMRR (µV/V)

Figure 9. Typical Distribution of Input Offset Current

Figure 6. Typical Distribution of CMRR, G = 1

90

80

70

60

50

40

30

20

10

0

500

400

300

200

100

0

G = 1

G = 2

G = 4

G = 8

–200

–100

0

100

200

1

100k

10

100

1k

10k

INPUT OFFSET VOLTAGE, V

, RTI (µV)

OSI

FREQUENCY (Hz)

Figure 7. Typical Distribution of Offset Voltage, V_OSI

Figure 10. Voltage Spectral Density Noise vs. Frequency

800

600

400

200

0

2µV/DIV

1s/DIV

–30

–20

–10

0

10

20

30

INPUT BIAS CURRENT (nA)

Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1

Figure 8. Typical Distribution of Input Bias Current

Rev. 0 | Page 8 of 24

AD8251

150

130

110

90

G = 4

G = 2

G = 1

70

G = 8

50

30

1.25µV/DIV

1s/DIV

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 8

Figure 15. Positive PSRR vs. Frequency, RTI

150

130

110

90

18

16

14

12

10

8

G = 4

G = 8

G = 1

70

6

50

4

G = 2

30

2

10

0

100

1k

10k

100k

1M

1

100k

10

100

1k

10k

FREQUENCY (Hz)

Figure 13. Current Noise Spectral Density vs. Frequency

Figure 16. Negative PSRR vs. Frequency, RTI

20

15

10

5

I

+

B

I

–

B

0

I

OS

–5

–10

140pA/DIV

1s/DIV

–60 –40 –20

0

20

40

60

80

100 120 140

TEMPERATURE (ºC)

Figure 14. 0.1 Hz to 10 Hz Current Noise

Figure 17. Input Bias Current and Offset Current vs. Temperature

Rev. 0 | Page 9 of 24

AD8251

140

120

100

80

25

20

15

10

5

V

R

= ±15V

S

G = 4

G = 8

= 200m Vp-p

= 2kΩ

IN

G = 8

G = 4

LOAD

G = 2

G = 1

0

60

–5

–10

40

10

100

1k

10k

100k

1M

130

1k

100M

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 18. CMRR vs. Frequency

Figure 21. Gain vs. Frequency

140

120

100

40

30

20

G = 8

10

G = 4

0

G = 2

80

60

40

G = 1

–10

–20

–30

–40

–10

–8

–6

–4

–2

0

2

4

6

8

10

100

1k

10k

100k

OUTPUT VOLTAGE (V)

FREQUENCY (Hz)

Figure 19. CMRR vs. Frequency, 1 kΩ Source Imbalance

Figure 22. Gain Nonlinearity, G = 1, R_L= 10 kΩ, 2 kΩ, 600 Ω

40

30

20

15

10

5

10

0

–10

–5

–10

–15

–20

–30

–40

–10

–8

–6

–4

–2

0

2

4

6

8

10

–50

–30

–10

10

30

50

70

90

110

OUTPUT VOLTAGE (V)

TEMPERATURE (°C)

Figure 23. Gain Nonlinearity, G = 2, R_L= 10 kΩ, 2 kΩ, 600 Ω

Figure 20. CMRR vs. Temperature, G = 1

Rev. 0 | Page 10 of 24

AD8251

16

12

8

40

30

20

–13V, +13.5V

0V, +13.5V

±15V

+13V, +13V

V

S

0V, +4V

–4V, +4V

+4V, +3.9V

4

10

0

V = ±5V

S

–10

–4

–8

–12

–16

–4V, –3.9V 0V, –3.9V +4V, –4V

–20

–30

–40

–13V, –13.1V

0V, –13.5V

0

+13V, –13.5V

16

–10

–8

–6

–4

–2

0

2

4

6

8

10

–16

–12

–8

–4

4

8

12

OUTPUT VOLTAGE (V)

Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G = 8

Figure 24. Gain Nonlinearity, G = 4, R_L= 10 kΩ, 2 kΩ, 600 Ω

+V

S

40

30

20

+85°C

+125°C

–40°C

–1

–2

+25°C

10

0

–10

+2

+1

–40°C

–20

+25°C

–30

–40

+125°C

+85°C

12

–V

S

–10

–8

–6

–4

–2

0

2

4

6

8

10

4

16

6

8

10

14

OUTPUT VOLTAGE (V)

SUPPLY VOLTAGE (±V )

S

Figure 25. Gain Nonlinearity, G = 8, R_L= 10 kΩ, 2 kΩ, 600 Ω

Figure 28. Input Voltage Limit vs. Supply Voltage, G = 1, V_REF= 0 V, R_L= 10 kΩ

16

15

0V, +13.5V

+V

S

12

8

–14.2V, +7.1V

+14V, +7V

0V, ±15V

10

5

FAULT CONDITION

(OVER DRIVEN INPUT)

G = 8

FAULT CONDITION

(OVER DRIVEN INPUT)

G = 8

0V, +3.85V

–4V, +2.2V

+4V, +2V

+4V, –2V

4

+IN

–IN

0

V = ±5V

S

0

–4V, –2V

–4

–8

–12

–16

0V, –3.9V

–5

–10

–15

–V

S

–14.2V, –7.1V

–12

+14V, –7V

12

0V, –13.5V

0

–16

16

–8

–4

4

8

–16

–12

–8

–4

0

4

8

12

16

OUTPUT VOLTAGE (V)

DIFFERENTIAL INPUT VOLTAGE (V)

Figure 26. Input Common-Mode Voltage Range vs. Output Voltage, G = 1

Figure 29. Fault Current Draw vs. Input Voltage, G = 8, R_L= 10 kΩ

Rev. 0 | Page 11 of 24

AD8251

+V

S

–0.2

–0.4

–0.6

–0.8

–1.0

+85°C

–0.4

–0.8

–1.2

–1.6

–2.0

+2.0

+1.6

+1.2

+0.8

+0.4

+125°C

+25°C

–40°C

+25°C

–40°C

+1.0

+0.8

+0.6

+0.4

+0.2

+25°C

+125°C

+85°C

–V

S

4

16

4

16

6

8

10

12

14

6

8

10

12

14

SUPPLY VOLTAGE (±V )

OUTPUT CURRENT (mA)

S

Figure 30. Output Voltage Swing vs. Supply Voltage, G = 8, R_L= 2 kΩ

Figure 33. Output Voltage Swing vs. Output Current

+V

S

100pF

–0.2

–0.4

–0.6

–0.8

–1.0

NO

LOAD

+125°C

47pF

+85°C

–40°C

+25°C

+1.0

+0.8

+0.6

+0.4

+0.2

+25°C +85°C

+125°C

20mV/DIV

2µs/DIV

–V

S

4

16

6

8

10

12

14

SUPPLY VOLTAGE (±V )

S

Figure 31. Output Voltage Swing vs. Supply Voltage, G = 8, R_L= 10 kΩ

Figure 34. Small Signal Pulse Response for Various Capacitive Loads

15

+25°C

+85°C

10

5

–40°C

+125°C

5V/DIV

0

585ns TO 0.01%

723ns TO 0.001%

–5

–10

–15

0.002%/DIV

+125°C

+85°C

–40°C

+25°C

2µs/DIV

100

10k

1k

LOAD RESISTANCE (Ω)

Figure 32. Output Voltage Swing vs. Load Resistance

Figure 35. Large Signal Pulse Response and Settling Time, G = 1, R_L= 10 kΩ

Rev. 0 | Page 12 of 24

AD8251

5V/DIV

400ns TO 0.01%

600ns TO 0.001%

0.002%/DIV

2µs/DIV

25mV/DIV

2µs/DIV

Figure 39. Small Signal Response,

G = 1, R_L= 2 kΩ, C_L= 100 pF

Figure 36. Large Signal Pulse Response and Settling Time,

G = 2, R_L= 10 kΩ

5V/DIV

376ns TO 0.01%

640ns TO 0.001%

0.002%/DIV

2µs/DIV

25mV/DIV

2µs/DIV

Figure 40. Small Signal Response,

G = 2, R_L= 2 kΩ, C_L= 100 pF

Figure 37. Large Signal Pulse Response and Settling Time,

G = 4, R_L= 10 kΩ

5V/DIV

364ns TO 0.01%

522ns TO 0.001%

0.002%/DIV

2µs/DIV

25mV/DIV

2µs/DIV

Figure 38. Large Signal Pulse Response and Settling Time,

G = 8, R_L= 10 kΩ

Figure 41. Small Signal Response,

G = 4, R_L= 2 kΩ, C_L= 100 pF

Rev. 0 | Page 13 of 24

AD8251

1200

1000

800

600

400

200

0

SETTLED TO 0.001%

SETTLED TO 0.01%

25mV/DIV

2µs/DIV

2

20

4

6

8

10

12

14

16

18

STEP SIZE (V)

Figure 42. Small Signal Response, G = 8, R_L= 2 kΩ, C_L= 100 pF

Figure 45. Settling Time vs. Step Size, G = 4, R_L= 10 kΩ

1200

1000

1200

1000

800

600

400

200

0

SETTLED TO 0.001%

800

SETTLED TO 0.001%

SETTLED TO 0.01%

600

SETTLED TO 0.01%

400

200

0

2

20

4

6

8

10

12

14

16

18

2

20

4

6

8

10

12

14

16

18

STEP SIZE (V)

Figure 43. Settling Time vs. Step Size, G = 1, R_L= 10 kΩ

Figure 46. Settling Time vs. Step Size, G = 8, R_L= 10 kΩ

1200

1000

800

600

400

200

0

–50

–55

–60

–65

–70

–75

–80

SETTLED TO 0.001%

–85

G = 8

–90

G = 4

–95

SETTLED TO 0.01%

–100

–105

–110

–115

–120

G = 2

G = 1

2

20

4

6

8

10

12

14

16

18

10

1M

100

1k

10k

100k

STEP SIZE (V)

FREQUENCY (Hz)

Figure 44. Settling Time vs. Step Size, G = 2, R_L= 10 kΩ

Figure 47. Total Harmonic Distortion vs. Frequency,

10 Hz to 22 kHz Band-Pass Filter, 2 kΩ Load

Rev. 0 | Page 14 of 24

AD8251

–50

–55

–60

–65

–70

–75

–80

G = 8

G = 4

–85

G = 2

–90

–95

–100

–105

–110

–115

–120

G = 1

1k

10

100

10k

100k

1M

FREQUENCY (Hz)

Figure 48. Total Harmonic Distortion vs. Frequency,

10 Hz to 500 kHz Band-Pass Filter, 2 kΩ Load

Rev. 0 | Page 15 of 24

AD8251

THEORY OF OPERATION

+V

–V

+V

–V

S

A0

A1

2.2kΩ

+V

–V

S

2.2kΩ

–IN

10kΩ

A1

S

+V

S

DIGITAL

GAIN

OUT

REF

A3

CONTROL

–V

+V

S

+V

–V

S

10kΩ

A2

+IN

2.2kΩ

–V

S

+V

–V

+V

S

2.2kΩ

DGND

WR

–V

S

Figure 49. Simplified Schematic

The AD8251 is a monolithic instrumentation amplifier based

on the classic, three op amp topology, as shown in Figure 49.

It is fabricated on the Analog Devices, Inc. proprietary iCMOS

process that provides precision, linear performance, and a robust

digital interface. A parallel interface allows users to digitally

program gains of 1, 2, 4, and 8. Gain control is achieved by

switching resistors in an internal, precision, resistor array (as

shown in Figure 49). Although the AD8251 has a voltage feed-

back topology, gain bandwidth product increases for gains of 1,

2, and 4 because each gain has its own frequency compensation.

This results in maximum bandwidth at higher gains.

Transparent Gain Mode

The easiest way to set the gain is to program it directly via a

logic high or logic low voltage applied to A0 and A1. Figure 50

shows an example of this gain setting method, referred to through-

WR

out the data sheet as transparent gain mode. Tie

to the

negative supply to engage transparent gain mode. In this mode,

any change in voltage applied to A0 and A1 from logic low to

logic high, or vice versa, immediately results in a gain change.

Table 5 is the truth table for transparent gain mode, and Figure 50

shows the AD8251 configured in transparent gain mode.

+15V

All internal amplifiers employ distortion cancellation circuitry

and achieve high linearity and ultralow THD. Laser trimmed

resistors allow for a maximum gain error of less than 0.03% for

G = 1 and minimum CMRR of 98 dB for G = 8. A pinout opti-

mized for high CMRR over frequency enables the AD8251 to

offer a guaranteed minimum CMRR over frequency of 80 dB at

50 kHz (G = 1). The balanced input reduces the parasitics that,

in the past, had adversely affected CMRR performance.

10μF

0.1µF

WR

–15V

+5V

A1

A0

+IN

+5V

G = 8

AD8251

REF

–IN

DGND

GAIN SELECTION

10μF

0.1µF

This section shows users how to configure the AD8251 for

basic operation. Logic low and logic high voltage limits are

listed in the Specifications section. Typically, logic low is 0 V

and logic high is 5 V; both voltages are measured with respect

to DGND. Refer to the specifications table (Table 2) for the

permissible voltage range of DGND. The gain of the AD8251

can be set using two methods.

–15V

NOTE:

1. IN TRANSPARENT GAIN MODE, WR IS TIED TO −V .

S

THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE

THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE

SET TO LOGIC HIGH, RESULTING IN A GAIN OF 8.

Figure 50. Transparent Gain Mode, A0 and A1 = High, G = 8

Rev. 0 | Page 16 of 24

AD8251

Table 5. Truth Table Logic Levels for Transparent Gain Mode

Table 6. Truth Table Logic Levels for Latched Gain Mode

WR

A1

A0

Gain

WR

A1

A0

Gain

−V_S

Low

High

Low

High

Low

High

1

2

4

8

High to Low

Low to Low

Low to High

High to High

Low

High

X¹

Low

High

Low

High

X¹

Change to 1

Change to 2

Change to 4

Change to 8

No Change

X¹

Latched Gain Mode

X¹

Some applications have multiple programmable devices such as

multiplexers or other programmable gain instrumentation

amplifiers on the same PCB. In such cases, devices can share a

data bus. The gain of the AD8251 can be set using

allowing other devices to share A0 and A1. Figure 51 shows a

schematic using this method, known as latched gain mode. The

¹X = don’t care.

On power-up, the AD8251 defaults to a gain of 1 when in

latched gain mode. In contrast, if the AD8251 is configured in

transparent gain mode, it starts at the gain indicated by the

voltage levels on A0 and A1 on power-up.

WR

as a latch,

WR

AD8251 is in this mode when

low, typically 5 V and 0 V, respectively. The voltages on A0 and

WR

is held at logic high or logic

Timing for Latched Gain Mode

A1 are read on the downward edge of the

signal as it

In latched gain mode, logic levels at A0 and A1 have to be held

for a minimum setup time, t_SU, before the downward edge of

transitions from logic high to logic low. This latches in the logic

levels on A0 and A1, resulting in a gain change. See the truth

table listing in Table 6 for more on these gain changes.

+15V

WR

latches in the gain. Similarly, they must be held for a

WR

minimum hold time of t_HDafter the downward edge of

to

ensure that the gain is latched in correctly. After t_HD, A0 and A1

may change logic levels but the gain does not change (until the

next downward edge of

can be held high is t _WR-HIGH, and t _WR-LOWis the minimum

WR

+5V

0V

WR

A1

10μF

0.1µF

WR WR

+5V

0V

A1

). The minimum duration that

+5V

0V

A0

+IN

WR

duration that

can be held low. Digital timing specifications

+

–

G = PREVIOUS G = 8

STATE

are listed in Table 2. The time required for a gain change is

dominated by the settling time of the amplifier. A timing

diagram is shown in Figure 52.

AD8251

REF

–IN

When sharing a data bus with other devices, logic levels applied

to those devices can potentially feed through to the output of

the AD8251. Feedthrough can be minimized by decreasing the

edge rate of the logic signals. Furthermore, careful layout of the

PCB also reduces coupling between the digital and analog

portions of the board.

DGND

10μF

0.1µF

–15V

NOTE:

1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS

FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0

AND A1 ARE READ AND LATCHED IN, RESULTING IN A

GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 8.

Figure 51. Latched Gain Mode, G = 8

t_WR-HIGH

t_WR-LOW

WR

t_SU

t_HD

A0, A1

Figure 52. Timing Diagram for Latched Gain Mode

Rev. 0 | Page 17 of 24

AD8251

INCORRECT

+V

CORRECT

+V

POWER SUPPLY REGULATION AND BYPASSING

S

The AD8251 has high PSRR. However, for optimal performance,

a stable dc voltage should be used to power the instrumentation

amplifier. Noise on the supply pins can adversely affect per-

formance. As in all linear circuits, bypass capacitors must be

used to decouple the amplifier.

AD8251

REF

Place a 0.1 ꢁF capacitor close to each supply pin. A 10 ꢁF tanta-

lum capacitor can be used farther away from the part (see

Figure 53) and, in most cases, it can be shared by other

precision integrated circuits.

–V

S

TRANSFORMER

+V

TRANSFORMER

+V

S

+V

S

0.1µF

WR

A1

10µF

AD8251

A0

+IN

–IN

REF

V

OUT

10Mꢀ

AD8251

LOAD

–V

S

REF

THERMOCOUPLE

DGND

+V

S

0.1µF

10µF

C

–V

DGND

S

R

1

f_HIGH-PASS

=

Figure 53. Supply Decoupling, REF, and Output Referred to Ground

AD8251

2πRC

AD8251

C

REF

INPUT BIAS CURRENT RETURN PATH

R

The AD8251 input bias current must have a return path to its

local analog ground. When the source, such as a thermocouple,

cannot provide a return current path, one should be created

(see Figure 54).

–V

S

–V

S

CAPACITIVELY COUPLED

Figure 54. Creating an I_BIASPath

INPUT PROTECTION

All terminals of the AD8251 are protected against ESD. Note

that 2.2 kꢀ series resistors precede the ESD diodes as shown in

Figure 49. They limit current into the diodes and allow for dc

overload conditions 13 V above the positive supply and 13 V

below the negative supply. An external resistor should be used

in series with each of the inputs to limit current for voltages

greater than 13 V beyond either supply rail. In either scenario,

the AD8251 safely handles a continuous 6 mA current at room

temperature. For applications where the AD8251 encounters

extreme overload voltages, external series resistors and low

leakage diode clamps such as BAV199Ls, FJH1100s, or SP720s

should be used.

Rev. 0 | Page 18 of 24

AD8251

Coupling Noise

REFERENCE TERMINAL

To prevent coupling noise onto the AD8251, follow these

guidelines:

The reference terminal, REF, is at one end of a 10 kꢀ resistor

(see Figure 49). The instrumentation amplifier output is

referenced to the voltage on the REF terminal; this is useful

when the output signal needs to be offset to voltages other than

its local analog ground. For example, a voltage source can be

tied to the REF pin to level shift the output so that the AD8251

can interface with a single-supply ADC. The allowable reference

voltage range is a function of the gain, common-mode input,

and supply voltages. The REF pin should not exceed either +V_S

or −V_Sby more than 0.5 V.

•

Do not run digital lines under the device.

Run the analog ground plane under the AD8251.

Shield fast switching signals with digital ground to avoid

radiating noise to other sections of the board, and never

run them near analog signal paths.

•

Avoid crossover of digital and analog signals.

Connect digital and analog ground at one point only

(typically under the ADC).

For best performance, especially in cases where the output is

not measured with respect to the REF terminal, source imped-

ance to the REF terminal should be kept low because parasitic

resistance can adversely affect CMRR and gain accuracy.

•

Power supply lines should use large traces to ensure a low

impedance path. Decoupling is necessary; follow the

guidelines listed in the Power Supply Regulation and

Bypassing section.

INCORRECT

CORRECT

Common-Mode Rejection

AD8251

The AD8251 has high CMRR over frequency, giving it greater

immunity to disturbances, such as line noise and its associated

harmonics, in contrast to typical in amps whose CMRR falls off

around 200 Hz. They often need common-mode filters at the

inputs to compensate for this shortcoming. The AD8251 is able

to reject CMRR over a greater frequency range, reducing the

need for input common-mode filtering.

V

REF

V

REF

+

OP1177

–

Figure 55. Driving the Reference Pin

Careful board layout maximizes system performance. To

maintain high CMRR over frequency, lay out the input traces

symmetrically. Ensure that the traces maintain resistive and

capacitive balance; this holds for additional PCB metal layers

under the input pins and traces. Source resistance and capaci-

tance should be placed as close to the inputs as possible. Should

a trace cross the inputs (from another layer), it should be routed

perpendicular to the input traces.

COMMON-MODE INPUT VOLTAGE RANGE

The three op amp architecture of the AD8251 applies gain and

then removes the common-mode voltage. Therefore, internal

nodes in the AD8251 experience a combination of both the

gained signal and the common-mode signal. This combined

signal can be limited by the voltage supplies even when the

individual input and output signals are not. Figure 26 and

Figure 27 show the allowable common-mode input voltage

ranges for various output voltages, supply voltages, and gains.

RF INTERFERENCE

RF rectification is often a problem when amplifiers are used in

applications where there are strong RF signals. The disturbance

can appear as a small dc offset voltage. High frequency signals

can be filtered with a low-pass, RC network placed at the input

of the instrumentation amplifier, as shown in Figure 56. The

filter limits the input signal bandwidth according to the

following relationship:

LAYOUT

Grounding

In mixed-signal circuits, low level analog signals need to be

isolated from the noisy digital environment. Designing with the

AD8251 is no exception. Its supply voltages are referenced to an

analog ground. Its digital circuit is referenced to a digital ground.

Although it is convenient to tie both grounds to a single ground

plane, the current traveling through the ground wires and PC

board can cause an error. Therefore, use separate analog and

digital ground planes. Only at one point, star ground, should

analog and digital ground meet.

1

FilterFreq_DIFF

=

2 π R(2C_D+ C_C)

1

FilterFreq_CM

=

2 π RC_C

The output voltage of the AD8251 develops with respect to the

potential on the reference terminal. Take care to tie REF to the

appropriate local analog ground or to connect it to a voltage that

is referenced to the local analog ground.

where C_D≥ 10 C_C.

Rev. 0 | Page 19 of 24

AD8251

+15V

In this example, a 1 nF capacitor and a 49.9 Ω resistor create an

antialiasing filter for the AD7612. The 1 nF capacitor also serves

to store and deliver necessary charge to the switched capacitor

input of the ADC. The 49.9 ꢀ series resistor reduces the burden

of the 1 nF load from the amplifier and isolates it from the

kickback current injected from the switched capacitor input of

the AD7612. Selecting too small a resistor improves the

correlation between the voltage at the output of the AD8251

and the voltage at the input of the AD7612 but may destabilize

the AD8251. A trade-off must be made between selecting a

resistor small enough to maintain accuracy and large enough to

maintain stability.

0.1µF

+IN

10µF

C

D

C

R

V

OUT

AD8251

REF

–IN

0.1µF

10µF

–15V

+15V

Figure 56. RFI Suppression

10μF

0.1µF

Values of R and C_Cshould be chosen to minimize RFI.

Mismatch between the R × C_Cat the positive input and the

R × C_Cat negative input degrades the CMRR of the AD8251.

By using a value of C_Dthat is 10 times larger than the value of

C_C, the effect of the mismatch is reduced and performance is

improved.

WR

+12V

0.1μF

–12V

0.1μF

A1

A0

+IN

49.9ꢀ

AD8251

AD7612

1nF

REF

+5V

ADR435

–IN

DRIVING AN ANALOG-TO-DIGITAL CONVERTER

DGND

An instrumentation amplifier is often used in front of an

analog-to-digital converter to provide CMRR. Usually,

instrumentation amplifiers require a buffer to drive an ADC.

However, the low output noise, low distortion, and low settle

time of the AD8251 make it an excellent ADC driver.

10μF

0.1µF

–15V

Figure 57. Driving an ADC

Rev. 0 | Page 20 of 24

AD8251

APPLICATIONS

When using this circuit to drive a differential ADC, V_REFcan be

set using a resistor divider from the ADC reference to make the

output ratiometric with the ADC.

DIFFERENTIAL OUTPUT

In certain applications, it is necessary to create a differential

signal. High resolution analog-to-digital converters often

require a differential input. In other cases, transmission over

a long distance can require differential signals for better

immunity to interference.

SETTING GAINS WITH A MICROCONTROLLER

+15V

10μF

0.1µF

Figure 59 shows how to configure the AD8251 to output a

differential signal. An op amp, the AD817, is used in an

inverting topology to create a differential voltage. V_REFsets the

output midpoint according to the equation shown in the figure.

Errors from the op amp are common to both outputs and are

thus common mode. Likewise, errors from using mismatched

resistors cause a common-mode dc offset error. Such errors are

rejected in differential signal processing by differential input

ADCs or instrumentation amplifiers.

WR

A1

MICRO-

CONTROLLER

A0

+IN

+

–

AD8251

REF

–IN

DGND

10μF

0.1µF

–15V

Figure 58. Programming Gain Using a Microcontroller

+12V

0.1μF

AMPLITUDE

WR

+5V

A1

A0

+IN

AMPLITUDE

–5V

+

V

A = V + V

IN REF

OUT

2

+2.5V

0V

–2.5V

AD8251

V

G = 1

IN

TIME

REF

–

4.99kꢀ

0.1μF

DGND

–12V

V

–

+

REF

0V

–12V

10pF

+12V

AD817

4.99kꢀ

AMPLITUDE

0.1µF

–12V

+12V

10μF

+2.5V

0V

–2.5V

10μF

DGND

V

B = –V + V

IN

OUT

REF

TIME

2

Figure 59. Differential Output with Level Shift

Rev. 0 | Page 21 of 24

AD8251

–70

–80

DATA ACQUISITION

The AD8251 makes an excellent instrumentation amplifier

for use in data acquisition systems. Its wide bandwidth, low

distortion, low settling time, and low noise enable it to

condition signals in front of a variety of 16-bit ADCs.

–90

–100

–110

–120

–130

–140

–150

–160

–170

–180

Figure 61 shows a schematic of the AD825x data acquisition

demonstration board. The quick slew rate of the AD8251 allows

it to condition rapidly changing signals from the multiplexed

inputs. An FPGA controls the AD7612, AD8251, and ADG1209.

In addition, mechanical switches and jumpers allow users to pin

strap the gains when in transparent gain mode.

This system achieved −106 dB of THD at 1 kHz and a signal-to-

noise ratio of 91 dB during testing, as shown in Figure 60.

0

50

5

10

15

20

25

30

35

40

45

FREQUENCY (kHz)

Figure 60. FFT of the AD825x DAQ Demo Board

Using the AD8251 1 kHz Signal

JMP

–V

S

+12V

–12V

+12V

14

+

+5V

0.1µF

10µF

2kꢀ

GND

2

V

DD

DGND

806ꢀ

EN

DGND

2

JMP

4

5

S1A

S2A

+CH1

+CH2

+5V

2kꢀ

DGND

806ꢀ

ALTERA

EPF6010ATC144-3

+CH3

+CH4

6

7

S3A

S4A

6

DGND

0ꢀ 0ꢀ

C

5

WR

DGND

VOUT

+IN

8

10

1

+

4

A1

ADG1209

S4B

+IN

A0

VREF

9

806ꢀ

7

AD7612

ADR435

AD8251

C

–CH4

10

11

12

D

0ꢀ 49.9ꢀ

–IN

1nF

806ꢀ

9

–V

3

–

S

S3B

S2B

–CH3

–CH2

–CH1

C

+V

8

C

S

15

A0

806ꢀ

S1B

1

A1

16

C4

0.1µF

C3

0.1µF

V

SS

3

+12V –12V

JMP

0.1µF

+5V

–12V

2kꢀ

DGND

JMP

+5V

R8

2kꢀ

DGND

Figure 61. Schematic of ADG1209, AD8251, and AD7612 in the AD825x DAQ Demo Board

Rev. 0 | Page 22 of 24

AD8251

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

6

5.15

4.90

4.65

3.10

3.00

2.90

1

5

PIN 1

0.50 BSC

0.95

0.85

0.75

1.10 MAX

0.80

0.60

0.40

8°

0°

0.15

0.05

0.33

0.17

SEATING

PLANE

0.23

0.08

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 62. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model

AD8251ARMZ¹

AD8251ARMZ-RL¹

AD8251ARMZ-R7¹

AD8251-EVALZ¹

Temperature Range

–40°C to +85°C

Package Description

10-Lead MSOP

Evaluation Board

Package Option

RM-10

Branding

H0T

–40°C to +85°C

RM-10

H0T

¹Z = RoHS Compliant Part.

Rev. 0 | Page 23 of 24

AD8251

NOTES

registered trademarks are the property of their respective owners.

D06287-0-5/07(0)

Rev. 0 | Page 24 of 24


型号：	AD8251ARMZ-RL
厂家：	ADI
描述：	10 MHz, 20 V/レs, G = 1, 2, 4, 8 i CMOS㈢ Programmable Gain Instrumentation Amplifier 10兆赫， 20 V /レS，G = 1 ， 2 ， 4 ， 8我CMOS㈢可编程增益仪表放大器仪表放大器
文件：	总24页 (文件大小：637K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD8251ARMZ-RL [ADI]

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