AD8042_07 [ADI]
Dual 160 MHz Rail-to-Rail Amplifier; 双160 MHz轨到轨放大器
| 型号： | AD8042_07 |
| 厂家： | 
ADI |
| 描述： | Dual 160 MHz Rail-to-Rail Amplifier |
| 文件： | 总16页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 160 MHz
Rail-to-Rail Amplifier
AD8042
CONNECTION DIAGRAM
FEATURES
Single AD8041 and quad AD8044 also available
Fully specified at +3 V, +5 V, and 5 V supplies
Output swings to within 30 mV of either rail
Input voltage range extends 200 mV below ground
No phase reversal with inputs 0.5 V beyond supplies
Low power of 5.2 mA per amplifier
High speed and fast settling on 5 V
160 MHz, −3 dB bandwidth (G = +1)
200 V/μs slew rate
39 ns settling time to 0.1%
Good video specifications (RL = 150 Ω, G = +2)
Gain flatness of 0.1 dB to 14 MHz
0.02% differential gain error
0.04° differential phase error
+V
1
2
3
4
8
7
6
5
S
OUT1
–IN1
+IN1
OUT2
–IN2
–V
S
+IN2
AD8042
Figure 2. 8-Lead PDIP and 8-Lead SOIC_N
The output voltage swing extends to within 30 mV of each rail,
providing the maximum output dynamic range. Additionally, it
features gain flatness of 0.1 dB to 14 MHz while offering differential
gain and phase error of 0.04% and 0.06° on a single 5 V supply.
This combination of features makes the AD8042 useful for
professional video electronics, such as cameras, video switchers,
or any high speed portable equipment. The low distortion and
fast settling of the AD8042 make it ideal for buffering single-
supply, high speed analog-to-digital converters (ADCs).
Low distortion: −64 dBc worst harmonic @ 10 MHz
Drives 50 mA 0.5 V from supply rails
APPLICATIONS
Video switchers
Distribution amplifiers
Analog-to-digital drivers
Professional cameras
The AD8042 offers a low power supply current of 12 mA
maximum and can run on a single 3.3 V power supply. These
features are ideally suited for portable and battery-powered
applications where size and power are critical.
CCD Imaging systems
Ultrasound equipment (multichannel)
The wide bandwidth of 160 MHz along with 200 V/μs of slew
rate on a single 5 V supply make the AD8042 useful in many
general-purpose, high speed applications where single supplies
from +3.3 V to +12 V and dual power supplies of up to 6 V are
needed. The AD8042 is available in 8-lead PDIP and 8-lead
SOIC_N packages.
GENERAL DESCRIPTION
The AD8042 is a low power voltage feedback, high speed amplifier
designed to operate on +3 V, +5 V, or 5 V supplies. It has true
single-supply capability with an input voltage range extending
200 mV below the negative rail and within 1 V of the positive rail.
15
V
= 5V
S
G = +1
12
9
C
R
= 5pF
= 2kΩ TO 2.5V
L
L
G = +1
6
R
= 2kΩ TO 2.5V
L
3
5.0V
2.5V
0V
0
–3
–6
–9
–12
–15
1
10
100
500
FREQUENCY (MHz)
1V
1µs
Figure 3. Frequency Response
Figure 1. Output Swing: Gain = +1, VS = +5 V
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD8042
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications Information.............................................................. 12
Circuit Description .................................................................... 12
Driving Capacitive Loads.......................................................... 12
Overdrive Recovery ................................................................... 12
Layout Considerations............................................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
General Description......................................................................... 1
Connection Diagram ....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Maximum Power Dissipation ..................................................... 6
ESD Caution.................................................................................. 6
REVISION HISTORY
12/07—Rev. D to Rev. E
Changes to Figure 1 Caption........................................................... 1
Changes to Table 1............................................................................ 3
Changes to Figure 5.......................................................................... 7
Changes to Figure 20........................................................................ 9
Changes to Layout and Figure 35................................................. 12
Changes to Figure 38...................................................................... 13
Changes to Single-Ended-to-Differential Driver Section......... 14
Updated Outline Dimensions....................................................... 16
3/06—Rev. C to Rev. D
Changes to Text Prior to Table 2..................................................... 4
8/04—Rev. B to Rev. C
Changes to Ordering Guide ............................................................ 5
Changes to Outline Dimensions................................................... 15
7/02—Rev. A to Rev. B
Changes to Specifications................................................................ 2
Rev. E | Page 2 of 16
AD8042
SPECIFICATIONS
TA = 25°C, VS = 5 V, RL = 2 kΩ to 2.5 V, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
125
130
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth, VO < 0.5 V p-p G = +1
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
160
14
200
30
MHz
MHz
V/μs
MHz
ns
G = +2, RL = 150 Ω, RF = 200 Ω
G = –1, VOUT = 2 V step
VO = 2 V p-p
Settling Time to 1%
G = –1, VOUT = 2 V step
26
Settling Time to 0.1%
39
ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC, 100 IRE)
fC = 5 MHz, VOUT = 2 V p-p, G = +2, RL = 1 kΩ
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 Ω to 2.5 V
G = +2, RL = 75 Ω to 2.5 V
G = +2, RL = 150 Ω to 2.5 V
G = +2, RL = 75 Ω to 2.5 V
f = 5 MHz, RL = 150 Ω to 2.5 V
–73
15
dB
nV/√Hz
fA/√Hz
%
700
0.04
0.04
0.06
0.24
–63
0.06
%
Differential Phase Error (NTSC, 100 IRE)
0.12 Degrees
Degrees
dB
Worst-Case Crosstalk
DC PERFORMANCE
Input Offset Voltage
3
9
12
mV
mV
μV/°C
ꢀA
ꢀA
ꢀA
TMIN to TMAX
Offset Drift
Input Bias Current
12
1.2
3.2
4.8
0.5
TMIN to TMAX
Input Offset Current
Open-Loop Gain
0.2
100
90
RL = 1 kΩ
TMIN to TMAX
90
68
dB
dB
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
300
1.5
−0.2 to +4
74
kΩ
pF
V
VCM = 0 V to 3.5 V
dB
RL = 10 kΩ to 2.5 V
RL = 1 kΩ to 2.5 V
RL = 50 Ω to 2.5 V
TMIN to TMAX, VOUT = 0.5 V to 4.5 V
Sourcing
0.03 to 4.97
0.10 to 4.9 0.05 to 4.95
V
V
V
mA
mA
mA
pF
0.4 to 4.4
0.36 to 4.45
50
90
100
20
Output Current
Short-Circuit Current
Sinking
G = +1
Capacitive Load Drive
POWER SUPPLY
Operating Range
3
12
V
Quiescent Current (Per Amplifier)
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
5.5
80
6.4
mA
dB
VS– = 0 V to −1 V, or VS+ = 5 V to 6 V
72
−40
+85 °C
Rev. E | Page 3 of 16
AD8042
TA = 25°C, VS = 3 V, RL = 2 kΩ to 1.5 V, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
120
120
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth, VO < 0.5 V p-p G = +1
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
140
11
170
25
MHz
MHz
V/μs
MHz
ns
G = +2, RL = 150 Ω, RF = 200 Ω
G = −1, VOUT = 2 V step
VO = 2 V p-p
Settling Time to 1%
G = −1, VOUT = 1 V step
30
Settling Time to 0.1%
45
ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
fC = 5 MHz, VOUT = 2 V p-p, G = −1, RL = 100 Ω
f = 10 kHz
–56
16
dB
nV/√Hz
Input Current Noise
Differential Gain Error (NTSC, 100 IRE)
f = 10 kHz
500
0.10
0.10
0.12
0.27
–68
fA/√Hz
%
%
Degrees
Degrees
dB
G = +2, RL = 150 Ω to 1.5 V, Input VCM = 1 V
RL = 75 Ω to 1.5 V, Input VCM = 1 V
G = +2, RL = 150 Ω to 1.5 V, Input VCM = 1 V
RL = 75 Ω to 1.5 V, Input VCM = 1 V
f = 5 MHz, RL = 1 kΩ to 1.5 V
Differential Phase Error (NTSC, 100 IRE)
Worst-Case Crosstalk
DC PERFORMANCE
Input Offset Voltage
3
9
12
mV
mV
μV/°C
μA
μA
μA
TMIN to TMAX
Offset Drift
Input Bias Current
12
1.2
3.2
4.8
0.6
TMIN to TMAX
Input Offset Current
Open-Loop Gain
0.2
100
90
RL = 1 kΩ
TMIN to TMAX
90
66
dB
dB
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
300
1.5
–0.2 to +2
74
kΩ
pF
V
VCM = 0 V to 1.5 V
dB
RL = 10 kΩ to 1.5 V
RL = 1 kΩ to 1.5 V
RL = 50 Ω to 1.5 V
TMIN to TMAX, VOUT = 0.5 V to 2.5 V
Sourcing
0.03 to 2.97
0.1 to 2.9 0.05 to 2.95
0.3 to 2.6 0.25 to 2.65
V
V
V
mA
mA
mA
pF
Output Current
Short-Circuit Current
50
50
70
17
Sinking
G = +1
Capacitive Load Drive
POWER SUPPLY
Operating Range
3
12
V
Quiescent Current (Per Amplifier)
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
5.5
80
6.4
mA
dB
°C
VS– = 0 V to –1 V, or VS+ = 3 V to 4 V
68
0
70
Rev. E | Page 4 of 16
AD8042
TA = 25°C, VS = 5 V, RL = 2 kΩ to 0 V, unless otherwise noted.
Table 3.
Parameter
Conditions
Min
125
145
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth, VO < 0.5 V p-p G = +1
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
170
18
225
35
MHz
MHz
V/ꢀs
MHz
ns
G = +2, RL = 150 Ω, RF = 200 Ω
G = −1, VOUT = 2 V step
VO = 2 V p-p
Settling Time to 1%
G = −1, VOUT = 2 V step
22
Settling Time to 0.1%
32
ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC, 100 IRE)
fC = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 kΩ
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 Ω
G = +2, RL = 75 Ω
G = +2, RL = 150 Ω
G = +2, RL = 75 Ω
–78
15
dB
nV/√Hz
fA/√Hz
%
700
0.02
0.02
0.04
0.12
–63
0.05
%
Differential Phase Error (NTSC, 100 IRE)
0.10 Degrees
Degrees
dB
Worst-Case Crosstalk
DC PERFORMANCE
Input Offset Voltage
f = 5 MHz, RL = 150 Ω
3
9.8
14
mV
mV
μV/°C
ꢀA
ꢀA
ꢀA
TMIN to TMAX
Offset Drift
Input Bias Current
12
1.2
3.2
4.8
0.6
TMIN to TMAX
Input Offset Current
Open-Loop Gain
0.2
94
86
RL = 1 kΩ
TMIN to TMAX
90
66
dB
dB
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
300
1.5
−5.2 to +4
74
kΩ
pF
V
VCM = –5 V to +3.5 V
dB
RL = 10 kΩ
−4.97 to +4.97
V
RL = 1 kΩ
−4.8 to +4.8 −4.9 to +4.9
V
RL = 50 Ω
−4 to +3.2
−4.2 to +3.5
V
Output Current
Short-Circuit Current
TMIN to TMAX, VOUT = −4.5 V to +4.5 V
50
mA
mA
mA
pF
Sourcing
Sinking
G = +1
100
100
25
Capacitive Load Drive
POWER SUPPLY
Operating Range
3
12
7
V
Quiescent Current (Per Amplifier)
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
6
80
mA
dB
°C
VS– = −5 V to −6 V, or VS+ = 5 V to 6 V
68
−40
+85
Rev. E | Page 5 of 16
AD8042
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Exceeding a junction temperature of 175°C for an extended
period can result in device failure.
Rating
Supply Voltage
Internal Power Dissipation1
8-Lead PDIP (N)
8-Lead SOIC_N (R)
Input Voltage (Common Mode)
Differential Input Voltage
Output Short-Circuit Duration
12.6 V
While the AD8042 is internally short-circuit protected, this
may not be sufficient to guarantee that the maximum junction
temperature (150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the
maximum power derating curves.
1.3 W
0.9 W
VS 0.5 V
3.4 V
Observe Power
Derating Curves
2.0
8-LEAD PLASTIC-DIP PACKAGE
Storage Temperature Range (N, R)
Lead Temperature (Soldering, 10 sec)
−65°C to +125°C
300°C
1.5
1 Specification is for the device in free air:
8-Lead PDIP: θJA = 90°C/W
J
T
= 150°C
8-Lead SOIC_N: θJA = 155°C/W.
1.0
0.5
0
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
8-LEAD SOIC PACKAGE
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Temperature
MAXIMUM POWER DISSIPATION
ESD CAUTION
The maximum power that can be safely dissipated by the
AD8042 is limited by the associated rise in junction temperature.
The maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Exceeding this limit temporarily
can cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package.
Rev. E | Page 6 of 16
AD8042
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
95
90
85
80
75
70
V
= 5V
V
= 5V
S
S
90
80
70
60
50
40
30
20
10
0
T = 25°C
T = 25°C
140 PARTS, SIDE 1 & 2
MEAN = –1.52mV
STD DEVIATION = 1.15
SAMPLE SIZE = 280
(140 AD8042s)
–6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
0
250
500
750
1000
1250
1500
1750
2000
V
(mV)
LOAD RESISTANCE (Ω)
OS
Figure 8. Open-Loop Gain vs. RL to 2.5 V
Figure 5. Typical Distribution of VOS
30
25
20
15
10
5
V
= 5V
100
98
96
94
92
90
88
86
S
MEAN = –12.6µV/°C
STD DEVIATION = 2.02µV/°C
SAMPLE SIZE = 60
V
R
= 5V
= 1kΩ
S
L
0
–18 –16 –14 –12 –10
–8
–6
–4
–2
0
–40
–20
0
20
40
60
80
V
DRIFT (µV/°C)
OS
TEMPERATURE (°C)
Figure 6. VOS Drift Over −40°C to +85°C
Figure 9. Open-Loop Gain vs. Temperature
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
–2.0
V
V
= 5V
100
S
= 0V
CM
V
= 5V
S
90
80
70
60
50
40
R
= 500Ω TO 2.5V
= 50Ω TO 2.5V
L
R
L
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT VOLTAGE (V)
Figure 7. IB vs. Temperature
Figure 10. Open-Loop Gain vs. Output Voltage
Rev. E | Page 7 of 16
AD8042
0.04
0.03
0.02
0.01
0
V
= +5V
S
NTSC SUBCARRIER (3.579MHz)
G = +2
R
300
100
30
10
3
= 150Ω TO 2.5V
L
V
= ±5V
S
G = +2
= 150Ω
R
L
–0.01
0.05
V
= +5V
S
G = +2
= 150Ω TO 2.5V
0.04
0.03
0.02
0.01
0
R
L
1
V
= ±5V
S
G = +2
= 150Ω
R
L
–0.01
10
100
1k
10k
100k
1M
10M
100M
1G
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY (Hz)
MODULATING RAMP LEVEL (IRE)
Figure 11. Input Voltage Noise vs. Frequency
Figure 14. Differential Gain and Phase Errors
–30
–40
–50
–60
–70
–80
–90
0.6
0.5
V
= 5V
S
G = +2
R
R
V
R
= 3V, A = –1,
V
= 100Ω TO 1.5V
S
= 200Ω
= 150Ω TO 2.5V
F
L
L
0.4
V
R
= 5V, A = +2,
V
= 100Ω TO 2.5V
S
0.3
L
V
R
= 5V, A = +1,
V
= 100Ω TO 2.5V
0.2
S
L
0.1
0
14MHz
–0.1
–0.2
–0.3
–0.4
V
= 5V, A = +2,
V
S
R
= 1kΩ TO 2.5V
L
V
= 5V, A = +1,
V
S
R
= 1kΩ TO 2.5V
L
–100
1
2
3
4
5
6
7
8
9 10
1
10
FREQUENCY (MHz)
100
500
FUNDAMENTAL FREQUENCY (MHz)
Figure 12. Total Harmonic Distortion vs. Frequency
Figure 15. 0.1 dB Gain Flatness
–30
–40
120
V
R
= 5V, G = +2,
= 1kΩ TO 2.5V
V
= 5V
S
S
G = +2
R
R
L
100
80
= 200Ω
= 150Ω TO 2.5V
F
L
–50
GAIN
10MHz
5MHz
60
45
–60
40
0
–70
20
–45
–90
–135
–180
–225
–270
PHASE
0
–80
–20
–40
–60
–80
1MHz
–90
–100
–110
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.01
0.1
1
10
100
500
OUTPUT VOLTAGE (V p-p)
FREQUENCY (MHz)
Figure 13. Worst Harmonic vs. Output Voltage
Figure 16. Open-Loop Gain and Phase vs. Frequency
Rev. E | Page 8 of 16
AD8042
10
8
60
55
50
45
40
35
30
25
20
V
= 5V
S
G = –1
V
= +3V, 0.1%
S
G = +1
C
R
R
C
= 2kΩ TO MIDPOINT
= 5pF
L
L
= 5pF
= 2kΩ TO 2.5V
L
L
T = +85°C
T = +25°C
6
4
2
V
= +3V, 1%
S
0
T = –40°C
V
= +5V, 0.1%
= ±5V, 0.1%
S
–2
–4
–6
–8
–10
V
S
V
V
= +5V, 1%
= ±5V, 1%
S
S
1
10
FREQUENCY (MHz)
100
500
0.5
1.0
1.5
2.0
INPUT STEP (V)
Figure 17. Closed-Loop Frequency Response vs. Temperature
Figure 20. Settling Time vs. Input Voltage
12
TEST CIRCUIT:
1.02kΩ
G = +1
V
R
= +3V
AND C TO 1.5V
S
V = 5V
S
C
R
= 5pF
= 2kΩ
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
L
L
1.02kΩ
10
8
L
L
V
R
= +5V
AND C TO 2.5V
IN
OUT
S
CM
L
L
V
= ±5V
1.02kΩ
S
6
1.02kΩ
4
2
0
–2
–4
–6
–8
10k
100k
1M
10M
100M
500M
1
10
FREQUENCY (MHz)
100
500
FREQUENCY (Hz)
Figure 21. Common-Mode Rejection vs. Frequency
Figure 18. Closed-Loop Frequency Response vs. Supply
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 5V
S
V
= 5V
G = +1
S
100
10
R
= 50Ω
BT
5V – V
(+125°C)
(+25°C)
(–55°C)
OH
5V – V
5V – V
OH
R
= 0Ω
OH
BT
R
BT
V
OUT
1
0.1
0.01
+V (+125°C)
OL
+V (+25°C)
OL
+V (–55°C)
OL
0.01
0.1
1
10
100
500
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (MHz)
LOAD CURRENT (mA)
Figure 22. Output Saturation Voltage vs. Load Current
Figure 19. Output Resistance vs. Frequency
Rev. E | Page 9 of 16
AD8042
12.0
11.5
11.0
10.5
10.0
9.5
50
40
30
20
10
0
V
V
= 5V
S
V
= ±5V
S
= 100mV STEP
OUT
G = +2
V
V
= +5V
= +3V
S
S
G = +3
9.0
8.5
8.0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
0
20
40
60
80
100 120 140 160 180 200
LOAD CAPACITANCE (pF)
Figure 23. Supply Current vs. Temperature
Figure 26. Overshoot vs. Load Capacitance
10
6
5
V
= 5V
V
= 5V
S
S
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
R
R
= 2kΩ
= 2kΩ to 2.5V
F
L
4
3
G = +2
2
1
–PSRR
+PSRR
0
G = +2
= 200Ω
–1
–2
–3
–4
R
F
G = +10
G = +5
10k
100k
1M
10M
100M
500M
1
10
FREQUENCY (MHz)
100
500
FREQUENCY (Hz)
Figure 27. Closed-Loop Gain vs. Frequency Response
Figure 24. PSRR vs. Frequency
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
10
9
8
7
6
5
4
3
2
1
0
V
V
= 5V
S
V
R
= ±5V
= 2kΩ
S
= 0.6V p-p
IN
L
G = +2
= 1kΩ
G = –1
R
F
V
V
1
2
OUT
R
= 1kΩ TO 2.5V
,
L
OUT
V
1
2
OUT
OUT
R
= 150Ω TO 2.5V
,
L
V
V
V
2
1
OUT
OUT
R
= 150Ω TO 2.5V
,
L
V
V
2
1
OUT
OUT
R
= 1kΩ TO 2.5V
,
L
0.1
1
10
100 200
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 28. Crosstalk (Output-to-Output) vs. Frequency
Figure 25. Output Voltage vs. Frequency
Rev. E | Page 10 of 16
AD8042
5V
4V
3V
2V
1V
0V
A
V
= 1
= 5V
= 100mV p-p
= 5pF
= 1kΩ TO 2.5V
V
= 5V
V
S
4.770V
G = –1
R
2.6V
2.5V
2.4V
S
V
= 150Ω TO 2.5V
IN
L
C
R
L
L
0.160V
25mV
10ns
0.5V
200µs
Figure 29. Output Swing with Load Reference to Supply Midpoint
Figure 32. 100 mV Pulse Response, VS = 5 V
5V
G = –1
V
= 5V
S
R
= 2kΩ TO 1.5V
G = –1
L
R
= 150Ω TO GND
L
3.0V
1.5V
0V
4V
3V
2V
1V
0V
4.59V
0.035V
0.5V
1µs
0.5V
200µs
Figure 30. Output Swing with Load Reference to Negative to Supply
Figure 33. Rail-to-Rail Output Swing, VS = 3 V
4.5V
A
V
= 1
= 3V
= 100mV p-p
= 5pF
= 1kΩ TO 1.5V
A
V
= 2
= 5V
= 5pF
= 1kΩ TO 2.5V
= 1V p-p
V
V
1.6V
1.5V
1.4V
S
S
V
C
R
V
IN
L
L
C
R
L
L
IN
3.5V
2.5V
1.5V
0.5V
25mV
10ns
0.5V
10ns
Figure 31. 1 V Pulse Response, VS = 5 V
Figure 34. 100 mV Pulse Response, VS = 3 V
Rev. E | Page 11 of 16
AD8042
APPLICATIONS INFORMATION
CIRCUIT DESCRIPTION
DRIVING CAPACITIVE LOADS
The AD8042 is fabricated on the Analog Devices, Inc.,
proprietary eXtra-Fast Complementary Bipolar (XFCB)
process, which enables the construction of PNP and NPN
transistors with similar fts in the 2 GHz to 4 GHz region. The
process is dielectrically isolated to eliminate the parasitic and
latch-up problems caused by junction isolation. These features
allow the construction of high frequency, low distortion
amplifiers with low supply currents. This design uses a
differential output input stage to maximize bandwidth and
headroom (see Figure 35). The smaller signal swings required
on the first stage outputs (nodes SIP, SIN) reduce the effect of
nonlinear currents due to junction capacitances and improve
the distortion performance. With this design, harmonic distortion
of better than −77 dB @ 1 MHz into 100 Ω with VOUT = 2 V p-p
(gain = +2) on a single 5 V supply is achieved.
The capacitive load drive of the AD8042 can be increased by
adding a low valued resistor in series with the load. Figure 36
shows the effects of a series resistor on capacitive drive for
varying voltage gains. As the closed-loop gain is increased, the
larger phase margin allows for larger capacitive loads with less
overshoot. Adding a series resistor with lower closed-loop gains
accomplishes the same effect. For large capacitive loads, the
frequency response of the amplifier is dominated by the roll-off
of the series resistor and capacitive load.
1000
V
= 5V
S
200mV STEP WITH 90% OVERSHOOT
R
= 5Ω
R
S
S
C
L
R
= 0Ω
S
100
V
CC
I1
I10
I2
I3
I9
Q50
Q39
Q25
Q51
R26
Q4
R39
Q5
Q36
I5
Q23
V
Q40
EE
R
= 20Ω
S
R15 R2
Q22
R27
R23
Q21
V
EE
C3
C9
Q31
Q7
Q17
V
P
Q13
V
OUT
IN
Q27
10
V
N
IN
1
2
3
4
5
SIN
SIP
CLOSED-LOOP GAIN (V/V)
Figure 36. Capacitive Load Drive vs. Closed-Loop Gain
Q2
Q11
R3
Q8
I8
Q3
Q24
I7
Q47
V
CC
OVERDRIVE RECOVERY
C7
R5
R21
V
EE
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this overdrive
condition. As shown in Figure 37, the AD8042 recovers within
30 ns from negative overdrive and within 25 ns from positive
overdrive.
Figure 35. Simplified Schematic
The rail-to-rail output range of the AD8042 is provided by a
complementary common-emitter output stage. High output
drive capability is provided by injecting all output stage predriver
currents directly into the bases of the output devices Q8 and
Q36. Biasing of Q8 and Q36 is accomplished by I8 and I5, along
with a common-mode feedback loop (not shown). This circuit
topology allows the AD8042 to drive 40 mA of output current
with the outputs within 0.5 V of the supply rails.
5.0V
2.5V
On the input side, the device can handle voltages from 0.2 V
below the negative rail to within 1.2 V of the positive rail.
Exceeding these values does not cause phase reversal; however,
the input ESD devices do begin to conduct if the input voltages
exceed the rails by greater than 0.5 V.
0V
G = +2
V
V
R
= 5V
S
= 5V p-p
= 1kΩ TO 2.5V
IN
L
1V
50ns
Figure 37. Overdrive Recovery
Rev. E | Page 12 of 16
AD8042
Single-Supply Composite Video Line Driver
The other extreme is for a video signal that is full white
The two op amps of an AD8042 can be configured as a single-
supply dual line driver for composite video. The wide signal
swing of the AD8042 enables this function to be performed
without using any type of clamping or dc restore circuit, which
can cause signal distortion.
everywhere. The blanking intervals and sync tips of such a
signal have negative going excursions in compliance with
composite video specifications. The combination of horizontal
and vertical blanking intervals limit such a signal to being at its
highest level (white) for only about 75% of the time.
Figure 38 shows a schematic for a circuit that is driven by a
single composite video source that is ac-coupled, level-shifted
and applied to both noninverting inputs of the two amplifiers.
Each op amp provides a separate 75 Ω composite video output.
To obtain single-supply operation, ac coupling is used throughout.
The large capacitor values are required to ensure that there is
minimal tilting of the video signals due to their low frequency
(30 Hz) signal content. The circuit shown was measured to have
a differential gain of 0.06% and a differential phase of 0.06°.
As a result of the duty cycle variations between the two extremes
presented, a 1 V p-p composite video signal that is multiplied by
a gain of 2 requires about 3.2 V p-p of dynamic voltage swing at
the output for an op amp to pass a composite video signal of
arbitrary duty cycle without distortion.
Some circuits use a sync tip clamp along with ac coupling to
hold the sync tips at a relatively constant level, which lowers the
amount of dynamic signal swing required. However, these
circuits can have artifacts, such as sync tip compression, unless
they are driven by sources with very low output impedance.
The input is terminated in 75 Ω and ac-coupled via CIN to a
voltage divider that provides the dc bias point to the input.
Setting the optimal bias point requires some understanding
of the nature of composite video signals and the video
performance of the AD8042.
The AD8042 not only has ample signal swing capability to handle
the dynamic range required without using a sync tip clamp but
also has good video specifications such as differential gain and
differential phase when buffering these signals in an ac-coupled
configuration.
+5V
4.99kΩ
0.1µF
1000µF
10µF
10µF
To test the dynamic range, the differential gain and differential
phase were measured for the AD8042 while the supplies were
varied. As the lower supply is raised to approach the video
signal, the first effect observed is that the sync tips become
compressed before the differential gain and differential phase are
adversely affected. Therefore, there must be adequate swing in
the negative direction to pass the sync tips without compression.
75Ω
COAX
4.99kΩ
3
2
8
1
V
OUT
R
T
75Ω
R
COMPOSITE
VIDEO IN
L
R
F
75Ω
1kΩ
0.1µF
75Ω
R
1kΩ
G
10kΩ
220µF
5
6
1000µF
0.1µF
7
V
OUT
As the upper supply is lowered to approach the video, the
differential gain and differential phase was not significantly
affected until the difference between the peak video output
and the supply reached 0.6 V. Therefore, the highest video level
should be kept at least 0.6 V below the positive supply rail.
R
T
75Ω
R
L
4
75Ω
R
R
G
F
1kΩ
1kΩ
220µF
Figure 38. Single-Supply Composite Video Line Driver Using AD8042
Therefore, it was found that the optimal point to bias the
noninverting input is at 2.2 V dc. Operating at this point, the
worst-case differential gain is measured at 0.06% and the worst-
case differential phase is 0.06°.
Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capability than their peak-
to-peak amplitude after ac coupling. As a worst case, the dynamic
signal swing required approaches twice the peak-to-peak value.
The two bounding cases are for a duty cycle that is mostly low,
but occasionally goes high at a fraction of a percent duty cycle,
and vice versa.
The ac-coupling capacitors used in the circuit at first glance
appear quite large. A composite video signal has a lower frequency
band edge of 30 Hz. The resistances at the various ac coupling
points, especially at the output, are quite small. To minimize
phase shifts and baseline tilt, the large value capacitors are required.
For video system performance that is not to be of the highest
quality, the value of these capacitors can be reduced by a factor
of up to five with only a slightly observable change in the picture
quality.
Composite video is not quite this demanding. One bounding
extreme is for a signal that is mostly black for an entire frame
but has a white (full intensity), minimum width spike at least
once per frame.
Rev. E | Page 13 of 16
AD8042
Single-Ended-to-Differential Driver
The cable has a characteristic impedance of about 120 Ω. Each
driver output is back terminated with a pair of 60.4 Ω resistors
to make the source look like 120 Ω. The receive end is terminated
with 121 Ω, and the signal is measured differentially with a pair
of scope probes. One channel on the oscilloscope is inverted
and then the signals are added.
Using a cross-coupled, single-ended-to-differential converter
(SEDC), the AD8042 makes a good general-purpose differential
line driver. This SEDC can be used for applications such as
driving Category-5 (CAT-5) twisted pair wires. Figure 39 shows
a configuration for a circuit that performs this function that can
be used for video transmission over a differential pair or various
data communication purposes.
Figure 40 shows the results of the circuit in Figure 39 driving
50 meters of CAT-5 cable.
+5V
200mV
1V
50ns
0.1µF
10µF
100
90
R
1kΩ
IN
R
1kΩ
F
3
2
V
8
IN
V
IN
60.4Ω
1
AMP1
49.9Ω
R
A
1kΩ
50m
R
1kΩ
R
1kΩ
B
B
V
OUT
121Ω
AD8042
V
OUT
10
R
A
1kΩ
0%
6
5
60.4Ω
7
AMP2
4
200mV
100Ω
Figure 40. Differential Driver Frequency Response
0.1µF
10µF
–5V
Single-Supply Differential A/D Driver
Figure 39. Single-Ended-to-Differential Twisted Pair Line Driver
The single-ended-to-differential converter circuit is also useful
as a differential driver for video speed, single-ended, differential
input ADCs. Figure 41 is a schematic that shows such a circuit
differentially driving an AD9220, a 12-bit, 10 MSPS ADC.
Each of the op amps of the AD8042 is configured as a unity gain
follower by the feedback resistors (RA). Each op amp output also
drives the other as a unity gain inverter via RB, creating a totally
symmetrical circuit.
+5V
If the noninverting input of AMP2 is grounded and a small
positive signal is applied to the noninverting input of AMP1,
the output of AMP1 is driven to saturation in the positive
direction and the input of AMP2 is driven to saturation in the
negative direction. This is similar to the way a conventional op
amp behaves without any feedback.
+5V
0.1µF
0.1µF
1kΩ
1kΩ
3
2
8
V
IN
1
+5V
+5V
+5V
1kΩ
0.1µF
0.1µF
26
0.1µF
15
AVDD
28
DVDD
1kΩ
1kΩ
If a resistor (RF) is connected from the output of AMP2 to the
noninverting input of AMP1, negative feedback is provided, which
closes the loop. An input resistor (RIN) makes the circuit look
like a conventional inverting op amp configuration with
differential outputs.
AD8042
AVDD
+5V
14
13
12
11
10
9
1kΩ
OTR
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
VINA
6
5
7
2.49kΩ
VINB
4
2.49kΩ
0.1µF
CAPT
AD9220
0.1µF
10/16 0.1µF
The gain of this circuit from input to either output is RF/RIN, or
the single-ended-to-differential gain is 2 × RF/RIN. This gives the
circuit the advantage of being able to adjust its gain by changing
a single resistor.
8
CAPB
7
18
17
22
0.1µF
6
VREF
5
SENSE
4
CML
3
0.1µF
1
2
CLOCK
CLK
REFCOM DVSS AVSS AVSS
19 25
27
16
Figure 41. AD8042 Differential Driver for the AD9220 12-Bit, 10 MSPS ADC
Rev. E | Page 14 of 16
AD8042
2kΩ
2kΩ
3kΩ
The circuit was tested with a 1 MHz input signal and clocked
at 10 MHz. An FFT response of the digital output is shown in
Figure 42.
ATT
6
5
2718AF
93DJ39
7
V
232Ω
OUT
V
IN
1/2
1
4
AD8042
Pin 5 is biased at 2.5 V by the voltage divider and bypassed.
This biases each output at 2.5 V. VIN is ac-coupled such that
3kΩ
10
5
2
3
VIN going positive makes VINA go positive and VINB go in
1
the negative direction. The opposite happens for a negative
going VIN.
1/2
2
9
7
AD8042
0.001µF
912Ω
1
6
0.0027µF
34Ω
2kΩ
2kΩ
2
3
249Ω
1
V
2kΩ
REC
1/4
AD8044
2kΩ
2kΩ
0.001µF
3
7
2
8
6
9
5
4
Figure 43. HDSL Line Driver
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8042 requires
careful attention to board layout and component selection.
Proper RF design techniques and low-pass parasitic component
selection are necessary.
HARMONICS (dBc)
FUND FRQ 1000977
THD
–82.00
71.13
2ND –88.34
6TH –99.47
7TH –91.16
8TH –97.25
9TH –91.61
SMPL FRQ 10000000 SNR
3RD –86.74
4TH –99.26
5TH –90.67
SINAD 70.79
SFDR –86.74
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance path. The ground plane should be removed from
the area near the input pins to reduce the stray capacitance.
Figure 42. FFT of the AD9220 Output When Driven by the AD8042
HDSL Line Driver
High bit rate digital subscriber line (HDSL) is a popular means
of providing data communication at DS1 rates (1.544 Mbps)
over moderate distances via conventional telephone twisted pair
wires. In these systems, the transceiver at the customer’s end is
powered sometimes via the twisted pair from a power source at
the central office. Sometimes, it is required to raise the dc voltage
of the power source to compensate for IR drops in long lines or
lines with narrow gauge wires.
Chip capacitors should be used for the supply bypassing. One
end should be connected to the ground plane and the other
within ⅛-inch of each power pin. An additional large (0.47 μF
to 10 μF) tantalum electrolytic capacitor should be connected in
parallel, but not necessarily so close to supply current, for fast,
large signal changes at the output.
The feedback resistor should be located close to the inverting
input pin to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the
inverting input significantly affect high speed performance.
Because of the IR drop, it is highly desirable to keep the power
consumption of the customer’s transceiver as low as possible.
One means to realize significant power savings is to run
the transceiver from a 5 V supply instead of the more
conventional 12 V.
Stripline design techniques should be used for long signal
traces (greater than approximately one inch). These should be
designed with a characteristic impedance of 50 ꢀ or 75 ꢀ and
be properly terminated at each end.
The high output swing and current drive capability of the
AD8042 make it ideally suited to this application. Figure 43
shows a circuit for the analog portion of an HDSL transceiver
using the AD8042 as the line driver.
Rev. E | Page 15 of 16
AD8042
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 44. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-8)—Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 45. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)—Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
AD8042AN
Temperature Range
Package Description
8-Lead PDIP
8-Lead SOIC_N
8-Lead SOIC_N, 13" Reel
8-Lead SOIC_N, 7" Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Reel
8-Lead SOIC_N, 7" Reel
DIE
Package Option
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-8
R-8
R-8
R-8
R-8
R-8
R-8
AD8042AR
AD8042AR-REEL
AD8042AR-REEL7
AD8042ARZ1
AD8042ARZ-REEL1
AD8042ARZ-REEL71
AD8042ACHIPS
1 Z = RoHS Compliant Part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01059-0-12/07(E)
Rev. E | Page 16 of 16
相关型号：
AD8044AR-REEL
IC QUAD OP-AMP, 8000 uV OFFSET-MAX, PDSO14, PLASTIC, SOIC-14, Operational Amplifier
ADI
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