AD795JN [ADI]
Low Power, Low Noise Precision FET Op Amp; 低功耗，低噪声精密FET运算放大器
| 型号： | AD795JN |
| 厂家： | 
ADI |
| 描述： | Low Power, Low Noise Precision FET Op Amp |
| 文件： | 总16页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power, Low Noise
Precision FET Op Amp
a
AD795
FEATURES
CO NNECTIO N D IAGRAMS
Low Pow er Replacem ent for Burr-Brow n
OPA-111, OPA-121 Op Am ps
Low Noise
8-P in P lastic Mini-D IP (N) P ackage
30
V
s
= ±15V
25
2.5 V p-p m ax, 0.1 Hz to 10 Hz
11 nV/ √Hz m ax at 10 kHz
0.6 fA/ √Hz at 1 kHz
20
15
10
High DC Accuracy
250 V m ax Offset Voltage
3 V/ ؇C m ax Drift
5
0
10
100
LOAD RESISTANCE –
1k
Ω
10k
1 pA m ax Input Bias Current
Low Pow er: 1.5 m A m ax Supply Current
Available in Low Cost Plastic Mini-DIP and Surface
Mount (SOIC) Packages
8-P in SO IC (R) P ackage
1
2
3
4
8
7
6
5
NC
–IN
+IN
NC
+V
S
OUTPUT
NC
APPLICATIONS
Low Noise Photodiode Pream ps
CT Scanners
–V
S
AD795
NC = NO CONNECT
Precision l-to-V Converters
P RO D UCT D ESCRIP TIO N
Furthermore, the AD795 features a guaranteed low input noise
of 2.5 µV p-p (0.1 Hz to 10 Hz) and a 11 nV/√Hz max noise
level at 10 kHz. T he AD795 has a fully specified and tested
input offset voltage drift of only 3 µV/°C max.
T he AD795 is a low noise, precision, FET input operational
amplifier. It offers both the low voltage noise and low offset drift
of a bipolar input op amp and the very low bias current of a
FET -input device. T he 1014 Ω common-mode impedance
insures that input bias current is essentially independent of
common-mode voltage and supply voltage variations.
T he AD795 is useful for many high input impedance, low noise
applications. T he AD795J and AD795K are rated over the
commercial temperature range of 0°C to +70°C.
T he AD795 has both excellent dc performance and a guaran-
teed and tested maximum input voltage noise. It features 1 pA
maximum input bias current and 250 µV maximum offset volt-
age, along with low supply current of 1.5 mA max.
T he AD795 is available in 8-pin plastic mini-DIP and 8-pin
surface mount (SOIC) packages.
1k
100
10
1
50
SAMPLE SIZE = 570
40
30
20
10
0
10
100
FREQUENCY – Hz
1k
10k
–5
–4
–3
–2
–1
0
1
2
3
4
5
INPUT OFFSET VOLTAGE DRIFT – µV/°C
AD795 Voltage Noise Spectral Density
Typical Distribution of Average Input Offset Voltage Drift
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD795–SPECIFICATIONS(@ +25؇C and ؎15 V dc unless otherwise noted)
AD 795JN/JR
AD 795K
Typ
P aram eter
Conditions
Min
Typ
Max
Min
Max
Units
INPUT OFFSET VOLT AGE1
Initial Offset
100
300
3
110
100
500
1000
10
50
100
1
110
100
250
400
3
µV
µV
µV/°C
dB
dB
Offset
T
MIN–T MAX
vs. T emperature
vs. Supply (PSRR)
vs. Supply (PSRR)
86
84
90
87
T MIN–T MAX
2
INPUT BIAS CURRENT
Either Input
Either Input @ T MAX
Either Input
Offset Current
Offset Current @ T MAX
VCM = 0 V
VCM = 0 V
VCM = +10 V
VCM = 0 V
VCM = 0 V
1
23
1
0.1
2
2/3
1.0
1
23
1
0.1
2
1
pA
pA
pA
pA
pA
=
0.6
=
OPEN-LOOP GAIN
VO = ±10 V
RLOAD ≥ 10 kΩ
RLOAD ≥ 10 kΩ
110
100
120
108
110
100
120
108
dB
dB
INPUT VOLT AGE NOISE
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
1.0
20
12
11
9
3.3
50
40
17
11
1.0
20
12
11
9
2.5
40
30
15
11
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
f = 10 kHz
INPUT CURRENT NOISE
f = 0.1 Hz to 10 Hz
f = 1 kHz
13
0.6
13
0.6
fA p-p
fA/√Hz
FREQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Response
G = –1
1.6
16
1
1.6
16
1
MHz
kHz
VO = 20 V p-p
RLOAD = 2 kΩ
VOUT = 20 V p-p
RLOAD = 2 kΩ
Slow Rate, Unity Gain
V/µs
SET T LING T IME3
T o 0.1%
10 V Step
10 V Step
50% Overdrive
f = 1 kHz
R1 ≥ 10 kΩ
VO = 3 V rms
10
11
2
10
11
2
µs
µs
µs
T o 0.01%
Overload Recovery4
T otal Harmonic
Distortion
–108
–108
dB
INPUT IMPEDANCE
Differential
Common Mode
VDIFF = ±1 V
1012ʈ2
1012ʈ2
ΩʈpF
ΩʈpF
1014ʈ2.2
1014ʈ2.2
INPUT VOLT AGE RANGE
Differential5
Common-Mode Voltage
Over Max Operating Temperature
Common-Mode Rejection Ratio
±20
±11
±20
±11
V
V
V
dB
dB
±10
±10
90
±10
±10
94
VCM = ±10 V
T MIN–T MAX
110
100
110
100
86
90
OUT PUT CHARACT ERIST ICS
Voltage
RLOAD ≥ 2 kΩ
T MIN–T MAX
VOUT = ±10 V
Short Circuit
VS –4
VS –4
±5
VS –2.5
VS –4
VS –4
±5
VS –2.5
V
V
mA
mA
Current
±10
±15
±10
±15
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
±15
±15
V
V
mA
±4
±18
1.5
±4
±18
1.5
1.3
1.3
–2–
REV. A
AD795
NOT ES
1Input offset voltage specifications are guaranteed after 5 minutes of operation at T A = +25°C.
2Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = +25°C. For higher temperature, the current doubles every 10 °C.
3Gain = –1, R1 = 10 kΩ.
4Defined as the time required for the amplifier’s output to return to normal operation after removal of a 50% overload from the amplifier input.
5Defined as the maximum continuous voltage between the inputs such that neither input exceeds ±10 V from ground.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS1
ESD SUSCEP TIBILITY
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
ESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without
detection. Although the AD795 features proprietary ESD pro-
tection circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic dis-
charges. T herefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.
Internal Power Dissipation2 (@ TA = +25°C)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
8-Pin Mini-DIP Package . . . . . . . . . . . . . . . . . . . . 750 mW
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS
Storage T emperature Range (N, R) . . . . . . . –65°C to +125°C
Operating T emperature Range
AD795J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
O RD ERING GUID E
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
28-Pin Plastic Mini-DIP Package: θJA = 100°C/Watt
Model
Tem perature Range
P ackage O ption*
AD795JN
AD795KN
AD795JR
0°C to +70°C
0°C to +70°C
0°C to +70°C
N-8
N-8
R-8
8-Pin Small Outline Package: θJA = 155°C/Watt
*N = Plastic mini-DIP; R = SOIC package.
REV. A
–3–
AD795–Typical Characteristics
20
20
R
= 10kΩ
L
R
= 10k
Ω
L
15
10
5
+V
15
10
5
IN
+V
OUT
–V
IN
–V
OUT
0
0
0
5
10
SUPPLY VOLTAGE – ±Volts
15
20
0
5
10
SUPPLY VOLTAGE – ±Volts
15
20
Figure 1. Com m on-Mode Voltage Range vs. Supply
Figure 2. Output Voltage Range vs. Supply Voltage
30
1.0
0.95
0.90
0.85
0.80
0.75
0.70
0.65
V
= ±15V
s
25
20
15
10
5
0
0.60
0
5
10
15
20
10
100
1k
10k
SUPPLY VOLTAGE – ±Volts
LOAD RESISTANCE – Ω
Figure 4. Input Bias Current vs. Supply
Figure 3. Output Voltage Swing vs. Load Resistance
10 –9
50
SAMPLE SIZE = 1058
40
10 –10
10 –11
30
20
10
0
10 –12
10 –13
10 –14
–60 –40 –20
0
20
40
60
80
100 120 140
0
.5
1
1.5
2
TEMPERATURE –
°
C
INPUT BIAS CURRENT – pA
Figure 5. Typical Distribution of Input Bias Current
Figure 6. Input Bias Current vs. Tem perature
–4–
REV. A
AD795
10–4
1.00
0.95
10–5
10–6
10–7
–I
+I
IN
IN
0.90
0.85
0.80
0.75
0.70
0.65
0.60
10–8
10–9
10–10
10–11
10–12
10–13
10–14
–5
–6
4
–2
–1
1
2
3
5
6
–4 –3
0
0
–15
–10
–5
+5
+10
+15
DIFFERENTIAL INPUT VOLTAGE – ±Volts
COMMON MODE VOLTAGE – Volts
Figure 8. Input Bias Current vs. Differential Input Voltage
Figure 7. Input Bias Current vs. Com m on-Mode Voltage
100
15
1k
f = 1kHz
Noise Bandwidth: 0.1 to 10Hz
10
12.5
10
VOLTAGE NOISE
100
10
1.0
CURRENT NOISE
7.5
5
0.1
0.01
1.0
0
20
40
60
80
100 120 140
–60 –40 –20
3
4
5
6
7
8
9
10
10
10
10
10
10
10
TEMPERATURE –
°C
SOURCE RESISTANCE – Ω
Figure 10. Input Voltage Noise vs. Source Resistance
Figure 9. Voltage and Current Noise Spectral Density vs.
Tem perature
1k
50
SAMPLE SIZE = 344
40
f = 0.1 TO 10Hz
100
10
30
20
10
0
1.0
1
10
100
1k
10k
100k
1M
10M
0
1
2
3
FREQUENCY – Hz
0.1 TO 10Hz INPUT VOLTAGE NOISE p-p – µV
Figure 11. Typical Distribution of Input Voltage Noise
Figure 12. Input Voltage Noise Spectral Density
REV. A
–5–
AD795–Typical Characteristics
30
10
8
25
6
0.1%
– OUTPUT CURRENT
4
0.01%
2
20
ERROR
0
–2
–4
15
+ OUTPUT CURRENT
0.1%
0.01%
10
–6
–8
–10
5
3
4
5
6
7
8
9
10
11
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE –
°C
SETTING TIME – µs
Figure 13. Short Circuit Current Lim it vs. Tem perature
Figure 14. Output Swing and Error vs. Settling Tim e
120
1000
900
800
700
600
500
400
300
200
100
0
100
+PSRR
–PSRR
80
60
40
20
0
1
10
100
1k
10k
100k
1M
10M
–15
–10
–5
0
5
10
15
FREQUENCY – Hz
INPUT COMMON MODE VOLTAGE – Volts
Figure 15. Absolute Input Error Voltage vs. Input
Com m on-Mode Voltage
Figure 16. Power Supply Rejection vs. Frequency
120
120
120
100
80
60
40
20
0
100
80
60
40
20
0
PHASE
100
80
60
40
20
0
GAIN
–20
10M
–20
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 17. Com m on-Mode Rejection vs. Frequency
Figure 18. Open-Loop Gain & Phase Margin vs. Frequency
–6–
REV. A
AD795
30
1000
100
10
R
= 10kΩ
L
25
20
15
10
5
1.0
0.1
0
1k
10k
100k
1M
1k
10k
100k
FREQUENCY – Hz
1M
10M
FREQUENCY – Hz
Figure 19. Large Signal Frequency Response
Figure 20. Closed-Loop Output Im pedance vs. Frequency
2.0
–60
V
= 3Vrms
= 10k
IN
R
L
–70
–80
1.5
1.0
–90
–100
–110
–120
0.5
0
0
5
10
15
20
100
1k
10k
FREQUENCY – Hz
100k
SUPPLY VOLTAGE ± Volts
Figure 21. Total Harm onic Distortion vs. Frequency
Figure 22. Quiescent Supply Current vs. Supply
Voltage Drift
50
SAMPLE SIZE = 1419
40
30
20
10
0
–500 –400 –300 –200 –100
0
100 200 300 400 500
INPUT OFFSET VOLTAGE – µV
Figure 23. Typical Distribution of Input Offset Voltage
REV. A
–7–
AD795
10kΩ
+V
S
0.1µF
20V
5µs
10mV
500ns
100
90
100
90
10kΩ
7
V
2
3
IN
V
6
OUT
AD795
C
R
L
L
100pF
10kΩ
4
0.1µF
10
10
0%
0%
–V
S
5V
Figure 24. Unity Gain Inverter
Figure 25. Unity Gain Inverter
Large Signal Pulse Response
Figure 26. Unity Gain Inverter
Sm all Signal Pulse Response
+VS
0.1µF
20mV
500ns
20V
5µs
100
90
100
90
7
2
VOUT
6
AD795
VIN
CL
100pF
RL
3
10kΩ
4
0.1µF
10
10
0%
0%
–VS
5V
Figure 27. Unity Gain Follower
Figure 28. Unity Gain Follower
Large Signal Pulse Response
Figure 29. Unity Gain Follower
Sm all Signal Pulse Response
current will double for every 10°C rise in junction temperature
(illustrated in Figure 6). On-chip power dissipation will raise the
device operating temperature, causing an increase in input
current. Reducing supply voltage to cut power dissipation will
reduce the AD795’s input current (Figure 4). Heavy output
loads can also increase chip temperature, maintaining a
minimum load resistance of 10 kΩ is recommended.
MINIMIZING INP UT CURRENT
T he AD795 is guaranteed to 1 pA max input current with ±15
volt supply voltage at room temperature. Careful attention to
how the amplifier is used will maintain or possibly better this
performance.
T he amplifier’s operating temperature should be kept as low as
possible. Like other JFET input amplifier’s, the AD795’s input
–8–
REV. A
AD795
CIRCUIT BO ARD NO TES
T he AD795 is designed for throughhole mounting on PC
boards, using either mini-DIP or surface mount (SOIC).
Maintaining picoampere resolution in those environments
requires a lot of care. Both the board and the amplifier’s
package have finite resistance. Voltage differences between the
input pins and other pins as well as PC board metal traces will
cause parasitic currents (Figure 30) larger than the AD795’s
input current unless special precautions are taken. T wo methods
of minimizing parasitic leakages are guarding of the input lines
and maintaining adequate insulation resistance.
C
F
R
F
V
E
2
3
6
+
AD795
I
S
V
OUT
–
I
P
R
P
C
P
V
R
dC
P
dV
S
S
I
=
+
V +
S
C
P
P
Figures 31 and 32 show the recommended guarding schemes for
follower and inverted topologies. Note that for the mini-DIP,
the guard trace should be on both sides of the board. On the
SOIC, Pin 1 is not connected, and can be safely connected to
the guard. T he high impedance input trace should be guarded
on both edges for its entire length.
dT
dT
P
V
S
Figure 30. Sources of Parasitic Leakage Currents
GUARD TRACES PARALLEL
TO BOTH EDGES OF
INPUT TRACE
CF
GUARD
1
8
RF
INPUT
TRACE
7
2
3
2
3
AD795
TOP VIEW
6
+
TO ANALOG
COMMON
6
5
AD795
IS
VOUT
("N" PACKAGE)
4
–
–VS
8
1
1
8
7
6
BOTTOM
VIEW
("N"
NOTE:
ON THE "R" PACKAGE
PINS 1, 5 AND 8 ARE OPEN
AND CAN BE CONNECTED
TO ANALOG COMMON OR
TO THE DRIVEN GUARD TO
REDUCE LEAKAGE.
2
3
7
6
2
3
PACKAGE)
TOP VIEW
("R" PACKAGE)
5
4
4
5
Figure 31. Guarding Schem e–lnverter
GUARD
GUARD TRACES
3
2
1
8
+
AD795
TOP VIEW
6
+
AD795
V
OUT
V
7
6
2
3
S
R
F
–
INPUT
TRACE
–V
S
4
5
CONNECT TO JUNCTION
OF R AND R , OR TO PIN 6
F
I
R
–
FOR UNITY GAIN.
I
Figure 32. Guard Schem e–Follower
REV. A
–9–
AD795
Leakage through the bulk of the circuit board will still occur
with the guarding schemes shown in Figures 31 and 32. Stan-
dard “G10” type printed circuit board material may not have
high enough volume resistivity to hold leakages at the sub-
picoampere level particularly under high humidity conditions.
One option that eliminates all effects of board resistance is
shown in Figure 33. T he AD795’s sensitive input pin (either
Pin 2 when connected as an inverter, or Pin 3 when connected
as a follower) is bent up and soldered directly to a T eflon*
insulated standoff. Both the signal input and feedback compo-
nent leads must also be insulated from the circuit board by
T eflon standoffs or low-leakage shielded cable.
Both proper shielding and rigid mechanical mounting of
components help minimize error currents from both of these
sources.
O FFSET NULLING
T he AD795’s input offset voltage can be nulled (mini-DIP
package only) by using balance Pins 1 and 5, as shown in
Figure 34. Nulling the input offset voltage in this fashion will
introduce an added input offset voltage drift component of
2.4 µV/°C per millivolt of nulled offset.
+V
S
INPUT PIN:
PIN 2 FOR INVERTER
OR PIN 3 FOR FOLLOWER
7
2
3
V
OUT
INPUT SIGNAL
+
AD795
1
6
LEAD
1
8
7
6
5
5
AD795
–
2
3
AD795
100kΩ
4
PC
BOARD
4
–V
S
TEFLON INSULATED STANDOFF
Figure 34. Standard Offset Null Circuit
Figure 33. Input Pin to Insulating Standoff
T he circuit in Figure 35 can be used when the amplifier is used
as an inverter. T his method introduces a small voltage in series
with the amplifier’s positive input terminal. T he amplifier’s
input offset voltage drift with temperature is not affected.
However, variation of the power supply voltages will cause
offset shifts.
Contaminants such as solder flux on the board’s surface and on
the amplifier’s package can greatly reduce the insulation resis-
tance between the input pin and those traces with supply or
signal voltages. Both the package and the board must be kept
clean and dry. An effective cleaning procedure is to first swab
the surface with high grade isopropyl alcohol, then rinse it with
deionized water and, finally, bake it at 100°C for 1 hour. Poly-
propylene and polystyrene capacitors should not be subjected to
the 100°C bake as they will be damaged at temperatures greater
than 80°C.
R
F
R
I
2
3
+
Other guidelines include making the circuit layout as compact
as possible and reducing the length of input lines. Keeping
circuit board components rigid and minimizing vibration will
reduce triboelectric and piezoelectric effects. All precision high
impedance circuitry requires shielding from electrical noise and
interference. For example, a ground plane should be used under
all high value (i.e., greater than 1 MΩ) feedback resistors. In
some cases, a shield placed over the resistors, or even the entire
amplifier, may be needed to minimize electrical interference
originating from other circuits. Referring to the equation in
Figure 30, this coupling can take place in either, or both, of two
different forms—coupling via time varying fields:
6
+
OUT
AD795
V
V
I
–
–
+V
–V
S
499kΩ
0.1µF
499kΩ
200Ω
100kΩ
S
Figure 35. Alternate Offset Null Circuit for Inverter
dV
CP
dT
or by injection of parasitic currents by changes in capacitance
due to mechanical vibration:
dCp
V
dT
*T eflon is a registered trademark of E.I. du Pont Co.
–10–
REV. A
AD795
AC RESP O NSE WITH H IGH VALUE SO URCE AND
FEED BACK RESISTANCE
10mV
5µs
Source and feedback resistances greater than 100 kΩ will
magnify the effect of input capacitances (stray and inherent to
the AD795) on the ac behavior of the circuit. T he effects of
common-mode and differential input capacitances should be
taken into account since the circuit’s bandwidth and stability
can be adversely affected.
100
90
10
0%
In a follower, the source resistance, RS, and input common-
mode capacitance, CS (including capacitance due to board and
capacitance inherent to the AD795), form a pole that limits
circuit bandwidth to 1/2 π RSCS. Figure 36 shows the follower
pulse response from a 1 MΩ source resistance with the
amplifier’s input pin isolated from the board, only the effect of
the AD795’s input common-mode capacitance is seen.
Figure 38. Inverter Pulse Response with 1 MΩ Source and
Feedback Resistance, 1 pF Feedback Capacitance
O VERLO AD ISSUES
Driving the amplifier output beyond its linear region causes
some sticking; recovery to normal operation is within 2 µs of the
input voltage returning within the linear range.
10mV
5µs
100
90
If either input is driven below the negative supply, the amplifier’s
output will be driven high, causing a phenomenon called phase
reversal. Normal operation is resumed within 30 µs of the input
voltage returning within the linear range.
10
Figure 39 shows the AD795’s input currents versus differential
input voltage. Picoamp level input current is maintained for
differential voltages up to several hundred millivolts. T his
behavior is only important if the AD795 is in an open-loop
application where substantial differential voltages are produced.
0%
Figure 36. Follower Pulse Response from 1 MΩ
Source Resistance
–4
10
In an inverting configuration, the differential input capacitance
forms a pole in the circuit’s loop transmission. T his can create
peaking in the ac response and possible instability. A feedback
capacitance can be used to stabilize the circuit. T he inverter
pulse response with RF and RS equal to 1 MΩ, and the input pin
isolated from the board appears in Figure 37. Figure 38 shows
the response of the same circuit with a 1 pF feedback
capacitance. T ypical differential input capacitance for the
AD795 is 2 pF.
–5
10
–I
+I
N
N
–6
10
–7
–8
–9
10
10
10
–10
–11
–12
10
10
10
10mV
5µs
–13
–14
10
10
100
90
–6 –5 –4
–3 –2 –1
0
1
2
3
4
5
6
DIFFERENTIAL INPUT VOLTAGE – ±Volts
Figure 39. Input Bias Current vs. Differential Input Voltage
10
0%
Figure 37. Inverter Pulse Response with 1 MΩ Source and
Feedback Resistance
REV. A
–11–
AD795
INP UT P RO TECTIO N
T he AD795 safely handles any input voltage within the supply
voltage range. Some applications may subject the input
terminals to voltages beyond the supply voltages—in these
cases, the following guidelines should be used to maintain the
AD795’s functionality and performance.
R
P
SOURCE
3
2
6
AD795
If the inputs are driven more than a 0.5 V below the minus sup-
ply, milliamp level currents can be produced through the input
terminals. T hat current should be limited to 10 mA for “tran-
sient” overloads (less than 1 second) and 1 mA for continuous
overloads, this can be accomplished with a protection resistor in
the input terminal (as shown in Figures 40 and 41). T he pro-
tection resistor’s Johnson noise will add to the amplifier’s input
voltage noise and impact the frequency response.
Figure 41. Follower with Input Current Lim it
Figure 42 is a schematic of the AD795 as an inverter with an
input voltage clamp. Bootstrapping the clamp diodes at the
inverting input minimizes the voltage across the clamps and
keeps the leakage due to the diodes low. Low leakage diodes
(less than 1 pA), such as the FD333s should be used, and
should be shielded from light to keep photocurrents from being
generated. Even with these precautions, the diodes will mea-
surably increase the input current and capacitance.
Driving the input terminals above the positive supply will cause
the input current to increase and limit at 40 µA. T his condition
is maintained until 15 volts above the positive supply—any
input voltage within this range does not harm the amplifier.
Input voltage above this range causes destructive breakdown
and should be avoided.
In order to achieve the low input bias currents of the AD795, it
is not possible to use the same on-chip protection as used in
other Analog Devices op amps. T his makes the AD795
sensitive to handling and precautions should be taken to
minimize ESD exposure whenever possible.
RF
RF
CF
RP
SOURCE
2
3
SOURCE
2
3
6
AD795
6
AD795
PROTECT DIODES
(LOW LEAKAGE)
Figure 42. Input Voltage Clam p with Diodes
Figure 40. Inverter with Input Current Lim it
–12–
REV. A
AD795
will typically drop by a factor of two for every 10°C rise in
temperature. In the AD795, both the offset voltage and drift are
low, this helps minimize these errors.
10pF
10 9
Ω
Minim izing Noise Contr ibutions
T he noise level limits the resolution obtainable from any pre-
amplifier. T he total output voltage noise divided by the
feedback resistance of the op amp defines the minimum
detectable signal current. T he minimum detectable current
divided by the photodiode sensitivity is the minimum detectable
light power.
GUARD
2
3
OUTPUT
6
AD795
PHOTODIODE
8
FILTERED
OUTPUT
Sources of noise in a typical preamp are shown in Figure 45.
T he total noise contribution is defined as:
2
2
Rf
Rf 1+ s (Cd ) Rd
Rd 1+ s (Cf ) Rf
OPTIONAL 26Hz
FILTER
2
2
2
V
=
(i
+
i
+ i )
s
+(en2
) 1+
n
f
OUT
1+ s (Cf ) Rf
Figure 43. The AD795 Used as a Photodiode Pream plifier
Cf
10pF
P r eam plifier Applications
T he low input current and offset voltage levels of the AD795
together with its low voltage noise make this amplifier an
excellent choice for preamplifiers used in sensitive photodiode
applications. In a typical preamp circuit, shown in Figure 43,
the output of the amplifier is equal to:
Rf
109
Ω
PHOTODIODE
en
i f
VOUT = ID (Rf) = Rp (P) Rf
in
where:
iS
Rd
Cd
50pF
OUTPUT
iS
ID = photodiode signal current (Amps)
Rp = photodiode sensitivity (Amp/Watt)
Rf = the value of the feedback resistor, in ohms.
P
= light power incident to photodiode surface, in watts.
Figure 45. Noise Contributions of Various Sources
An equivalent model for a photodiode and its dc error sources is
shown in Figure 44. T he amplifier’s input current, IB, will
contribute an output voltage error which will be proportional to
Figure 46, a spectral density versus frequency plot of each
source’s noise contribution, shows that the bandwidth of the
amplifier’s input voltage noise contribution is much greater than
its signal bandwidth. In addition, capacitance at the summing
junction results in a “peaking” of noise gain in this configura-
tion. T his effect can be substantial when large photodiodes with
large shunt capacitances are used. Capacitor Cf sets the signal
bandwidth and also limits the peak in the noise gain. Each
source’s rms or root-sum-square contribution to noise is ob-
tained by integrating the sum of the squares of all the noise
sources and then by obtaining the square root of this sum.
Minimizing the total area under these curves will optimize the
preamplifier’s overall noise performance.
the value of the feedback resistor. T he offset voltage error, VOS
will cause a “dark” current error due to the photodiode’s finite
shunt resistance, Rd. T he resulting output voltage error, VE, is
equal to:
,
VE = (1 + Rf/Rd) VOS + Rf IB
A shunt resistance on the order of 109 ohms is typical for a
small photodiode. Resistance Rd is a junction resistance which
Cf
10pF
An output filter with a passband close to that of the signal can
greatly improve the preamplifier’s signal to noise ratio. T he
photodiode preamplifier shown in Figure 45—without a
bandpass filter—has a total output noise of 50 µV rms. Using a
26 Hz single pole output filter, the total output noise drops to
23 µV rms, a factor of 2 improvement with no loss in signal
bandwidth.
Rf
9
10
Ω
PHOTODIODE
V
OS
I
B
OUTPUT
Cd
50pF
I
Rd
D
Figure 44. A Photodiode Model Showing DC Error
Sources
REV. A
–13–
AD795
voltage contributions are also amplified by the “T ” network
gain. A low noise, low offset voltage amplifier, such as the
AD795, is needed for this type of application.
10µV
&
i
i
f
s
SIGNAL BANDWIDTH
A pH P r obe Buffer Am plifier
A typical pH probe requires a buffer amplifier to isolate its 106
to 109 Ω source resistance from external circuitry. Just such an
amplifier is shown in Figure 48. T he low input current of the
AD795 allows the voltage error produced by the bias current
and electrode resistance to be minimal. T he use of guarding,
shielding, high insulation resistance standoffs, and other such
standard methods used to minimize leakage are all needed to
maintain the accuracy of this circuit.
1µV
i
n
WITH FILTER
NO FILTER
100nV
e
n
en
T he slope of the pH probe transfer function, 50 mV per pH
unit at room temperature, has a +3300 ppm/°C temperature
coefficient. T he buffer of Figure 48 provides an output voltage
equal to 1 volt/pH unit. T emperature compensation is provided
by resistor RT which is a special temperature compensation
resistor, part number Q81, 1 kΩ, 1%, +3500 ppm/°C, available
from T el Labs Inc.
10nV
1
10
100
1k
10k
100k
FREQUENCY – Hz
Figure 46. Voltage Noise Spectral Density of the Circuit of
Figure 45 With and Without an Output Filter
10pF
R
G
10kΩ
VOS ADJUST
100kΩ
Rf
+VS
+15V
COM
–15V
0.1µF
0.1µF
8
R
1.1kΩ
10
Ω
i
–VS
–VS
V
1
OUT
GUARD
AD795
4
3
2
OUTPUT
1VOLT/pH UNIT
5
PHOTODIODE
R
R
G
AD795
6
V
= I Rf (1+
D
)
OUT
i
7
PH
PROBE
19.6kΩ
8
+VS
Figure 47. A Photodiode Pream p Em ploying a “T”
Network for Added Gain
RT
1kΩ
+3500ppm/ °C
Using a “ T” Networ k
A “T ” network, shown in Figure 47, can be used to boost the
effective transimpedance of an I-to-V converter, for a given
feedback resistor value. However, amplifier noise and offset
Figure 48. A pH Probe Am plifier
–14–
REV. A
AD795
LOW NOISE
OP AMPS
Low V
Low I
N
N
(V ≤ 10 nV/√Hz @ 1 kHz)
(I ≤ 10 fA/√Hz @ 1 kHz)
N
N
Fast
Audio
Amplifiers
Precision
Low V
Fast
FET Input
Low Power
Electrometer
N
(SR ≥ 45 V/µs)
AD OP27
OP27
AD OP37
OP37
AD645
AD711
AD645
AD743
AD795
AD548
AD648
OP80
OP61
OP275
Low
Power
AD795
AD712 (Dual)
SSM2015
SSM2016
SSM2017
SSM2134
SSM2139
OP249 (Dual)
AD713 (Quad)
Faster
Lower V
N
OP80
OP227 (Dual)
Faster
(SR ≥ 230 V/µs)
Fast
AD743
OP270 (Dual)
OP271 (Dual)
OP470 (Quad)
OP471 (Quad)
(SR ≥ 8 V/µs)
Faster
AD745
General
Purpose
AD5539
AD829
AD840
AD844
AD846
AD848
AD849
Faster
OP282 (Dual)
OP482 (Quad)
AD744
OP42
AD745
AD546
OP44
AD746 (Dual)
High Output
Current
Lowest I
B
60 fA Max
OP50
AD549
Ultrafast
(SR ≥ 1000 V/µs)
AD811
AD844
AD9610
AD9617
AD9618
Low Noise Op Am p Selection Tree
REV. A
–15–
AD795
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
P lastic Mini-D IP (N) P ackage
8
5
0.25
(6.35)
0.31
(7.87)
PIN 1
1
4
0.30 (7.62)
REF
0.39 (9.91) MAX
0.035±0.01
(0.89±0.25)
0.165±0.01
(4.19±0.25)
0.011±0.003
(0.28±0.08)
0.18±0.03
(4.57±0.76)
0.125
(3.18)
MIN
15
°
0
°
0.10
(2.54)
0.018±0.003
(0.46±0.08)
0.033
(0.84)
NOM
SEATING
PLANE
BSC
8-P in SO IC (R) P ackage
0.150 (3.81)
8
5
0.244 (6.20)
0.228 (5.79)
0.157 (3.99)
0.150 (3.81)
PIN 1
1
4
0.020 (0.051) x 45
CHAMF
°
0.190 (4.82)
0.170 (4.32)
0.197 (5.01)
0.189 (4.80)
8
0
°
°
0.090
(2.29)
0.102 (2.59)
0.094 (2.39)
0.010 (0.25)
0.004 (0.10)
10
°
0°
0.019 (0.48)
0.014 (0.36)
0.050
(1.27)
BSC
0.030 (0.76)
0.018 (0.46)
0.098 (0.2482)
0.075 (0.1905)
All brand or product nam es m entioned are tradem arks or registered tradem arks of their respective holders.
–16–
REV. A
相关型号：
AD795SH-883B
IC OP-AMP, 500 uV OFFSET-MAX, 1.6 MHz BAND WIDTH, MBCY8, HERMETIC SEALED, METAL CAN, HEADER, TO-99, 8 PIN, Operational Amplifier
ADI
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