AD7910AKS [ADI]
IC 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6, PLASTIC, MO-203AB, SC-70, 6 PIN, Analog to Digital Converter;
| 型号： | AD7910AKS |
| 厂家： | 
ADI |
| 描述： | IC 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6, PLASTIC, MO-203AB, SC-70, 6 PIN, Analog to Digital Converter 光电二极管 转换器 |
| 文件： | 总20页 (文件大小：347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
250 kSPS,
10-/12-Bit ADCs in 6-Lead SC70
AD7910/AD7920
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Throughput Rate: 250 kSPS
Specified for VDD of 2.35 V to 5.25 V
Low Power:
V
DD
3.6 mW Typ at 250 kSPS with 3 V Supplies
12.5 mW Typ at 250 kSPS with 5 V Supplies
Wide Input Bandwidth:
10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
V
T/H
IN
71 dB SNR at 100 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPI™/QSPI™/MICROWIRE™/DSP Compatible
Standby Mode: 1 A Max
SCLK
SDATA
CS
CONTROL
LOGIC
6-Lead SC70 Package
8-Lead MSOP Package
AD7910/AD7920
GND
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High Speed Modems
The reference for the part is taken internally from VDD. This
allows the widest dynamic input range to the ADC. Thus the
analog input range for the part is 0 to VDD. The conversion rate
is determined by the SCLK.
Optical Sensors
PRODUCT HIGHLIGHTS
1. 10-/12-Bit ADCs in SC70 and MSOP Packages.
2. Low Power Consumption.
GENERAL DESCRIPTION
The AD7910/AD7920 are respectively 10-bit and 12-bit, high
speed, low power, successive approximation ADCs. The parts
operate from a single 2.35 V to 5.25 V power supply and feature
throughput rates up to 250 kSPS. The parts contain a low noise,
wide bandwidth track-and-hold amplifier that can handle input
frequencies in excess of 13 MHz.
3. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption to
be reduced when Power-Down mode is used while not convert-
ing. The part also features a Power-Down mode to maximize
power efficiency at lower throughput rates. Current consumption
is 1 ꢀA max and 50 nA typically when in Power-Down mode.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
4. Reference derived from the power supply.
5. No Pipeline Delay.
The parts feature a standard successive approximation ADC
with accurate control of the sampling instant via a CS input
and once-off conversion control.
The AD7910/AD7920 use advanced design techniques to achieve
very low power dissipation at high throughput rates.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2002 Analog Devices, Inc. All rights reserved.
(V = 2.35 V to 5.25 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless
AD7910–SPECIFICATIONS1 otDhDerwise noted.)
Parameter
A Grade1, 2
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fIN = 100 kHz Sine Wave
Signal-to-Noise + Distortion (SINAD)3
Total Harmonic Distortion (THD)3
61
–72
dB min
dB max
dB max
Peak Harmonic or Spurious Noise (SFDR)3 –73
Intermodulation Distortion (IMD)3
Second Order Terms
Third Order Terms
Aperture Delay
–82
–82
10
dB typ
dB typ
ns typ
fa = 100.73 kHz, fb = 90.7 kHz
fa = 100.73 kHz, fb = 90.7 kHz
Aperture Jitter
30
ps typ
Full Power Bandwidth
13.5
2
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
DC ACCURACY
Resolution
10
0.5
0.5
1
1
1.2
Bits
Integral Nonlinearity
Differential Nonlinearity
Offset Error3, 4
LSB max
LSB max
LSB max
LSB max
LSB max
Guaranteed No Missed Codes to 10 Bits
Gain Error3, 4
Total Unadjusted Error (TUE)3, 4
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to VDD
0.5
20
V
µA max
pF typ
Track-and-Hold in Track, 6 pF typ when in Hold
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
2.4
0.8
0.4
0.5
10
5
V min
V max
V max
µA max
nA typ
pF max
VDD = 5 V
VDD = 3 V
Typically 10 nA, VIN = 0 V or VDD
Input Current, IIN, SCLK Pin
Input Current, IIN, CS Pin
Input Capacitance, CIN
5
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance5
Output Coding
VDD – 0.2
0.4
1
V min
ISOURCE = 200 µA, VDD = 2.35 V to 5.25 V
ISINK = 200 µA
V max
µA max
pF max
5
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
2.8
250
250
µs max
14 SCLK cycles with SCLK at 5 MHz
Track-and-Hold Acquisition Time3
Throughput Rate
ns max
kSPS max
POWER REQUIREMENTS
VDD
2.35/5.25
V min/max
IDD
Digital I/Ps = 0 V or VDD
Normal Mode(Static)
2.5
1.2
3
1.4
1
mA typ
mA typ
mA max
mA max
µA max
VDD = 4.75 V to 5.25 V, SCLK On or Off
VDD = 2.35 V to 3.6 V, SCLK On or Off
VDD = 4.75 V to 5.25 V, fSAMPLE = 250 kSPS
VDD = 2.35 V to 3.6 V, fSAMPLE = 250 kSPS
Typically 50 nA
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation6
Normal Mode (Operational)
15
4.2
5
mW max
mW max
µW max
µW max
VDD = 5 V, fSAMPLE = 250 kSPS
VDD = 3 V, fSAMPLE = 250 kSPS
VDD = 5 V
Full Power-Down
3
VDD = 3 V
NOTES
1Temperature range from –40°C to +85°C.
2Operational from VDD = 2.0 V, with input high voltage (VINH) 1.8 V min.
3See Terminology section.
4SC70 values guaranteed by characterization.
5Sample tested @ 25°C to ensure compliance.
6See Power Versus Throughput Rate section.
Specifications subject to change without notice.
–2–
REV. 0
AD7910/AD7920
(VDD = 2.35 V to 5.25 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless
otherwise noted.)
AD7920–SPECIFICATIONS1
Parameter
A Grade1, 2 B Grade1, 2 Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fIN = 100 kHz Sine Wave
Signal-to-Noise + Distortion (SINAD)3
70
69
71.5
69
68
71
70
70
69
70
69
71.5
69
68
71
70
70
69
dB min
dB min
dB typ
dB min
dB min
dB min
dB min
dB min
dB min
dB typ
dB typ
VDD = 2.35 V to 3.6 V, TA = 25oC
VDD = 2.4 V to 3.6 V
VDD = 2.35 V to 3.6 V
VDD = 4.75 V to 5.25 V, TA = 25oC
VDD = 4.75 V to 5.25 V
Signal-to-Noise Ratio (SNR)3
VDD = 2.35 V to 3.6 V, TA = 25oC
VDD = 2.4 V to 3.6 V
VDD = 4.75 V to 5.25 V, TA = 25oC
VDD = 4.75 V to 5.25 V
Total Harmonic Distortion (THD)3
–80
–80
–82
Peak Harmonic or Spurious Noise (SFDR)3 –82
Intermodulation Distortion (IMD)3
Second-Order Terms
Third-Order Terms
Aperture Delay
–84
–84
10
–84
–84
10
dB typ
dB typ
ns typ
fa = 100.73 kHz, fb = 90.72 kHz
fa = 100.73 kHz, fb = 90.72 kHz
Aperture Jitter
30
30
ps typ
Full Power Bandwidth
13.5
2
13.5
2
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
DC ACCURACY
Resolution
B Grade4
12
12
1.5
Bits
Integral Nonlinearity3
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
0.75
Differential Nonlinearity
Offset Error3, 5
–0.9/+1.5
Guaranteed No Missed Codes to 12 Bits
0.75
1.5
1.5
0.2
1.5
0.5
2
Gain Error3, 5
1.5
Total Unadjusted Error (TUE)3,5
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to VDD
0.5
20
0 to VDD
0.5
20
V
µA max
pF typ
Track-and-Hold in Track, 6 pF typ when in Hold
LOGIC INPUTS
Input High Voltage, VINH
2.4
1.8
0.8
0.4
0.5
10
2.4
1.8
0.8
0.4
0.5
10
V min
V min
V max
V max
µA max
nA typ
pF max
VDD = 2.35 V
Input Low Voltage, VINL
VDD = 3.6 V to 5.25 V
VDD = 2.35 V to 3.6 V
Typically 10 nA, VIN = 0 V or VDD
Input Current, IIN, SCLK Pin
Input Current, IIN, CS Pin
Input Capacitance, CIN
6
5
5
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance6
Output Coding
VDD – 0.2
0.4
1
VDD – 0.2
0.4
1
V min
ISOURCE = 200 µA, VDD = 2.35 V to 5.25 V
ISINK = 200 µA
V max
µA max
pF max
5
5
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
3.2
250
250
3.2
250
250
µs max
16 SCLK Cycles with SCLK at 5 MHz
Track-and-Hold Acquisition Time3
Throughput Rate
ns max
kSPS max See Serial Interface Section
REV. 0
–3–
AD7910/AD7920
AD7920–SPECIFICATIONS1 (continued)
Parameter
A Grade1, 2
B Grade1, 2 Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
2.35/5.25
2.35/5.25
V min/max
IDD
Digital I/Ps = 0 V or VDD.
Normal Mode (Static)
2.5
1.2
3
1.4
1
2.5
1.2
3
1.4
1
mA typ
mA typ
mA max
mA max
µA max
VDD = 4.75 V to 5.25 V, SCLK On or Off
VDD = 2.35 V to 3.6 V, SCLK On or Off
VDD = 4.75 V to 5.25 V, fSAMPLE = 250 kSPS
VDD = 2.35 V to 3.6 V, fSAMPLE = 250 kSPS
Typically 50 nA
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation7
Normal Mode (Operational)
15
4.2
5
15
4.2
5
mW max
mW max
µW max
µW max
VDD = 5 V, fSAMPLE = 250 kSPS
VDD = 3 V, fSAMPLE = 250 kSPS
VDD = 5 V
Full Power-Down
3
3
VDD = 3 V
NOTES
1Temperature range from –40°C to +85°C.
2Operational from VDD = 2.0 V, with input low voltage (VINL) 0.35 V max.
3See Terminology Section.
4B Grade, maximum specs apply as typical figures when VDD = 4.75 V to 5.25 V.
5SC70 values guaranteed by characterization.
6Sample tested @ 25°C to ensure compliance.
7See Power Versus Throughput Rate section.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1
(VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)
AD7910/AD7920
Limit at TMIN, TMAX
Parameter
Unit
Description
2
fSCLK
10
5
kHz min3
MHz max
tCONVERT
tQUIET
14 ꢁ tSCLK
16 ꢁ tSCLK
50
AD7910
AD7920
ns min
Minimum Quiet Time Required between Bus Relinquish and
Start of Next Conversion
t1
10
10
22
40
ns min
ns min
ns max
ns max
ns min
ns min
Minimum CS Pulsewidth
CS to SCLK Setup Time
Delay from CS until SDATA Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK Low Pulsewidth
t24
t34
t4
t5
0.4 ꢁ tSCLK
0.4 ꢁ tSCLK
t65
SCLK High Pulsewidth
t7
SCLK to Data Valid Hold Time
VDD ≤ 3.3 V
3.3 V < VDD ≤ 3.6 V
VDD > 3.6 V
SCLK Falling Edge to SDATA Three-State
SCLK Falling Edge to SDATA Three-State
Power-Up Time from Full Power-Down
10
9.5
7
36
See Note 7
1
ns min
ns min
ns min
ns max
ns min
µs max
6
t8
8
tPOWER-UP
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3Minimum fSCLK at which specifications are guaranteed.
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 1.8 V when V DD = 2.35 V and 0.8 V or 2.0 V for VDD > 2.35 V.
5Measured with a 50 pF load capacitor.
6t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the Timing Characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
7t7 values apply to t8 minimum values also.
8See Power-Up Time section.
Specifications subject to change without notice.
–4–
REV. 0
AD7910/AD7920
TIMING EXAMPLES
Figures 2 and 3 show some of the timing parameters from the
Timing Specifications table.
I
200A
200A
OL
TO OUTPUT
PIN
1.6V
Timing Example 1
C
50pF
L
From figure 3, having fSCLK = 5 MHz and a throughput rate of
250 kSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 4 µs.
With t2 = 10 ns min, this leaves tACQ to be 1.49 µs. This 1.49 µs
satisfies the requirement of 250 ns for tACQ. From Figure 3, tACQ
comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 36 ns max.
This allows a value of 954 ns for tQUIET, satisfying the minimum
requirement of 50 ns.
I
OH
Figure 1. Load Circuit for Digital Output Timing
Specifications
t1
CS
tCONVERT
t2
t6
B
SCLK
1
2
3
4
5
13
14
t5
15
16
t8
t3
t4
t7
tQUIET
SDATA
Z
ZERO
ZERO
ZERO
DB11
DB10
DB2
DB1
DB0
THREE-
STATE
THREE-STATE
4 LEADING ZEROS
Figure 2. AD7920 Serial Interface Timing Diagram
CS
tCONVERT
t2
B
C
SCLK
1
2
3
4
5
13
14
15
16
t8
tQUIET
tACQ
12.5(1/f
)
SCLK
1/THROUGHPUT
Figure 3. Serial Interface Timing Example
Timing Example 2
The AD7920 can also operate with slower clock frequencies.
From Figure 3, having fSCLK = 3.4 MHz and a throughput rate
This allows a value of 2.19 µs for tQUIET satisfying the minimum
requirement of 50 ns. As in this example and with other slower
clock values, the signal may already be acquired before the con-
version is complete, but it is still necessary to leave 50 ns minimum
tQUIET between conversions. In this example, the signal should
be fully acquired at approximately point C in Figure 3.
of 150 kSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ
=
6.66 µs. With t2 = 10 ns min, this leaves tACQ to be 2.97 µs. This
2.97 µs satisfies the requirement of 250 ns for tACQ. From Fig-
ure 3, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, t8 = 36 ns max.
REV. 0
–5–
AD7910/AD7920
ABSOLUTE MAXIMUM RATINGS1
SC70 Package
(TA = 25°C, unless otherwise noted.)
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 340.2°C/W
θ
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 228.9°C/W
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V
Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . 10 mA
Operating Temperature Range
Commercial (A, B Grade) . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
MSOP Package
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.5 kV
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2 Transient currents of up to 100 mA will not cause SCR latch-up.
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 205.9°C/W
θ
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 43.74°C/W
ORDERING GUIDE
Temperature
Range
Linearity
Package
Option2
Model
Error (LSB)1
Branding
AD7910AKS
AD7910ARM
AD7920AKS
AD7920BKS
AD7920BRM
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0.5 max
0.5 max
0.75 typ
1.5 max
1.5 max
KS-6
RM-8
KS-6
KS-6
RM-8
CVA
CVA
CUA
CUB
CUB
NOTES
1Linearity Error here refers to integral nonlinearity.
2KS = SC70, RM = MSOP.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7910/AD7920 feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–6–
REV. 0
AD7910/AD7920
PIN CONFIGURATION
6-Lead SC70
8-Lead MSOP
1
6
5
4
CS
V
1
2
3
4
8
7
6
5
DD
V
V
AD7910/
AD7920
IN
DD
AD7910/
AD7920
2
3
SDATA
SCLK
GND
GND
SDATA
CS
V
IN
TOP VIEW
(Not to Scale)
SCLK
NC
TOP VIEW
(Not to Scale)
NC
NC = NO CONNECT
PIN FUNCTION DESCRIPTION
Mnemonic
Function
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7910/
AD7920 and also framing the serial data transfer.
VDD
Power Supply Input. The VDD range for the AD7910/AD7920 is from 2.35 V to 5.25 V.
Analog Ground. Ground reference point for all circuitry on the AD7910/AD7920. All analog input signals should be
referred to this GND voltage.
GND
VIN
Analog Input. Single-ended analog input channel. The input range is 0 to VDD.
SDATA
Data Out. Logic output. The conversion result from the AD7910/AD7920 is provided on this output as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7920 consists
of four leading zeros followed by the 12 bits of conversion data, which is provided MSB first. The data stream from
the AD7910 consists of four leading zeros followed by the 10 bits of conversion data followed by two trailing zeros,
which is also provided MSB first.
SCLK
NC
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also
used as the clock source for the AD7910/AD7920 conversion process.
No Connect
REV. 0
–7–
AD7910/AD7920
TERMINOLOGY
Total Unadjusted Error
Integral Nonlinearity
This is a comprehensive specification that includes gain error,
linearity error, and offset error.
This is the maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. For the AD7920 and
AD7910, the endpoints of the transfer function are zero scale, a
point 1 LSB below the first code transition, and full scale, a point
1 LSB above the last code transition.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of har-
monics to the fundamental. It is defined as:
2
2
2
2
2
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
V2 +V3 +V4 +V5 +V6
THD (dB) = 20log
V1
where V1 is the rms amplitude of the fundamental and V2, V3, V4,
V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e, GND + 1 LSB.
Peak Harmonic or Spurious Noise
Gain Error
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output spec-
trum (up to fS/2 and excluding dc) to the rms value of the funda-
mental. Normally, the value of this specification is determined by
the largest harmonic in the spectrum, but for ADCs whose har-
monics are buried in the noise floor, it will be a noise peak.
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal, i.e, VREF – 1 LSB after the offset
error has been adjusted out.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode at the end
of conversion. Track-and-Hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within 0.5 LSB, after the end of conversion. See
the Serial Interface section for more details.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digitiza-
tion process; the more levels, the smaller the quantization noise.
The theoretical signal-to-(noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:
The AD7910/AD7920 are tested using the CCIF standard where
two input frequencies are used (see fa and fb in the specification
page). In this case, the second-order terms are usually distanced
in frequency from the original sine waves while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification, the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals, expressed in dB.
Signal-to-(Noise + Distortion) = (6.02N +1.76) dB
Thus, for a 12-bit converter this is 74 dB, and for a 10-bit converter
this is 62 dB.
–8–
REV. 0
Typical Performance Characteristics–AD7910/AD7920
TPC 1 and TPC 2 show a typical FFT plot for the AD7920 and
AD7910, respectively, at 250 kSPS sampling rate and 100 kHz
input frequency.
TPC 6 shows a graph of the total harmonic distortion versus analog
input frequency for different source impedances when using a
supply voltage of 3.6 V and sampling at a rate of 250 kSPS. See the
Analog Input section.
TPC 3 shows the signal-to-(noise + distortion) ratio performance
versus input frequency for various supply voltages while sampling
at 250 kSPS with a SCLK frequency of 5 MHz for the AD7920.
TPC 7 shows a graph of the total harmonic distortion versus analog
input signal frequency for various supply voltages while sampling
at 250 kSPS with an SCLK frequency of 5 MHz.
TPC 4 and TPC 5 show typical INL and DNL performance for the
AD7920.
5
–71.0
8192 POINT FFT
V
= 2.7V
= 250kSPS
= 100kHz
DD
V
DD
= 5.25V
= 4.75V
–15
–35
f
IN
SAMPLE
f
–71.5
SINAD = 72.05dB
THD = –82.87dB
SFDR = –87.24dB
–72.0
–72.5
V
DD
V
= 3.6V
V
= 2.7V
DD
DD
–55
–75
V
= 2.35V
DD
–73.0
–73.5
–95
–115
10
100
FREQUENCY – kHz
1000
0
25
50
75
100
125
FREQUENCY – kHz
TPC 3. AD7920 SINAD vs. Input Frequency at 250 kSPS
TPC 1. AD7920 Dynamic Performance at 250 kSPS
1.0
8192 POINT FFT
V
= 2.35V
DD
0.8
V
= 2.35V
DD
TEMP = 25؇C
fSAMPLE = 250kSPS
–5
–25
f
IN
= 250kSPS
= 100kHz
SAMPLE
f
0.6
0.4
0.2
0
SINAD = 61.67dB
THD = –79.59dB
SFDR = –82.93dB
–45
–0.2
–65
–0.4
–0.6
–85
–0.8
–1.0
–105
0
25
50
75
100
125
0
512
1024
1536
2048
2560 3072
3584
4096
CODE
FREQUENCY – kHz
TPC 4. AD7920 INL Performance
TPC 2. AD7910 Dynamic Performance at 250 kSPS
REV. 0
–9–
AD7910/AD7920
1.0
–65
V
= 2.35V
DD
0.8
TEMP = 25؇C
fSAMPLE = 250kSPS
0.6
0.4
0.2
0
–70
–75
V
= 2.35V
DD
–80
–85
–90
–0.2
V
= 4.75V
DD
–0.4
–0.6
V
= 3.6V
DD
–0.8
–1.0
V
= 2.7V
100
DD
V
= 5.25V
DD
10
1000
0
512
1024
1536
2048
2560 3072
3584
4096
INPUT FREQUENCY – kHz
CODE
TPC 7. THD vs. Analog Input Frequency for
Various Supply Voltages
TPC 5. AD7920 DNL Performance
–10
V
= 3.6V
DD
–20
–30
–40
–50
R
= 10k⍀
= 1k⍀
IN
–60
R
IN
–70
–80
R
= 130⍀
IN
R
= 13⍀
IN
R
= 0⍀
IN
–90
10
100
INPUT FREQUENCY – kHz
1000
TPC 6. THD vs. Analog Input Frequency for
Various Source Impedances
CONVERTER OPERATION
CIRCUIT INFORMATION
The AD7910/AD7920 is a successive approximation analog-
to-digital converter based around a charge redistribution DAC.
Figures 4 and 5 show simplified schematics of the ADC.
Figure 4 shows the ADC during its acquisition phase. SW2 is
closed, and SW1 is in position A, the comparator is held in a
balanced condition, and the sampling capacitor acquires the
signal on VIN.
The AD7910/AD7920 are fast, micropower, 10-bit/12-bit,
single-supply A/D converters, respectively. The parts can be
operated from a 2.35 V to 5.25 V supply. When operated from
either a 5 V supply or a 3 V supply, the AD7910/AD7920 are
capable of throughput rates of 250 kSPS when provided with a
5 MHz clock.
The AD7910/AD7920 provide the user with an on-chip track-
and-hold, A/D converter, and a serial interface housed in a tiny
6-lead SC70 package or 8-lead MSOP package, which offers the
user considerable space saving advantages over alternative solu-
tions. The serial clock input accesses data from the part but also
provides the clock source for the successive approximation A/D
converter. The analog input range is 0 V to VDD. An external
reference is not required for the ADC and there is no reference
on-chip. The reference for the AD7910/AD7920 is derived from
the power supply and thus gives the widest dynamic input range.
CHARGE
REDISTRIBUTION
DAC
SAMPLING
CAPACITOR
A
V
IN
CONTROL
LOGIC
SW1
B
ACQUISITION
PHASE
SW2
COMPARATOR
AGND
V
/2
DD
The AD7910/AD7920 also feature a power-down option to
allow power saving between conversions. The power-down feature
is implemented across the standard serial interface, as described
in the Modes of Operation section.
Figure 4. ADC Acquisition Phase
–10–
REV. 0
AD7910/AD7920
When the ADC starts a conversion (see Figure 5), SW2 opens
and SW1 moves to position B, causing the comparator to become
unbalanced. The control logic and charge redistribution DAC are
used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
Figure 6 shows the ADC transfer function.
Alternatively, because the supply current required by the AD7910/
AD7920 is so low, a precision reference can be used as the
supply source to the AD7910/AD7920. An REF19x voltage
reference (REF195 for 5 V or REF193 for 3 V) can be used to
supply the required voltage to the ADC (see Figure 7). This con-
figuration is especially useful if the power supply is quite noisy
or if the system supply voltages are at a value other than 5 V or
3 V (e.g., 15 V). The REF19x will output a steady voltage to the
AD7910/AD7920. If the low dropout REF193 is used, the current
it needs to supply to the AD7910/AD7920 is typically 1.2 mA.
When the ADC is converting at a rate of 250 kSPS the REF193
needs to supply a maximum of 1.4 mA to the AD7910/AD7920.
The load regulation of the REF193 is typically 10 ppm/mA
(REF193, VS = 5 V), which results in an error of 14 ppm (42 µV)
for the 1.4 mA drawn from it. This corresponds to a 0.057 LSB
error for the AD7920 with VDD = 3 V from the REF193 and a
0.014 LSB error for the AD7910. For applications where power
consumption is of concern, the Power-Down mode of the ADC
and the sleep mode of the REF19x reference should be used to
improve power performance. See the Modes of Operation section.
CHARGE
REDISTRIBUTION
DAC
SAMPLING
CAPACITOR
A
V
IN
CONTROL
LOGIC
SW1
SW2
CONVERSION
PHASE
B
COMPARATOR
AGND
V
/2
DD
Figure 5. ADC Conversion Phase
ADC Transfer Function
The output coding of the AD7910/AD7920 is straight binary.
The designed code transitions occur at the successive integer
LSB values, i.e, 1 LSB, 2 LSBs, and so on. The LSB size is
VDD/4096 for the AD7920 and VDD/1024 for the AD7910. The
ideal transfer characteristic for the AD7910/AD7920 is shown
in Figure 6.
3V
5V
REF193
SUPPLY
1F
TANT
0.1F
10F
0.1F
1.2mA
680nF
V
DD
0VTOV
DD
INPUT
SCLK
V
IN
AD7910/
AD7920/
C/P
SDATA
GND
111...111
111...110
CS
SERIAL
INTERFACE
111...000
1LSB =V /1024 (AD7910)
DD
1LSB =V /4096 (AD7920)
DD
Figure 7. REF193 as Power Supply
011...111
Table I provides typical performance data with various references
used as a VDD source for a 100 kHz input tone at room temper-
ature under the same setup conditions.
000...010
000...001
000...000
1LSB
+V –1LSB
DD
0V
ANALOG INPUT
Table I. AD7920 Typical Performance
for Various Voltage References IC
Figure 6. Transfer Characteristic
Typical Connection Diagram
Reference
Tied to VDD
AD7920 SNR
Performance (dB)
Figure 7 shows a typical connection diagram for the AD7910/
AD7920. VREF is taken internally from VDD and, as such, VDD
should be well decoupled. This provides an analog input range of
0 V to VDD. The conversion result is output in a 16-bit word with
four leading zeros followed by the MSB of the 12-bit or 10-bit
result. The 10-bit result from the AD7910 will be followed by two
trailing zeros.
AD780 @ 3 V
REF193
AD780 @ 2.5 V
REF192
72.65
72.35
72.5
72.2
REF43
72.6
REV. 0
–11–
AD7910/AD7920
Analog Input
Digital Inputs
Figure 8 shows an equivalent circuit of the analog input structure
of the AD7910/AD7920. The two diodes D1 and D2 provide
ESD protection for the analog input. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 300 mV. This will cause these diodes to become
forward-biased and start conducting current into the substrate.
10 mA is the maximum current these diodes can conduct without
causing irreversible damage to the part. The capacitor C1 in
Figure 8 is typically about 6 pF and can be attributed primarily to
pin capacitance. The resistor R1 is a lumped component made
up of the on resistance of a switch. This resistor is typically about
100 Ω. The capacitor C2 is the ADC sampling capacitor and has
a capacitance of 20 pF typically. For ac applications, removing
high frequency components from the analog input signal is
recommended by use of a band-pass filter on the relevant analog
input pin. In applications where harmonic distortion and signal-
to-noise ratio are critical, the analog input should be driven from
a low impedance source. Large source impedances will signifi-
cantly affect the ac performance of the ADC. This may necessitate
the use of an input buffer amplifier. The choice of the op amp is
a function of the particular application.
The digital inputs applied to the AD7910/AD7920 are not
limited by the maximum ratings that limit the analog input. Instead,
the digital inputs applied can go to 7 V and are not restricted
by the VDD + 0.3 V limit as on the analog input. For example, if
the AD7910/AD7920 were operated with a VDD of 3 V, then 5 V
logic levels could be used on the digital inputs. However it is
important to note that the data output on SDATA will still have 3 V
logic levels when VDD = 3 V. Another advantage of SCLK and
CS not being restricted by the VDD + 0.3 V limit is that power
supply sequencing issues are avoided. If CS or SCLK is applied
before VDD, there is no risk of latch-up as there would be on the
analog inputs if a signal greater than 0.3 V was applied prior to VDD
.
MODES OF OPERATION
The mode of operation of the AD7910/AD7920 is selected by
controlling the logic state of the CS signal during a conversion.
There are two possible modes of operation, Normal mode and
Power-Down mode. The point at which CS is pulled high
after the conversion has been initiated determines whether the
AD7910/AD7920 enters Power-Down mode. Similarly, if
already in Power-Down mode then CS can control whether the
device returns to Normal operation or remains in Power-Down
mode. These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for different
application requirements.
V
DD
C2
20pF
D1
D2
R1
V
IN
Normal Mode
C1
6pF
This mode is intended for fastest throughput rate performance
as the user does not have to worry about any power-up times,
with the AD7910/AD7920 remaining fully powered all the time.
Figure 9 shows the general diagram of the operation of the
AD7910/AD7920 in this mode.
CONVERSION PHASE – SWITCH OPEN
TRACK PHASE – SWITCH CLOSED
Figure 8. Equivalent Analog Input Circuit
The conversion is initiated on the falling edge of CS as described in
the Serial Interface section. To ensure the part remains fully pow-
ered up at all times, CS must remain low until at least 10 SCLK
falling edges have elapsed after the falling edge of CS. If CS is
brought high any time after the 10th SCLK falling edge but before
the end of the tCONVERT, the part will remain powered up but
the conversion will be terminated and SDATA will go back into
three-state.
Table II provides some typical performance data with various
op amps used as the input buffer for a 100 kHz input tone at room
temperature under the same setup conditions.
Table II. AD7920 Typical Performance
for Various Input Buffers, VDD = 3 V
Op Amp in the
Input Buffer
AD7920 SNR
Performance (dB)
For the AD7920, 16 serial clock cycles are required to complete
the conversion and access the complete conversion result. For the
AD7910, a minimum of 14 serial clock cycles is required to com-
plete the conversion and access the complete conversion result.
AD711
AD797
AD845
72.3
72.5
71.4
CS may idle high until the next conversion or may idle low until CS
returns high sometime prior to the next conversion, effectively
idling CS low.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of total harmonic distortion
(THD) that can be tolerated. The THD increases as the source
impedance increases, and performance degrades (see TPC 6).
Once a data transfer is complete (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
t
QUIET, has elapsed by bringing CS low again.
–12–
REV. 0
AD7910/AD7920
Power-Down Mode
as long as CS is held low until after the falling edge of the 10th
SCLK. The device will be fully powered up once 16 SCLKs
have elapsed and valid data will result from the next conversion,
as shown in Figure 11. If CS is brought high before the 10th SCLK
falling edge, the AD7910/AD7920 will go back into Power-Down
mode again. This avoids accidental power-up due to glitches on
the CS line or an inadvertent burst of eight SCLK cycles while
CS is low. Although the device may begin to power up on the
falling edge of CS, it will power down again on the rising edge
of CS as long as it occurs before the 10th SCLK falling edge.
This mode is intended for use in applications where slower through-
put rates are required; either the ADC is powered down between
each conversion, or a series of conversions may be performed at a
high throughput rate and the ADC is powered down for a rela-
tively long duration between these bursts of several conversions.
When the AD7910/AD7920 is in Power-Down mode, all analog
circuitry is powered down.
To enter Power-Down mode, the conversion process must be
interrupted by bringing CS high anywhere after the second
falling edge of SCLK, and before the 10th falling edge of SCLK
as shown in Figure 10. Once CS has been brought high in this
window of SCLKs, the part will enter Power-Down mode, the
conversion that was initiated by the falling edge of CS will be
terminated, and SDATA will go back into three-state. If CS is
brought high before the second SCLK falling edge, the part will
remain in Normal mode and will not power down. This will
avoid accidental power-down due to glitches on the CS line.
Power-Up Time
The power-up time of the AD7910/AD7920 is 1 µs, which means
that one dummy cycle will always be sufficient to allow the device
to power up. Once the dummy cycle is complete, the ADC will
be fully powered up and the input signal will be acquired properly.
The quiet time, tQUIET, must still be allowed from the point where
the bus goes back into three-state after the dummy conversion,
to the next falling edge of CS.
To exit this mode of operation and power up the AD7910/AD7920
again, a dummy conversion is performed. On the falling edge of CS,
the device will begin to power up, and will continue to power up
When powering up from the Power-Down mode with a dummy
cycle, as in Figure 11, the track-and-hold that was in hold mode
while the part was powered down returns to track mode after
AD7910/AD7920
CS
1
10
12
14
16
SCLK
SDATA
VALID DATA
Figure 9. Normal Mode Operation
CS
1
2
10
12
14
16
SCLK
THREE-STATE
SDATA
Figure 10. Entering Power-Down Mode
THE PART IS FULLY
POWERED UPWITH
FULLY ACQUIRED
THE PART
BEGINSTO
POWER UP
V
IN
CS
A1
10
12
14
16
1
16
SCLK
SDATA
INVALID DATA
VALID DATA
Figure 11. Exiting Power-Down Mode
REV. 0
–13–
AD7910/AD7920
the first SCLK edge the part receives after the falling edge of
CS. This is shown as point A in Figure 11. Although at any
SCLK frequency one dummy cycle is sufficient to power up the
device and acquire VIN, it does not necessarily mean that a full
dummy cycle of 16 SCLKs must always elapse to power up the
device and fully acquire VIN; 1 ꢀs will be sufficient to power the
device up and acquire the input signal. So, if a 5 MHz SCLK
frequency is applied to the ADC, the cycle time will be 3.2 ꢀs.
In one dummy cycle, 3.2 ꢀs, the part will be powered up and
VIN fully acquired. However after 1 µs with a 5 MHz SCLK,
only five SCLK cycles will have elapsed. At this stage, the ADC
will be fully powered up and the signal acquired. In this case, the
CS can be brought high after the 10th SCLK falling edge and
brought low again after a time, tQUIET, to initiate the conversion.
dummy conversion (when the part is exiting Power-Down mode
and powering up), and the power dissipated during conversion.
As mentioned in the Power-Down mode section, to enter Power-
Down mode, CS has to be brought high anywhere between the
second and 10th SCLK falling edge. Therefore, the power con-
sumption when entering Power-Down mode will vary depending
on the number of SCLK cycles used. In this example, five SCLK
cycles will be used to enter Power-Down mode. This gives a
period time of 5 ꢁ (1/fSCLK) = 1 ꢀs.
The power-up time is 1 ꢀs, which implies that only five SCLK
cycles are required to power up the part. However, CS has to
remain low until at least the 10th SCLK falling edge when
exiting Power-Down mode. This means that a minimum of nine
SCLK cycles have to be used to exit Power-Down mode and
power up the part.
When power supplies are first applied to the AD7910/AD7920,
the ADC may power up in either power down mode or in normal
mode. Because of this, it is best to allow a dummy cycle to elapse
to ensure the part is fully powered up before attempting a valid
conversion. Likewise, if it is intended to keep the part in Power-
Down mode while not in use and the user wishes the part to
power up in Power-Down mode, the dummy cycle may be used
to ensure the device is in power-down by executing a cycle such
as that shown in Figure 10. Once supplies are applied to the
AD7910/AD7920, the power-up time is the same as that when
powering up from Power-Down mode. It takes approximately 1 ꢀs
to power up fully if the part powers up in normal mode. It is not
necessary to wait 1 µs before executing a dummy cycle to ensure
the desired mode of operation. Instead, the dummy cycle can
occur directly after power is supplied to the ADC. If the first valid
conversion is performed directly after the dummy conversion,
care must be taken to ensure that adequate acquisition time is
allowed. As mentioned earlier, when powering up from the
Power-Down mode, the part will return to track upon the first
SCLK edge applied after the falling edge of CS. However when
the ADC powers up initially after supplies are applied, the
track-and-hold will already be in track. This means, assuming one
has the facility to monitor the ADC supply current, if the ADC
powers up in the desired mode of operation and thus a dummy
cycle is not required to change mode, neither is a dummy cycle
required to place the track-and-hold into track.
So, if nine SCLK cycles are used, the time to power up the part
and exit Power-Down mode is 9 ꢁ (1/fSCLK) = 1.8 ꢀs.
Finally, the conversion time is 16 ꢁ (1/fSCLK) = 3.2 ꢀs.
Therefore, the AD7910/AD7920 can be said to dissipate 15 mW
for 3.2 ꢀs + 1.8 ꢀs + 1 ꢀs = 6 ꢀs during each conversion cycle. If
the throughput rate is 100 kSPS, the cycle time is 10 ꢀs and the
average power dissipated during each cycle is (6/10) ꢁ (15 mW) =
9 mW. The power dissipation when the part is in power-down has
not been taken into account as the shutdown current is so low and
it does not have any effect on the overall power dissipation value.
If VDD = 3 V, SCLK = 5 MHz and the device is again in Power-
Down mode between conversions, the power dissipation during
normal operation is 4.2 mW. Assuming the same timing conditions
as before, the AD7910/AD7920 can now be said to dissipate
4.2 mW for 6 µs during each conversion cycle. With a throughput
rate of 100 kSPS, the average power dissipated during each cycle is
(6/10) ꢁ (4.2 mW) = 2.52 mW. Figure 12 shows the power versus
throughput rate when using the Power-Down mode between
conversions with both 5 V and 3 V supplies.
Power-Down mode is intended for use with throughput rates of
approximately 160 kSPS and under, because at higher sampling
rates there is no power saving made by using the Power-Down mode.
100
POWER VS. THROUGHPUT RATE
By using the Power-Down mode on the AD7910/AD7920 when
not converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 12 shows how as the
throughput rate is reduced, the device remains in its power-down
state longer and the average power consumption over time
drops accordingly.
V
= 5V, SCLK = 5MHz
DD
10
1
V
= 3V, SCLK = 5MHz
DD
For example, if the AD7910/AD7920 is operated in a continuous
sampling mode with a throughput rate of 100 kSPS and a SCLK
of 5 MHz (VDD = 5 V), and the device is placed in the Power-
Down mode between conversions, the power consumption is
calculated as follows:
0.1
0.01
0
20
40
60
80
100
120
140
160
180
The power dissipation during normal mode is 15 mW (VDD = 5 V).
The power dissipation includes the power dissipated while the part
is entering Power-Down mode, the power dissipated during the
THROUGHPUT RATE – kSPS
Figure 12. Power vs. Throughput Rate
–14–
REV. 0
AD7910/AD7920
t1
CS
tCONVERT
t2
t6
B
SCLK
1
2
3
4
5
13
14
t5
15
16
t8
t3
t4
t7
tQUIET
SDATA
Z
ZERO
ZERO
ZERO
DB11
DB10
DB2
DB1
DB0
THREE-
STATE
THREE-STATE
4 LEADING ZEROS
1/THROUGHPUT
Figure 13. AD7920 Serial Interface Timing Diagram
t1
CS
tCONVERT
t2
t6
B
1
2
3
4
5
13
15
14
t5
SCLK
16
t8
t7
tQUIET
t4
t3
DB0
ZERO
ZERO
DB9
ZERO
ZERO
Z
ZERO
DB8
SDATA
THREE-STATE
THREE-STATE
4 LEADING ZEROS
2 TRAILING ZEROS
1/THROUGHPUT
Figure 14. AD7910 Serial Interface Timing Diagram
SERIAL INTERFACE
If the rising edge of CS occurs before 14 SCLKs have elapsed,
the conversion is terminated and the SDATA line goes back into
three-state. If 16 SCLKs are used in the cycle, SDATA returns to
three-state on the 16th SCLK falling edge, as shown in Figure 14.
Figures 13 and 14 show the detailed timing diagram for serial
interfacing to the AD7920 and AD7910, respectively. The serial
clock provides the conversion clock and also controls the transfer
of information from the AD7910/AD7920 during conversion.
CS going low clocks out the first leading zero to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges beginning with the sec-
ond leading zero. Thus the first falling clock edge on the serial
clock has the first leading zero provided and also clocks out the
second leading zero. The final bit in the data transfer is valid on
the 16th falling edge, having being clocked out on the previous
(15th) falling edge.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
takes the bus out of three-state and the analog input is sampled
at that point. The conversion is also initiated at this point.
For the AD7920, the conversion requires 16 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, track-and-
hold goes back into track on the next SCLK rising edge as shown
in Figure 13 at point B. On the 16th SCLK falling edge, the
SDATA line goes back into three-state. If the rising edge of CS
occurs before 16 SCLKs have elapsed, then the conversion will
be terminated and the SDATA line goes back into three-state;
otherwise, SDATA returns to three-state on the 16th SCLK
falling edge, as shown in Figure 13. Sixteen serial clock cycles
are required to perform the conversion process and to access data
from the AD7920.
In applications with a slower SCLK, it is possible to read in data on
each SCLK rising edge. In this case, the first falling edge of SCLK
will clock out the second leading zero and it could be read in the
first rising edge. However, the first leading zero that was clocked
out when CS went low will be missed unless it was not read in
the first falling edge. The 15th falling edge of SCLK will clock
out the last bit and it could be read in the 15th rising SCLK edge.
If CS goes low just after the SCLK falling edge has elapsed, CS
clocks out the first leading zero as before, and it may be read on the
SCLK rising edge. The next SCLK falling edge clocks out the second
leading zero and it could be read on the following rising edge.
For the AD7910, the conversion requires 14 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, track-and-
hold goes back into track on the next SCLK rising edge, as shown
in Figure 14 at point B.
REV. 0
–15–
AD7910/AD7920
MICROPROCESSOR INTERFACING
AD7910/AD7920 to ADSP-218x
The serial interface on the AD7910/AD7920 allows the part to
be directly connected to a range of different microprocessors.
This section explains how to interface the AD7910/AD7920
with some of the more common microcontroller and DSP serial
interface protocols.
The ADSP-218x family of DSPs is interfaced directly to the
AD7910/AD7920 without any glue logic required. The SPORT
control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
AD7910/AD7920 to TMS320C541 Interface
The serial interface on the TMS320C541 uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices like the AD7910/
AD7920. The CS input allows easy interfacing between the
TMS320C541 and the AD7910/AD7920 without any glue logic
required. The serial port of the TMS320C541 is set up to operate
in burst mode (FSM = 1 in the Serial Port Control register, SPC)
with internal serial clock CLKX (MCM = 1 in SPC register) and
internal frame signal (TXM = 1 in the SPC), so both pins are
configured as outputs. For the AD7920, the word length should
be set to 16 bits (FO = 0 in the SPC register). This DSP allows
frames with a word length of 16 or 8 bits. Therefore, in the case
of the AD7910 where just 14 bits could be required, the FO bit
would be set up to 16 bits also. This means that to obtain the
conversion result, 16 SCLKs are needed and two trailing zeros will
be clocked out in the two last clock cycles.
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0, Sets up RFS as an Input
ITFS = 1, Sets up TFS as an Output
SLEN = 1111, 16 Bits for the AD7920
SLEN = 1101, 14 Bits for the AD7910
To implement Power-Down mode, SLEN should be set to 1001
to issue an 8-bit SCLK burst. The connection diagram is shown
in Figure 16. The ADSP-218x has the TFS and RFS of the
SPORT tied together, with TFS set as an output and RFS set as
an input. The DSP operates in alternate framing mode and the
SPORT control register is set up as described. The frame syn-
chronization signal generated on the TFS is tied to CS and, as
with all signal processing applications, equidistant sampling is
necessary. However, in this example, the timer interrupt is used
to control the sampling rate of the ADC and, under certain
conditions, equidistant sampling may not be achieved.
To summarize, the values in the SPC register are:
FO = 0
The timer registers are loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
received, a value is transmitted with TFS/DT (ADC control word).
The TFS is used to control the RFS and thus the reading of
data. The frequency of the serial clock is set in the SCLKDIV
register. When the instruction to transmit with TFS is given,
i.e., AX0 = TX0, the state of the SCLK is checked. The DSP
waits until the SCLK has gone high, low, and high before trans-
mission starts. If the timer and SCLK values are chosen such
that the instruction to transmit occurs on or near the rising edge
of SCLK, the data may be transmitted or it may wait until the
next clock edge.
FSM = 1
MCM = 1
TXM = 1
The format bit, FO, may be set to 1 to set the word length to
eight bits, in order to implement the Power-Down mode on the
AD7910/AD7920.
The connection diagram is shown in Figure 15. It should be noted
that for signal processing applications, it is imperative that the
frame synchronization signal from the TMS320C541 provides
equidistant sampling.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained and eight master clock periods will
elapse for every one SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs will occur between interrupts
and subsequently between transmit instructions. This situation
will result in nonequidistant sampling as the transmit instruction
is occurring on a SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling
will be implemented by the DSP.
TMS320C541*
AD7910/AD7920*
SCLK
CLKX
CLKR
DR
SDATA
CS
FSX
FSR
ADSP-218x*
SCLK
AD7910/AD7920
*
*ADDITIONAL PINS OMITTED FOR CLARITY
SCLK
SDATA
CS
Figure 15. Interfacing to the TMS320C541
DR
RFS
TFS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. Interfacing to the ADSP-218x
–16–
REV. 0
AD7910/AD7920
AD7910/AD7920 to DSP563xx Interface
APPLICATION HINTS
Grounding and Layout
The diagram in Figure 17 shows how the AD7910/AD7920 can
be connected to the SSI (synchronous serial interface) of the
DSP563xx family of DSPs from Motorola. The SSI is operated
in Synchronous and Normal mode (SYN = 1 and MOD = 0 in
the Control Register B, CRB) with internally generated word
frame sync for both Tx and Rx (bits FSL1 = 0 and FSL0 = 0 in
the CRB). Set the word length in the Control Register A (CRA)
to 16 by setting bits WL2 = 0, WL1 = 1 and WL0 = 0 for the
AD7920. This DSP does not offer the option for a 14-bit word
length, so the AD7910 word length will be set to 16 bits like the
AD7920. For the AD7910, the conversion process will use 16
SCLK cycles, with the last two clock periods clocking out two
trailing zeros to fill the 16-bit word.
The printed circuit board that houses the AD7910/AD7920
should be designed such that the analog and digital sections are
separated and confined to certain areas of the board. This
facilitates the use of ground planes that can be easily separated.
A minimum etch technique is generally best for ground planes as
it gives the best shielding. Digital and analog ground planes
should be joined at only one place. If the AD7910/AD7920 is in a
system where multiple devices require an AGND to DGND
connection, the connection should still be made at one point only,
a star ground point that should be established as close to the
AD7910/AD7920 as possible.
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7910/AD7920 to avoid noise coupling. The
power supply lines to the AD7910/AD7920 should use as large
a trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line. Fast switching
signals like clocks should be shielded with digital ground to avoid
radiating noise to other sections of the board, and clock signals
should never be run near the analog inputs. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This will reduce the
effects of feedthrough through the board. A microstrip technique
is by far the best but is not always possible with a double-sided
board. In this technique, the component side of the board is dedi-
cated to ground planes while signals are placed on the solder side.
To implement the Power-Down mode on the AD7910/AD7920,
the word length can be changed to eight bits by setting bits
WL2 = 0, WL1 = 0, and WL0 = 0 in CRA. The FSP bit in the
CRB register can be set to 1, which means the frame goes low and
a conversion starts. Likewise, by means of bits SCD2, SCKD,
and SHFD in the CRB register, it will be established that pin
SC2 (the frame sync signal) and SCK in the serial port will be
configured as outputs and the MSB will be shifted first.
To summarize,
MOD = 0
SYN = 1
WL2, WL1, WL0 Depend on the Word Length
FSL1 = 1, FSL0 = 0
FSP = 1, Negative Frame Sync
SCD2 = 1
SCKD = 1
SHFD = 0
Good decoupling is also very important. The supply should be
decoupled with, for instance, a 680 nF 0805 to GND. When using
the SC70 package in applications where the size of the components
is of concern, a 220 nF 0603 capacitor, for example, could be used
instead. However, in that case, the decoupling may not be as
effective and may result in an approximate SINAD degradation of
0.3 dB. To achieve the best performance from these decoupling com-
ponents, the user should endeavor to keep the distance between
the decoupling capacitor and the VDD and GND pins to a minimum
with short track lengths connecting the respective pins. Figures 18
and 19 show the recommended positions of the decoupling
capacitor for the MSOP and SC70 packages respectively.
It should be noted that for signal processing applications, it is
imperative that the frame synchronization signal from the
DSP563xx provides equidistant sampling.
DSP563xx*
AD7910/AD7920*
SCK
SCLK
SDATA
SRD
SC2
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. Interfacing to the DSP563xx
REV. 0
–17–
AD7910/AD7920
As it can be seen in Figure 18, for the MSOP package the
decoupling capacitor has been placed as close as possible to the IC
with short track lengths to VDD and GND pins. The decoupling
capacitor could also be placed on the underside of the PCB directly
underneath the IC, between the VDD and GND pins attached by
vias. This method would not be recommended on PCBs above a
standard 1.6 mm thickness. The best performance will be seen with
the decoupling capacitor on the top of the PCB next to the IC.
Figure 19. Recommended Supply Decoupling
Scheme for the AD7910/AD7920 SC70 Package
Evaluating the AD7910/AD7920 Performance
Although there is no specific evaluation board to evaluate the
performance of the AD7910/AD7920, the AD7476/AD7477CB
and AD7476A/AD7477ACB evaluation boards could be used.
These evaluation boards have a similar serial interface to the
AD7910/AD7920, so they will help the user to get familiar with
the serial interface operation and also see how the part is imple-
mented in a system where the supply can be taken from different
voltage references, and how the ADC is connected to a DSP.
Figure 18. Recommended Supply Decoupling
Scheme for the AD7910/AD7920 MSOP Package
Similarly, for the SC70 package, the decoupling capacitor should
be located as close as possible to the VDD and GND pins. Because
of its pinout, i.e., VDD being next to GND, the decoupling capaci-
tor can be placed extremely close to the IC. The decoupling
capacitor could be placed on the underside of the PCB directly
under the VDD and GND pins, but, as before, the best perfor-
mance will be seen with the decoupling capacitor on the same
side as the IC.
The evaluation board package for any of the above mentioned
evaluation boards includes a fully assembled and tested evaluation
board, documentation, and software for controlling the board
from the PC via the Eval-Board Controller. The Eval-Board
Controller can be used in conjunction with the evaluation
board, as well as with many other Analog Devices evaluation
boards ending in the CB designator, to demonstrate/evaluate
the ac and dc performance of the ADC.
The software allows the user to perform ac (fast Fourier transform)
and dc (histogram of codes) tests on the ADC. See the evaluation
board technical note for more information.
–18–
REV. 0
AD7910/AD7920
OUTLINE DIMENSIONS
6-Lead Plastic Surface-Mount Package [SC70]
(KS-6)
Dimensions shown in millimeters
2.00 BSC
6
5
2
4
3
2.10 BSC
1.25 BSC
1
PIN 1
1.30 BSC
0.65 BSC
1.00
0.90
0.70
1.10 MAX
0.22
0.08
0.46
0.36
0.26
8؇
4؇
0؇
0.30
0.15
0.10 MAX
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203AB
8-Lead MSOP Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
8
5
4
4.90
BSC
3.00
BSC
1
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.80
0.40
8؇
0؇
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA
REV. 0
–19–
–20–
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