AD7835AP-REEL_技术文档

LC²MOS

Quad 14-Bit DACs

AD7834/AD7835

The AD7834 is a serial input device. Data is loaded in 16-bit

format from the external serial bus, MSB first after two leading

FEATURES

Four 14-bit DACs in one package

AD7834—serial loading

0s, into one via DIN, SCLK, and

.

FSYNC

AD7835—parallel 8-bit/14-bit loading

Voltage outputs

Power-on reset function

Max/Min output voltage range of 8.192 V

Maximum output voltage span of 14 V

Common voltage reference inputs

User-assigned device addressing

Clear function to user-defined voltage

Surface-mount packages

The AD7834 has five dedicated package address pins, PA0 to

PA4, that can be wired to AGND or V_CCto permit up to 32

AD7834s to be individually addressed in a multipackage

application.

The AD7835 can accept either 14-bit parallel loading or double-

byte loading, where right-justified data is loaded in one 8-bit

byte and one 6-bit byte. Data is loaded from the external bus

into one of the input latches under the control of the

,

WR CS

, and DAC channel address pins, A0 to A2.

BYSHF

AD7834—28-lead SOIC and PDIP

AD7835—44-lead MQFP and PLCC

With each device, the

signal is used to update all four

LDAC

APPLICATIONS

Process control

Automatic test equipment

General purpose instrumentation

DAC outputs simultaneously, or individually, on reception of

new data. In addition, for each device, the asynchronous

CLR

input can be used to set all signal outputs, V_OUT1 to V_OUT4, to

the user-defined voltage level on the Device Sense Ground pin,

DSG. On power-on, before the power supplies have stabilized,

internal circuitry holds the DAC output voltage levels to within

2 V of the DSG potential. As the supplies stabilize, the DAC

output levels move to the exact DSG potential (assuming

is exercised).

GENERAL DESCRIPTION

The AD7834 and AD7835 parts contain four 14-bit DACs on

one monolithic chip. The AD7834 and AD7835 have out-

put voltages in the range of 8.192 V with a maximum

span of 14 V.

CLR

The AD7834 is available in 28-lead 0.3" SOIC package and

28-lead 0.6" PDIP package, and the AD7835 is available in a

44-lead MQFP package and a 44-lead PLCC package.

AD7834 FUNCTIONAL BLOCK DIAGRAM

AD7835 FUNCTIONAL BLOCK DIAGRAM

V

(–)

V

(–)A

V

REF

V

(+)

V

(+)A

DSG A

REF

CC

REF

CC

DD

SS

REF

DD

SS

INPUT

AD7835

AD7834

INPUT

DAC 1

DAC 2

REGISTER

1

DAC 1

DAC 2

REGISTER

1

LATCH

PAEN

BYSHF

×

1

×1

V

1

2

V

1

2

OUT

14

DB13

DB0

PA0

PA1

INPUT

BUFFER

INPUT

REGISTER

2

INPUT

REGISTER

2

DAC 2

LATCH

DAC 2

LATCH

CONTROL

LOGIC

AND

ADDRESS

DECODE

V

OUT

PA2

PA3

PA4

OUT

WR

CS

INPUT

REGISTER

3

INPUT

REGISTER

3

DAC 3

LATCH

DAC 3

LATCH

DAC 3

DAC 4

DAC 3

DAC 4

×

1

V

3

4

×1

V

3

4

OUT

FSYNC

A0

A1

A2

INPUT

REGISTER

4

INPUT

REGISTER

4

ADDRESS

DECODE

DAC 4

LATCH

DAC 4

LATCH

SERIAL-TO-

PARALLEL

CONVERTER

DIN

V

OUT

CLR

SCLK

CLR

AGND

DGND

LDAC

DSG

DSG B

(+)B

AGND

DGND

V

(–)B

REF

V

LDAC

REF

Figure 1.

Figure 2.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD7834/AD7835

TABLE OF CONTENTS

Specifications..................................................................................... 3

DSG Voltage Range.................................................................... 18

Power-On of the AD7834/AD7835.............................................. 19

Microprocessor Interfacing........................................................... 20

AD7834 to 80C51 Interface ...................................................... 20

AD7834 to 68HC11 Interface................................................... 20

AD7834 to ADSP-2101 Interface ............................................. 20

AD7834 to DSP56000/DSP56001 Interface............................ 21

AD7834 to TMS32020/TMS320C25 Interface....................... 21

Interfacing the AD7835—16-Bit Interface.............................. 21

8-Bit Interface ............................................................................. 22

Applications..................................................................................... 23

Serial Interface to Multiple AD7834s ...................................... 23

Opto-Isolated Interface ............................................................. 23

Automated Test Equipment ...................................................... 23

Power Supply Bypassing and Grounding................................ 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 27

AC Performance Characteristics .................................................... 4

Timing Specifications....................................................................... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Terminology .................................................................................... 11

Typical Performance Characteristics ........................................... 12

Theory of Operation ...................................................................... 14

DAC Architecture—General..................................................... 14

Data Loading—AD7834, Serial Input Device ........................ 14

Data Loading—AD7835, Parallel Loading Device ................ 14

Unipolar Configuration............................................................. 15

Bipolar Configuration................................................................ 16

Controlled Power-On of the Output Stage.................................. 17

Power-On with

Low, LDAC High ................................... 17

CLR

Power-On with LDAC Low,

High ................................... 17

CLR

Loading the Dac and Using the

Input ............................ 17

CLR

REVISION HISTORY

7/05—Rev. B to Rev. C

Updated Format..................................................................Universal

Changes to Figure 40...................................................................... 25

Changes to Ordering Guide .......................................................... 27

7/03—Rev. A to Rev. B

Revision 0: Initial Version

Rev. C | Page 2 of 28

AD7834/AD7835

SPECIFICATIONS

1

V_CC= +5 V 5%; V_DD= +15 V 5%; V_SS= −15 V 5%; AGND = DGND = 0 V; T_A= T_MINto T_MAX, unless otherwise noted.

Table 1.

Parameter

A

B

S

Unit

Test Conditions/Comments

ACCURACY

Resolution

Relative Accuracy

Differential Nonlinearity ±±.ꢀ

Full-Scale Error

14

±2

14

±1

±±.ꢀ

14

±2

±±.ꢀ

Bits

LSB max

Guaranteed Monotonic over Temperature.

V_REF(+) = +7 V, V_REF(−) = −7 V.

T_MINto T_MAX

Zero-Scale Error

Gain Error

Gain Temperature

Coefficient²

±ꢁ

±4

±±.ꢁ

4

±ꢁ

±4

±±.ꢁ

4

±8

±ꢁ

±±.ꢁ

4

mV max

mV typ

ppm FSR/°C typ

V_REF(+) = +7 V, V_REF(−) = −7 V.

2±

ꢁ±

2±

ꢁ±

2±

ꢁ±

ppm FSR/°C

max

μV max

DC Crosstalk²

REFERENCE INPUTS

DC Input Resistance

Input Current

See the Terminology section. R_L= 1± kΩ.

Per Input.

3±

±1

3±

±1

3±

±1

MΩ typ

μA max

V_REF(+) Range

V_REF(−) Range

[V_REF(+) − V_REF(−)]

±/8.1ꢀ2

−8.1ꢀ2/±

ꢁ/14

±/8.1ꢀ2

−8.1ꢀ2/±

7/14

±/8.1ꢀ2

−8.1ꢀ2/±

ꢁ/14

V min/max

For specified performance. Can go as low as ± V,

but performance not guaranteed.

DEVICE SENSE GROUND

INPUTS

Input Current

±2

μA max

Per input. V_DSG= −2 V to +2 V.

DIGITAL INPUTS

V_INH, Input High Voltage 2.4

2.4

±.8

±1±

1±

2.4

±.8

±1±

1±

V min

V_INL, Input Low Voltage

I_INH, Input Current

±.8

±1±

1±

V max

μA max

pF max

C_IN, Input Capacitance

POWER REQUIREMENTS

V_CC

V_DD

V_SS

ꢁ.±

1ꢁ.±

−1ꢁ.±

ꢁ.±

1ꢁ.±

−1ꢁ.±

ꢁ.±

1ꢁ.±

−1ꢁ.±

V nom

±ꢁ5 for specified performance.

Power Supply

Sensitivity

ΔFull Scale/ΔV_DD

ΔFull Scale/ΔV_SS

I_CC

11±

1±±

±.2

3

11±

1±±

±.2

3

11±

1±±

±.ꢁ

3

dB typ

mA max

V_INH= V_CC, V _INL= DGND.

AD7834: V _INH= 2.4 V min, V_INL= ±.8 V max.

AD783ꢁ: V _INH= 2.4 V min, V_INL= ±.8 V max.

AD7834: outputs unloaded.

AD783ꢁ: outputs unloaded.

Outputs unloaded.

6

I_DD

I_SS

13

1ꢁ

13

1ꢁ

13

1ꢁ

¹Temperature range is as follows: A version: −4±°C to +8ꢁ°C; B version: −4±°C to +8ꢁ°C. S version: −4±°C to +8ꢁ°C

²Guaranteed by design.

Rev. C | Page 3 of 28

AD7834/AD7835

AC PERFORMANCE CHARACTERISTICS

These characteristics are included for design guidance and are not subject to production testing.

Table 2.

Unit

(typ)

Parameter

A

B

S

Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

1±

μs

Full-scale change to ±1/2 LSB. DAC latch contents alternately

loaded with all ±s and all 1s.

Digital-to-Analog Glitch Impulse

12±

nV-s

Measured with V_REF(+) = V_REF(−) = ± V. DAC latch alternately

loaded with all ±s and all 1s.

DC Output Impedance

Channel-to-Channel Isolation

DAC to DAC Crosstalk

Digital Crosstalk

±.ꢁ

1±±

2ꢁ

3

±.ꢁ

1±±

2ꢁ

3

±.ꢁ

1±±

2ꢁ

3

Ω

dB

nV-s

See the Terminology section.

See the Terminology section; applies to the AD783ꢁ only.

See the Terminology section.

Feedthrough to DAC output under test due to change in

digital input code to another converter.

Digital Feedthrough—AD7834

Digital Feedthrough—AD783ꢁ

Output Noise Spectral Density at

1 kHz

±.2

1.±

4±

±.2

1.±

4±

±.2

1.±

4±

nV-s

nV/√Hz

Effect of input bus activity on DAC output under test.

All 1s loaded to DAC. V_REF(+) = V_REF(−) = ± V.

Rev. C | Page 4 of 28

AD7834/AD7835

1

V_CC= +5 V 5%; V_DD= +12 V 5%; V_SS= −12 V 5%; AGND = DGND = 0 V; T_A= T_MINto T_MAX, unless otherwise noted.

Table 3.

Parameter

A

B

S

Unit

Test Conditions/Comments

ACCURACY

Resolution

14

Bits

Relative Accuracy

Differential

±2

±±.ꢀ

±1

±±.ꢀ

±2

±±.ꢀ

LSB max

Guaranteed monotonic over temperature.

V_REF(+) = +ꢁ V, V_REF(−) = –ꢁ V.

Nonlinearity

Full-Scale Error

T_MINto T_MAX

Zero-Scale Error

Gain Error

Gain Temperature

Coefficient²

±ꢁ

±4

±±.ꢁ

4

±ꢁ

±4

±±.ꢁ

4

±8

±ꢁ

±±.ꢁ

4

mV max

mV typ

ppm FSR/°C typ

V_REF(+) = +ꢁ V, V_REF(−) = −ꢁ V.

2±

ꢁ±

2±

ꢁ±

2±

ꢁ±

ppm FSR/°C max

μV max

DC Crosstalk²

REFERENCE INPUTS

DC Input Resistance

Input Current

See the Terminology section. R_L= 1± kΩ.

Per input.

3±

±1

3±

±1

3±

±1

MΩ typ

μA max

V_REF(+) Range

V_REF(−) Range

[V_REF(+) − V_REF(−)]

±/8.1ꢀ2

−ꢁ/±

ꢁ/13.1ꢀ2

±/8.1ꢀ2

−ꢁ/±

7/13.1ꢀ2

±/8.1ꢀ2

−ꢁ/±

ꢁ/13.1ꢀ2

V min/max

For specified performance. Can go as low as ± V,

but Performance Not Guaranteed.

DEVICE SENSE GROUND

INPUTS

Input Current

±2

μA max

Per input. V_DSG= −2 V to +2 V.

DIGITAL INPUTS

V_INH, Input High

Voltage

V_INL, Input Low

Voltage

2.4

±.8

2.4

±.8

2.4

±.8

V min

V max

I_INH, Input Current

±1±

1±

±1±

1±

±1±

1±

μA max

pF max

C_IN, Input

Capacitance

POWER REQUIREMENTS

V_CC

V_DD

V_SS

ꢁ.±

1ꢁ.±

−1ꢁ.±

ꢁ.±

1ꢁ.±

−1ꢁ.±

ꢁ.±

1ꢁ.±

−1ꢁ.±

V nom

±ꢁ5 for specified performance.

Power Supply

Sensitivity

ΔFull Scale/ΔV_DD

ΔFull Scale/ΔV_SS

I_CC

11±

1±±

±.2

3

11±

1±±

±.2

3

11±

1±±

±.ꢁ

3

dB typ

mA max

V_INH= V_CC, V_INL= DGND.

AD7834: V_INH= 2.4 V min, V_INL= ±.8 V max.

AD783ꢁ: V_INH= 2.4 V min, V_INL= ±.8 V max.

AD7834: Outputs unloaded.

AD783ꢁ: Outputs unloaded.

Outputs unloaded.

6

I_DD

I_SS

13

1ꢁ

13

1ꢁ

13

1ꢁ

¹Temperature range is as follows: A version: −4±°C to +8ꢁ°C; B version: −4±°C to +8ꢁ°C. S version: −4±°C to +8ꢁ°C.

²Guaranteed by design.

Rev. C | Page ꢁ of 28

AD7834/AD7835

TIMING SPECIFICATIONS

V_CC= +5 V 5%; V_DD= +11.4 V to +15.75 V; V_SS= −11.4 V to −15.75 V; AGND = DGND = 0 V¹

Table 4.

Parameter

Limit at T_MIN, T_MAX

Unit

Description

AD7834 SPECIFIC

2

t₁

t₂

t₃

t₄

1±±

ꢁ±

3±

4±

3±

1±

±

ns min

SCLK cycle time

SCLK low

SCLK high time

FSYNC, PAEN setup time

FSYNC, PAEN hold time

Data setup time

2

t_ꢁ

t₆

t₇

t₈

Data hold time

LDAC to FSYNC setup time

LDAC toFSYNC hold time

Delay between write operations

t_ꢀ

4±

2±

t₂₁

AD783ꢁ SPECIFIC

t₁₁

t₁₂

t₁₃

t₁₄

t_1ꢁ

t₁₆

t₁₇

t₁₈

t_1ꢀ

t_2±

1ꢁ

±

ns min

A±, A1, A2, BYSHF to CS setup time

A±, A1, A2, BYSHF to CS hold time

CS to WR setup time

CS to WR hold time

±

4±

1±

±

WR pulsewidth

Data setup time

Data hold time

LDAC to CS setup time

CS to LDAC setup time

LDAC to CS hold time

±

general

t_1±

4±

ns min

LDAC, CLR pulsewidth

¹All input signals are specified with tr = tf = ꢁ ns (1±5 to ꢀ±5 of ꢁ V) and timed from a voltage level of 1.6 V.

²Rise and fall times should be no longer than ꢁ± ns.

A0 A1 A2

BYSHF

t₁₁

t₁₂

CS

1ST 2ND

CLK CLK

24TH

CLK

t₁

t₁₄

t₁₃

t₁₅

SCLK

WR

t₅

t₄

t₃

t₂

t₁₇

t₁₆

FSYNC

t₂₁

LSB

t₆

DATA

t₇

MSB

D23 D22

D0

DIN

D1

t₁₀

LDAC

(SIMULTANEOUS

UPDATE)

t₁₀

LDAC

(SIMULTANEOUS

UPDATE)

t₁₉

t₂₀

t₁₈

t₈

t₉

LDAC

(PER-CHANNEL

UPDATE)

LDAC

(PER-CHANNEL

UPDATE)

Figure 3. AD7834 Timing Diagram

Figure 4. AD7835 Timing Diagram

Rev. C | Page 6 of 28

AD7834/AD7835

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C unless otherwise noted.^{1, 2}

Table 5.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameters

Rating

V_CCto DGND3

−±.3 V, +7 V or V_DD+ ±.3 V

(whichever is lower)

−±.3 V, +17 V

V_DDto AGND

V_SSto AGND

+±.3 V, –17 V

AGND to DGND

−±.3 V, +±.3 V

Digital Inputs to DGND

V_REF(+) to V_REF(–)

−±.3 V, V_CC+ ±.3 V

−±.3 V, +18 V

V_DD

V_CC

IN4148

SD103C

V_REF(+) to AGND

V_REF(–) to AGND

DSG to AGND

V_OUT(1–4) to AGND

Operating Temperature Range

Industrial (A Version)

Storage Temperature Range

Junction Temperature

Plastic Package

V_SS– ±.3 V, V_DD+ ±.3 V

V_DD

V_CC

AD7834/

AD7835

−4±°C to +8ꢁ°C

−6ꢁ°C to +1ꢁ±°C

1ꢁ±°C

Figure 5.

θ_JAThermal Impedance

Lead Temperature, Soldering

(1± sec)

7ꢁ°C/W

26±°C

SOIC Package

θ_JAThermal Impedance

Lead Temperature, Soldering

Vapor Phase (6± sec)

Infrared (1ꢁ sec)

7ꢁ°C/W

21ꢁ°C

22±°C

MQFP Package

θ_JAThermal Impedance

Lead Temperature, Soldering

Vapor Phase (6± sec)

Infrared (1ꢁ sec)

ꢀꢁ°C/W

21ꢁ°C

22±°C

PLCC Package

θ_JAThermal Impedance

Lead Temperature, Soldering

Vapor Phase (6± sec)

Infrared (1ꢁ sec)

ꢁꢁ°C/W

21ꢁ°C

22±°C

Power Dissipation (Any Package) 48± mW

¹Transient currents of up to 1±± mA will not cause SCR latch-up.

²V_CCmust not exceed V_DDby more than ±.3 V. If it is possible for this to

happen during power supply sequencing, the diode protection scheme in

Figure ꢁ will ensure protection.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4±±± V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. C | Page 7 of 28

AD7834/AD7835

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AGND

V

1

2

3

4

5

6

7

8

9

28

SS

DSG

(–)

27 NC

26 NC

25 NC

24 NC

V

REF

(+)

REF

NC

2

AD7834

TOP VIEW

(Not to Scale)

V

23

V

OUT

DD

V

4

V

1

3

22

21

20

OUT

DGND

V

CLR

CC

SCLK 10

DIN 11

19 LDAC

FSYNC

18

PA0 12

17 PAEN

PA1

13

16

15

PA4

PA3

PA2 14

NC = NO CONNECT

Figure 6. AD7834 PDIP AND SOIC

Table 6. AD7834 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

V_SS

DSG

Negative Analog Power Supply; −1ꢁ V ± ꢁ5 or −12 V ± ꢁ5.

Device Sense Ground Input. Used in conjunction with the CLR input for power-on protection of the DACs.

When CLR is low, the DAC outputs are forced to the potential on the DSG pin.

3

4

V_REF(−)

V_REF(+)

NC

Negative Reference Input. The negative reference voltage is referred to AGND.

Positive Reference Input. The positive reference voltage is referred to AGND.

No Connect.

ꢁ, 24 to 27

22, 6, 7, 21

8

ꢀ

V_OUT1 to V_OUT

DGND

V_CC

4

DAC Outputs.

Digital Ground.

Logic Power Supply; +ꢁ V ± ꢁ5.

1±

SCLK

Clock Input for writing data to the device. Data is clocked into the input register on the falling edge of

SCLK.

11

DIN

Serial Data Input.

12,13,14,1ꢁ,16 PA± to PA4

Package Address Inputs. These inputs are hardwired high (V_CC) or low (DGND) to assign dedicated

package addresses in a multipackage environment.

17

PAEN

Package Address Enable Input. When low, this input allows normal operation of the device. When high,

the device ignores the package address, but not the channel address, in the serial data stream and loads

the serial data into the input registers. This feature is useful in a multipackage application where it can be

used to load the same data into the same channel in each package.

18

1ꢀ

FSYNC

LDAC

Frame Sync Input. Active low logic input used, in conjunction with DIN and SCLK, to write data to the

device with serial data expected after the falling edge of this signal. The contents of the 24-bit serial-to-

parallel input register are transferred on the rising edge of this signal.

Load DAC Input (Level Sensitive). This input signal, in conjunction with the FSYNC input signal,

determines how the analog outputs are updated. If LDAC is maintained high while new data is being

loaded into the device’s input registers, no change occurs on the analog outputs. Subsequently, when

LDAC is brought low, the contents of all four input registers are transferred into their respective DAC

latches, updating the analog outputs.

2±

CLR

Asynchronous Clear Input (Level Sensitive, Active Low). When this input is brought low, all analog

outputs are switched to the externally set potential on the DSG pin. When CLR is brought high, the signal

outputs remain at the DSG potential until LDAC is brought low. When LDAC is brought low, the analog

outputs are switched back to reflect their individual DAC output levels. As long as CLR remains low, the

LDAC signals are ignored, and the signal outputs remain switched to the potential on the DSG pin.

23

28

V_DD

AGND

Positive Analog Power Supply; +1ꢁ V ± ꢁ5 or +12 V ± ꢁ5.

Analog Ground.

Rev. C | Page 8 of 28

AD7834/AD7835

6

5

4

3

2

1

44 43 42 41 40

44 43 42 41 40 39 38 37 36 35 34

PIN 1

IDENTIFIER

NC

7

8

9

39

NC

1

2

3

NC

33

32

31

30

29

PIN 1

IDENTIFIER

DSGA

38 DSGB

DSGA

DSGB

V

1

V

3

4

37

V

1

2

V

3

4

OUT

2 10

36 V

V

4

5

OUT

NC

DB13

DB12

DB11

11

12

13

14

35

34

33

NC

A2

DB13

AD7835

TOP VIEW

(Not to Scale)

AD7835

TOP VIEW

(Not to Scale)

A2

6

28 DB12

27

A1

A0

A1

7

8

DB11

26 DB10

32 DB10

A0

31

CLR 15

LDAC

DB9

25

24

23

CLR

DB9

DB8

9

30 DB8

16

LDAC 10

11

29

BYSHF 17

DB7

BYSHF

DB7

19

26

27 28

18

20 21 22 23 24 25

12 13 14 15 16 17 18 19

21 22

20

NC = NO CONNECT

Figure 7. AD7835 MQFP

Figure 8. AD7835 PLCC

Table 7. AD7835 Pin Function Descriptions

Pin No. Pin No.

MQFP PLCC

1, ꢁ, 33, 3, 6, 7,

Mnemonic

Description

NC

No Connect.

41, 44,

11, 3ꢀ,

4±, 43

2

8

DSGA

Device Sense Ground A Input. Used in conjunction with the CLR input for power-on protection of the

DACs. When CLR is low, DAC outputs V_OUT1 and V_OUT2 are forced to the potential on the DSGA pin.

3, 4, 31, ꢀ, 1±,

V_OUT1 to

DAC Outputs

3±

37, 36

V_OUT4

8, 7, 6

14, 13,

12

1ꢁ

A±, A1, A2

CLR

Address Inputs. A± and A1 are decoded to select one of the four input latches for a data transfer.

A2 is used to select all four DACs simultaneously.

ꢀ

Asynchronous Clear Input (level sensitive, active low). When this input is brought low, all analog

outputs are switched to the externally set potentials on the DSG pins (V_OUT1 and V_OUT2 follow DSGA

while V_OUT3 and V_OUT4 follow DSGB). When CLR is brought high, the signal outputs remain at the DSG

potentials until LDAC is brought low. When LDAC is brought low, the analog outputs are switched

back to reflect their individual DAC output levels. As long as CLR remains low, the LDAC signals are

ignored and the signal outputs remain switched to the potential on the DSG pins.

1±

16

LDAC

Load DAC Input (level sensitive). This input signal, in conjunction with the WR and CS input signals,

determines how the analog outputs are updated. If LDAC is maintained high while new data is being

loaded into the device’s input registers, no change occurs on the analog outputs. Subsequently,

when LDAC is brought low, the contents of all four input registers are transferred into their respective

DAC latches, updating the analog outputs simultaneously.

Alternatively, if LDAC is brought low while new data is being entered, the addressed DAC latch and

corresponding analog output is updated immediately on the rising edge of WR.

11

17

BYSHF

Byte Shift Input. When low, it shifts the data on DB± to DB7 into the DB8 to DB13 half of the input

register.

12

13

18

1ꢀ

CS

Level-Triggered Chip Select Input (Active Low). The device is selected when this input is low.

WR

Level-Triggered Write Input (Active Low). When active, it is used in conjunction with CS to write data

over the input databus.

Logic Power Supply; +ꢁ V ± ꢁ5.

Digital Ground.

14

1ꢁ

2±

21

V_CC

DGND

Rev. C | Page ꢀ of 28

AD7834/AD7835

Pin No. Pin No.

MQFP PLCC

Mnemonic

Description

16 to 2ꢀ 22 to 3ꢁ DB± to

DB13

Parallel Data Inputs. The AD783ꢁ can accept a straight 14-bit parallel word on DB± to DB13, where

DB13 is the MSB and the BYSHF input is hardwired to a logic high. Alternatively for byte loading, the

bottom eight data inputs, DB± to DB7, are used for data loading, while the top six data inputs, DB8 to

DB13, should be hardwired to a logic low. The BYSHF control input selects whether 8 LSBs or 6 MSBs

of data are being loaded into the device.

32

38

DSGB

Device Sense Ground B Input. Used in conjunction with the CLR input for power-on protection of the

DACs. When CLR is low, DAC outputs V_OUT3 and V_OUT4 are forced to the potential on the DSGB pin.

36, 3ꢁ

42, 41

V_REF(+)B,

V_REF(−)B

Reference Inputs for DACs 3 and 4. These reference voltages are referred to AGND.

38

3ꢀ

4±

43, 42

44

1

2

AGND

V_DD

V_SS

Analog Ground

Positive Analog Power Supply; +1ꢁ V ±ꢁ 5 or +12 V ± ꢁ5

Negative Analog Power Supply; −1ꢁ V ± ꢁ5 or −12 V ± ꢁ5

Reference Inputs for DACs 1 and 2. These reference voltages are referred to AGND.

4, ꢁ

V_REF(+)A,

V

_REF(−)A

Rev. C | Page 1± of 28

AD7834/AD7835

TERMINOLOGY

Relative Accuracy

DAC-to-DAC Crosstalk

Relative accuracy or endpoint linearity is a measure of the

maximum deviation from a straight line passing through the

endpoints of the DAC transfer function. It is measured after

adjusting for zero error and full-scale error. It is normally

expressed inLSBs or as a percentage of full-scale reading.

DAC-to-DAC crosstalk is defined as the glitch impulse that

appears at the output of one converter due to both the digital

change and subsequent analog O/P change at another converter.

It is specified in nV-secs.

Digital Crosstalk

Differential Nonlinearity

The glitch impulse transferred to the output of one converter

due to a change in digital input code to the other converter is

defined as the digital crosstalk and is specified in nV-secs.

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of 1 LSB maximum

ensures monotonicity.

Digital Feedthrough

When the device is not selected, high frequency logic activity

on its digital inputs can be capacitively coupled both across and

through the device to show up as noise on the V_OUTpins. This

noise is digital feedthrough.

DC Crosstalk

Although the common input reference voltage signals are

internally buffered, small IR drops in the individual DAC

reference inputs across the die means an update to one chan-

nel produces a dc output change in one or other channel

outputs.

DC Output Impedance

This is the effective output source resistance. It is dominated

by package lead resistance.

The four DAC outputs are buffered by op amps sharing

common V_DDand V_SSpower supplies. If the dc load current

changes in one channel due to an update, this results in a

further dc change in one or more of the channel outputs.

This effect is most obvious at high load currents and reduces

as the load currents are reduced. With high impedance loads,

the effect is virtually unmeasurable.

Full-Scale Error

This is the error in DAC output voltage when all 1s are

loaded into the DAC latch. Ideally, the output voltage, with

all 1s loaded into the DAC latch, should be V_REF(+) – 1 LSB.

Full-scale error does not include zero-scale error.

Zero-Scale Error

Output Voltage Settling Time

Zero-scale error is the error in the DAC output voltage when

all 0s are loaded into the DAC latch. Ideally, the output voltage,

with all 0s in the DAC latch, is equal to V_REF(−). Zero-scale

error is due mainly to offsets in the output amplifier.

This is the amount of time it takes for the output to settle to

a specified level for a full-scale input change.

Digital-to-Analog Glitch Impulse

This is the amount of charge injected into the analog output

when the inputs change state. It is specified as the area of the

glitch in nV-secs. It is measured with the reference inputs

connected to 0 V and the digital inputs toggled between all

1s and all 0s.

Gain Error

Gain error is defined as (full-scale error) − (zero-scale error).

Channel-to-Channel Isolation

Channel-to-channel isolation refers to the proportion of input

signal from the reference input of one DAC which appears at the

output of the other DAC. It is expressed in dBs. The AD7834 has

no specification for channel-to-channel isolation because it has

one reference for all DACs. Channel-to-channel isolation is

specified for the AD7835.

Rev. C | Page 11 of 28

AD7834/AD7835

TYPICAL PERFORMANCE CHARACTERISTICS

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

1.0

0.8

DAC 1

0.6

0.4

DAC 3

DAC 4

0.2

0

DAC 2

–0.2

–0.4

–0.6

–0.8

–1.0

TEMP = 25°C

ALL DACs FROM 1 DEVICE

0

2.5

V

5.0

8.0

0

2

4

6

8

10

12

14

16

(+) (V)

CODE/1000

REF

Figure 12. Typical INL vs. V_REF(+), [V_REF(+) – V_REF(−) = 5 V]

Figure 9. Typical INL Plot

0.5

0.4

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

ALL DACs FROM ONE DEVICE

0.3

0.2

DAC 1

DAC 3

0.1

DAC 4

0

–0.1

–0.2

–0.3

–0.4

–0.5

DAC 2

0

2

4

6

8

10

12

14

16

–40

25

85

CODE/1000

TEMPERATURE (°C)

Figure 10. Typical DNL Plot

Figure 13. Typical INL vs. Temperature

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

1

2

3

4

5

6

7

8

0

2

4

6

8

10

12

14

16

V

(+) (V)

CODE/1000

REF

Figure 14. Typical DAC-to-DAC Matching

Figure 11. Typical INL vs. V_REF(+), [V_REF(−) = −6 V]

Rev. C | Page 12 of 28

AD7834/AD7835

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

–2.985

8

6

VERT = 100mV/DIV

HORIZ = 1μs/DIV

VERT = 10mV/DIV

HORIZ = 1μs/DIV

ꢀ

–3.005

–3.025

–3.045

–3.065

–3.085

–3.105

4

V

(+) = +7V

(–) = –3V

REF

2

0

–2

–4

–0.1

–0.2

VERT = 2V/DIV

HORIZ = 1μs/DIV

Figure 15. Typical Digital/Analog Glitch Impulse

Figure 17. Settling Time (−)

7.250

7.225

7.200

7.175

7.150

7.125

7.100

8

6

VERT = 2V/DIV

HORIZ = 1.2μs/DIV

4

V

(+) = +7V

(–) = –3V

REF

2

0

–2

–4

VERT = 25mV/DIV

HORIZ = 2.5μs/DIV

Figure 16. Settling Time (+)

Rev. C | Page 13 of 28

AD7834/AD7835

THEORY OF OPERATION

DAC ARCHITECTURE—GENERAL

Table 8. D23 Control

D23

±

Control Function

Each channel consists of a segmented 14-bit R-2R voltage-mode

DAC. The full-scale output voltage range is equal to the entire

reference span of V_REF(+) – V_REF(−). The DAC coding is straight

binary; all 0s produce an output of V_REF(−); all 1s produce an

output of V_REF(+) − 1 LSB.

Ignore following 23 bits of information.

1

Use following 23 bits of address and data as normal.

D22 and D21: Decoded to select one of the four DAC channels

within a device. See Table 9 for the D22 and D21 truth table.

Table 9. D22, D21 Control

The analog output voltage of each DAC channel reflects the

contents of its own DAC latch. Data is transferred from the

external bus to the input register of each DAC latch on a per

channel basis. The AD7835 has a feature whereby using the

A2 pin data can be transferred from the input databus to all

four input registers simultaneously.

D22

D21

Control Function

Select Channel 1

Select Channel 2

Select Channel 3

Select Channel 4

±

1

±

1

±

1

Bringing the

V

line low switches all the signal outputs,

CLR

_OUT1 to V_OUT4, to the voltage level on the DSG pin. The signal

outputs are held at this level after the removal of the signal

D20 to D16: Determines the package address. The five address

bits allow up to 32 separate packages to be individually decoded.

Successful decoding is accomplished when these five bits match

up with the five hardwired pins on the physical package.

CLR

LDAC

and will not switch back to the DAC outputs until the

signal is exercised.

D15 to D0: DAC data to be loaded into the identified DAC

input register. This data must have two leading 0s followed by

14 bits of data, MSB first. The MSB is in location D13 of the

24-bit data stream.

DATA LOADING—AD7834, SERIAL INPUT DEVICE

A write operation transfers 24 bits of data to the AD7834. The

first 8 bits are control data and the remaining 16 bits are DAC

data (see Figure 18). The control data identifies the DAC chan-

nel to be updated with new data and which of 32 possible

packages the DAC resides in. In any communication with the

device, the first 8 bits must always be control data.

DATA LOADING—AD7835, PARALLEL LOADING

DEVICE

Data is loaded into the AD7835 in either straight 14-bit wide

words or in two 8-bit bytes.

The DAC output voltages, V_OUT1 to V_OUT4, can be updated to

reflect new data in the DAC input registers in one of two ways.

In systems that transfer 14-bit wide data, the

should be hardwired to V_CC. This sets up the AD7835 as a

straight 14-bit parallel-loading DAC.

input

BYSHF

The first method normally keeps

high and only pulses

LDAC

low momentarily to update all DAC latches

LDAC

simultaneously with the contents of their respective input

registers. The second method ties low and channel

In 8-bit bus systems where it is required to transfer data in two

LDAC

updating occurs on a per channel basis after new data has

been clocked into the AD7834. With low, the rising

bytes, it is necessary to have the

input under logic control.

BYSHF

In such a system, the top six pins of the device databus, DB8 to

DB13, must be hardwired to DGND. New low byte data is

loaded into the lower eight places of the selected input register

LDAC

transfers the new data directly into the DAC

edge of

FSYNC

by carrying out a write operation while holding

high.

BYSHF

latch, updating the analog output voltage.

A second write operation is subsequently executed with

low and the 6 MSBs on the DB0 to DB5 inputs (DB5 = MSB).

BYSHF

Data being shifted into the AD7834 enters a 24-bit long shift

register. If more than 24 bits are clocked in before

goes

FSYNC

high, the last 24 bits transmitted are used as the control data

and DAC data.

Individual bit functions are discussed in Figure 15.

D23: Determines whether the following 23 bits of address and

data should be used or ignored. This is effectively a software

chip select bit. D23 is the first bit to be transmitted in the 24-bit

long word.

Rev. C | Page 14 of 28

AD7834/AD7835

NOTE: D23 IS THE FIRST BIT TRANSMITTED IN THE SERIAL WORD.

D23 D22 D21 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D20 D19

LSB, DB0

CONTROL BIT TO USE/IGNORE

FOLLOWING 23 BITS OF INFORMATION

SECOND LSB, DB1

THIRD LSB, DB2

DB3

CHANNEL ADDRESS MSB, D1

CHANNEL ADDRESS LSB, D2

PACKAGE ADDRESS MSB, PA4

PACKAGE ADDRESS, PA3

PACKAGE ADDRESS, PA2

PACKAGE ADDRESS, PA1

PACKAGE ADDRESS LSB, PA0

DB4

DB5

DB6

DB7

DB8

DB9

DB10

THIRD MSB, DB11

SECOND MSB, DB12

MSB, DB13

SECOND LEADING ZERO

FIRST LEADING ZERO

Figure 18. Bit Assignments for 24-Bit Data Stream of AD7834

When 14-bit transfers are being used, the DAC output voltages,

V_OUT1 to V_OUT4, can be updated to reflect new data in the DAC

input registers in one of two ways. The first method normally

UNIPOLAR CONFIGURATION

Figure 19 shows the AD7834/AD7835 in the unipolar binary

circuit configuration. The V_REF(+) input of the DAC is driven by

the AD586, a 5 V reference. V_REF(−) is tied to ground. Table 4

gives the code table for unipolar operation of the AD7834/

AD7835.

keeps

high and only pulses

low momentarily to

LDAC

update all DAC latches simultaneously with the contents of

their respective input registers. The second method ties

LDAC

low, and channel updating occurs on a per channel basis after

new data is loaded to an input register.

+15V

+5V

2

V

To avoid the DAC output going to an intermediate value during

CC

DD

6

5

V

OUT

(0V TO 5V)

a 2-byte transfer,

should not be tied low permanently but

V

(+)

LDAC

V

REF

OUT

8

AD586

4

R1

10kΩ

AD7834/

AD7835¹

should be held high until the two bytes are written to the input

register. When the selected input register has been loaded with

C1

1nF

AGND

(–)

REF

DGND

the two bytes,

should then be pulsed low to update the

LDAC

V

SS

SIGNAL

GND

DAC latch and, consequently, perform the digital-to-analog

conversion.

SIGNAL

GND

–15V

ADDITIONAL PINS OMITTED FOR CLARITY

1

In many applications, it may be acceptable to allow the DAC

output to go to an intermediate value during a 2-byte transfer.

Figure 19. Unipolar 5 V Operation

In such applications,

control line.

can be tied low, thus using one less

LDAC

Offset and gain may be adjusted in Figure 19 as follows:

To adjust offset, disconnect the V_REF(−) input from 0 V, load the

DAC with all 0s, and adjust the V_REF(−) voltage until V_OUT= 0 V.

For gain adjustment, the AD7834/AD7835 should be loaded

with all 1s and R1 adjusted until V_OUT= 5 V(16383/16384)

= 4.999695.

The actual DAC input register that is being written to is deter-

mined by the logic levels present on the devices address lines,

as shown in Table 10.

Table 10. AD7835—Address Line Truth Table

Many circuits do not require these offset and gain adjustments.

In these circuits, R1 can be omitted. Pin 5 of the AD586 can be

left open circuit, and Pin 2 (V_REF(−)) of the AD7834/AD7835 is

tied to 0 V.

A2

A1

A0

DAC Selected

±

DAC 1

±

1

±

1

X

1

±

1

X

DAC 2

DAC 3

DAC 4

All DACs Selected

Table 11. Code Table for Unipolar Operation^{1, 2}

Binary Number in DAC Latch

MSB

LSB

Analog Output (V_OUT)

11

1111

V_REF(16383/16384) V

1±

±1

±±

±±±±

1111

±±±±

1111

±±±±

1111

±±±1

±±±±

V_REF(81ꢀ2/16384) V

V_REF(81ꢀ1/16384) V

V_REF(1/16384) V

± V

¹VREF = V_REF(+); V_REF(−) = ± V for unipolar operation.

²For V_REF(+) = +ꢁ V, 1 LSB = +ꢁ V/2¹⁴= +ꢁ V/16384 = 3±ꢁ μV.

Rev. C | Page 1ꢁ of 28

AD7834/AD7835

In Figure 20, full-scale and bipolar zero adjustments are

provided by varying the gain and balance on the AD588.

R2 varies the gain on the AD588 while R3 adjusts the offset

of both the +5 V and –5 V outputs together with respect to

ground.

BIPOLAR CONFIGURATION

+15V

+5V

R1

39kΩ

6

4

7

9

V

2

3

CC

DD

C1

1μF

V

OUT

(–5V TO +5V)

For bipolar-zero adjustment, the DAC is loaded with

1000 . . . 0000 and R3 is adjusted until V_OUT= 0 V.

Full scale is adjusted by loading the DAC with all 1s and

adjusting R2 until V_OUT= 5(8191/8192) V = 4.99939 V.

V

(+)

V

REF

OUT

1

AD588

AD7834/

AD7835¹

14

5

10

11

R2

100kΩ

AGND

15

16

V

(–)

REF

DGND

V

SS

12

8

13

R3

100kΩ

SIGNAL

GND

When bipolar zero and full-scale adjustment are not needed,

R2 and R3 are omitted. Pin 12 on the AD588 should be con-

nected to Pin 11, and Pin 5 should be left floating.

–15V

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 20. Bipolar 5 V Operation

Figure 20 shows the AD7834/AD7835 setup for 5 V operation.

The AD588 provides precision 5 V tracking outputs that are

fed to the V_REF(+) and V_REF(−) inputs of the AD7834/AD7835.

The code table for bipolar operation of the AD7834/AD7835 is

shown in Table 12.

Table 12. Code Table for Bipolar Operation^{1, 2}

Binary Number in DAC Latch

MSB

11

LSB

1111 1111 1111

±±±± ±±±± ±±±1

±±±± ±±±± ±±±±

1111 1111 1111

±±±± ±±±± ±±±1

±±±± ±±±± ±±±±

Analog Output (V_OUT)

V_REF(−) + V_REF(16383/16384) V

V_REF(−) + V_REF(81ꢀ3/16384) V

V_REF(−) + V_REF(81ꢀ2/16384) V

V_REF(−) + V_REF(81ꢀ1/16384) V

V_REF(−) + V_REF(1/16384) V

V_REF(−) V

1±

±1

±±

¹V_REF= [V_REF(+) – V_REF(−)].

²For V_REF(+) = +ꢁ V and V_REF(−) = –ꢁ V, 1 LSB = 1± V/2¹⁴= 1± V/16384 = 61± μV.

Rev. C | Page 16 of 28

AD7834/AD7835

CONTROLLED POWER-ON OF THE OUTPUT STAGE

G

1

A block diagram of the output stage of the AD7834/AD7835 is

shown in Figure 21. It is capable of driving a load of 10 kΩ in

parallel with 200 pF. G₁to G₆are transmission gates used to

control the power-on voltage present at V_OUT. G₁and G₂are

G

6

DAC

V

OUT

G

3

G

4

G

2

also used in conjunction with the

input to set V_OUTto the

CLR

G

5

R

user defined voltage present at the DSG pin.

G

1

DSG

G

6

DAC

V

OUT

CLR

Figure 23. Output Stage with V_DD> 10 V and

Low

G

3

G

4

V_OUThas been disconnected from the DSG pin by the opening

of G₅but will track the voltage present at DSG via the unity gain

buffer.

G

2

G

5

R

POWER-ON WITH LDAC LOW,

HIGH

DSG

CLR

In many applications of the AD7834/AD7835,

is kept

LDAC

continuously low, updating the DAC after each valid data

transfer. If is low when power is applied, then G₁is

Figure 21. Block Diagram of AD7834/AD7835 Output Stage

POWER-ON WITH

LOW, LDAC HIGH

CLR

LDAC

The output stage of the AD7834/AD7835 is designed to allow

output stability during power-on. If is kept low during

power-on, and power is applied to the part, G₁, G₄, and G₆are

open while G₂, G₃, and G₅are closed (see Figure 22).

closed and G₂is open, connecting the output of the DAC to

the input of the output amplifier. G₃and G₅are closed and

G₄and G₆open, connecting the amplifier as a unity gain buffer,

as before. V_OUTis connected to DSG via G₅and R (a thin-film

resistance between DSG and V_OUT) until V_DDand V_SSreach

approximately 10 V. Then, the internal power-on circuitry

opens G₃and G₅and closes G₄and G₆. This is the situation

shown in Figure 24. V_OUTis now at the same voltage as the

DAC output.

CLR

G

1

G

6

DAC

V

OUT

G

3

G

4

G

2

G

5

G

1

R

G

6

DAC

V

OUT

DSG

G

3

G

4

Figure 22. Output Stage with V_DD< 10 V

G

2

G

5

R

V_OUTis kept within a few hundred millivolts of DSG via G₅and

R. R is a thin-film resistor between DSG and V_OUT. The output

amplifier is connected as a unity gain buffer via G₃, and the

DSG voltage is applied to the buffer input via G₂. The amplifier’s

output is thus at the same voltage as the DSG pin. The output

stage remains configured as in Figure 22 until the voltage at V_DD

and V_SSreaches approximately 10 V. By now, the output ampli-

fier has enough headroom to handle signals at its input and has

also had time to settle. The internal power-on circuitry opens

G₃and G₅and closes G₄and G₆(see Figure 23). Now, the output

amplifier is connected in unity gain mode via G₄and G₆. The

DSG voltage is still applied to the noninverting input via G₂.

DSG

LDAC

Figure 24. Output Stage with

Low

LOADING THE DAC AND USING THE

INPUT

CLR

When

goes low, it closes G₁and opens G₂as in Figure 24.

The voltage at V_OUTnow follows the voltage present at the out-

put of the DAC. The output stage remains connected in this

LDAC

manner until a

signal is applied. Then, the situation reverts

CLR

(see Figure 23). Once again, V_OUTremains at the same voltage as

DSG until goes low. This reconnects the DAC output to

LDAC

the unity gain buffer.

This voltage appears at V_OUT

.

Rev. C | Page 17 of 28

AD7834/AD7835

Once the AD7834/AD7835 has powered on and the on-chip

amplifiers have settled, the situation is shown in Figure 23.

Any voltage now applied to the DSG pin is buffered by the

same amplifier that buffers the DAC output voltage in normal

operation. Thus, for specified operations, the maximum voltage

applied to the DSG pin increases to the maximum allowable

DSG VOLTAGE RANGE

During power-on, the V_OUTpins of the AD7834/AD7835 are

connected to the relevant DSG pins via G₆and the thin-film

resistor, R. The DSG potential must obey the maximum ratings

at all times. Thus, the voltage at DSG must always be within the

range V_SS– 0.3 V, V_DD+ 0.3 V. However, to keep the voltages at

the V_OUTpins of the AD7834/AD7835 within 2 V of the rele-

vant DSG potential during power-on, the voltage applied to

DSG should also be kept within the range AGND – 2 V,

AGND + 2 V.

V_REF(+) voltage, and the minimum voltage applied to DSG is the

minimum V_REF(−) voltage. After the AD7834/AD7835 has fully

powered on, the outputs can track any DSG voltage within this

minimum/maximum range.

Rev. C | Page 18 of 28

AD7834/AD7835

POWER-ON OF THE AD7834/AD7835

Power is normally applied to the AD7834/AD7835 in the

following sequence: first V_DDand V_SS, then V_CC, and then

V

(+)

REF

SD103C

1N5711

1N5712

AD7834¹

V_REF(+) and V_REF(−). The V_REFpins are not allowed to float

when power is applied to the part. V_REF(+) is not allowed to

go below V_REF(−) − 0.3 V. V_REF(−) is not allowed to go below

V

(–)

REF

1

ADDITIONAL PINS OMITTED FOR CLARITY

V_SS− 0.3 V. V_DDis not allowed to go below V_CC− 0.3 V.

Figure 25. Power-On Protection

In some systems, it is necessary to introduce one or more

Schottky diodes between pins to prevent the above situations

arising at power-on. These diodes are shown in Figure 25.

However in most systems, with careful consideration given

to power supply sequencing, the above rules are adhered to,

and protection diodes are not necessary.

Rev. C | Page 1ꢀ of 28

AD7834/AD7835

MICROPROCESSOR INTERFACING

To load data to the AD7834, PC7 is left low after the first 8 bits

are transferred. A second byte of data is then transmitted seri-

ally to the AD7834. Then, a third byte is transmitted, and when

this transfer is complete, the PC7 line is taken high.

AD7834 TO 80C51 INTERFACE

A serial interface between the AD7834 and the 80C51 micro-

controller is shown in Figure 26. TXD of the 80C51 drives SCLK

of the AD7834, while RXD drives the serial data line of the part.

68HC11¹

PC5

AD7834¹

The 80C51 provides the LSB of its SBUF register as the first bit

in the serial data stream. The AD7834 expects the MSB of the

24-bit write first. Therefore, the user has to ensure the data in

the SBUF register is arranged correctly so the data is received

MSB first by the AD7834/AD7835. When data is to be trans-

mitted to the part, P3.3 is taken low. Data on RXD is valid on

the falling edge of TXD. The 80C51 transmits its data in 8-bit

bytes with only 8 falling clock edges occurring in the transmit

cycle. To load data to the AD7834, P3.3 is left low after the first

8 bits are transferred. A second byte is then transferred, with

P3.3 still kept low. After the third byte has been transferred, the

P3.3 line is taken high.

CLR

PC6

PC7

SCK

LDAC

FSYNC

SCLK

MOSI

DIN

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 27. AD7834 to 68HC11 Interface

In Figure 27,

and

are controlled by the PC6 and

CLR

LDAC

PC5 port outputs, respectively. As with the 80C51, each DAC

of the AD7834 can be updated after each 3 byte transfer, or

else all DACs can be simultaneously updated after 12 bytes

are transferred.

80C51¹

AD7834¹

P3.5

CLR

LDAC

FSYNC

SCLK

P3.4

P3.3

TXD

AD7834 TO ADSP-2101 INTERFACE

An interface between the AD7834 and the ADSP-2101 is shown

in Figure 28. In the interface shown, SPORT0 is used to transfer

data to the part. SPORT1 is configured for alternate functions.

RXD

DIN

1

ADDITIONAL PINS OMITTED FOR CLARITY

FO, the flag output on SPORT0, is connected to

and is

LDAC

used to load the DAC latches. In this way, data is transferred

from the ADSP-2101 to all the input registers in the DAC, and

the DAC latches are updated simultaneously. In the application

Figure 26. AD7834 to 80C51 Interface

and

on the AD7834 are also controlled by 80C51

CLR

LDAC

port outputs. The user can bring

low after every 3 bytes

LDAC

shown, the

pin on the AD7834 is controlled by circuitry

CLR

have been transmitted to update the DAC, which has been

programmed. Alternatively, it is possible to wait until all the

input registers have been loaded (12-byte transmits) and then

update the DAC outputs.

that monitors the power in the system.

POWER

MONITOR

ADSP-2101¹

AD7834¹

CLR

AD7834 TO 68HC11 INTERFACE

LDAC

FSYNC

SCLK

FO

TFS

SCK

Figure 27 shows a serial interface between the AD7834 and the

68HC11 microcontroller. SCK of the 68HC11 drives SCLK of

the AD7834, while the MOSI output drives the serial data line,

DT

DIN

DIN, of the AD7834. The

signal is derived from port

FSYNC

line PC7, as shown in Figure 27.

1

ADDITIONAL PINS OMITTED FOR CLARITY

For correct operation of this interface, the 68HC11 should

be configured so its CPOL bit is a 0, and its CPHA bit is 1.

When data is to be transferred to the part, PC7 is taken low.

When the 68HC11 is configured like this, data on MOSI is

valid on the falling edge of SCK. The 68HC11 transmits its

serial data in 8-bit bytes, MSB first. The AD7834 also expects

the MSB of the 24-bit write first. Eight falling clock edges

occur in the transmit cycle.

Figure 28. AD7834 to ADSP-2101 Interface

The AD7834 requires 24 bits of serial data framed by a single

pulse. It is necessary that this

pulse stays low

FSYNC

until all the data is transferred. This can be provided by the

ADSP-2101 in one of two ways. Both require setting the serial

word length of the SPORT to 12 bits, with the following condi-

tions: internal SCLK, alternate framing mode, and active low

framing signal.

Rev. C | Page 2± of 28

AD7834/AD7835

First, data can be transferred using the autobuffering feature of

the ADSP-2101, sending two 12-bit words directly after each

other. This ensures a continuous TFS pulse. Second, the first

data word is loaded to the serial port, the subsequent generated

interrupt is trapped, and then the second data word is sent

immediately after the first. Again, this produces a continuous

TFS pulse that frames the 24 data bits.

CLOCK/

TIMER

TMS32020/

TMS320C25

AD7834¹

1

LDAC

CLR

XF

FSX

FSYNC

SCLK

CLKX

DX

DIN

AD7834 TO DSP56000/DSP56001 INTERFACE

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 29 shows a serial interface between the AD7834 and the

DSP56000/DSP56001. The serial port is configured for a word

length of 24 bits, gated clock, and with FSL0 and FSL1 control

bits each set to 0. Normal mode synchronous operation is

selected which allows the use of SC0 and SC1 as outputs

Figure 30. AD7834 to TMS32020/TMS320C25 Interface

INTERFACING THE AD7835—16-BIT INTERFACE

The AD7835 can be interfaced to a variety of microcontrollers

or DSP processors, both 8-bit and 16-bit. Figure 31 shows the

AD7835 interfaced to a generic 16-bit microcontroller/DSP

controlling

and

, respectively. The framing signal on

CLR

LDAC

SC2 has to be inverted before being applied to

. SCK is

FSYNC

processor.

is tied to V_CCin this interface. The lower

BYSHF

internally generated on the DSP56000/DSP56001 and is applied

to SCLK on the AD7834. Data from the DSP56000/DSP56001 is

valid on the falling edge of SCK.

address lines from the processor are connected to A0, A1,

and A2 on the AD7835 as shown. The upper address lines are

decoded to provide a chip select signal for the AD7835. They

are also decoded, in conjunction with the lower address lines if

DSP56000/

DSP56001

AD7834¹

1

need be, to provide an

signal. Alternatively,

can be

LDAC

SC0

CLR

driven by an external timing circuit or just tied low. The data

lines of the processor are connected to the data lines of the

AD7835. The selection of the DACs is provided in Table 10.

LDAC

FSYNC

SCLK

SC1

SC2

SCK

AD7835¹

μCONTROLLER/

STD

DIN

V

CC

DSP

1

PROCESSOR

ADDITIONAL PINS OMITTED FOR CLARITY

BYSHF

D13

D0

Figure 29. AD7834 to DSP56000/DSP56001 Interface

DATABUS

D0

AD7834 TO TMS32020/TMS320C25 INTERFACE

UPPER BITS OF

ADDRESS BUS

CS

A serial interface between the AD7834 and the TMS32020/

TMS320C25 DSP processor is shown in Figure 30. The

CLKX and FSX signals for the TMS32020/TMS32025 are

generated using an external clock/timer circuit. The CLKX

and FSX pins are configured as inputs. The TMS32020/

TMS320C25 are set up for an 8-bit serial data length. Data can

then be written to the AD7834 by writing 3 bytes to the serial

port of the TMS32020/TMS320C25. In the configuration shown

in Figure 30, the CLR input on the AD7834 is controlled by the

XF output on the TMS32020/TMS320C25. The clock/timer

ADDRESS

DECODE

LDAC

A2

A1

A2

A1

A0

R/W

WR

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 31. AD7835 16-Bit Interface

circuit controls the

input on the AD7834. Alternatively,

LDAC

can also be tied to ground to allow automatic update of

LDAC

the DAC latches after each transfer.

Rev. C | Page 21 of 28

AD7834/AD7835

Table 13. DAC Selection, 8-Bit Interface

8-BIT INTERFACE

Processor Address Lines

Figure 32 shows an 8-bit interface between the AD7835 and

a generic 8-bit microcontroller/DSP processor. Pin D13 to

Pin D8 of the AD7835 are tied to DGND. Pin D7 to Pin D0 of

the processor are connected to Pin D7 to Pin D0 of the AD7835.

A3

1

±

A2

X

±

1

A1

X

±

1

±

1

A0

±

1

±

1

±

1

±

1

DAC Selected

Upper 6 Bits of All DACs

Lower 8 Bits of All DACs

Upper 6 Bits, DAC 1

Lower 8 Bits, DAC 1

Upper 6 Bits, DAC 2

Lower 8 Bits, DAC 2

Upper 6 Bits, DAC 3

Lower 8 Bits, DAC 3

Upper 6 Bits, DAC 4

Lower 8-Bits, DAC 4

is driven by the A0 line of the processor. This maps the

BYSHF

DAC upper bits and lower bits into adjacent bytes in the proces-

sor’s address space. Table 13 shows the truth table for addressing

the DACs in the AD7835. For example, if the base address for the

DACs in the processor address space is decoded by the upper

address bits to location HC000, then the first DAC’s upper and

lower bits are at locations HC000 and HC001, respectively.

±

1

D13

μCONTROLLER/

DSP

PROCESSOR

1

D8

AD7835¹

DGND

D7

D0

D7

D0

DATABUS

UPPER BITS OF

ADDRESS BUS

CS

ADDRESS

DECODE

LDAC

A3

A2

A1

A0

BYSHF

WR

R/W

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 32. AD7835 8-Bit Interface

When writing to the DACs, the lower eight bits must be written

first, followed by the upper six bits. The upper six bits should be

output on data lines D0 to D5. Once again, the upper address

lines of the processor are decoded to provide a

signal. They

CS

are also decoded in conjunction with lines A3 to A0 to provide

an signal. Alternatively, can be driven by an exter-

LDAC

nal timing circuit or, if it is acceptable to allow the DAC output

to go to an intermediate value between 8-bit writes,

be tied low.

can

LDAC

Rev. C | Page 22 of 28

AD7834/AD7835

APPLICATIONS

Figure 34 shows a 5-channel isolated interface to the AD7834.

Multiple devices are connected to the outputs of the opto-

coupler and controlled as explained above. To reduce the

SERIAL INTERFACE TO MULTIPLE AD7834S

Figure 33 shows how the package address pins of the AD7834

are used to address multiple AD7834s. This figure shows only

10 devices, but up to 32 AD7834s can each be assigned a unique

address by hardwiring each of the package address pins to V_CC

number of opto-isolators, the

line doesn’t need to be

PAEN

controlled if it is not used. If the

line is not controlled

PAEN

by the microcontroller, then it should be tied low at each device.

If simultaneous updating of the DACs is not required, then the

or DGND. Normal operation of the device occurs when

PAEN

is low. When serial data is being written to the AD7834s, only

the device with the same package address as the package address

contained in the serial data accepts data into the input registers.

pin on each part can be tied permanently low and a

LDAC

further opto-isolator is not needed.

Conversely, if

is high, the package address is ignored, and

PAEN

V

CC

the data is loaded into the same channel on each package.

μCONTROLLER

The primary limitation with multiple packages is the output

update rate. For example, if an output update rate of 10 kHz

is required, there are 100 μs to load all DACs. Assuming a

serial clock frequency of 10 MHz, it takes 2.5 μs to load data

to one DAC. Thus 40 DACs or 10 packages can be updated in

this time. As the update rate requirement decreases, the number

of possible packages increases.

TO PAENs

TO LDACs

TO FSYNCs

TO SCLKs

TO DINs

CONTROL OUT

SYNC OUT

SERIAL CLOCK OUT

SERIAL DATA OUT

AD7834¹

OPTO-COUPLER

μCONTROLLER

DEVICE 0

Figure 34. Opto-Isolated Interface

PAEN

LDAC

FSYNC

SCLK

CONTROL OUT

PA0

CONTROL OUT

SYNC OUT

PA1

PA2

AUTOMATED TEST EQUIPMENT

PA3

PA4

SERIAL CLOCK OUT

SERIAL DATA OUT

The AD7834/AD7835 is particularly suited for use in an

automated test environment. Figure 35 shows the AD7835

providing the necessary voltages for the pin driver and the

window comparator in a typical ATE pin electronics configu-

ration. Two AD588s are used to provide reference voltages

for the AD7835. In the configuration shown, the AD588s

are configured, so the voltage at Pin 1 is 5 V greater than

the voltage at Pin 9, and the voltage at Pin 15 is 5 V less

than the voltage at Pin 9.

DIN

AD7834¹

DEVICE 1

V

CC

PAEN

PA0

LDAC

FSYNC

SCLK

PA1

PA2

PA3

PA4

DIN

One of the AD588s is used as a reference for DACs 1 and 2.

These DACs are used to provide high and low levels for the pin

driver. The pin driver can have an associated offset. This can be

nulled by applying an offset voltage to Pin 9 of the AD588. First,

the code 1000 . . . 0000 is loaded into the DAC 1 latch, and the

pin driver output is set to the DAC 1 output. The V_OFFSETvoltage

is adjusted until 0 V appears between the pin driver output and

DUT GND. This causes both V_REF(+)A and V_REF(−)A to be off-

AD7834¹

V

CC

DEVICE 9

PAEN

PA0

LDAC

FSYNC

SCLK

PA1

PA2

PA3

PA4

DIN

1

ADDITIONAL PINS OMITTED FOR CLARITY

set with respect to AGND by an amount equal to V_OFFSET

.

Figure 33. Serial Interface to Multiple AD7834s

OPTO-ISOLATED INTERFACE

However, the output of the pin driver varies from −5 V to

+5 V with respect to DUT GND as the DAC input code varies

from 000 . . . 000 to 111 . . . 111. The V_OFFSETvoltage is also applied

to the DSG A pin. When a clear is performed on the AD7835, the

output of the pin driver is 0 V with respect to DUT GND.

In many process control applications, it is necessary to

provide an isolation barrier between the controller and the

unit being controlled. Opto-isolators can provide voltage

isolation in excess of 3 kV. The serial loading structure of

the AD7834 makes it ideal for opto-isolated interfaces as

the number of interface lines is kept to a minimum.

Rev. C | Page 23 of 28

AD7834/AD7835

V

–15V

+15V

OFFSET

If the AD7834/AD7835 is the only device requiring an AGND to

DGND connection, then the ground planes should be connected

at the AGND and DGND pins of the AD7834/ AD7835. If the

AD7834/AD7835 is in a system where multiple devices require an

AGND to DGND connection, the connection can still be made at

one point only, a star ground point, which can be established as

close as possible to the AD7834/AD7835.

2

16

3

1

4

6

8

+15V

V

(+)A

(–)A

REF

V

1

OUT

15

14

AD588

13

7

DRIVER

V

REF

V

OUT

2

9

1μF

DSG A

0.1μF

–15V

AD7835¹

10 11 12

+15V –15V

DSG B

Digital lines running under the device must be avoided as these

will couple noise onto the die. The analog ground plane can run

under the AD7834/AD7835 to avoid noise coupling. The power

supply lines of the AD7834/AD7835 can use as large a trace as

possible to provide low impedance paths and reduce the effects

of glitches on the power supply line. Shield fast switching signals,

such as clocks, with digital ground to avoid radiating noise to

other parts of the board. These signals should never be run near

the analog inputs. Avoid crossover of digital and analog signals.

Traces on opposite sides of the board should run at right angles

to each other. This reduces the effects of feedthrough through the

board. A microstrip method is best, but not always possible with

a double-sided board. With this method, the component side of

the board is dedicated to ground plane while signal traces are

placed on the solder side.

DUT

GND

V

DUT

2

16

V

OUT

3

4

6

3

1

DUT

GND

V

(+)B

(–)B

REF

8

V

OUT

4

15

14

13

V

AD588

REF

10

11

12

AGND

WINDOW

COMPARATOR

7

8

1μF

DUT

GND

TO TESTER

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 35. ATE Application

The other AD588 provides a reference voltage for DACs 3

and 4. These provide the reference voltages for the window

comparator shown in Figure 35. Pin 9 of this AD588 is con-

nected to DUT GND. This causes V_REF(+)B and V_REF(−)B to

be referenced to DUT GND. As DAC 3 and DAC 4 input

codes vary from 000 . . . 000 to 111 . . . 111, V_OUT3 and V_OUT

vary from −5 V to +5 V with respect to DUT GND. DUT GND

is also connected to DSG B. When the AD7835 is cleared,

The AD7834/AD7835 must have ample supply bypassing

located as close as possible to the package, ideally right up

against the device. Figure 36 shows the recommended capacitor

values of 10 μF in parallel with 0.1 μF on each of the supplies.

The 10 μF capacitors are the tantalum bead type. The 0.1 μF

capacitor can have low Effective Series Resistance (ESR) and

Effective Series Inductance (ESI), such as the common ceramic

types, which provide a low impedance path to ground at high

frequencies to handle transient currents due to internal logic

switching.

4

V

_OUT3 and V_OUT4 are cleared to 0 V with respect to DUT GND.

Care must be taken to ensure that the maximum and minimum

voltage specifications for the AD7835 reference voltages are

followed as shown in Figure 35.

POWER SUPPLY BYPASSING AND GROUNDING

In any circuit where accuracy is important, careful consid-

eration of the power supply and ground return layout helps

to ensure the rated performance. The printed circuit board on

which the AD7834/AD7835 is mounted should be designed

so the analog and digital sections are separated and confined

to certain areas of the board. This facilitates the use of ground

planes that can be easily separated. A minimum etch tech-

nique is generally best for ground planes since it gives the best

shielding. Digital and analog ground planes should be joined

at only one place.

V

CC

DD

0.1μF

10μF

0.1μF

10μF

AD7834/

AD7835¹

DGND

AGND

V

SS

10μF

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 36. Power Supply Decoupling

Rev. C | Page 24 of 28

AD7834/AD7835

OUTLINE DIMENSIONS

18.10 (0.7126)

17.70 (0.6969)

28

1

15

14

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

0.75 (0.0295)

0.25 (0.0098)

× 45°

0.30 (0.0118)

0.10 (0.0039)

8°

0°

1.27 (0.0500)

SEATING

PLANE

0.51 (0.0201)

0.31 (0.0122)

1.27 (0.0500)

0.40 (0.0157)

0.33 (0.0130)

0.20 (0.0079)

COPLANARITY

0.10

BSC

COMPLIANT TO JEDEC STANDARDS MS-013-AE

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 37. 28-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(R-28)

Dimensions shown in millimeters and (inches)

1.565 (39.75)

1.380 (35.05)

28

1

15

0.580 (14.73)

0.485 (12.31)

14

0.625 (15.88)

PIN 1

0.600 (15.24)

0.100 (2.54)

BSC

0.195 (4.95)

0.125 (3.17)

0.250

0.015 (0.38)

GAUGE

(6.35)

MAX

PLANE

0.015

(0.38)

MIN

0.200 (5.08)

0.115 (2.92)

0.015 (0.38)

0.008 (0.20)

SEATING

PLANE

0.700 (17.78)

MAX

0.022 (0.56)

0.014 (0.36)

0.005 (0.13)

MIN

0.070 (1.78)

0.030 (0.76)

COMPLIANT TO JEDEC STANDARDS MS-011-AB

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 38. 28-Lead Plastic Dual In-Line Package [PDIP]

Wide Body

(N-28-2)

Dimensions shown in inches and (millimeters)

Rev. C | Page 2ꢁ of 28

AD7834/AD7835

0.180 (4.57)

0.165 (4.19)

0.048 (1.22)

0.042 (1.07)

0.056 (1.42)

0.042 (1.07)

0.020 (0.51)

MIN

6

7

40

39

0.048 (1.22)

0.042 (1.07)

0.021 (0.53)

0.013 (0.33)

PIN 1

IDENTIFIER

0.630 (16.00)

0.590 (14.99)

BOTTOM VIEW

(PINS UP)

0.050

(1.27)

BSC

TOP VIEW

(PINS DOWN)

0.032 (0.81)

0.026 (0.66)

17

18

29

28

0.040 (1.01)

0.025 (0.64)

R

0.656 (16.66)

0.650 (16.51)

0.120 (3.05)

0.090 (2.29)

SQ

0.695 (17.65)

0.685 (17.40)

SQ

COMPLIANT TO JEDEC STANDARDS MO-047-AC

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 39. 44-Lead Plastic Leaded Chip Carrier [PLCC}

(P-44A)

Dimensions shown in inches and (millimeters)

1.03

0.88

0.73

2.45

MAX

13.90

BSC SQ

33

23

34

22

SEATING

PLANE

10.00

BSC SQ

TOP VIEW

(PINS DOWN)

10°

6°

2°

2.10

2.00

1.95

0.23

0.11

VIEW A

PIN 1

44

12

7°

0°

1

11

0.25 MIN

0.10

COPLANARITY

0.45

0.30

0.80 BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

LEAD WIDTH

COMPLIANT TO JEDEC STANDARDS MO-112-AA-1

Figure 40. 44-Lead Metric Quad Flat Package [MQFP]

(S-44-2)

Dimensions show in millimeters

Rev. C | Page 26 of 28

AD7834/AD7835

ORDERING GUIDE

Package

Model

Temperature Range

−4±°C to +8ꢁ°C

Linearity Error (LSBs)

DNL (LSBs)

±±.ꢀ

Description

Option

R-28

N-28-2

P-44A

S-44-2

AD7834AR

±2

±1

±2

±1

±2

28-Lead SOIC

28-Lead PDIP

44-Lead PLCC

44-Lead-MQFP

AD7834AR-REEL

AD7834ARZ¹

AD7834ARZ-REEL¹

AD7834BR

AD7834BR-REEL

AD7834BRZ¹

AD7834BZR-REEL¹

AD7834AN

AD7834ANZ¹

AD7834BN

AD7834BNZ¹

AD783ꢁAP

AD783ꢁAP-REEL

AD783ꢁAPZ¹

AD783ꢁAPZ-REEL¹

AD783ꢁAS

AD783ꢁAS-REEL

AD783ꢁASZ¹

AD783ꢁASZ-REEL¹

¹Z = Pb-free part.

Rev. C | Page 27 of 28

AD7834/AD7835

NOTES

©

registered trademarks are the property of their respective owners.

C01006–0–7/05(C)

Rev. C | Page 28 of 28


型号：	AD7835AP-REEL
厂家：	ADI
描述：	LC2MOS Quad 14-Bit DAC PC 转换器
文件：	总28页 (文件大小：386K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7835AP-REEL [ADI]

相关型号：

AD7835APZ

AD7835APZ-REEL

AD7835AS

AD7835AS

AD7835AS-REEL

AD7835ASZ

AD7835ASZ

AD7835ASZ-REEL

AD7835BS

AD7835BSZ-REEL

AD7835_15

AD7836