AD7790BRMZ-REEL [ADI]

Low Power, 16-Bit Buffered Sigma-Delta ADC; 低功耗, 16位缓冲Σ-Δ型ADC
AD7790BRMZ-REEL
型号: AD7790BRMZ-REEL
厂家: ADI    ADI
描述:

Low Power, 16-Bit Buffered Sigma-Delta ADC
低功耗, 16位缓冲Σ-Δ型ADC

转换器 模数转换器 光电二极管
文件: 总20页 (文件大小:415K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Low Power, 16-Bit  
Buffered Sigma-Delta ADC  
Data Sheet  
AD7790  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
Power  
GND  
V
REFIN  
DD  
Supply: 2.5 V to 5.25 V operation  
Normal: 75 μA maximum  
Power-down: 1 μA maximum  
RMS noise: 1.1 μV at 9.5 Hz update rate  
16-bit p-p resolution  
V
INTERNAL  
CLOCK  
DD  
16-BIT  
ADC  
SERIAL  
INTERFACE  
DIGITAL  
PGA  
BUF  
AIN  
Integral nonlinearity: 3.5 ppm typical  
Simultaneous 50 Hz and 60 Hz rejection  
Internal clock oscillator  
AD7790  
GND  
03538-0-001  
Programmable gain amplifier  
Rail-to-rail input buffer  
Figure 1.  
VDD monitor channel  
Temperature range: –40°C to +105°C  
10-lead MSOP  
GENERAL DESCRIPTION  
The AD7790 is a low power, complete analog front end for  
low frequency measurement applications. It contains a low  
noise 16-bit ∑-Δ ADC with one differential input that can be  
buffered or unbuffered along with a digital PGA, which allows  
gains of 1, 2, 4, and 8.  
INTERFACE  
3-wire serial  
SPI®, QSPI™, MICROWIRE™, and DSP compatible  
Schmitt trigger on SCLK  
The device operates from an internal clock. Therefore, the user  
does not have to supply a clock source to the device. The output  
data rate from the part is software programmable and can be  
varied from 9.5 Hz to 120 Hz, with the rms noise equal to  
1.1 μV at the lower update rate. The internal clock frequency  
can be divided by a factor of 2, 4, or 8, which leads to a reduc-  
tion in the current consumption. The update rate, cutoff  
frequency, and settling time will scale with the clock frequency.  
APPLICATIONS  
Smart transmitters  
Battery applications  
Portable instrumentation  
Sensor measurement  
Temperature measurement  
Pressure measurement  
Weigh scales  
The part operates with a power supply from 2.5 V to 5.25 V.  
When operating from a 3 V supply, the power dissipation for  
the part is 225 μW maximum. It is housed in a 10-lead MSOP.  
4 to 20 mA loops  
Rev. A  
Document Feedback  
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sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
AD7790  
Data Sheet  
TABLE OF CONTENTS  
AD7790—Specifications.................................................................. 3  
Timing Characteristics, ................................................................... 5  
Absolute Maximum Ratings............................................................ 7  
ESD Caution.................................................................................. 7  
Pin Configuration and Function Descriptions............................. 8  
Typical Performance Characteristics ............................................. 9  
On-Chip Registers.......................................................................... 10  
Communications Register (RS1, RS0 = 0, 0) .......................... 10  
Status Register (RS1, RS0 = 0, 0; Power-on/Reset = 0x88) ... 11  
Mode Register (RS1, RS0 = 0, 1; Power-on/Reset = 0x02).... 11  
Filter Register (RS1, RS0 = 1, 0; Power-on/Reset = 0x04)..... 12  
Data Register (RS1, RS0 = 1, 1; Power-on/Reset = 0x0000) . 12  
ADC Circuit Information.............................................................. 13  
Overview...................................................................................... 13  
Noise Performance ..................................................................... 13  
Reduced Current Modes ........................................................... 13  
Digital Interface.......................................................................... 14  
Single Conversion Mode....................................................... 15  
Continuous Conversion Mode............................................. 15  
Continuous Read Mode ........................................................ 16  
Circuit Description......................................................................... 17  
Analog Input Channel ............................................................... 17  
Programmable Gain Amplifier................................................. 17  
Bipolar Configuration................................................................ 17  
Data Output Coding .................................................................. 17  
Reference Input........................................................................... 17  
VDD Monitor................................................................................ 18  
Grounding and Layout .............................................................. 18  
Outline Dimensions....................................................................... 19  
Ordering Guide .......................................................................... 19  
REVISION HISTORY  
3/13—Rev. 0 to Rev. A  
Added ESD Caution Section............................................................7  
Changes to Figure 10.......................................................................15  
Change to Reference Input Section...............................................17  
Updated Outline Dimensions........................................................19  
Changes to Ordering Guide ...........................................................19  
8/03—Revision 0: Initial Version  
Rev. A | Page 2 of 20  
Data Sheet  
AD7790  
AD7790—SPECIFICATIONS1  
Table 1. (VDD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(–) = GND; CDIV1 = CDIV0 = 0; GND = 0 V;  
all specifications TMIN to TMAX, unless otherwise noted.)  
Parameter  
AD7790B  
Unit  
Test Conditions/Comments  
ADC CHANNEL SPECIFICATION  
Output Update Rate  
9.5  
120  
Hz min nom  
Hz max nom  
ADC CHANNEL  
No Missing Codes2  
16  
Bits min  
Bits p-p  
±±REF Range, Update Rate 20 Hz  
9.5 Hz Update Rate  
Resolution  
16  
Output Noise  
Integral Nonlinearity  
Offset Error  
1.1  
±15  
±3  
µ± rms typ  
ppm of FSR max 3.5 ppm typ  
µ± typ  
Offset Error Drift vs. Temperature  
Full-Scale Error3  
Gain Drift vs. Temperature  
Power Supply Rejection  
ANALOG INPUTS  
±10  
±10  
±0.5  
90  
n±/°C typ  
µ± typ  
ppm/°C typ  
dB min  
Input Range = ±REFIN, 100 dB typ  
REFIN = REFIN(+) – REFIN(–); GAIN = 1, 2, 4, or 8  
Differential Input ±oltage Ranges  
Absolute AIN ±oltage Limits2  
±REFIN/GAIN  
GND + 100 m±  
± nom  
± min  
± max  
Buffered Mode of Operation  
±
DD – 100 m±  
Analog Input Current  
Buffered Mode of Operation  
Average Input Current2  
Average Input Current Drift  
Absolute AIN ±oltage Limits2  
±1  
±5  
nA max  
pA/°C typ  
± min  
GND – 30 m±  
Unbuffered Mode of Operation  
±
DD + 30 m±  
± max  
Analog Input Current  
Unbuffered Mode of Operation  
Input current varies with input voltage.  
Average Input Current  
Average Input Current Drift  
Normal Mode Rejection2  
@ 50 Hz, 60 Hz  
@ 50 Hz  
@ 60 Hz  
Common Mode Rejection  
@ DC  
@ 50 Hz, 60 Hz2  
±400  
±50  
nA/± typ  
pA/±/°C typ  
65  
80  
80  
dB min  
dB min  
dB min  
73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004  
90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014  
90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114  
Input Range = ±REFIN, AIN = 1 ±  
90  
100  
dB min  
dB min  
100 dB typ (FS[2:0] = 1004)  
50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114)  
REFERENCE INPUT  
REFIN ±oltage  
Reference ±oltage Range2  
REFIN = REFIN(+) – REFIN(–)  
2.5  
0.1  
± nom  
± min  
±
± max  
± min  
DD  
Absolute REFIN ±oltage Limits2  
GND – 30 m±  
±
DD + 30 m±  
± max  
Average Reference Input Current  
Average Reference Input Current Drift  
0.5  
±0.03  
µA/± typ  
nA/±/°C typ  
1 Temperature Range –40°C to +105°C.  
2 Specification is not production tested, but is supported by characterization data at initial product release.  
3 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (±DD = 4 ±).  
4 FS[2:0] are the three bits used in the filter register to select the output word rate.  
Rev. A | Page 3 of 20  
 
 
 
AD7790  
Data Sheet  
SPECIFICATIONS (continued)1  
Parameter  
AD7790B  
Unit  
Test Conditions/Comments  
REFERENCE INPUT (continued)  
Normal Mode Rejection2  
@ 50 Hz, 60 Hz  
@ 50 Hz  
@ 60 Hz  
Common Mode Rejection  
@ DC  
@ 50 Hz, 60 Hz  
65  
80  
80  
dB min  
dB min  
dB min  
73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004  
90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014  
90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114  
Input Range = ±2.5 ±, AIN = 1 ±  
100  
110  
dB typ  
dB typ  
FS[2:0] = 1004  
50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114)  
LOGIC INPUTS  
All Inputs Except SCLK2  
±
INL, Input Low ±oltage  
0.8  
0.4  
2.0  
± max  
± max  
± min  
±
±
±
DD = 5 ±  
DD = 3 ±  
DD = 3 ± or 5 ±  
±
INH, Input High ±oltage  
SCLK Only (Schmitt-Triggered Input)2  
±T(+)  
±T(–)  
±T(+) – ±T(–)  
±T(+)  
±T(–)  
±T(+) - ±T(–)  
Input Currents  
Input Capacitance  
1.4/2  
± min/± max  
± min/± max  
± min/± max  
± min/± max  
± min/± max  
± min/± max  
µA max  
±
±
±
±
±
±
DD = 5 ±  
DD = 5 ±  
DD = 5 ±  
DD = 3 ±  
DD = 3 ±  
DD = 3 ±  
0.8/1.4  
0.3/0.85  
0.9/2  
0.4/1.1  
0.3/0.85  
±1  
±IN = ±DD or GND  
All Digital Inputs  
10  
pF typ  
LOGIC OUTPUTS  
±OH, Output High ±oltage2  
±OL, Output Low ±oltage2  
±OH, Output High ±oltage2  
±OL, Output Low ±oltage2  
Floating-State Leakage Current  
Floating-State Output Capacitance  
Data Output Coding  
POWER REQUIREMENTS5  
Power Supply ±oltage  
±
0.4  
4
0.4  
±1  
10  
DD – 0.6  
± min  
± max  
± min  
± max  
µA max  
pF typ  
±
±
±
±
DD = 3 ±, ISOURCE = 100 µA  
DD = 3 ±, ISINK = 100 µA  
DD = 5 ±, ISOURCE = 200 µA  
DD = 5 ±, ISINK = 1.6 mA  
Offset Binary  
±
DD – GND  
2.5/5.25  
± min/max  
Power Supply Currents  
IDD Current6  
75  
145  
80  
160  
1
µA max  
µA max  
µA max  
µA max  
µA max  
65 µA typ, ±DD = 3.6 ±, Unbuffered Mode  
130 µA typ, ±DD = 3.6 ±, Buffered Mode  
73 µA typ, ±DD = 5.25 ±, Unbuffered Mode  
145 µA typ, ±DD = 5.25 ±, Buffered Mode  
IDD (Power-Down Mode)  
5 Digital inputs equal to ±DD or GND.  
6 The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 15).  
Rev. A | Page 4 of 20  
 
 
Data Sheet  
AD7790  
TIMING CHARACTERISTICS1, 2  
Table 2. (VDD = 2.5 V to 5.25 V; GND = 0 V, REFIN(+) = 2.5 V, REFIN(–) = GND, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V,  
Input Logic 1 = VDD, unless otherwise noted.)  
Limit at TMIN, TMAX  
(B Version)  
Parameter  
Unit  
Conditions/Comments  
SCLK High Pulsewidth  
SCLK Low Pulsewidth  
t3  
t4  
100  
100  
ns min  
ns min  
Read Operation  
t1  
0
ns min  
ns max  
ns max  
ns min  
ns max  
ns max  
ns min  
ns max  
ns max  
ns min  
CS Falling Edge to DOUT/RDY Active Time  
60  
80  
0
60  
80  
10  
80  
100  
10  
±
±
DD = 4.75 ± to 5.25 ±  
DD = 2.5 ± to 3.6 ±  
t2  
SCLK Active Edge to Data ±alid Delay4  
3
±
±
DD = 4.75 ± to 5.25 ±  
DD = 2.5 ± to 3.6 ±  
5, 6  
t5  
Bus Relinquish Time after CS Inactive Edge  
t6  
SCLK Inactive Edge to CS Inactive Edge  
SCLK Inactive Edge to DOUT/RDY High  
t7  
Write Operation  
t8  
0
ns min  
ns min  
ns min  
ns min  
CS Falling Edge to SCLK Active Edge Setup Time4  
Data ±alid to SCLK Edge Setup Time  
Data ±alid to SCLK Edge Hold Time  
CS Rising Edge to SCLK Edge Hold Time  
t9  
t10  
t11  
30  
25  
0
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of ±DD) and timed from a voltage level of 1.6 ±.  
2 See Figure 3 and Figure 4.  
3 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the ±OL or ±OH limits.  
4 SCLK active edge is falling edge of SCLK.  
5 These numbers are derived from the measured time taken by the data output to change 0.5 ± when loaded with the circuit of Figure 2. The measured number is then  
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus  
relinquish times of the part and, as such, are independent of external bus loading capacitances.  
6 RDY  
RDY  
returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while  
is high,  
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read  
only once.  
Rev. A | Page 5 of 20  
 
 
AD7790  
Data Sheet  
I
(1.6mA WITH V = 5V,  
DD  
SINK  
100µA WITH V = 3V)  
DD  
TO OUTPUT  
PIN  
1.6V  
50pF  
I
(200µA WITH V = 5V,  
DD  
SOURCE  
100µA WITH V = 3V)  
DD  
03538-0-002  
Figure 2. Load Circuit for Timing Characterization  
CS (I)  
t6  
t1  
t5  
MSB  
LSB  
t7  
DOUT/RDY (O)  
t2  
t3  
SCLK (I)  
t4  
03538-0-003  
I = INPUT, O = OUTPUT  
Figure 3. Read Cycle Timing Diagram  
CS (I)  
t11  
t8  
SCLK (I)  
DIN (I)  
t9  
t10  
MSB  
LSB  
03538-0-004  
I = INPUT, O = OUTPUT  
Figure 4. Write Cycle Timing Diagram  
Rev. A | Page 6 of 20  
 
 
 
Data Sheet  
AD7790  
ABSOLUTE MAXIMUM RATINGS  
Table 3. (TA= 25°C, unless otherwise noted.)  
Parameter  
Rating  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those listed in the operational sections  
of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
±
DD to GND  
–0.3 ± to +7 ±  
–0.3 ± to ±DD + 0.3 ±  
–0.3 ± to ±DD + 0.3 ±  
30 mA  
–0.3 ± to ±DD + 0.3 ±  
–0.3 ± to ±DD + 0.3 ±  
–40°C to +105°C  
–65°C to +150°C  
150°C  
Analog Input ±oltage to GND  
Reference Input ±oltage to GND  
Total AIN/REFIN Current (Indefinite)  
Digital Input ±oltage to GND  
Digital Output ±oltage to GND  
Operating Temperature Range  
Storage Temperature Range  
Maximum Junction Temperature  
MSOP  
ESD CAUTION  
θJA Thermal Impedance  
θJC Thermal Impedance  
Lead Temperature, Soldering (10 sec)  
IR Reflow, Peak Temperature  
206°C/W  
44°C/W  
300°C  
220°C  
Rev. A | Page 7 of 20  
 
 
AD7790  
Data Sheet  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
SCLK  
1
2
3
4
5
10 DIN  
Pin  
CS  
9
8
7
6
DOUT/RDY  
AD7790  
No. Mnemonic Function  
AIN(+)  
AIN(–)  
REF(+)  
V
DD  
TOP VIEW  
(Not to Scale)  
6
REFIN(–)  
Negative Reference Input. This reference  
input can lie anywhere between GND and  
GND  
REF(–)  
±
DD – 0.1 ±.  
03538-0-005  
7
8
9
GND  
Ground Reference Point.  
Figure 5. Pin Configuration  
±
Supply ±oltage, 2.5 ± to 5.25 ±.  
DD  
DOUT/RDY Serial Data Output/Data Ready Output.  
DOUT/RDY serves a dual purpose. It functions  
as a serial data output pin to access the output  
shift register of the ADC. The output shift reg-  
ister can contain data from any of the on-chip  
data or control registers. In addition,  
Table 4. Pin Function Descriptions  
Pin  
No. Mnemonic Function  
1
SCLK  
Serial Clock Input for Data Transfers to and  
from the ADC. The SCLK has a Schmitt-  
triggered input, making the interface suita-  
ble for opto-isolated applications. The serial  
clock can be continuous with all data  
transmitted in a continuous train of pulses.  
Alternatively, it can be a noncontinuous  
clock with the information being trans-  
mitted to or from the ADC in smaller  
batches of data.  
DOUT/RDY operates as a data ready pin,  
going low to indicate the completion of a  
conversion. If the data is not read after the  
conversion, the pin will go high before the  
next update occurs.  
The DOUT/RDY falling edge can be used as an  
interrupt to a processor, indicating that valid  
data is available. With an external serial clock,  
the data can be read using the DOUT/RDY pin.  
With CS low, the data/control word informa-  
tion is placed on the DOUT/RDY pin on the  
SCLK falling edge and is valid on the SCLK  
rising edge.  
2
CS  
Chip Select Input. This is an active low logic  
input used to select the ADC. CS can be  
used to select the ADC in systems with  
more than one device on the serial bus or as  
a frame synchronization signal in communi-  
cating with the device. CS can be hardwired  
low, allowing the ADC to operate in 3-wire  
mode with SCLK, DIN, and DOUT used to  
interface with the device.  
The end of a conversion is also indicated by  
the RDY bit in the status register. When CS is  
high, the DOUT/RDY pin is three-stated but  
the RDY bit remains active.  
3
4
5
AIN(+)  
Analog Input. AIN(+) is the positive terminal  
of the fully differential analog input.  
10  
DIN  
Serial Data Input to the Input Shift Register  
on the ADC. Data in this shift register is trans-  
ferred to the control registers within  
the ADC, the register selection bits of the  
communications register identifying the  
appropriate register.  
AIN(–)  
Analog Input. AIN(–) is the negative termi-  
nal of the fully differential analog input.  
REFIN(+)  
Positive Reference Input. REFIN(+) can lie  
anywhere between ±DD and GND + 0.1 ±.  
The nominal reference voltage (REFIN(+) –  
REFIN(–)) is 2.5 ±, but the part functions with  
a reference from 0.1 ± to ±DD.  
Rev. A | Page 8 of 20  
 
Data Sheet  
AD7790  
TYPICAL PERFORMANCE CHARACTERISTICS  
0
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
V
= 5V  
DD  
UPDATE RATE = 16.6Hz  
= 25°C  
–10  
T
A
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
–120  
0
20  
40  
60  
80  
100  
120  
140  
160  
0
0.5  
1.0  
1.5  
2.0  
2.5  
(V)  
3.0  
3.5  
4.0  
4.5  
5.0  
FREQUENCY (Hz)  
V
REF  
03538-0-007  
03538-0-013  
Figure 6. Frequency Response for a 16.6 Hz Update Rate  
Figure 7. RMS Noise vs. Reference Voltage  
Rev. A | Page 9 of 20  
 
 
AD7790  
Data Sheet  
ON-CHIP REGISTERS  
The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following  
descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.  
COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0)  
The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the  
communications register. The data written to the communications register determines whether the next operation is a read or write oper-  
ation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the  
selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default  
state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communica-  
tions register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns  
the ADC to this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0  
through CR7 indicate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data  
stream. The number in brackets indicates the power-on/reset default status of that bit.  
CR7  
CR6  
CR5  
CR4  
CR3  
CR2  
CR1  
CR0  
WEN(0)  
0(0)  
RS1(0)  
RS0(0)  
R/W(0)  
CREAD(0)  
CH1(0)  
CH0(0)  
Table 5. Communications Register Bit Designations  
Bit Location  
Bit Name  
Description  
CR7  
WEN  
Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually  
occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay  
at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits  
will be loaded to the communications register.  
CR6  
0
This bit must be programmed to Logic 0 for correct operation.  
CR5–CR4  
RS1–RS0  
Register Address Bits. These address bits are used to select which of the ADC’s registers are being select-  
ed during this serial interface communication. See Table 6.  
CR3  
CR2  
R/W  
A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this  
position indicates that the next operation will be a read from the designated register.  
CREAD  
Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the  
serial interface is configured so that the data register can be continuously read, i.e., the contents of the  
data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The commu-  
nications register does not have to be written to for data reads. To enable continuous read mode, the  
instruction 001111XX must be written to the communications register. To exit the continuous read  
mode, the instruction 001110XX must be written to the communications register while the RDY pin is  
low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the  
instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on  
DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to  
the device.  
CR1–CR0  
CH1–CH0  
These bits are used to select the analog input channel. The differential channel can be selected  
(AIN(+)/AIN(–)) or an internal short (AIN(–)/AIN(–)) can be selected. Alternatively, the power supply can  
be selected, i.e., the ADC can measure the voltage on the power supply, which is useful for monitoring  
power supply variation. The power supply voltage is divided by 5 and then applied to the modulator for  
conversion. The ADC uses a 1.17 ± ± 5% on-chip reference as the reference source for the analog to digi-  
tal conversion. Any change in channel resets the filter and a new conversion is started.  
Table 6. Register Selection  
Table 7. Channel Selection  
RS1  
RS0  
Register  
Register Size  
CH1 CH0 Channel  
0
0
Communications Register 8-Bit  
during a Write Operation  
0
0
1
1
0
1
0
1
AIN(+) – AIN(–)  
Reserved  
AIN(–) – AIN(–)  
0
0
Status Register during a  
Read Operation  
8-Bit  
±
DD Monitor  
0
1
1
1
0
1
Mode Register  
Filter Register  
Data Register  
8-Bit  
8-Bit  
16-Bit  
Rev. A | Page 10 of 20  
 
 
 
 
Data Sheet  
AD7790  
STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0x88)  
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,  
select the next operation to be a read, and load bits RS1 and RS0 with 0. Table 8 outlines the bit designations for the status register. SR0  
through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The  
number in brackets indicates the power-on/reset default status of that bit.  
SR7  
SR6  
SR5  
SR4  
SR3  
SR2  
SR1  
SR0  
RDY(1)  
ERR(0)  
0(0)  
0(0)  
1(1)  
WL(0)  
CH1(0)  
CH0(0)  
Table 8. Status Register Bit Designations  
Bit Location  
Bit Name  
Description  
SR7  
RDY  
Ready bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically  
after the ADC data register has been read or a period of time before the data register is updated with a  
new conversion result to indicate to the user not to read the conversion data. It is also set when the part  
is placed in powe-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin  
can be used as an alternative to the status register for monitoring the ADC for conversion data.  
SR6  
ERR  
ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written  
to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, under-  
range. Cleared by a write operation to start a conversion.  
SR5  
SR4  
SR3  
SR2  
0
0
1
0
This bit is automatically cleared.  
This bit is automatically cleared.  
This bit is automatically set.  
This bit is automatically cleared if the device is an AD7790. It can be used to distinguish between the  
AD7790 and AD7791, in which the bit is set.  
SR1–SR0  
CH1–CH0  
These bits indicate which channel is being converted by the ADC.  
MODE REGISTER (RS1, RS0 = 0, 1; POWER-ON/RESET = 0x02)  
The mode register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the  
ADC for range, enable or disable the buffer, or place the device into power-down mode. Table 9 outlines the bit designations for the mode  
register. MR0 through MR7 indicate the bit locations, MR denoting the bits are in the mode register. MR7 denotes the first bit of the data  
stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator  
and filter and sets the  
bit.  
RDY  
MR6  
MD0(0)  
MR7  
MR5  
MR4  
MR3  
MR2  
MR1  
MR0  
MD1(0)  
G1(0)  
G0(0)  
BO(0)  
0(0)  
BUF(1)  
0(0)  
Table 9. Mode Register Bit Designations  
Bit Location  
Bit Name  
Description  
MR7–MR6  
MD1–MD0  
Mode Select Bits. These bits select between continuous conversion mode, single conversion mode, and  
standby mode. In continuous conversion mode, the ADC continuously performs conversions and places  
the result in the data register. RDY goes low when a conversion is complete. The user can read these  
conversions by placing the device in continuous read mode whereby the conversions are automatically  
placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to  
output the conversion by writing to the communications register. After power-on, the first conversion is  
available after a period 2/ fADC while subsequent conversions are available at a frequency of fADC. In single  
conversion mode, the ADC is placed in power-down mode when conversions are not being performed.  
When single conversion mode is selected, the ADC powers up and performs a single conversion, which  
occurs after a period 2/fADC. The conversion result in placed in the data register, RDY goes low, and the  
ADC returns to power-down mode. The conversion remains in the data register and RDY remains active  
(low) until the data is read or another conversion is performed. See Table 10.  
MR5–MR4  
MR3  
G1–G0  
BO  
Range Bits. The AD7790 can be operated with four analog input ranges (see Table 11).  
Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal  
path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled  
only when the buffer is active.  
Rev. A | Page 11 of 20  
 
 
 
 
AD7790  
Data Sheet  
Bit Location  
MR2  
Bit Name  
Description  
0
This bit must be programmed with a Logic 0 for correct operation.  
MR1  
BUF  
Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in un-  
buffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered  
mode, allowing the user to place source impedances on the front end without contributing gain errors  
to the system.  
MR0  
0
This bit must be programmed with a Logic 0 for correct operation.  
Table 10. Operating Modes  
Table 11. Analog Input Ranges  
MD1  
MD0  
Mode  
AD7790 LSB Size with VREF = +2.5 V  
G1 G0 Range (µV)  
0
0
Continuous Conversion Mode (De-  
fault)  
Reserved  
Single Conversion Mode  
Power-Down Mode  
0
0
1
1
0
1
0
1
±±REF  
76.3  
0
1
1
1
0
1
±±REF/2 38.14  
±±REF/4 19.07  
±±REF/8 9.54  
FILTER REGISTER (RS1, RS0 = 1, 0; POWER-ON/RESET = 0x04)  
The filter register is an 8-bit register from which data can be read or to which data can be written. This register is used to set the output  
word rate. Table 12 outlines the bit designations for the filter register. FR0 through FR7 indicate the bit locations, FR denoting the bits are in  
the filter register. FR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.  
FR7  
FR6  
FR5  
FR4  
FR3  
FR2  
FR1  
FR0  
0(0)  
0(0)  
CDI±1(0)  
CDI±0(0)  
0(0)  
FS2(1)  
FS1(0)  
FS0(0)  
Table 12. Filter Register Bit Designatins  
Bit Location  
Bit Name  
Description  
FR7–FR6  
0
These bits must be programmed with a Logic 0 for correct operation.  
FR5–FR4  
CLKDI±1–  
CDI±0  
These bits are used to operate the AD7790 in the lower power modes. The clock is internally divided and  
the power is reduced.  
00  
01  
10  
11  
Normal Mode  
Clock Divided by 2  
Clock Divided by 4  
Clock Divided by 8  
FR3  
0
This bit must be programmed with a Logic 0 for correct operation.  
FR2–FR0  
FS2–FS0  
These bits set the output word rate of the ADC. The update rate influences the 50 Hz/60 Hz rejection and  
noise. The noise is the same for all gain settings. See Table 13 for the allowable update rates in full power  
mode. In the low power modes, the update rates will be reduced. (See Reduced Current Modes.)  
Table 13. Update Rates  
FS2  
FS1  
FS0  
fADC (Hz)  
120  
100  
33.3  
20  
16.6  
16.7  
13.3  
9.5  
f3dB (Hz)  
RMS Noise (µV)  
Rejection  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
28  
24  
8
4.7  
4
4
3.2  
2.3  
40  
25  
25 dB @ 60 Hz  
25 dB @ 50 Hz  
3.36  
1.6  
1.5  
1.5  
1.2  
1.1  
80 dB @ 60 Hz  
65 dB @ 50 Hz/60 Hz (Default Setting)  
80 dB @ 50 Hz  
62 dB @ 50/60 Hz  
DATA REGISTER (RS1, RS0 = 1, 1; POWER-ON/RESET = 0x0000)  
The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from  
this register, the bit/pin is set.  
RDY  
Rev. A | Page 12 of 20  
 
 
 
 
 
 
Data Sheet  
AD7790  
ADC CIRCUIT INFORMATION  
numbers given are with a reference of 2.5 V. The numbers are  
typical and generated with a differential input volta g e of 0 V.  
The peak-to-peak resolution figures represent the resolution for  
which there will be no code flicker within a six-sigma limit. The  
output noise comes from two sources. The first is the electrical  
noise in the semiconductor devices (device noise) used in the  
implementation of the modulator. The second is quantization  
noise, which is added when the analog input is converted into  
the digital domain. The device noise is at a low level and is  
independent of frequency. The quantization noise starts at an  
even lower level but rises rapidly with increasing frequency to  
become the dominant noise source.  
OVERVIEW  
The AD7790 is a low power ADC that incorporates a ∑-∆ mod-  
ulator, a buffer, a PGA, and on-chip digital filtering intend-ed  
for the measurement of wide dynamic range, low frequency  
signals such as those in pressure transducers, weigh scales, and  
temperature measurement applications.  
The part has one differential input that can be buffered or  
unbuffered. Buffering the input channel means that the part can  
accommodate significant source impedances on the analog  
input and that R, C filtering (for noise rejection or RFI reduc-  
tion) can be placed on the analog input, if required. The device  
requires an external reference of 2.5 nominal. Figure 7 shows  
the basic connections required to operate the part.  
Table 14. Typical Peak-to-Peak Resolution (Effective  
Resolution) vs. Update Rate and Input Range  
Input Range  
POWER  
SUPPLY  
Update Rate  
9.5  
13.3  
16.7  
16.6  
20  
33.3  
100  
120  
0.3125  
16 (16)  
16 (16)  
16 (16)  
16 (16)  
0.625  
16 (16)  
16 (16)  
16 (16)  
16 (16)  
1.25  
2.5  
0.1µF  
10µF  
16 (16)  
16 (16)  
16 (16)  
16 (16)  
16 (16)  
16 (16)  
16 (16)  
16 (16)  
16 (16)  
16 (16)  
16 (16)  
V
DD  
REFIN(+)  
IN+  
AD7790  
15.5 (16) 16 (16)  
14.5 (16) 15.5 (16) 16 (16)  
11.5 (14) 12.5 (15) 13.5 (16) 14.5 (16)  
11 (13.5) 12 (14.5) 13 (15.5) 14 (16)  
OUT–  
OUT+  
CS  
AIN(+)  
DOUT/RDY  
SCLK  
MICROCONTROLLER  
AIN(–)  
IN–  
REFIN(–)  
GND  
REDUCED CURRENT MODES  
03538-0-006  
Figure 7. Basic Connection Diagram  
The AD7790 has a current consumption of 160 µA maximum  
when operated with the buffer enabled and with a 5 V power  
supply. The power can be reduced further by setting bits CDIV1  
and CDIV0 in the filter register appropriately (see Table 15).  
The output rate of the AD7790 (fADC) is user programmable  
with the settling time equal to 2 × tADC. Normal mode rejection  
is the major function of the digital filter. Table 13 lists the avail-  
able output rates from the AD7790. Simultaneous 50 Hz and  
60 Hz rejection is optimized when the update rate equals  
16.6 Hz as notches are placed at both 50 Hz and 60 Hz with this  
update rate (see Figure 6).  
By setting these bits, the internal clock is divided by 2, 4, or 8  
before being applied to the modulator and filter, resulting in a  
reduction in the digital current.  
When the internal clock is reduced, the update rate will also be  
reduced. For example, if the filter bits are set to give an update  
rate of 16.6 Hz when the AD7790 is operated in full clock  
mode, the update rate will equal 8.3 Hz in divide by 2 mode. In  
these low power modes, there may be some degradation in the  
ADC performance.  
NOISE PERFORMANCE  
Table 14 shows the output rms noise, rms resolution, and peak-  
to-peak resolution (rounded to the nearest 0.5 LSB) for the  
different update rates and input ranges for the AD7790. The  
Table 15. Low Power Mode Selection  
CDIV[1:0]  
Clock  
Typ Current, Buffered (µA)  
Typ Current, Unbuffered (µA)  
50 Hz/60 Hz Rejection (dB)  
00  
10  
10  
11  
1
146  
87  
56  
75  
45  
30  
25  
70  
72  
88  
89  
1/2  
1/4  
1/8  
41  
Rev. A | Page 13 of 20  
 
 
 
 
 
 
 
AD7790  
Data Sheet  
shift register while Figure 4 shows the timing for a write opera-  
tion to the input shift register. In all modes except continuous  
read mode, it is possible to read the same word from the data  
DIGITAL INTERFACE  
As previously outlined, the AD7790s programmable functions  
are controlled using a set of on-chip registers. Data is written to  
these registers via the parts serial interface and read access to  
the on-chip registers is also provided by this interface. All  
communications with the part must start with a write to the  
communications register. After power-on or reset, the device  
expects a write to its communications register. The data written  
to this register determines whether the next operation is a read  
operation or a write operation and also determines to which  
register this read or write operation occurs. Therefore, write  
access to any of the other registers on the part begins with a  
write operation to the communications register followed by a  
write to the selected register. A read operation from any other  
register (except when continuous read mode is selected) starts  
with a write to the communications register followed by a read  
operation from the selected register.  
register several times even though the DOUT/  
line returns  
RDY  
high after the first read operation. However, care must be taken  
to ensure that the read operations have been completed before  
the next output update occurs. In continuous read mode, the  
data register can be read only once.  
The serial interface can operate in 3-wire mode by tying  
low.  
CS  
In this case, the SCLK, DIN, and DOUT/  
lines are used to  
RDY  
communicate with the AD7790. The end of the conversion can  
be monitored using the bit in the status register. This  
RDY  
scheme is suitable for interfacing to microcontrollers. If  
is  
CS  
required as a decoding signal, it can be generated from a port  
pin. For microcontroller interfaces, it is recommended that  
SCLK idles high between data transfers.  
The AD7790 can be operated with  
being used as a frame  
CS  
The AD7790s serial interface consists of four signals: , DIN,  
CS  
synchronization signal. This scheme is useful for DSP interfac-  
es. In this case, the first bit (MSB) is effectively clocked out by  
SCLK, and DOUT/  
. The DIN line is used to transfer data  
RDY  
into the on-chip registers while DOUT/  
is used for access-  
RDY  
ing from the on-chip registers. SCLK is the serial clock input for  
the device and all data transfers (either on DIN or DOUT/  
since  
would normally occur after the falling edge of  
CS  
CS  
SCLK in DSPs. The SCLK can continue to run between data  
transfers, provided the timing numbers are obeyed.  
)
RDY  
pin  
occur with respect to the SCLK signal. The DOUT/  
RDY  
operates as a Data Ready signal also, the line going low when a  
new data-word is available in the output register. It is reset high  
when a read operation from the data register is complete. It also  
goes high prior to the updating of the data register to indicate  
when not to read from the device to ensure that a data read is  
The serial interface can be reset by writing a series of 1s on the  
DIN input. If a Logic 1 is written to the AD7790 line for at least  
32 serial clock cycles, the serial interface is reset. This ensures  
that in 3-wire systems, the interface can be reset to a known  
state if the interface gets lost due to a software error or some  
glitch in the system. Reset returns the interface to the state in  
which it is expecting a write to the communications register.  
This operation resets the contents of all registers to their power-  
on values.  
not attempted while the register is being updated.  
is used to  
CS  
select a device. It can be used to decode the AD7790 in systems  
where several components are connected to the serial bus.  
Figure 3 and Figure 4 show timing diagrams for interfacing to  
the AD7790 with  
shows the timing for a read operation from the AD7790s output  
being used to decode the part. Figure 3  
CS  
The AD7790 can be configured to continuously convert or to  
perform a single conversion. See Figure 8 through Figure 10.  
Rev. A | Page 14 of 20  
 
Data Sheet  
AD7790  
Single Conversion Mode  
Continuous Conversion Mode  
This is the default power-up mode. The AD7790 will continu-  
ously convert, the pin in the status register going low each  
In single conversion mode, the AD7790 is placed in shutdown  
mode between conversions. When a single conversion is initiat-  
ed by setting MD1 to 1 and MD0 to 0 in the mode register, the  
AD7790 powers up, performs a single conversion, and then  
returns to shutdown mode. A conversion will require a time  
RDY  
time a conversion is complete. If  
is low, the DOUT/  
line  
RDY  
CS  
will also go low when a conversion is complete. To read a con-  
version, the user can write to the communications register,  
indicating that the next operation is a read of the data register.  
period of 2 × tADC. DOUT/  
goes low to indicate the com-  
RDY  
pletion of a conversion. When the data-word has been read  
from the data register, DOUT/ will go high. If is low,  
The digital conversion will be placed on the DOUT/  
pin as  
RDY  
RDY  
CS  
soon as SCLK pulses are applied to the ADC. DOUT/  
will  
RDY  
DOUT/  
will remain high until another conversion is initi-  
RDY  
return high when the conversion is read. The user can read this  
register additional times, if required. However, the user must  
ensure that the data register is not being accessed at the comple-  
tion of the next conversion or else the new conversion word will  
be lost.  
ated and completed. The data register can be read several times,  
if required, even when DOUT/  
has gone high.  
RDY  
CS  
0x10  
0x82  
0x38  
DIN  
DATA  
DOUT/RDY  
SCLK  
03538-0-011  
Figure 8. Single Conversion  
CS  
0x38  
0x38  
DIN  
DATA  
DATA  
DOUT/RDY  
SCLK  
03538-0-012  
Figure 9. Continuous Conversion  
Rev. A | Page 15 of 20  
 
 
 
AD7790  
Data Sheet  
Continuous Read Mode  
before the next conversion is complete. If the user has not read  
the conversion before the completion of the next conversion or  
if insufficient serial clocks are applied to the AD7790 to read  
the word, the serial output register is reset when the next con-  
version is complete and the new conversion is placed in the  
output serial register.  
Rather than write to the communications register each time a  
conversion is complete to access the data, the AD7790 can be  
placed in continuous read mode. By writing 001111XX to the  
communications register, the user only needs to apply the  
appropriate number of SCLK cycles to the ADC and the 16-bit  
word will automatically be placed on the DOUT/  
when a conversion is complete.  
line  
RDY  
To exit the continuous read mode, the instruction 001110XX  
must be written to the communications register while the  
RDY  
pin is low. While in the continuous read mode, the ADC  
monitors activity on the DIN line so that it can receive the  
instruction to exit the continuous read mode. Additionally, a  
reset will occur if 32 consecutive 1s are seen on DIN. Therefore,  
DIN should be held low in continuous read mode until an  
instruction is to be written to the device.  
When DOUT/  
goes low to indicate the end of a conver-  
RDY  
sion, sufficient SCLK cycles must be applied to the ADC and  
the data conversion will be placed on the DOUT/ line.  
RDY  
will return high  
When the conversion is read, DOUT/  
RDY  
until the next conversion is available. In this mode, the data can  
be read only once. Also, the user must ensure that the data-  
word is read  
CS  
0x3C  
DIN  
DATA  
DATA  
DATA  
DOUT/RDY  
SCLK  
03538-0-011  
Figure 10. Continuous Read  
Rev. A | Page 16 of 20  
 
 
Data Sheet  
AD7790  
CIRCUIT DESCRIPTION  
ANALOG INPUT CHANNEL  
BIPOLAR CONFIGURATION  
The AD7790 has one differential analog input channel. This is  
connected to the on-chip buffer amplifier when the device is  
operated in buffered mode and directly to the modulator when  
the device is operated in unbuffered mode. In buffered mode  
(the BUF bit in the mode register is set to 1), the input channel  
feeds into a high impedance input stage of the buffer amplifier.  
Therefore, the input can tolerate significant source impedances  
and is tailored for direct connection to external resistive-type  
sensors such as strain gauges or resistance temperature detec-  
tors (RTDs).  
The analog input to the AD7790 accepts a bipolar input voltage  
range. A bipolar input range does not imply that the part can  
tolerate negative voltages with respect to system GND. Bipolar  
signals on the AIN(+) input are referenced to the voltage on the  
AIN(–) input. For example, if AIN(–) is 2.5 V and the ADC is  
configured for a gain of 1, the analog input range on the AIN(+)  
input is 0 V to 5 V.  
DATA OUTPUT CODING  
The output code is offset binary with a negative full-scale volt-  
age resulting in a code of 000...000, a zero differential input  
voltage resulting in a code of 100...000, and a positive full-scale  
input voltage resulting in a code of 111...111. The output code  
for any analog input voltage can be represented as  
When BUF = 0, the part is operated in unbuffered mode.  
This results in a higher analog input current. Note that this  
unbuffered input path provides a dynamic load to the driving  
source. Therefore, resistor/capacitor combinations on the  
input pins can cause dc gain errors, depending on the output  
impedance of the source that is driving the ADC input. Table 16  
shows the allowable external resistance/capacitance values for  
unbuffered mode such that no gain error at the 16-bit level is  
introduced.  
Code = 2N – 1 × [(AIN × GAIN/VREF) + 1]  
where AIN is the analog input voltage, GAIN is the PGA gain,  
and N = 16.  
REFERENCE INPUT  
The AD7790 has a fully differential input capability for the  
channel. The common-mode range for these differential inputs  
is from GND to VDD. The reference input is unbuffered and,  
therefore, excessive R-C source impedances will introduce gain  
errors. The reference voltage REFIN (REFIN(+) – REFIN(–)) is  
2.5 V nominal for specified operation, but the AD7790 is func-  
tional with reference voltages from 0.1 V to VDD. In applications  
where the excitation (voltage or current) for the transducer on  
the analog input also drives the reference voltage for the part,  
the effect of the low frequency noise in the excitation source  
will be removed because the application is ratiometric. If the  
AD7790 is used in a nonratiometric application, a low noise  
reference should be used.  
Table 16. External R-C Combination for No 16-Bit Gain Error  
C (pF)  
R (Ω)  
22.8K  
13.1K  
3.3K  
50  
100  
500  
1000  
5000  
1.8K  
360  
The absolute input voltage range in buffered mode is restricted  
to a range between GND + 100 mV and VDD – 100 mV. Care  
must be taken in setting up the common-mode voltage so that  
these limits are not exceeded. Otherwise, there will be degrada-  
tion in linearity and noise performance.  
Recommended 2.5 V reference voltage sources for the AD7790  
include the ADR381 and ADR391 because these are low noise,  
low power references. If the complete analog section is driven  
from a 2.5 V power supply, the reference voltage source will  
require some headroom. In this case, a 2.048 V reference such  
as the ADR380 is recommended, again low noise, low power  
references. Also note that the reference inputs provide a high  
impedance, dynamic load. Because the input impedance of each  
reference input is dynamic, resistor/capacitor combinations on  
these inputs can cause dc gain errors, depending on the output  
impedance of the source that is driving the reference inputs.  
Reference voltage sources like those recommended above (e.g.,  
ADR391) will typically have low output impedances and are,  
therefore, tolerant to having decoupling capacitors on  
The absolute input voltage in unbuffered mode includes the  
range between GND – 30 mV and VDD + 30 mV as a result of  
being unbuffered. The negative absolute input voltage limit does  
allow the possibility of monitoring small true bipolar signals  
with respect to GND.  
PROGRAMMABLE GAIN AMPLIFIER  
The output from the buffer on the ADC is applied to the input  
of the on-chip programmable gain amplifier (PGA). The PGA  
gain range is programmed via the gain bits G1 and G0 in the  
mode register. With an external 2.5 V reference applied, the  
PGA can be programmed to have a bipolar range of 2.5 V,  
1.25 V, 625 mV, or 312.5 mV. These are the ranges that  
should appear at the input to the on-chip PGA.  
Rev. A | Page 17 of 20  
 
 
 
 
 
 
 
AD7790  
Data Sheet  
and confined to certain areas of the board. A minimum etch  
technique is generally best for ground planes because it gives  
the best shielding.  
REFIN(+) without introducing gain errors in the system. Deriv-  
ing the reference input voltage across an external resistor will  
mean that the reference input sees a significant external source  
impedance. External decoupling on the REFIN pins would not  
be recommended in this type of circuit configuration.  
It is recommended that the AD7790s GND pin be tied to the  
AGND plane of the system. In any layout, it is important that  
the user keep in mind the flow of currents in the system, ensur-  
ing that the return paths for all currents are as close as possible  
to the paths the currents took to reach their destinations. Avoid  
forcing digital currents to flow through the AGND sections of  
the layout.  
VDD MONITOR  
Along with converting external voltages, the analog input chan-  
nel can be used to monitor the voltage on the VDD pin. When  
the CH1 and CH0 bits in the communications register are set to  
1, the voltage on the VDD pin is internally attenuated by 5 and  
the resultant voltage is applied to the ∑-∆ modulator using an  
internal 1.17 V reference for analog to digital conversion. This  
is useful because variations in the power supply voltage can be  
monitored.  
The AD7790s ground plane should be allowed to run under the  
AD7790 to prevent noise coupling. The power supply lines to  
the AD7790 should use as wide a trace as possible to provide  
low impedance paths and reduce the effects of glitches on the  
power supply line. Fast switching signals such as clocks should  
be shielded with digital ground to avoid radiating noise to other  
sections of the board, and clock signals should never be run  
near the analog inputs. Avoid crossover of digital and analog  
signals. Traces on opposite sides of the board should run at  
right angles to each other. This will reduce the effects of feed-  
through through the board. A microstrip technique is by far the  
best, but it is not always possible with a double-sided board. In  
this technique, the component side of the board is dedicated to  
ground planes, while signals are placed on the solder side.  
GROUNDING AND LAYOUT  
Since the analog inputs and reference inputs of the ADC are  
differential, most of the voltages in the analog modulator are  
common-mode voltages. The excellent common-mode rejec-  
tion of the part will remove common-mode noise on these  
inputs. The digital filter will provide rejection of broadband  
noise on the power supply, except at integer multiples of the  
modulator sampling frequency. The digital filter also removes  
noise from the analog and reference inputs, provided that these  
noise sources do not saturate the analog modulator. As a result,  
the AD7790 is more immune to noise interference than a con-  
ventional high resolution converter. However, because the  
resolution of the AD7790 is so high, and the noise levels from  
the AD7790 are so low, care must be taken with regard to  
grounding and layout.  
Good decoupling is important when using high resolution  
ADCs. VDD should be decoupled with 10 µF tantalum in parallel  
with 0.1 µF capacitors to GND. To achieve the best from these  
decoupling components, they should be placed as close as  
possible to the device, ideally right up against the device. All  
logic chips should be decoupled with 0.1 µF ceramic capacitors  
to DGND.  
The printed circuit board that houses the AD7790 should be  
designed such that the analog and digital sections are separated  
Rev. A | Page 18 of 20  
 
 
Data Sheet  
AD7790  
OUTLINE DIMENSIONS  
3.10  
3.00  
2.90  
10  
1
6
5
5.15  
4.90  
4.65  
3.10  
3.00  
2.90  
PIN 1  
IDENTIFIER  
0.50 BSC  
0.95  
0.85  
0.75  
15° MAX  
1.10 MAX  
0.70  
0.55  
0.40  
0.15  
0.05  
0.23  
0.13  
6°  
0°  
0.30  
0.15  
COPLANARITY  
0.10  
COMPLIANT TO JEDEC STANDARDS MO-187-BA  
Figure 11. 10-Lead Mini Small Outline Package [MSOP]  
(RM-10)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Model1  
Temperature Range  
Package Description  
Package Option  
RM-10  
RM-10  
RM-10  
RM-10  
Branding  
AD7790BRM  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +105°C  
10-Lead Mini Small Outline Package (MSOP)  
10-Lead Mini Small Outline Package (MSOP)  
10-Lead Mini Small Outline Package (MSOP)  
10-Lead Mini Small Outline Package (MSOP)  
COS  
COS#  
COS  
AD7790BRMZ  
AD7790BRM-REEL  
AD7790BRMZ-REEL  
COS#  
1 Z = RoHS Compliant Part.  
Rev. A | Page 19 of 20  
 
 
AD7790  
NOTES  
Data Sheet  
©2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D03538-0-3/13(A)  
Rev. A | Page 20 of 20  

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