AD7740YRM [ADI]
3 V/5 V Low Power, Synchronous Voltage-to-Frequency Converter; 3 V / 5 V低功耗，同步电压频率转换器
| 型号： | AD7740YRM |
| 厂家： | 
ADI |
| 描述： | 3 V/5 V Low Power, Synchronous Voltage-to-Frequency Converter |
| 文件： | 总11页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 V/5 V Low Power, Synchronous
Voltage-to-Frequency Converter
a
AD7740*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Synchronous Operation
Full-Scale Frequency Set by External System Clock
8-Lead SOT-23 and 8-Lead microSOIC Packages
3 V or 5 V Operation
REFIN/OUT
VDD
AD7740
2.5V
REFERENCE
Low Power: 3 mW (Typ)
Nominal Input Range: 0 to VREF
True –150 mV Capability Without Charge Pump
VREF Range: 2.5 V to VDD
Internal 2.5 V Reference
1 MHz Max Input Frequency
VOLTAGE-TO-
FREQUENCY
MODULATOR
X1
VIN
FOUT
Selectable High Impedance Buffered Input
Minimal External Components Required
CLOCK
GENERATION
APPLICATIONS
Isolation of High Common-Mode Voltages
Low-Cost Analog-to-Digital Conversion
Battery Monitoring
BUF
CLKOUT
CLKIN
GND
Automotive Sensing
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7740 is a low-cost, ultrasmall synchronous Voltage-to-
Frequency Converter (VFC). It works from a single 3.0 V to
3.6 V or 4.75 V to 5.25 V supply consuming 0.9 mA. The AD7740
is available in an 8-lead SOT-23 and also in an 8-lead microSOIC
package. Small package, low cost and ease of use were major
design goals for this product. The part contains an on-chip 2.5 V
bandgap reference but the user may overdrive this using an
external reference. This external reference range includes VDD.
1. The AD7740 is a single channel, single-ended VFC. It is
available in 8-lead SOT-23 and 8-lead microSOIC packages,
and is intended for low-cost applications. The AD7740 offers
considerable space saving over alternative solutions.
2. The AD7740 operates from a single 3.0 V to 3.6 V or 4.75 V
to 5.25 V supply and consumes typically 0.9 mA when the
input is unbuffered. It also contains an automatic power-down
function.
The full-scale output frequency is synchronous with the clock
signal on the CLKIN pin. This clock can be generated with the
addition of an external crystal (or resonator) or supplied from a
CMOS-compatible clock source. The part has a maximum
input frequency of 1 MHz.
3. The AD7740 does not require external resistors and capaci-
tors to set the output frequency. The maximum output
frequency is set by a crystal or a clock. No trimming or cali-
bration is required.
4. The analog input can be taken to 150 mV below GND for
true bipolar operation.
For an analog input signal that goes from 0 V to VREF, the out-
put frequency goes from 10% to 90% of fCLKIN. In buffered mode,
the part provides a very high input impedance and accepts a
range of 0.1 V to VDD – 0.2 V on the VIN pin. There is also
an unbuffered mode of operation that allows VIN to go from
–0.15 V to VDD + 0.15 V. The modes are interchangeable using
the BUF pin.
5. The specified voltage reference range on REFIN is from
2.5 V to the supply voltage, VDD.
The AD7740 (Y Grade) is guaranteed over the automotive
temperature range of –40°C to +105°C. The AD7740 (K Grade)
is guaranteed from 0°C to 85°C.
*Patents pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(VDD = 3.0 V to 3.6 V, 4.75 V to 5.25 V, GND = 0 V, REFIN = 2.5 V; CLKIN = 1 MHz; All
AD7740 SPECIFICATIONS specifications TMIN to TMAX unless otherwise noted.)
K, Y Versions1
Parameter2
Min
Typ
Max
Unit
Test Conditions/Comments
DC PERFORMANCE
Integral Nonlinearity
CLKIN = 32 kHz3
CLKIN = 1 MHz
CLKIN = 32 kHz3
CLKIN = 1 MHz
Offset Error
0.012
0.012
0.018
0.018
35
% of Span4
% of Span
% of Span
% of Span
mV
Unbuffered Mode, External Clock at CLKIN
Unbuffered Mode, Crystal at CLKIN
Buffered Mode, External Clock at CLKIN
Buffered Mode, Crystal at CLKIN
Unbuffered Mode, VIN = 0 V
7
7
35
mV
Buffered Mode, VIN = 0.1 V
Gain Error
0.1
20
4
–55
–65
0.7
% of Span
µV/°C
Offset Error Drift3
Gain Error Drift3
ppm of Span/°C
Power Supply Rejection Ratio3
dB
dB
∆VDD = 5% (5 V)
∆VDD = 10% (3.3 V)
ANALOG INPUT, VIN
Nominal Input Span
0 – VREF
V
V
µA
nA
150 mV Overrange Available
Buffered Mode
Unbuffered Mode, VIN = 5.4 V, REFIN = 5.25 V
Buffered Mode, VIN = 0.1 V, REFIN = 2.5 V
0.1
2.3
VDD – 0.2
10
100
Input Current
8
5
REFERENCE VOLTAGE
REFIN5
Nominal Input Voltage
REFOUT
2.5
VDD
2.7
V
Output Voltage
2.5
1
50
–75
–60
100
V
Output Impedance3
Reference Drift3
kΩ
See Pin Function Description
ppm/°C
Line Rejection3
dB
∆VDD = 5% (5 V)
∆VDD = 10% (3.3 V)
Line Rejection3
dB
µV p–p
Reference Noise (0.1 Hz to 10 Hz)3
FOUT OUTPUT
Nominal Frequency Span
0.1 fCLKIN to 0.9 fCLKIN
Hz
VIN = 0 V to VREF. See Figure 2
LOGIC INPUTS (CLKIN, BUF)3
CLKIN
Input frequency
32
3.5
2.5
1000
kHz
V
V
V
V
µA
pF
For Specified Performance
VDD = 5 V 5%
VDD = 3.3 V 10%
VDD = 5 V 5%
VDD = 3.3 V 10%
VIN = 0 V to VDD
Input High Voltage, VIH
Input High Voltage, VIH
Input Low Voltage, VIL
Input Low Voltage, VIL
Input Current
0.8
0.4
2
Pin Capacitance
3
10
BUF
Input High Voltage, VIH
Input High Voltage, VIH
Input Low Voltage, VIL
Input Low Voltage, VIL
Input Current
2.4
2.1
V
V
V
V
nA
pF
VDD = 5 V 5%
VDD = 3.3 V 10%
VDD = 5 V 5%
VDD = 3.3 V 10%
0.8
0.4
100
Pin Capacitance
3
10
LOGIC OUTPUTS (FOUT, CLKOUT)3
Output High Voltage, VOH
Output High Voltage, VOH
4.0
2.1
V
V
V
Output Sourcing 200 µA6. VDD = 5 V 5%
Output Sourcing 200 µA6. VDD = 3.3 V 10%
Output Sinking 1.6 mA6
Output Low Voltage, VOL
0.1
0.4
POWER REQUIREMENTS
7
VDD
3.0
5.25
1.25
1.5
V
I
I
I
DD (Normal Mode)8
DD (Normal Mode)8
DD (Power-Down)
0.9
1.1
30
mA
mA
µA
µs
VIH = VDD, VIL= GND. Unbuffered Mode
VIH = VDD, VIL= GND. Buffered Mode
100
Power-Up Time3
30
Exiting Power-Down (Ext. Clock at CLKIN)
NOTES
1Temperature range: K Version, 0°C to +85°C; Y Version, –40°C to +105°C; typical specifications are at 25°C.
2See Terminology.
3Guaranteed by design and characterization, not production tested.
4Span = Max output frequency–Min output frequency.
5Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400 µA in order to overdrive the internal reference.
6These logic levels apply to CLKOUT only when it is loaded with one CMOS load.
7Operation at VDD = 2.7 V is also possible with degraded specifications.
8Outputs unloaded. IDD increases by CL × VOUT × fFOUT when FOUT is loaded. If using a crystal/resonator as the clock source, IDD will vary depending on the crystal/resonator
type (see Clock Generation section).
Specifications subject to change without notice.
REV. 0
–2–
AD7740
TIMING CHARACTERISTICS1, 2, 3
(VDD = 3.0 V to 3.6 V, 4.75 V to 5.25 V, GND = O V, REFIN = 2.5 V)
Limit at TMIN, TMAX
Limit at TMIN, TMAX
Parameter
VDD = 3.0 V to 3.6 V
VDD = 4.75 V to 5.25 V
Unit
Conditions/Comments
fCLKIN
32
1
40:60
60:40
50
2.3
1.6
tHIGH 20
32
1
40:60
60:40
35
1.8
1.4
kHz min
MHz max
min
Clock Frequency
tHIGH:tLOW
Clock Mark/Space Ratio
max
t1
t2
t3
t4
ns typ
ns typ
ns typ
ns typ
CLKIN Edge to FOUT Edge Delay
FOUT Rise Time
FOUT Fall Time
tHIGH
8
FOUT Pulsewidth
NOTES
1Guaranteed by design and characterization, not production tested.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3See Figure 1.
Specifications subject to change without notice
tHIGH
CLKIN
tLOW
t4
FOUT
t1
t2
t3
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
microSOIC Package
Power Dissipation . . . . . . . . . . . . . . . . . (TJ Max – TA)/θJA
θ
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44°C/W
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
Logic Input Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V
FOUT Voltage to GND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Lead Temperature (10 secs) . . . . . . . . . . . . . . . . . . . 300°C
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . 220 +5/0°C
Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec
Commercial (K Version) . . . . . . . . . . . . . . . . 0°C to +85°C
Automotive (Y Version) . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ Max) . . . . . . . . . . . . . . . . . . 150°C
SOT-23 Package
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Power Dissipation . . . . . . . . . . . . . . . . . . (TJ Max – TA)/θJA
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 240°C/W
Lead Temperature (10 secs) . . . . . . . . . . . . . . . . . . 300°C
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . 220 + 5/0°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7740 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD7740
PIN CONFIGURATIONS
8-Lead microSOIC
8-Lead SOT-23
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
BUF
FOUT
VDD
VIN
CLKOUT
CLKIN
CLKOUT
BUF
AD7740
AD7740
SOT-23
TOP VIEW
CLKIN
GND
FOUT
VDD
microSOIC
TOP VIEW
(Not to Scale)
GND
(Not to Scale)
REFIN/OUT
VIN
REFIN/OUT
PIN FUNCTION DESCRIPTIONS
8-LEAD microSOIC PIN NUMBERS*
Pin
No.
Mnemonic
Function
1
CLKOUT
The crystal/resonator is tied between this pin and CLKIN. In the case of an external clock driving CLKIN, an
inverted clock signal appears on this pin and can be used to drive other circuitry provided it is buffered first.
2
CLKIN
The master clock for the device may be in the form of a crystal/resonator tied between this pin and CLKOUT.
An external CMOS-compatible clock may also be applied to this input as the clock for the device. If CLKIN
is inactive low for 1 ms (typ), the AD7740 automatically enters power-down.
3
4
GND
Ground reference for all the circuitry on-chip.
REFIN/OUT Voltage Reference Input. This is the reference input to the core of the VFC and defines the span of the VFC.
If this pin is left unconnected, the internal 2.5 V reference is the default reference. Alternatively, a precision
external reference may be used to overdrive the internal reference. The internal reference has high output
impedance in order to allow it to be overdriven.
5
6
VIN
The analog input to the VFC. It has a nominal input range from 0 V to VREF which corresponds to an output
frequency of 10% fCLKIN to 90% fCLKIN. It has a 150 mV overrange. If buffered, it draws virtually no current
from whatever source is driving it.
Power Supply Input. These parts can be operated at 3.3 V 10% or 5 V 5%. The supply should be
adequately decoupled with a 10 µF and a 0.1 µF capacitor to GND.
VDD
7
8
FOUT
BUF
Frequency Output. FOUT goes from 10% to 90% of fCLKIN, depending on VIN.
Buffered Mode Select Pin. When BUF is tied low, the VIN input is unbuffered and the range on the VIN
pin is –0.15 V to VDD + 0.15 V. When it is tied high, VIN is buffered and the range on the VIN pin
is restricted to 0.1 V to VDD – 0.2 V.
*Note that the SOT-23 and microSOIC packages have different pinouts.
ORDERING GUIDE
Package
Option
Branding
Information
Model
Temperature Range
Package Description
AD7740KRM
AD7740YRT
AD7740YRM
0°C to 85°C
–40°C to +105°C
–40°C to +105°C
microSOIC Package
SOT-23 Package
microSOIC Package
RM-8
RT-8
RM-8
VOK
VOY
VOY
–4–
REV. 0
AD7740
TERMINOLOGY
POWER SUPPLY REJECTION RATIO (PSRR)
INTEGRAL NONLINEARITY
This indicates how the apparent input voltage of the VFC is
affected by changes in the supply voltage. The input voltage is
kept constant at 2 V, VREF is 2.5 V and the VDD supply is varied
Ϯ10% at 3.3 V and 5% at 5 V. The ratio of the apparent change
in input voltage to the change in VDD is measured in dBs.
For the VFC, Integral Nonlinearity (INL) is a measure of the maxi-
mum deviation from a straight line passing through the actual
endpoints of the VFC transfer function. The error is expressed in
% of the actual frequency span:
Frequency Span = FOUT(max) – FOUT(min)
OUTPUT
FREQUENCY
FOUT
OFFSET ERROR
0.9 f
CLKIN
Ideally, the output frequency for 0 V input voltage is 10% of
fCLKIN in unbuffered mode. The deviation from this value referred
to the input is the offset error at BUF = 0. In buffered mode the
minimum output frequency (corresponding to 0.10 V minimum
input voltage) is 13.2% of fCLKIN at VREF = 2.5 V. The deviation
from this value referred to the input is the offset error at BUF = 1.
Offset error is expressed in mV.
GAIN ERROR
IDEAL
WITH OFFSET
ERROR ONLY
WITH OFFSET
ERROR AND
GAIN ERROR
GAIN ERROR
0.1
CLKIN
f
This is a measure of the span error of the VFC. The gain is the
scale factor that relates the input VIN to the output FOUT.
The gain error is the deviation in slope of the actual VFC transfer
characteristic from the ideal expressed as a percentage of the full-
scale span. See Figure 2.
INPUT
VOLTAGE
VIN
0
OFFSET
ERROR
REFIN
Figure 2. Offset and Gain
OFFSET ERROR DRIFT
This is a measure of the change in Offset Error with changes in
temperature. It is expressed in µV/°C.
GAIN ERROR DRIFT
This is a measure of the change in Gain Error with changes in
temperature. It is expressed in (ppm of span)/°C.
REV. 0
–5–
AD7740–Typical Performance Characteristics
0.1
0.015
–4
V
= 5V
VDD = 5V
REFIN = 2.5V
CLKIN = 1MHz
DD
REFIN = 2.5V
= 25ꢀC
BUFFER
OFF
0.01
T
A
0.05
T
= 25ꢀC
–5
–6
A
0.005
0
BUFFER OFF
BUFFER ON
BUFFER ON
0
–0.05
–0.1
–0.005
–0.01
–0.015
BUFFER ON
–7
–8
V
= 5V
DD
BUFFER OFF
REFIN = 2.5V
T
= 25ꢀC
A
1
1.5
2.5
–0.5
0
0.5
2
0
200
400
600
800
1000
600
200
400
800
1000
0
VIN – V
CLKIN FREQUENCY – kHz
CLKIN FREQUENCY – kHz
TPC 1. INL vs. VIN (Buffered and
Unbuffered)
TPC 2. Offset Error vs. CLKIN
(Buffered and Unbuffered)
TPC 3. Gain Error vs. CLKIN
(Buffered and Unbuffered)
–50
–60
–70
–80
12
8
0.08
1.25
1
BUFFER OFF
REFIN = 2.5V
CLKIN = 1MHz
T
= 25ꢀC
GAIN ERROR
0.04
0
A
BUFFER ON
BUF = 0
BUFFER ON
0.75
0.5
0.25
0
4
GAIN ERROR
BUFFER OFF
VDD = 5V
0
–4
–8
–0.04
–0.08
–0.12
VDD = 5V
REFIN = 4.75V
CLKIN = 1MHz
REFIN = 5V
OFFSET ERROR
T
= 25ꢀC
A
C
C
= 43pF
FOUT
CLKOUT
T
= 25ꢀC
= 22pF
1000
800
A
0
–1
0
2
3
200
400
600
0
3
4
5
6
1
4
5
VDD – V
VIN – V
CLKIN FREQUENCY – kHz
TPC 6. IDD vs. CLKIN (Buffered and
Unbuffered)
TPC 4. Offset and Gain Error vs. VDD
TPC 5. PSRR vs. VIN (Buffered and
Unbuffered)
2.520
T
= 25ꢀC
A
2.515
2.510
2.505
2.500
FOUT
1
VDD = 5V
REFIN = 5V
= 25ꢀC
T
A
CLKIN ꢂ 1 MHz
CLKIN
2
CH1 2.00V CH2 2.00V M 2.00ꢁs
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD – V
TPC 7. REFOUT vs. VDD
TPC 8. Typical FOUT Pulse Train
(VIN = VREF/4)
–6–
REV. 0
AD7740
GENERAL DESCRIPTION
VFC Modulator
The AD7740 is a CMOS synchronous Voltage-to-Frequency
Converter (VFC) which uses a charge-balance conversion
technique. The input voltage signal is applied to a proprietary
front-end based around an analog modulator which converts the
input voltage into an output pulse train.
The analog input signal to the AD7740 is continuously sampled
by a switched capacitor modulator whose sampling rate is set
by a master clock. The input signal may be buffered on-chip
(BUF = 1) before being applied to the sampling capacitor of the
modulator. This isolates the sampling capacitor charging currents
from the analog input pin.
The part also contains an on-chip 2.5 V bandgap reference and
operates from a single 3.3 V or 5 V supply. A block diagram of
the AD7740 is shown in Figure 3.
This system is a negative feedback loop that acts to keep the net
charge on the integrator capacitor at zero, by balancing charge
injected by the input voltage with charge injected by VREF. The
output of the comparator provides the digital input for the 1-bit
DAC, so that the system functions as a negative feedback loop
that acts to minimize the difference signal. See Figure 5.
INTEGRATOR
COMPARATOR
FOUT
SWITCHED
CAPS
VIN
SWITCHED
CAPS
CLK
AD7740
INTEGRATOR
GND
BUF
COMPARATOR
INPUT
Figure 3. Block Diagram
Input Amplifier Buffering and Voltage Range
1-BIT
BITSTREAM
The analog input VIN can be buffered by setting BUF = 1. This
presents a high impedance, typically 100 MΩ, which allows
significant external source impedances to be tolerated. The VIN
voltage range is now 0.1 V to VDD – 0.2 V. By setting BUF = 0
the AD7740 input circuit accepts an analog input below GND
and the analog input VIN has a voltage range from –0.15 V to
VDD + 0.15 V. In this case the input impedance is typically
650 kΩ.
AD7740
+V
REF
–V
REF
Figure 5. Modulator Loop
The digital data that represents the analog input voltage is con-
tained in the duty cycle of the pulse train appearing at the output
of the comparator. The output is a pulse train whose frequency
depends on the analog input signal. A full-scale input gives an
output frequency of 0.9 fCLKIN and zero-scale input gives an
output frequency of 0.1 fCLKIN. The output allows simple inter-
facing to either standard logic families or opto-couplers. The
pulsewidth of FOUT is fixed and is determined by the high period
of CLKIN. The pulse is synchronized to the rising edge of the
clock signal. The delay time between the edge of CLKIN and the
edge of FOUT is typically 35 ns. Figure 6 shows the waveform
of this frequency output. (See TPC 8.)
The transfer function for the AD7740 is represented by:
FOUT = 0.1 fCLKIN + 0.8 (VIN/VREF) fCLKIN
It is shown in Figure 4 for unbuffered mode.
OUTPUT
FREQUENCY
FOUT
FOUT MAX
0.90 f
CLKIN
AD7740
f
CLKIN
FOUT = f
CLKIN
/2
/2
VIN = V
REF
0.10 f
CLKIN
FOUT = f
VIN = V
/5
/8
CLKIN
FOUT MIN
–0.15V
INPUT
REF
VOLTAGE
V
0
VIN
V
+ 0.15V
REF
REF
FOUT = f
CLKIN
ꢃ 3/10
/4
Figure 4. Transfer Function
VIN = V
REF
Sample Calculation:
VREF = 2.5 V, BUF = 0
3tCLKIN
AVERAGE FOUT IS f
4tCLKIN
ꢃ 3/10 BUT THE ACTUAL PULSE STREAM VARIES
CKLIN
/3 and f
FOUT (min) = 0.1 fCLKIN + 0.8(–0.15/2.5) fCLKIN
= 0.052 fCLKIN
BETWEEN f
CKLIN
/4
CKLIN
Figure 6. Frequency Output Waveforms
FOUT (max) = 0.1 fCLKIN + 0.8(2.65/2.5) fCLKIN
= 0.948 fCLKIN
If there is a step change in input voltage, there is a settling time
that must elapse before valid data is obtained. This is typically
two CLKIN cycles.
REV. 0
–7–
AD7740
Clock Generation
Reference Input
As distinct from the asynchronous VFCs that rely on the
stability of an external capacitor to set their full-scale frequency,
the AD7740 uses an external clock to define the full-scale output
frequency. The result is a more stable transfer function, which
allows the designer to determine the system stability and drift
based upon the selected external clock.
The AD7740 performs conversions relative to the applied refer-
ence voltage. This reference may be taken from the internal 2.5 V
bandgap reference by leaving REFIN/OUT unconnected. Alterna-
tively an external precision reference may be used. This is
connected to the REFIN/OUT pin, overdriving the internal
reference. Drive capability, initial error, noise, and drift charac-
teristics should be considered when selecting an external refer-
ence. The AD780 and REF192 are suitable choices for external
references.
The AD7740 requires a master clock input, which may be an
external CMOS-compatible clock signal applied to the CLKIN
pin (CLKOUT not used). For frequencies greater than 500 kHz,
a crystal or resonator can be connected between CLKIN and
CLKOUT so that the clock circuit functions as a crystal con-
trolled oscillator. Figure 7 shows a simple model of this.
The internal reference is most suited to applications where
ratiometric operation of the signal source is possible. Using the
internal reference in systems where the signal source varies with
time, temperature, loading, etc., tends to cancel out errors.
ON-CHIP
CIRCUITRY
Power-Down Mode
When CLKIN is inactive low for 1 ms (typ), the AD7740 auto-
matically enters a power-down mode. In this mode most of the
digital and analog circuitry is shut down and REFOUT floats.
FOUT goes high. This reduces the power consumption to 525 µW
max (5 V) and 360 µW (3.3 V).
5Mꢄ
CLKIN
C1
CLKOUT
OFF-CHIP
CIRCUITRY
C2
APPLICATIONS
Figure 7. On-Chip Oscillator
The basic connection diagram for the part is shown in Figure 8.
In the connection diagram shown, the AD7740 is configured in
unbuffered mode. The 5 V power supply is used as a reference to
the AD7740. A quartz crystal provides the master clock source
for the part. It may be necessary to connect capacitors (C1 and
C2 in the diagram) to the crystal to ensure that it does not oscil-
late at overtones of its fundamental operating frequency. The
values of capacitors will vary depending on the manufacturer’s
specifications.
Using the part with a crystal or ceramic resonator between the
CLKIN and CLKOUT pins generally causes more current to
be drawn from VDD than when the part is clocked from a driven
clock signal at the CLKIN pin. This is because the on-chip
oscillator is active in the case of the crystal or resonator. The
amount of additional current depends on a number of factors.
First, the larger the value of the capacitor on CLKIN and
CLKOUT pins, the larger the current consumption. Typical
values recommended by the crystal and resonator manufacturers
are in the range of 30 pF to 50 pF. Another factor that influ-
ences IDD is Effective Series Resistance of the crystal (ESR).
The lower the ESR value, the lower the current taken by the
oscillator circuit.
5V
0.1ꢁF
10ꢁF
VDD
The on-chip oscillator also has a start-up time associated with it
before it oscillates at its correct frequency and voltage levels. The
typical start-up time is 10 ms with a VDD of 5 V and 15 ms with
a VDD of 3.3 V (both with a 1 MHz crystal).
REFIN
FOUT
GND
VIN
AD7740
CLKIN
The AD7740 master clock appears inverted on the CLKOUT
pin of the device. The maximum recommended load on this pin is
one CMOS load. When using a crystal to generate the AD7740’s
clock it may be desirable to then use this clock as the clock
source for the entire system. In this case, it is recommended that
the CLKOUT signal be buffered with a CMOS buffer before
being applied to the rest of the circuit (as shown in Figure 7).
BUF
CLKOUT
C1
C2
Figure 8. Basic Connection Diagram
REV. 0
–8–
AD7740
A/D Conversion Techniques Using the AD7740
Since TGATE × FOUTMAX = number of counts at full scale, the
fastest conversion for a given resolution can be performed with
the highest CLKIN frequency.
One method of using a VFC in an A/D system is to count the
output pulses of FOUT for a fixed gate interval (see Figure 9).
This fixed gate interval should be generated by dividing down
the clock input frequency. This ensures that any errors due to
clock jitter or clock frequency drift are eliminated. The ratio of
the FOUT frequency to the clock frequency is what is important
here, not the absolute value of FOUT. The frequency divi-
sion can be done by a binary counter where CLKIN is the
counter input.
If the output frequency is measured by counting pulses gated to
a signal derived from the clock, the clock stability is unimportant
and the device simply performs as a voltage-controlled frequency
divider, producing a high-resolution ADC. The inherent mono-
tonicity of the transfer function and wide range of input clock
frequencies allows the conversion time and resolution to be
optimized for specific applications.
Figure 10 shows the waveforms of CLKIN, FOUT, and the
Gate signal. A counter counts the rising edges of FOUT while the
Gate signal is high. Since the gate interval is not synchronized with
FOUT, there is a possibility of a counting inaccuracy. Depending
on FOUT, an error of one count may occur.
Another parameter is taken into account when choosing the
length of the gate interval. Because the integration period of the
VFC is equal to the gate interval, any interfering signal can be
rejected by counting for an integer number of periods of the
interfering signal. For example, a gate interval of 100 ms will
give normal-mode rejection of 50 Hz and 60 Hz signals.
FOUT
Isolation Applications
TO ꢁP
COUNTER
VIN
AD7740
The AD7740 can also be used in isolated analog signal trans-
mission applications. Due to noise, safety requirements or distance,
it may be necessary to isolate the AD7740 from any controlling
circuitry. This can easily be achieved by using opto-isolators.
This is extremely useful in overcoming ground loops between
equipment.
CLKIN
GATE
SIGNAL
FREQUENCY
DIVIDER
CLOCK
GENERATOR
The analog voltage to be transmitted is converted to a pulse
train using the VFC. An opto-isolator circuit is used to couple
this pulse train across an isolation barrier using light as the
connecting medium. The input LED of the isolator is driven
from the output of the AD7740. At the receiver side, the output
transistor is operated in the photo-transistor mode. The pulse
train can be reconverted to an analog voltage using a frequency-
to-voltage converter; alternatively, the pulse train can be fed into
a counter to generate a digital signal.
Figure 9. A/D Conversion Using the AD7740 VFC
CLKIN
FOUT
The analog and digital sections of the AD7740 have been designed
to allow operation from a single-ended power source, simplify-
ing its use with isolated power supplies.
GATE
tGATE
Figure 10. Waveforms in an A/D Converter Using a VFC
Figure 11 shows a general purpose VFC circuit using a low cost
opto-isolator. A 5 V power supply is assumed for both the iso-
lated (VDD) and local (VCC) supplies.
The clock frequency and the gate time determine the resolution
of such an ADC. If 12-bit resolution is required and CLKIN is
1 MHz (therefore, FOUTMAX is 0.9 MHz), the minimum gate
time required is calculated as follows:
V
CC
V
DD
0.1ꢁF
10ꢁF
N counts at Full Scale (0.9 MHz) will take
(N/0.9 × 106) seconds = minimum gate time
R
N is the total number of codes for a given resolution; 4096 for
12 bits.
OPTOCOUPLER
minimum gate time = (4096/0.9 × 106) seconds = 4.551 ms
AD7740
GND1
VIN
FOUT
ISOLATION
BARRIER
GND2
Figure 11. Opto-Isolated Application
REV. 0
–9–
AD7740
Temperature Sensor Application
Power Supply Bypassing and Grounding
The AD7740 can be used with an AD22100S temperature
sensor to give a digital measure of ambient temperature. The
output voltage of the AD22100S is proportional to the tempera-
ture times the supply voltage. It uses a single 5 V supply, and its
output swings from 0.25 V at –50°C to 4.75 V at +150°C. By
feeding its output through the AD7740, the value of ambient
temperature is converted into a digital pulse train. See Figure 12.
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board housing the
AD7740 should be designed such that the analog and digital
sections are separated and confined to certain areas of the board.
To minimize capacitive coupling between them, digital and
analog ground planes should only be joined in one place, close
to the AD7740, and should not overlap.
5V
Avoid running digital lines under the device, as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7740 to avoid noise coupling. The power
supply lines to the AD7740 should use as large a trace as pos-
sible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals like
clocks should be shielded with digital ground to avoid radiating
noise to other parts of the board, and clock signals should never
be run near analog inputs. Avoid crossover of digital and analog
signals. Traces on opposite sides of the board should run at right
angles to each other. This reduces the effect of feedthrough
through the board. A microstrip technique is by far the best but
is not always possible with a double-sided board. In this technique,
the component side of the board is dedicated to the ground plane
while the signal traces are placed on the solder side.
0.1ꢁF
10ꢁF
0.1ꢁF
VDD
V+
REFIN
AD22100S
FOUT
BUF
VIN
AD7740
GND
CLKIN CLKOUT
C1
C2
Figure 12. Using the AD7740 with a Temperature Sensor
Good decoupling is also important. All analog supplies should
be decoupled to GND with surface mount capacitors, 10 µF in
parallel with 0.1 µF located as close to the package as possible,
ideally right up against the device. The lead lengths on the by-
pass capacitor should be as short as possible. It is essential that
these capacitors be placed physically close to the AD7740 to
minimize the inductance of the PCB trace between the capacitor
and the supply pin. The 10 µF are the tantalum bead type and
are located in the vicinity of the VFC to reduce low-frequency
ripple. The 0.1 µF capacitors should have low Effective Series
Resistance (ESR) and Effective Series Inductance (ESI), such
as the common ceramic types, which provide a low imped-
ance path to ground at high frequencies to handle transient
currents due to internal logic switching. Additionally, it is ben-
eficial to have large capacitors (> 47 µF) located at the point
where the power connects to the PCB.
Due to its ratiometric nature this application provides an
extremely cost-effective solution. The need for an external pre-
cision reference is eliminated since the 5 V power-supply is used
as a reference to both the VFC and the AD22100S.
32 kHz Operation
The AD7740 oscillator circuit will not operate at 32 kHz. If
the user wishes to use a 32 kHz watch crystal, some additional
external circuitry is required. The circuit in Figure 13 is for a
crystal with a required drive of 1 µW. Resistors R1 and R2 re-
duce the power to this level.
R3
1Mꢄ
40106
40106
CLKIN
R1
220kꢄ
R2
100kꢄ
32kHz
Figure 13. 32 kHz Watch Crystal Circuit
–10–
REV. 0
AD7740
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead microSOIC
(RM-8)
0.122 (3.10)
0.114 (2.90)
8
5
4
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
1
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
33ꢀ
0.018 (0.46)
0.008 (0.20)
27ꢀ
0.028 (0.71)
0.016 (0.41)
0.011 (0.28)
0.003 (0.08)
SEATING
PLANE
8-Lead SOT-23
(RT-8)
0.122 (3.10)
0.110 (2.80)
8
1
7
2
6
3
5
4
0.071 (1.80)
0.059 (1.50)
PIN 1
0.026 (0.65) BSC
0.077 (1.95)
BSC
0.051 (1.30)
0.035 (0.90)
0.057 (1.45)
0.035 (0.90)
10ꢀ
0ꢀ
0.015 (0.38)
0.009 (0.22)
0.022 (0.55)
0.014 (0.35)
0.006 (0.15)
0.000 (0.00)
SEATING
PLANE
0.009 (0.23)
0.003 (0.08)
REV. 0
–11–
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