AD7723 [ADI]
16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC; 16位， 1.2 MSPS CMOS ， Σ-Δ ADC
| 型号： | AD7723 |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| 文件： | 总23页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, 1.2 MSPS
a
CMOS, Sigma-Delta ADC
AD7723
FEATURES
FUNCTIONAL BLOCK DIAGRAM
16-Bit Sigma-Delta ADC
1.2 MSPS Output Word Rate
32/16
؋
Oversampling Ratio Low-Pass and Band-Pass Digital Filter
Linear Phase
REF2
REF1
2.5V
REFERENCE
AV
DD
AD7723
AGND
DV
DD
VIN(+)
VIN(–)
FIR
FILTER
MODULATOR
On-Chip 2.5 V Voltage Reference
Standby Mode
DGND
Flexible Parallel or Serial Interface
Crystal Oscillator
Single +5 V Supply
XTAL_OFF
XTAL
UNI
HALF_PWR
XTAL
CLOCK
CLKIN
STBY
MODE 1
DGND/DB15
DGND/DB14
MODE 2
SCR/DB13
SLDR/DB12
SLP/DB11
TSI/DB10
FSO/DB9
SYNC
DV /CS
DD
CONTROL
LOGIC
CFMT/RD
DGND/DRDY
DGND/DB0
DOE/
DB4
DGND/ DGND/ DGND/
DB1 DB2 DB3
SFMT/ FSI/ SCO/ SDO/
DB5 DB6 DB7 DB8
The part provides an on-chip 2.5 V reference. Alternatively, an
external reference can be used.
GENERAL DESCRIPTION
The AD7723 is a complete 16-bit, sigma-delta ADC. The part
operates from a +5 V supply. The analog input is continuously
sampled, eliminating the need for an external sample-and-hold.
The modulator output is processed by a finite impulse response
(FIR) digital filter. The on-chip filtering combined with a high
oversampling ratio reduces the external antialias requirements
to first order in most cases. The digital filter frequency response
can be programmed to be either low pass or band pass.
A power-down mode reduces the idle power consumption to
200 µW.
The AD7723 is available in a 44-lead PQFP package and is
specified over the industrial temperature range from –40°C to
+85°C.
Two input modes are provided, allowing both unipolar and
bipolar input ranges.
The AD7723 provides 16-bit performance for input bandwidths
up to 460 kHz at an output word rate up to 1.2 MHz. The
sample rate, filter corner frequencies and output word rate are
set by the crystal oscillator or external clock frequency.
Data can be read from the device in either serial or parallel
format. A stereo mode allows data from two devices to share a
single serial data line. All interface modes offer easy, high speed
connections to modern digital signal processors.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
(AVDD = DVDD = +5 V ؎ 5%; AGND = AGND1 = AGND2 = DGND = 0 V;
fCLKIN = 19.2 MHz; REF2 = 2.5 V; TA = TMIN to TMAX; unless otherwise noted)
AD7723–SPECIFICATIONS1
B Version
Parameter
Test Conditions/Comments
Min
Typ
Max
Units
DYNAMIC SPECIFICATIONS2, 3
HALF_PWR = 0 or 1
f
CLKIN = 10 MHz When HALF-PWR = 1
Decimate by 32
Bipolar Mode
Signal to Noise
Full Power
2.5 V Reference
3 V Reference
87
88.5
86.5
90
91
89
–96
dB
dB
dB
dB
dB
dB
Half Power
Total Harmonic Distortion4
Spurious Free Dynamic Range4
–90
–92
–90
2.5 V Reference
3 V Reference
Unipolar Mode
Signal to Noise
87
–89
–90
dB
dB
dB
Total Harmonic Distortion4
Spurious Free Dynamic Range4
Bandpass Filter Mode
Bipolar Mode
Signal to Noise
76
79
dB
Decimate by 16
Bipolar Mode
Signal to Noise
Measurement Bandwidth = 0.383 × FO
2.5 V Reference
82
83
78
86
87
81.5
dB
dB
dB
dB
dB
dB
dB
3 V Reference
Measurement Bandwidth = 0.5 × FO
2.5 V Reference
3 V Reference
2.5 V Reference
Signal to Noise
Total Harmonic Distortion4
–88
–86
–90
–88
Spurious Free Dynamic Range4
3 V Reference
Unipolar Mode
Signal to Noise
Measurement Bandwidth = 0.383 × FO
Measurement Bandwidth = 0.5 × FO
84
81
–89
dB
dB
dB
Signal to Noise
Total Harmonic Distortion4
DIGITAL FILTER RESPONSE
Low Pass Decimate by 32
0 kHz to fCLKIN/83.5
±0.001
dB
dB
dB
dB
f
f
f
CLKIN/66.9
CLKIN/64
CLKIN/51.9 to fCLKIN/2
–3
–6
–90
Group Delay
Settling Time
1293/2fCLKIN
1293/fCLKIN
Low Pass Decimate by 16
0 kHz to fCLKIN/41.75
±0.001
dB
dB
dB
dB
f
f
f
CLKIN/33.45
CLKIN/32
CLKIN/25.95 to fCLKIN/2
–3
–6
–90
Group Delay
Settling Time
541/2fCLKIN
541/fCLKIN
Band Pass Decimate by 32
f
f
f
CLKIN/51.90 to fCLKIN/41.75
CLKIN/62.95, fCLKIN/33.34
CLKIN/64, fCLKIN/32
±0.001
dB
dB
dB
dB
–3
–6
0 kHz to fCLKIN/83.5, fCLKIN/25.95 to fCLKIN/2
Group Delay
Settling Time
–90
1293/2fCLKIN
1293/fCLKIN
Output Data Rate, FO
Decimate by 32
Decimate by 16
fCLKIN/32
fCLKIN/16
ANALOG INPUTS
Full-Scale Input Span
Bipolar Mode
Unipolar Mode
VIN(+) – VIN(–)
±4/5 × VREF2
8/5 × VREF2
V
V
0
–2–
REV. 0
AD7723
B Version
Typ
Parameter
Test Conditions/Comments
Min
Max
Units
ANALOG INPUTS (Continued)
Absolute Input Voltage
Input Sampling Capacitance
Input Sampling Rate, fCLKIN
VIN(+) and/or VIN(–)
AGND
AVDD
19.2
V
pF
MHz
2
CLOCK
CLKIN Duty Ratio
45
55
%
REFERENCE
REF1 Output Resistance
Using Internal Reference
REF2 Output Voltage
REF2 Output Voltage Drift
Using External Reference
REF2 Input Impedance
REF2 External Voltage Range
3
kΩ
2.39
2.54
60
2.69
V
ppm/°C
REF1 = AGND
4
2.5
kΩ
V
1.2
16
3.15
STATIC PERFORMANCE
Resolution
Bits
Differential Nonlinearity
Integral Nonlinearity
DC CMRR
Guaranteed Monotonic
±0.5
±2
80
±1
LSB
LSB
dB
Offset Error
±20
±0.5
mV
% FSR
Gain Error 5
LOGIC INPUTS (Excluding CLKIN)
VINH, Input High Voltage
VINL, Input Low Voltage
2.0
3.8
V
V
0.8
0.4
CLOCK INPUT (CLKIN)
VINH, Input High Voltage
V
V
VINL, Input Low Voltage
ALL LOGIC INPUTS
I
IN, Input Current
VIN = 0 V to DVDD
±10
µA
CIN, Input Capacitance
10
pF
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
|IOUT| = 200 µA
|IOUT| = 1.6 mA
4.0
V
V
0.4
POWER SUPPLIES
AVDD
IAVDD
4.75
4.75
5.25
60
33
5.25
35
20
V
HALF_PWR = Logic Low
HALF_PWR = Logic High
50
25
mA
mA
V
mA
mA
µW
DVDD
IDVDD
HALF_PWR = Logic Low
HALF_PWR = Logic High
Standby Mode
25
15
Power Consumption6
NOTES
200
1Operating temperature range is as follows: B Version: –40°C to +85°C.
2Typical values for SNR apply for parts soldered directly to a printed circuit board ground plane.
3Dynamic specifications apply for input signal frequencies from dc to 0.0240 × fCLKIN in decimate by 16 mode and from dc to 0.0120 × fCLKIN in decimate by 32 mode.
4When using the internal reference, THD and SFDR specifications apply only to input signals above 10 kHz with a 10 µF decoupling capacitor between REF2 and
AGND2. At frequencies below 10 kHz, THD degrades to 84 dB and SFDR degrades to 86 dB.
5Gain Error excludes Reference Error.
6CLKIN and digital inputs static and equal to 0 or DVDD
.
Specifications subject to change without notice.
REV. 0
–3–
AD7723
(AVDD = DVDD = +5 V ؎ 5%; AGND = AGND1 = DGND = 0 V; fCLKIN = 19.2 MHz; CL = 50 pF; SFMT =
Logic Low or High, CFMT = Logic Low or High; TA = TMIN to TMAX unless otherwise noted)
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Units
CLKIN Frequency
FCLK
t1
t2
t3
t4
1
19.2
1
0.55 × t1
0.55 × t1
MHz
µs
CLKIN Period (tCLK = 1/fCLK
CLKIN Low Pulsewidth
CLKIN High Pulsewidth
CLKIN Rise Time
)
0.052
0.45 × t1
0.45 × t1
5
5
ns
ns
CLKIN Fall Time
t5
FSI Setup Time
t6
t7
t8
t9
t10
t10
t11
t12
t13
t14
t15
t16
0
0
5
5
1
40
ns
ns
tCLK
ns
tCLK
tCLK
ns
FSI Hold Time
FSI High Time1
CLKIN to SCO Delay
SCO Period2, SCR = 1
SCO Period2, SCR = 0
SCO Transition to FSO High Delay
SCO Transition to FSO Low Delay
SCO Transition to SDO Valid Delay
SCO Transition from FSI3
25
2
1
0
0
5
60
5
5
5
ns
ns
12
tCLK + t2
20
SDO Enable Delay Time
SDO Disable Delay Time
ns
ns
5
20
DRDY High Time2
t17
t18
t19
t20
t21
t22
t23
t24
2
tCLK
tCLK
ns
ns
ns
ns
ns
ns
Conversion Time2 (Refer to Tables I and II)
CLKIN to DRDY Transition
CLKIN to DATA Valid
16/32
35
20
50
35
CS/RD Setup Time to CLKIN
CS/RD Hold Time to CLKIN
Data Access Time
0
20
20
20
35
35
Bus Relinquish Time
SYNC Input Pulsewidth
t25
t26
t27
t28
1
0
tCLK
ns
ns
SYNC Low Time before CLKIN Rising
DRDY High Delay after Rising SYNC
DRDY Low Delay after SYNC Low
25
35
2049
tCLK
NOTES
1FSO pulses are gated by the release of FSI (going low).
2Guaranteed by design.
3Frame Sync is initiated on the falling edge of CLKIN.
Specifications subject to change without notice.
I
OL
1.6mA
TO
OUTPUT
PIN
+1.6V
C
L
50pF
I
OH
200A
Figure 1. Load Circuit for Timing Specifications
–4–
REV. 0
AD7723
t5
t4
t2
2.3V
CLKIN
FSI
0.8V
t3
t1
t7
t6
t8
t9
SCO
t9
t10
Figure 2. Serial Mode Timing for Clock Input, Frame Sync Input and Serial Clock Output
32 CLKIN CYCLES
CLKIN
t8
FSI
(SFMT = 1)
t14
SCO
(CFMT = 0)
t11
FSO
(SFMT = 0)
t11
t12
FSO
(SFMT = 1)
t13
D15
D14
D13
D2
D1
D0
D15
D14
SDO
Figure 3. Serial Mode 1. Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output and Serial Data Output
(Refer to Table I for Control Inputs, TSI = DOE)
32 CLKIN CYCLES
CLKIN
t8
FSI
t14
SCO
(CFMT = 0)
t11
t12
FSO
t13
SDO
D2
D1
D0
D15
D14
D13
D12
D11
D3
D2
D1
D0
D15
D14
D5
D4
Figure 4. Serial Mode 2. Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output and Serial Data Output
(Refer to Table I for Control Inputs, TSI = DOE)
REV. 0
–5–
AD7723
16 CLKIN CYCLES
CLKIN
FSI
t8
t14
SCO
(CFMT = 0)
t11
t12
FSO
SDO
t13
D2
D1
D0
D15
D14
D13
D12
D11
D5
D4
D3
D2
D1
D0
D15
D14
Figure 5. Serial Mode 3. Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output and Serial Data Output
(Refer to Table I for Control Inputs, TSI = DOE)
Table I. Serial Interface (Mode1 = 0, Mode2 = 0)
Decimation
Serial Mode Ratio (SLDR) Mode (SLP)
Digital Filter SCO Frequency Output Data
Control Inputs
SLDR SLP SCR
(SCR)
Rate
1
1
2
2
3
32
32
32
32
16
Low Pass
Band Pass
Low Pass
Band Pass
Low Pass
fCLKIN
fCLKIN
fCLKIN/2
fCLKIN/2
fCLKIN
fCLKIN/32
fCLKIN/32
fCLKIN/32
fCLKIN/32
fCLKIN/16
1
1
1
1
0
1
0
1
0
1
0
0
1
1
0
Table II. Parallel Interface
Digital Filter Decimation Output
Control Inputs
Mode
Ratio
Data Rate
MODE1 MODE2
Band Pass
Low Pass
Low Pass
32
32
16
fCLKIN/32
fCLKIN/32
fCLKIN/16
0
1
1
1
0
1
DOE
t16
t15
SDO
Figure 6. Serial Mode Timing for Data Output Enable and Serial Data Output
–6–
REV. 0
AD7723
t18
CLKIN
DRDY
t19
t19
t17
t20
WORD N
DB0–DB15
WORD N – 1
WORD N + 1
Figure 7a. Parallel Mode Read Timing, CS and RD Tied Logic Low
CLKIN
t18
t19
DRDY
t19
t22
RD/CS
t21
t22
t21
t24
DB0–DB15
VALID DATA
t23
Figure 7b. Parallel Mode Read Timing, CS = RD
t
28
CLKIN
t
26
SYNC
t
25
DRDY
t
27
Figure 8. SYNC Timing
REV. 0
–7–
AD7723
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
(TA = +25°C unless otherwise noted)
Temperature
Range
Package
Description
Package
Option
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD, AVDD1 to AGND . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD, AVDD1 to DVDD . . . . . . . . . . . . . . . . . . . –1 V to +1 V
AGND, AGND1 to DGND . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Inputs to DGND . . . . . . . . . –0.3 V to DVDD + 0.3 V
Digital Outputs to DGND . . . . . . . . –0.3 V to DVDD + 0.3 V
VIN(+), VIN(–) to AGND . . . . . . . . –0.3 V to AVDD + 0.3 V
REF1 to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
REF2 to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range . . . . . . . . . . – 40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 95°C/W
Lead Temperature, Soldering
Model
AD7723BS –40°C to +85°C Plastic Quad Flatpack S-44
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7723 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
44-Lead PQFP Package
44 43 42 41 40 39 38 37 36 35 34
1
2
33
32
31
30
29
28
27
DGND/DB2
DGND/DB1
DGND/DB0
SCR/DB13
PIN 1
IDENTIFIER
DGND/DB14
DGND/DB15
3
4
CFMT/RD
DGND/DRDY
DGND
DV /CS
DD
5
SYNC
DGND
STBY
AD7723
6
TOP VIEW
(Not to Scale)
7
MODE2
8
26 AV
MODE1
AGND1
AGND1
DD
9
25 AGND
10
11
24
23
UNI
REF2
AV
DD1
12 13 14 15 16 17 18 19 20 21 22
–8–
REV. 0
AD7723
PIN FUNCTION DESCRIPTIONS
Mnemonic
Pin No.
Description
AVDD1
AGND1
AVDD
AGND
AGND2
DVDD
11
Digital Logic Power Supply Voltage for the Analog Modulator.
Digital Logic Power Supply Ground for the Analog Modulator.
Positive Power Supply Voltage for the Analog Modulator.
Power Supply Ground for the Analog Modulator.
Power Supply Ground Return to the Reference Circuitry, REF2, of the Analog Modulator.
Digital Power Supply Voltage; +5 V ± 5%.
9, 10
17, 26
16, 18, 25
22
39
DGND
REF1
6, 28
21
Ground Reference for Digital Circuitry.
Reference Output. REF1 connects through 3 kΩ to the output of the internal 2.5 V reference and to
a buffer amplifier that drives the Σ−∆ modulator.
REF2
23
Reference Input. REF2 connects to the output of an internal buffer amplifier that drives the Σ−∆
modulator. When REF2 is used as an input, REF1 must be connected to AGND to disable the inter-
nal buffer amplifier.
VIN(+)
VIN(–)
UNI
20
19
24
Positive Terminal of the Differential Analog Input.
Negative Terminal of the Differential Analog Input.
Analog Input Range Select Input. The UNI pin selects the analog input range for either bipolar or unipo-
lar operation. A logic high input selects unipolar operation and a logic low selects bipolar operation.
CLKIN
12
Clock Input. An external clock source can be applied directly to this pin with XTAL_OFF tied high.
Alternatively, a parallel resonant fundamental frequency crystal, in parallel with a 1 MΩ resistor can
be connected between the XTAL pin and the CLKIN pin with XTAL_OFF tied low. External
capacitors are then required from the CLKIN and XTAL pins to ground. Consult the crystal
manufacturer’s recommendation for the load capacitors.
XTAL
XTAL_OFF
13
14
Input to Crystal Oscillator Amplifier. If an external clock is used, XTAL should be tied to AGND1.
Oscillator Enable Input. A logic high disables the crystal oscillator amplifier to allow use of an exter-
nal clock source. Set low when using an external crystal between the CLKIN and XTAL pins.
MODE1/2
HALF_PWR
SYNC
8, 7
15
Mode Control Inputs. The MODE1 and MODE2 pins choose either parallel or serial data interface
operation and select the operating mode for the digital filter in parallel mode. Refer to Tables I and II.
When set high, the power dissipation is reduced by approximately one-half and a maximum CLKIN
frequency of 10 MHz applies.
Synchronization Logic Input. When using more than one AD7723, operated from a common master
clock, SYNC allows each ADC to simultaneously sample its analog input and update its output
register. A rising edge resets the AD7723 digital filter sequencer counter to zero. When the rising
edge of CLKIN senses a logic low on SYNC, the reset state is released. Because the digital filter and
sequencer are completely reset during this action, SYNC pulses cannot be applied continuously.
29
STBY
27
Standby Logic Input. A logic high sets the AD7723 into the power-down state.
REV. 0
–9–
AD7723
PARALLEL MODE PIN FUNCTION DESCRIPTIONS
Description
Mnemonic
Pin No.
DVDD/CS
CFMT/RD
30
4
Chip Select Logic Input.
Read Logic Input. Used in conjunction with CS to read data from the parallel bus. The output data
bus is enabled when the rising edge of CLKIN senses a logic low level on RD if CS is also low. When
RD is sensed high, the output data bits, DB15–DB0 will be high impedance.
DGND/DRDY
5
Data Ready Logic Output. A falling edge indicates a new output word is available to be read from
the output data register. DRDY will return high upon completion of a read operation. If a read operation
does not occur between output updates, DRDY will pulse high for two CLKIN cycles before the next
output update. DRDY also indicates when conversion results are available after a SYNC sequence.
DGND/DB15
DGND/DB14
SCR/DB13
SLDR/DB12
SLP/DB11
TSI/DB10
FSO/DB9
SDO/DB8
SCO/DB7
FSI/DB6
SFMT/DB5
DOE/DB4
DGND/DB3
DGND/DB2
DGND/DB1
DGND/DB0
31
32
33
34
35
36
37
38
40
41
42
43
44
1
Data Output Bit, (MSB)
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit, (LSB).
2
3
–10–
REV. 0
AD7723
SERIAL MODE PIN FUNCTION DESCRIPTIONS
Description
Mnemonic
Pin No.
CFMT/RD
4
Serial Clock Format Logic Input. The clock format pin selects whether the serial data, SDO, is valid
on the rising or falling edge of the serial clock, SCO. When CFMT is logic low, serial data is valid on
the falling edge of the serial clock, SCO. If CFMT is logic high, SDO is valid on the rising edge of
SCO.
DOE/DB4
SFMT/DB5
FSI/DB6
43
42
41
Data Output Enable Logic Input. The DOE pin controls the three-state output buffer of the SDO
pin. The active state of DOE is determined by the logic level on the TSI pin. When the DOE logic
level equals the level on the TSI pin the serial data output, SDO, is active. Otherwise SDO will be
high impedance. SDO can be three-state after a serial data transmission by connecting DOE to FSO.
In normal operations, TSI and DOE should be tied low.
Serial Data Format Logic Input. The logic level on the SFMT pin selects the format of the FSO
signal for Serial Mode 1. A logic low makes the FSO output a pulse, one SCO cycle wide at the
beginning of a serial data transmission. With SFMT set to a logic high, the FSO signal is a frame
pulse that is active low for the duration of the 16-bit transmission. For Serial Modes 2 and 3, SFMT
should be tied high.
Frame Synchronization Logic Input. The FSI input is used to synchronize the AD7723 serial output
data register to an external source and to allow more than one AD7723, operated from a common
master clock, to simultaneously sample its analog input and update its output register.
SCO/DB7
SDO/DB8
40
38
Serial Clock Output.
Serial Data Output. The serial data is shifted out MSB first, synchronous with the SCO. Serial
Mode 1 data transmissions last 32 SCO cycles. After the LSB is output, trailing zeros are output for
the remaining 16 SCO cycles. Serial Modes 2 and 3 data transmissions last 16 SCO cycles.
FSO/DB9
TSI/DB10
37
36
Frame Sync Output. FSO indicates the beginning of a word transmission on the SDO pin. Depend-
ing on the logic level of the SFMT pin, the FSO signal is either a positive pulse approximately one
SCO period wide, or a frame pulse which is active low for the duration of the 16-data bit transmission.
Time Slot Logic Input. The logic level on TSI sets the active state of the DOE pin. With TSI set
logic high, DOE will enable the SDO output buffer when it is a logic high, and vice versa. TSI is
used when two AD7723s are connected to the same serial data bus. When this function is not
needed, TSI and DOE should be tied low.
SLP/DB11
35
34
Serial Mode Low Pass/Band Pass Filter Select Input. With SLP set logic high, the low-pass filter
response is selected. A logic low selects band pass.
Serial Mode Low/High Output Data Rate Select Input. With SLDR set logic high, the low data rate
is selected. A logic low selects the high data rate. The high data rate corresponds to data at the out-
put of the fourth decimation filter (Decimate by 16). The low data rate corresponds to data at the
output of the fifth decimation filter (Decimate by 32).
SLDR/DB12
SCR/DB13
33
Serial Clock Rate Select Input. With SCR set logic low, the serial clock output frequency, SCO, is
equal to the CLKIN frequency. A logic high sets it equal to one-half the CLKIN frequency.
DVDD/CS
30
32
31
5
3
2
Tie to DVDD.
DGND/DB14
DGND/DB15
DGND/DRDY
DGND/DB0
DGND/DB1
DGND/DB2
DGND/DB3
Tie to DGND.
Tie to DGND.
Tie to DGND.
Tie to DGND.
Tie to DGND.
Tie to DGND.
Tie to DGND.
1
44
REV. 0
–11–
AD7723
Integral Nonlinearity
TERMINOLOGY
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are minus full scale, a point
0.5 LSB below the first code transition (100 . . . 00 to 100 . . . 01
in bipolar mode, 000 . . . 00 to 000 . . . 01 in unipolar mode)
and plus full scale, a point 0.5 LSB above the last code transi-
tion (011 . . . 10 to 011 . . . 11 in bipolar mode, 111 . . . 10 to
111 . . . 11 in unipolar mode). The error is expressed in LSBs.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all of the nonfundamental signals up to
half the output data rate (FO/2), excluding dc. The ADC is
evaluated by applying a low noise, low distortion sine wave
signal to the input pins. By generating a Fast Fourier Transform
(FFT) plot, the SNR data can then be obtained from the out-
put spectrum.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between two adjacent codes in the ADC.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the harmonics to the rms
value of the fundamental. THD is defined as:
Common-Mode Rejection Ratio
The ability of a device to reject the effect of a voltage applied to
both input terminals simultaneously—often through variation of
a ground level—is specified as a common–mode rejection ratio.
CMRR is the ratio of gain for the differential signal to the gain
for the common-mode signal.
2
V22 +V32 +V42 +V52 +V6
THD = 20 log
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through
sixth harmonics. The THD is also derived from the FFT plot of
the ADC output spectrum.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
(10 . . . 000 to 10 . . . 001) from the ideal differential voltage
(VIN(+) – VIN(–)+ 0.5 LSB) when operating in the unipolar
mode.
Spurious Free Dynamic Range (SFDR)
Defined as the difference, in dB, between the peak spurious or
harmonic component in the ADC output spectrum (up to FO/2
and excluding dc) and the rms value of the fundamental.
Normally, the value of this specification will be determined by
the largest harmonic in the output spectrum of the FFT. For
input signals whose second harmonics occur in the stop band
region of the digital filter, the spur in the noise floor limits the
SFDR.
Bipolar Offset Error
This is the deviation of the midscale transition code (111 . . . 11
to 000 . . . 00) from the ideal differential voltage (VIN(+) –
VIN(–) – 0.5 LSB) when operating in the bipolar mode.
Gain Error
The first code transition should occur at an analog value 1/2 LSB
above –full scale. The last transition should occur for an analog
value 1 1/2 LSB below the nominal full scale. Gain error is the
deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Passband Ripple
The frequency response variation of the AD7723 in the defined
passband frequency range.
Passband Frequency
The frequency up to which the frequency response variation is
within the passband ripple specification.
Cutoff Frequency
The frequency below which the AD7723’s frequency response
will not have more than 3 dB of attenuation.
Stopband Frequency
The frequency above which the AD7723’s frequency response
will be within its stopband attenuation.
Stopband Attenuation
The AD7723’s frequency response will not have less than 90 dB
of attenuation in the stated frequency band.
–12–
REV. 0
Typical Performance Characteristics–
AD7723
(AVDD = DVDD = 5 V; TA = +25؇C; CLKIN = 19.2 MHz; External +2.5 V Reference, unless otherwise noted)
106
104
102
100
98
110
100
90
SIGNAL FREQUENCY = 98kHz
MEASUREMENT BANDWIDTH = 300kHz
SIGNAL FREQUENCY = 98kHz
MEASUREMENT BANDWIDTH = 460kHz
3RD
THD
80
SFDR
96
70
2ND
THD
94
SNR
60
92
SNR
50
90
88
–50
40
–28
–25
0
25
50
75
100
–23
–18
–13
–8
–3
2
TEMPERATURE – ؇C
ANALOG INPUT LEVEL – dB
Figure 9. SNR, THD and SFDR vs. Analog Input Level
Relative to Full Scale (Output Data Rate = 1.2 MHz)
Figure 12. SNR and THD vs. Temperature (Output Data
Rate = 600 kHz)
110
106
SIGNAL FREQUENCY = 98kHz
MEASUREMENT BANDWIDTH = 300kHz
100
104
SFDR
102
100
90
THD
THD
98
80
96
SFDR
INPUT SIGNAL = 10kHz
MEASUREMENT BANDWIDTH = 0.383
؋
OWR 94
70
92
90
SNR
60
88
SNR
50
40
86
84
–28
–23
–18
–13
–8
–3
2
100
500
1000
1500
2150
ANALOG INPUT LEVEL – dB
OUTPUT WORD RATE – kHz
Figure 13. SNR, THD and SFDR vs. Sampling Frequency
(Decimate by 16)
Figure 10. SNR, THD and SFDR vs. Analog Input Level
Relative to Full Scale (Output Data Rate = 600 kHz)
102
115
SIGNAL FREQUENCY = 98kHz
INPUT SIGNAL = 10kHz
MEASUREMENT BANDWIDTH = 0.5
؋
OWR MEASUREMENT BANDWIDTH = 460kHz
100
3RD
110
98
SFDR
2ND
THD
96
94
92
90
88
86
84
105
100
THD
95
SNR
SNR
90
–25
0
25
50
75
100
–50
50
150
450
OUTPUT WORD RATE – kHz
750
300
600
900
TEMPERATURE – ؇C
Figure 11. SNR and THD vs. Temperature (Output Data
Rate = 1.2 MHz)
Figure 14. SNR, THD and SFDR vs. Sampling Frequency
(Decimate by 32)
REV. 0
–13–
AD7723
2000
V
1800 8192 SAMPLES TAKEN
1.00
0.80
0.60
0.40
0.20
(+) = V (–)
67108864 SAMPLES TAKEN
DIFFERENTIAL MODE
IN
IN
1600
1400
1200
1000
800
0.00
–0.20
–0.40
–0.60
–0.80
–1.00
600
400
200
0
0
16384
32768
CODE
49152
65535
32700
32702
32704
32706
CODE
32708
32710 32712 32713
Figure 18. Differential Nonlinearity (Output Data
Rate = 600 kHz)
Figure 15. Histogram of Output Codes with DC Input
(Output Data Rate = 1.2 MHz)
5000
1.00
V
(+) = V (–)
IN
IN
67108864 SAMPLES TAKEN
DIFFERENTIAL MODE
4500 8192 SAMPLES TAKEN
0.80
0.60
4000
3500
3000
2500
2000
1500
1000
0.40
0.20
0.00
–0.20
–0.40
–0.60
500
0
–0.80
–1.00
32703
32704
32705
32706
CODE
32707
32708 32709 32710
0
16384
32768
CODE
49152
65535
Figure 16. Histogram of Output Codes with DC Input
(Output Data Rate = 600 kHz)
Figure 19. Integral Nonlinearity (Output Data
Rate = 1.2 MHz)
1.00
1.00
67108864 SAMPLES TAKEN
DIFFERENTIAL MODE
67108864 SAMPLES TAKEN
DIFFERENTIAL MODE
0.80
0.60
0.80
0.60
0.40
0.40
0.20
0.20
0.00
0.00
–0.20
–0.40
–0.60
–0.20
–0.40
–0.60
–0.80
–1.00
–0.80
–1.00
0
16384
32768
CODE
49152
65535
0
16384
32768
CODE
49152
65535
Figure 20. Integral Nonlinearity (Output Data
Rate = 600 kHz)
Figure 17. Differential Nonlinearity (Output Data
Rate = 1.2 MHz)
–14–
REV. 0
AD7723
quantization noise, a high order modulator is employed to shape
the noise spectrum, so that most of the noise energy is shifted
out of the band of interest (Figure 24b).
225
200
175
150
125
100
AI (HALF_POWER = 0)
DD
The digital filter that follows the modulator removes the large
out-of-band quantization noise, (Figure 24c) while also reduc-
ing the data rate from fCLKIN at the input of the filter to fCLKIN/32
or fCLKIN/16 at the output of the filter, depending on the state
on the MODE1/2 pins in parallel interface mode or the pin
SLDR in serial interface mode. The AD7723 output data rate is
a little over twice the signal bandwidth, which guarantees that
there is no loss of data in the signal band.
AI (HALF_POWER = 1)
DD
75
50
DI
DD
25
0
Digital filtering has certain advantages over analog filtering.
Firstly, since digital filtering occurs after the A/D conversion, it
can remove noise injected during the conversion process. Ana-
log filtering cannot remove noise injected during conversion.
Secondly, the digital filter combines low passband ripple with a
steep roll-off, while also maintaining a linear phase response.
0
5
10
15
20
25
CLOCK FREQUENCY – MHz
Figure 21. Power Consumption vs. CLKIN Frequency
0
SNR = –86.19dB
SNR&D = –85.9dB
THD = –96.42dB
SFDR = –99.61dB
2ND HARMONIC = –100.98dB
3RD HARMONIC = –99.61dB
–25
–50
QUANTIZATION NOISE
f
/2
CLKIN
BAND OF INTEREST
A
= 100kHz
IN
(a)
MEASURED BW = 460kHz
–75
–100
NOISE SHAPING
f
/2
–125
–150
CLKIN
BAND OF INTEREST
(b)
0E+0
100E+3 200E+3 300E+3
400E+3
500E+3 600E+3
FREQUENCY – Hz
DIGITAL FILTER CUTOFF FREQUENCY
Figure 22. 16K Point FFT (Output Data Rate = 1.2 MHz)
f
/2
CLKIN
0
BAND OF INTEREST
(c)
SNR = –89.91dB
SNR&D = –89.7dB
THD = –101.16dB
SFDR = –102.1dB
2ND HARMONIC = –102.1dB
3RD HARMONIC = –110.3dB
–20
–40
Figure 24. Sigma-Delta ADC
The AD7723 employs four or five Finite Impulse Response
(FIR) filters in series. Each individual filter’s output data rate is
half that of the filter’s input data rate. When data is fed to the
interface from the output of the fourth filter, the output data
rate is fCLKIN/16 and the resulting Over Sampling Ratio (OSR)
of the converter is 16. Data fed to the interface from the output
of the fifth filter results in an output data rate of fCLKIN/32 and a
corresponding OSR for the converter of 32. When an Output
Data Rate (ODR) of fCLKIN/32 is selected, the digital filter re-
sponse can be set to either low-pass or band-pass. The band-
pass response is useful when the input signal is band limited
since the resulting output data rate is half that required to con-
vert the band when the low pass operating mode is used. To
illustrate the operation of this mode, consider a band-limited
signal as shown in Figure 25a. This signal band can be correctly
converted by selecting the (low pass) ODR = fCLKIN/16 mode, as
shown in Figure 25b. Note that the output data rate is a little
over twice the maximum frequency in the frequency band. Alterna-
tively the band-pass mode can be selected as shown in Figure 25c.
The band-pass filter removes unwanted signals from dc to just
below fCLKIN/64. Rather than outputting data at fCLKIN/16, the
output of the band-pass filter is sampled at fCLKIN/32. This
A
= 50kHz
IN
–60
MEASURED BW = 300kHz
–80
–100
–120
–140
–160
150E+3
FREQUENCY – Hz
200E+3 250E+3 300E+3
0E+0
50E+3
100E+3
Figure 23. 16K Point FFT (Output Data Rate = 600 kHz)
CIRCUIT DESCRIPTION
The AD7723 ADC employs a sigma-delta conversion technique
to convert the analog input into an equivalent digital word. The
modulator samples the input waveform and outputs an equiva-
lent digital word at the input clock frequency, fCLKIN
.
Due to the high oversampling rate, which spreads the quantiza-
tion noise from 0 to fCLKIN/2, the noise energy contained in the
band of interest is reduced (Figure 24a). To further reduce the
REV. 0
–15–
AD7723
effectively translates the wanted band to a maximum frequency
of a little less than fCLKIN/64 as shown in Figure 25d. Halving
the output data rate reduces the work load of any following
signal processor and also allows a lower serial clock rate to be
used.
0dB
–100dB
BAND LIMITED SIGNAL
0dB
f
/16
CLKIN
(a)
LOW PASS FILTER RESPONSE
ODR
0dB
SAMPLE
IMAGE
0.0
0.5
1.0
f
CLKIN
f
/16
Figure 26b. Low-Pass Filter Decimate by 32
CLKIN
LOW PASS FILTER. OUTPUT DATA RATE = f
/16
CLKIN
(b)
BAND-PASS FILTER
RESPONSE
SAMPLE
IMAGE
0dB
0dB
f
/16
CLKIN
BAND-PASS FILTER.
–100dB
(c)
FREQUENCY
SAMPLE
TRANSLATED
INPUT SIGNAL
ODR
IMAGE
0dB
f
/16
CLKIN
0.0
0.5
1.0
LOW PASS FILTER. OUTPUT DATA RATE = f
/32
CLKIN
f
CLKIN
(d)
Figure 26c. Band-Pass Filter Decimate by 32
Figure 25. Band-Pass Operation
Figure 27a shows the frequency response of the digital filter in
both low-pass and band-pass modes. Due to the sampling
nature of the converter, the pass-band response is repeated
about the input sampling frequency, fCLKIN and at integer mul-
tiples of fCLKIN. Out-of-band noise or signals coincident with
any of the filter images are aliased down to the passband. How-
ever, due to the AD7723’s high oversampling ratio, these bands
occupy only a small fraction of the spectrum, and most broad-
band noise is attenuated by at least 90 dB. In addition, as shown
in Figure 27b, with even a low order filter, there is significant
attenuation at the first image frequency. This contrasts with a
normal Nyquist rate converter where a very high order antialias
filter is required to allow most of the band width to be used
The frequency response of the three digital filter operating modes
is shown in Figures 26a, 26b, and 26c.
0dB
–100dB
while ensuring sufficient attenuation at multiples of fCLKIN
.
0dB
0.0
0.5
1.0
1f
2f
3f
CLKIN
CLKIN
CLKIN
f
CLKIN
Figure 27a. Digital Filter Frequency Response
Figure 26a. Low-Pass Filter Decimate by 16
OUTPUT
DATA RATE
ANTIALIAS FILTER
RESPONSE
REQUIRED
0dB
ATTENUATION
f
/32
f
CLKIN
CLKIN
Figure 27b. Frequency Response of Antialias Filter
REV. 0
–16–
AD7723
APPLYING THE AD7723
Analog Input Range
while also settling to the required accuracy by the end of each
half-clock phase.
The AD7723 has differential inputs to provide common-mode
noise rejection. In unipolar mode the analog input range is 0 to
8/5 × VREF2, while in bipolar mode the analog input range is
±4/5 × VREF2. The output code is twos complement binary in
both modes with 1 LSB = 61 µV. The ideal input/output trans-
fer characteristics for the two modes are shown in Figure 28
below. In both modes the absolute voltage on each input must
remain within the supply range AGND to AVDD. The bipolar
mode allows either single-ended or complementary input
signals.
⌽A
AD7723
500⍀
VIN(+)
2pF
⌽B
2pF
⌽A
500⍀
VIN(–)
AC
GROUND
⌽B
⌽
⌽
⌽
⌽
A
A
CLKIN
B
B
011…111
011…110
Figure 30. Analog Input Equivalent Circuit
Driving the Analog Inputs
To interface the signal source to the AD7723, at least one op
amp will generally be required. Choice of op amp will be critical
to achieving the full performance of the AD7723. The op amp
not only has to recover from the transient loads that the ADC
imposes on it, but must also have good distortion characteristics
and very low input noise. Resistors in the signal path will also
add to the overall thermal noise floor, necessitating the choice of
low value resistors.
000…010
000…001
000…000
111…111
111…110
100…001
100…000
Placing an RC filter between the drive source and the ADC
inputs, as shown in Figure 31, has a number of beneficial af-
fects: transients on the op amp outputs are significantly reduced
since the external capacitor now supplies the instantaneous
charge required when the sampling capacitors are switched to
the ADC input pins and, input circuit noise at the sample im-
ages is now significantly attenuated resulting in improved over-
all SNR. The external resistor serves to isolate the external
capacitor from the ADC output, thus improving op amp stabil-
ity while also isolating the op amp output from any remaining
transients on the capacitor. By experimenting with different
filter values, the optimum performance can be achieved for each
application. As a guideline, the RC time constant (R × C)
should be less than a quarter of the clock period to avoid non-
linear currents from the ADC inputs being stored on the exter-
nal capacitor and degrading distortion. This restriction means
that this filter cannot form the main antialias filter for the ADC.
0V
–4/5
؋
V +4/5
؋
V – 1LSB BIPOLAR
REF2
REF2
(0V)
(+4/5
؋
V REF2
)
(+8/5
؋
V – 1LSB) UNIPOLAR
REF2
Figure 28. Bipolar (Unipolar) Mode Transfer Function
The AD7723 will accept full-scale inband signals, however,
large scale out of band signals can overload the modulator in-
puts. Figure 29 shows the maximum input signal level as a func-
tion of frequency. A minimal single-pole RC antialias filter set
to fCLKIN/24 will allow full-scale input signals over the entire
frequency spectrum.
2.200
2.100
2.000
1.900
1.800
1.700
1.600
1.500
R
VIN(+)
C
AD7723
R
VIN(–)
V
= 2.5V
0.04
REF
1.400
1.300
Figure 31. Input RC Network
0
0.02
0.06
0.08
0.10
0.12
0.14
0.5
INPUT SIGNAL FREQUENCY RELATIVE TO f
CLKIN
With the unipolar input mode selected, just one op amp is re-
quired to buffer single ended input signals. However, driving
the AD7723 with complementary signals and with the bipolar
input range selected has some distinct advantages: even order
harmonics in both the drive circuits and the AD7723 front end
are attenuated; and the peak to peak input signal range on both
inputs is halved. Halving the input signal range allows some op
amps to be powered from the same supplies as the AD7723.
Although a complementary driver will require the use of two op
amps per ADC, it may avoid the need to generate additional
supplies just for these op amps.
Figure 29. Peak Input Signal Level vs. Signal Frequency
Analog Input
The analog input of the AD7723 uses a switched capacitor
technique to sample the input signal. For the purpose of driving
the AD7723, an equivalent circuit of the analog inputs is shown
in Figure 30. For each half clock cycle, two highly linear sam-
pling capacitors are switched to both inputs, converting the
input signal into an equivalent sampled charge. A signal source
driving the analog inputs must be able to source this charge,
REV. 0
–17–
AD7723
Figures 32 and 33 show two such circuits for driving the AD7723.
Figure 32 is intended for use when the input signal is biased
about 2.5 V while Figure 33 is used when the input signal is
biased about ground. While both circuits convert the input
signal into a complementary signal, the circuit in Figure 33
also level shifts the signal so that both outputs are biased
about 2.5 V.
modulator’s switched cap DAC (REF2). When using the inter-
nal reference a 1 µF capacitor is required between REF1 and
AGND to decouple the bandgap noise. If the internal reference
is required to bias external circuits, use an external precision op
amp to buffer REF1.
COMPARATOR
1V
AD7723
Suitable op amps include the AD8047, AD8044, AD8041 and
its dual equivalent the AD8042. The AD8047 has lower input
noise than the AD8041/42 but has to be supplied from a +7.5 V/
–2.5 V supply. The AD8041/AD8042 will typically degrade
SNR from 90 dB to 88 dB but can be powered from the same
single +5 V supply as the AD7723.
REFERENCE
BUFFER
REF1
SWITCHED-CAP
DAC REFERENCED
1F
3k⍀
2.5V
REFERENCE
R
220⍀
FB
REF2
R
R
IN
390⍀
SOURCE
50⍀
AIN = ؎2V
BIASED
AD8047
27⍀
ABOUT 2.5V
A1
VIN(+)
Figure 34. Reference Circuit Block Diagram
Where gain error or gain error drift requires the use of an exter-
nal reference, the reference buffer in Figure 34 can be turned off
by grounding the REF1 pin and the external reference can be
applied directly to pin REF2. The AD7723 will accept an exter-
nal reference voltage between 1.2 V to 3.15 V. By applying a 3 V
rather than a 2.5 V reference, SNR is typically improved by
about 1 dB. Where the output common-mode range of the
amplifier driving the inputs is restricted, the full-scale input
signal span can be reduced by applying a lower than 2.5 V refer-
ence. For example, a 1.25 V reference would make the bipolar
input span ±1 V, but would degrade SNR.
220⍀
220⍀
220pF
AD7723
27⍀
VIN(–)
REF2
A2
10k⍀
AD8047
220nF
10nF
REF1
1F
GAIN = 2
؋
R /(R + R )
IN
FB
SOURCE
Figure 32. Single-Ended to Differential Input Circuit for
Bipolar Mode Operation (Analog Input Biased About +2.5 V)
In all cases, since the REF2 voltage connects to the analog
modulator, a 220 nF and 10 nF capacitor must connect directly
from REF2 to AGND. The external capacitor provides the
charge required for the dynamic load presented at the REF2 pin
(See Figure 35).
R
FB
220⍀
R
R
IN
SOURCE
AIN = ؎2V
BIASED
ABOUT
390⍀
50⍀
AD8047
A1
27⍀
VIN(+)
GROUND
⌽
A
R
BALANCE2
⌽
R
BALANCE1
220⍀
4pF
B
A
REF2
10nF
220⍀
220pF
R
220nF
BALANCE2
4pF
⌽
AD7723
⌽
⌽
B
220⍀
R
SWITCHED-CAP
DAC REFERENCED
27⍀
REF1
10k⍀
A2
VIN(–)
REF2
AD8047
⌽
R
20k⍀
⌽
⌽
CLKIN
REF2
A
A
B
B
220nF
10nF
Figure 35. REF2 Equivalent Input Circuit
REF1
1F
GAIN = 2
؋
R /(R + R ) SOURCE
FB
IN
The AD780 is ideal to use as an external reference with the
AD7723. Figure 36 shows a suggested connection diagram.
Grounding Pin 8 on the AD780 selects the 3 V output mode.
R
R
= R
؋
(R + R )/(2
؋
R )
FB
BALANCE1
BALANCE2
IN
SOURCE
)/R
= R
؋
(R + R REF2
REF1
IN
SOURCE FB
Figure 33. Single-Ended to Differential Input Circuit for
Bipolar Mode Operation (Analog Input Biased About
Ground)
2.5V
+5V
O/P
SELECT
REF2
NC
+V
1
2
3
4
8
7
6
5
IN
NC
Applying the Reference
AD7723
REF1
220nF
10nF
1F
V
TEMP
GND
OUT
The reference circuitry used in the AD7723 includes an on-chip
2.5 V bandgap reference and a reference buffer circuit. The
block diagram of the reference circuit is shown in Figure 34.
The internal reference voltage is connected to REF1 through a
3 kΩ resistor and is internally buffered to drive the analog
22nF
22F
TRIM
AD780
NC = NO CONNECT
Figure 36. External Reference Circuit Connection
–18–
REV. 0
AD7723
Clock Generation
applied synchronous to the falling edge of CLKIN. This way, on
the next rising edge of CLKIN, SYNC is sensed low, the filter is
taken out of its reset state and multiple parts begin to gather
input samples.
The AD7723 contains an oscillator circuit to allow a crystal or
an external clock signal to generate the master clock for the
ADC. The connection diagram for use with a crystal is shown in
Figure 37. Consult the manufacturer’s recommendation for the
load capacitors. To enable the oscillator circuit on board the
AD7723, XTAL_OFF should be tied low.
Following a SYNC, the modulator and filter need time to settle
before data can be read from the AD7723. DRDY goes high
following a synchronization and it remains high until valid data
is available at the interface.
AD7723
DATA INTERFACING
XTAL
CLKIN
The AD7723 offers a choice of serial or parallel data interface
options to meet the requirements of a variety of system configu-
rations. In parallel mode, multiple AD7723s can easily be con-
figured to share a common data bus. Serial mode is ideal when
it is required to minimize the number of data interface lines
connected to a host processor. In either case, careful attention
to the system configuration is required to realize the high dy-
namic range available with the AD7723. Consult the recom-
mendation in the Layout and Grounding section. The following
recommendations for parallel interfacing also apply for the sys-
tem design when using the serial mode.
1M⍀
Figure 37. Crystal Oscillator Connection
When an external clock source is being used, the internal oscil-
lator circuit can be disabled by tying XTAL_OFF high. A low
phase noise clock should be used to generate the ADC sampling
clock because sampling clock jitter effectively modulates the
input signal and raises the noise floor. The sampling clock gen-
erator should be isolated from noisy digital circuits, grounded
and heavily decoupled to the analog ground plane.
Parallel Interface
When using the AD7723, place a buffer/latch adjacent to the
converter to isolate the converter’s data lines from any noise
which may be on the data bus. Even though the AD7723 has
three state outputs, use of an isolation latch represents good
design practice.
The sampling clock generator should be referenced to the ana-
log ground in a split ground system. However, this is not always
possible because of system constraints. In many applications,
the sampling clock must be derived from a higher frequency
multipurpose system clock that is generated on the digital
ground plane. If the clock signal is passed between its origin on
a digital ground plane to the AD7723 on the analog ground
plane, the ground noise between the two planes adds directly to
the clock and will produce excess jitter. The jitter can cause
degradation in the signal-to-noise ratio and also produce un-
wanted harmonics. This can be remedied somewhat by trans-
mitting the sampling signal as a differential one, using either a
small RF transformer or a high speed differential driver and a
receiver such as PECL. In either case, the original master sys-
tem clock should be generated from a low phase noise crystal
oscillator.
Figure 38 shows how the parallel interface of the AD7723 can
be configured to interface with the system data bus of a micro-
processor or a microcontroller such as the MC68HC16 or
8XC251. With CS and RD tied permanently low, the data out-
put bits are always active. When DRDY goes high for two clock
cycles, the rising edge of DRDY is used to latch the conversion
data before a new conversion result is loaded into the output
data register. The falling edge of DRDY then sends an appropri-
ate interrupt signal for interface control. Alternatively, if buffers
are used instead of latches, the falling edge of DRDY provides
the necessary interrupt when a new output word is available
from the AD7723.
DSP
SYSTEM SYNCHRONIZATION
AD7723
The SYNC input provides a synchronization function for use in
parallel or serial mode. SYNC allows the user to begin gathering
samples of the analog input from a known point in time. This
allows a system using multiple AD7723s, operated from a com-
mon master clock, to be synchronized so that each ADC simul-
taneously updates its output register.
74XX16374
16
16
DB0–15
D0–15
ADDR
ADDR
DECODE
DRDY
OE
RD
CS
RD
In a system using multiple AD7723s, a common signal to their
sync inputs will synchronize their operation. On the rising edge
of SYNC, the digital filter sequencer is reset to zero. The filter
is held in a reset state until a rising edge on CLKIN senses
SYNC low. A SYNC pulse, one CLKIN cycle long, can be
INTERRUPT
Figure 38. Parallel Interface Connection
REV. 0
–19–
AD7723
SERIAL INTERFACE
In Serial Modes 2 and 3, SFMT should be tied high. TSI and
DOE should be tied low in these modes. The FSO is a pulse,
approximately one SCO cycle in duration, occurring at the
beginning of the serial data transmission.
The AD7723’s serial data interface can operate in three modes,
depending on the application requirements. The timing dia-
grams in Figures 3, 4 and 5 show how the AD7723 may be used
to transmit its conversion results. Table I shows the control
inputs required to select each serial mode, and the digital filter
operating mode. The AD7723 operates solely in the master
mode providing three serial data output pins for transfer of the
conversion results. The serial data clock output, SCO, serial
data output, SDO, and frame sync output, FSO, are all synchro-
nous with CLKIN. FSO is continuously output at the conversion
rate of the ADC.
Two-Channel Multiplexed Operation
Two additional serial interface control pins, DOE and TSI, are
provided to allow the serial data outputs of two AD7723s, to
easily share one serial data line when operating in Serial Mode 1.
Figure 39 shows the connection diagram. Since a serial data
transmission frame lasts 32 SCO cycles, two ADCs can share a
single data line by alternating transmission of their 16-bit out-
put data onto one SDO pin.
Serial data shifts out of the SDO pin synchronous with SCO.
The FSO is used to frame the output data transmission to an
external device. An output data transmission is either 16 or 32
SCO cycles in duration (refer to Table I). Serial data shifts out
of the SDO pin, MSB first, LSB last, for a duration of 16 SCO
cycles. In Serial Mode 1, SDO outputs zeros for the last 16
SCO cycles of the 32-cycle data transmission frame.
AD7723
MASTER
DV
DD
SFMT
CFMT
TSI
SDO
SCO
FSO
TO HOST
PROCESSOR
DGND
FSI
DOE
CLKIN
The clock format pin, CFMT, selects the active edge of SCO.
With CFMT tied logic low, the serial interface outputs FSO and
SDO change state on the SCO rising edge and are valid on the
falling edge of SCO. With CFMT set high, FSO and SDO
change state on the falling SCO edge and are valid on the SCO
rising edge.
FROM
CONTROL
LOGIC
AD7723
SLAVE
DOE
SDO
SCO
FSO
FSI
DV
DD
CLKIN
SFMT
TSI
The Frame Sync Input, FSI, can be used if the AD7723 conver-
sion process must be synchronized to an external source. FSI
allows the conversion data presented to the serial interface to be
a filtered and decimated result derived from a known point in
time. A common frame sync signal can be applied to two or
more AD7723s to synchronize them to a common master clock.
CFMT
DGND
Figure 39. Serial Mode 1 Connection for Two-Channel
Multiplexed Operation
The Data Output Enable pin, DOE, controls the SDO output
buffer. When the logic level on DOE matches the state of the
TSI pin, the SDO output buffer drives the serial data line, other-
wise the output of the buffer goes high impedance. The serial
format pin, SFMT, is set high to choose the frame sync output
format. The clock format pin, CFMT, is set low so that serial
data is made available on SDO after the rising edge of SCO and
can be latched on the SCO falling edge.
When FSI is applied for the first time, the digital filter sequencer
counter is reset to zero, the AD7723 interrupts the current data
transmission, reloads the output shift register, resets SCO and
transmits the conversion result. Synchronization starts immedi-
ately and the following conversions are invalid while the digital
filter settles. FSI can be applied once after power-up, or it can
be a periodic signal, synchronous to CLKIN, occurring every
32 CLKIN cycles. Subsequent FSI inputs applied every 32
CLKIN cycles do not alter the serial data transmission and do
not reset the digital filter sequencer counter. FSI is an optional
signal; if synchronization is not required, FSI can be tied to a
logic low and the AD7723 will generate FSO outputs.
The Master device is selected by setting TSI to a logic low and
connecting its FSO to DOE. The Slave device is selected with
its TSI pin tied high and both its FSI and DOE controlled from
the Master’s FSO. Since the FSO of the Master controls the
DOE input of both the Master and Slave, one ADC’s SDO is
active while the other is high impedance (Figure 40). When the
Master transmits its conversion result during the first 16 SCO
cycles of a data transmission frame, the low level on DOE sets
the slave’s SDO high impedance. Once the Master completes
transmitting its conversion data, its FSO goes high, triggers the
Slave’s FSI to begin its data transmission frame.
In Serial Mode 1, the control input, SFMT, can be used to
select the format for the serial data transmission (refer to Figure
3). FSO is either a pulse, approximately one SCO cycle in dura-
tion, or a square wave with a period of 32 SCO cycles. With a
logic low level on SFMT, FSO pulses high for one SCO cycle at
the beginning of a data transmission frame. With a logic high
level on SFMT, FSO goes low at the beginning of a data trans-
mission frame and returns high after 16 SCO cycles.
Since FSO pulses are gated by the release of FSI (going low)
and the FSI of the Slave device is held high during its data
transmission, the FSO from the Master device must be used for
connection to the host processor.
Note that in Serial Mode 1, FSI can be used to synchronize the
AD7723 if SFMT is set to a logic high. If SFMT is set low, the
FSI input will have no effect on synchronization.
–20–
REV. 0
AD7723
CLKIN
FSI
t9
t12
t15
SCO
t11
FSO (MASTER)
FSI (SLAVE)
DOE (MASTER & SLAVE)
t13
t16
SDO (MASTER)
SDO (SLAVE)
D15
t16
D14
D1
D0
t15
D1
D0
D15
D14
Figure 40. Serial Mode 1 Timing for Two-Channel Multiplexed Operation
SERIAL INTERFACE TO DSPS
(the receive data will be latched into the DSP on the falling
clock edge), LAFS = 0 (the DSP begins reading the 16-bit word
after the DSP has identified the frame sync signal rather than
the DSP reading the word at the same instant as the frame sync
signal has been identified), LRFS = 0 (RFS is active high).
The AD7723 can be used in Modes 1, 2 or 3 when interfaced to
the ADSP-2106x SHARC DSP.
In serial mode, the AD7723 can be directly interfaced to several
industry standard digital signal processors. In all cases, the
AD7723 operates as the master with the DSP operating as the
slave. The AD7723 provides its own serial clock (SCO) to
transmit the digital word on the SDO pin to the DSP. The
AD7723 also generates the frame synchronization signal that
synchronizes the transfer of the 16-bit word from the AD7723
to the DSP. Depending on the serial mode used, SCO will have
a frequency equal to CLKIN or equal to CLKIN/2. When SCO
equals 19.2 MHz, the AD7723 can be interfaced to Analog
Devices’ ADSP-2106x SHARC DSP. With a 19.2 MHz master
clock and SCO equal to CLKIN/2, the AD7723 can be inter-
faced with the ADSP-21xx family of DSPs, the DSP56002
and the TMS320C5x-57. When the AD7723 is used in the
HALF_PWR mode, i.e., CLKIN is less than 10 MHz, then the
AD7723 can be used with DSPs such as the TMS320C20/C25
and the DSP56000/1.
AD7723-to-DSP56002 Interface
Figure 42 shows the AD7723-to-DSP56002 interface. To inter-
face the AD7723 to the DSP56002, the ADC is operated in
Mode 2 when the ADC is operated with a 19.2 MHz clock. The
DSP56002 is configured as follows: SYN = 1 (synchronous
mode), SCD1 = 0 (RFS is an input), GCK = 0 (a continuous
serial clock is used), SCKD = 0 (the serial clock is external),
WL1 = l, WL0 = 0 (transfers will be 16 bits wide), FSL1 = 0,
FSL0 = 1 (the frame sync will be active at the beginning of each
transfer). Alternatively, the DSP56002 can be operated in asyn-
chronous mode (SYN = 0).
AD7723-to-ADSP-21xx Interface
In this mode, the serial clock for the receive section is input to
the SCO pin. This is accomplished by setting bit SCDO to 0
(external Rx clock).
Figure 41 shows the interface between the ADSP-21xx and the
AD7723. The AD7723 is operated in Mode 2 so that SCO =
CLKIN/2. For the ADSP-21xx, the bits in the serial port con-
trol register should be set up as RFSR = 1 (a frame sync is
needed for each transfer), SLEN = 15 (16-bit word lengths),
RFSW = 0 (normal framing mode for receive operations),
INVRFS = 0 (active high RFS), IRFS = 0 (external RFS) and
ISCLK = 0 (external serial clock).
DSP56002
AD7723
SDR
SC1
SCK
SDO
FSO
SCO
ADSP-21xx
AD7723
Figure 42. AD7723-to-DSP56002 Interface
AD7723-to-TMS320C5x Interface
Figure 43 shows the AD7723-to-TMS320C5x interface. For the
TMS320C5x, FSR and CLKR are automatically configured as
inputs. The serial port is configured as follows: FO = 0 (16-bit
word transfers), FSM = 1 (a frame sync occurs for each transfer).
DR
RFS
SDO
FSO
SCO
SCLK
Figure 41. AD7723-to-ADSP-21xx Interface
AD7723-to-SHARC Interface
TMS320C5x
AD7723
The interface between the AD7723 and the ADSP-2106x
SHARC DSP is the same as shown in Figure 41 but, the DSP is
configured as follows: SLEN = 15 (16-bit word transfers),
SENDN = 0 (the MSB of the 16-bit word will be received by
the DSP first), ICLK = 0 (an external serial clock will be used),
RFSR = 0 (a frame sync is required for every word transfer),
IRFS = 0 (the receive frame sync signal is external), CKRE = 0
DR
FSR
SDO
FSO
SCO
CLKR
Figure 43. AD7723-to-TMS320C5x Interface
REV. 0
–21–
AD7723
GROUNDING AND LAYOUT
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7723 to shield it from noise coupling. The
power supply lines to the AD7723 should use as large a trace as
possible (preferably a plane) to provide a low impedance path
and reduce the effects of glitches on the power supply line.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
will reduce the effects of feedthrough through the board.
The analog and digital power supplies to the AD7723 are inde-
pendent and separately pinned out to minimize coupling be-
tween analog and digital sections within the device. All the
AD7723 AGND and DGND pins should be soldered directly to
a ground plane to minimize series inductance. In addition, the
ac path from any supply pin or reference pin (REF1 and REF2)
through its decoupling capacitors to its associated ground must be
made as short as possible (Figure 44). To achieve the best decou-
pling, place surface mount capacitors as close as possible to the
device, ideally right up against the device pins.
REF2
All ground planes must not overlap to avoid capacitive coupling.
The AD7723’s digital and analog ground planes must be con-
nected at one place by a low inductance path, preferably right
under the device. Typically, this connection will either be a
trace on the Printed Circuit Board of 0.5 cm wide when the
ground planes are on the same layer, or 0.5 cm wide minimum
plated through holes when the ground planes are on different
layers. Any external logic connected to the AD7723 should use
a ground plane separate from the AD7723’s digital ground
plane. These two digital ground planes should also be con-
nected at just one place.
10nF
220nF
AGND2
REF1
1F
AV
1
DD
10nF
AGND1
AGND1
+5V
AV
DD
10nF
10F
100nF
100nF
AGND
AV
DD
Separate power supplies for AVDD and DVDD are also highly
desirable. The digital supply pin DVDD should be powered from
a separate analog supply, but if necessary DVDD may share its
power connection to AVDD. Refer to the connection diagram
(Figure 44). The ferrites are also recommended to filter high
frequency signals from corrupting the analog power supply.
10nF
10nF
AGND
AD7723 ANALOG
GROUND PLANE
AD7723 DIGITAL
GROUND PLANE
DV
DD
100nF
10nF
10F
DGND
DGND
A minimum etch technique is generally best for ground planes
as it gives the best shielding. Noise can be minimized by paying
attention to the system layout and preventing different signals
from interfering with each other. High level analog signals
should be separated from low level analog signals, and both
should be kept away from digital signals. In waveform sampling
and reconstruction systems the sampling clock (CLKIN) is as
vulnerable to noise as any analog signal. CLKIN should be
isolated from the analog and digital systems. Fast switching
signals like clocks should be shielded with their associated
ground to avoid radiating noise to other sections of the board,
and clock signals should never be routed near the analog inputs.
Figure 44. Reference and Power Supply Decoupling
–22–
REV. 0
AD7723
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Plastic Quad Flatpack
(S-44)
0.548 (13.925)
0.546 (13.875)
0.096 (2.44)
0.398 (10.11)
MAX
0.390 (9.91)
0.037 (0.94)
0.025 (0.64)
8°
0.8°
33
23
34
22
SEATING
PLANE
TOP VIEW
(PINS DOWN)
44
12
1
11
0.040 (1.02)
0.032 (0.81)
0.040 (1.02)
0.032 (0.81)
0.033 (0.84) 0.016 (0.41)
0.029 (0.74) 0.012 (0.30)
0.083 (2.11)
0.077 (1.96)
REV. 0
–23–
相关型号：
AD7724BS
IC 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL/PARALLEL ACCESS, PQFP44, PLASTIC, QFP-44, Analog to Digital Converter
ADI
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