AD7720BRUZ-REEL [ADI]
1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28, TSSOP-28;
| 型号： | AD7720BRUZ-REEL |
| 厂家： | 
ADI |
| 描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28, TSSOP-28 光电二极管 转换器 |
| 文件： | 总17页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
CMOS Sigma-Delta Modulator
AD7720
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
12.5 MHz Master Clock Frequency
0 V to +2.5 V or ؎1.25 V Input Range
Single Bit Output Stream
90 dB Dynam ic Range
Pow er Supplies: AVDD, DVDD: +5 V ؎ 5%
On-Chip 2.5 V Voltage Reference
28-Lead TSSOP
AVDD
AGND
DVDD
DGND
REF1
AD7720
2.5V
REFERENCE
REF2
VIN(+)
VIN(–)
DATA
SCLK
SIGMA-DELTA
MODULATOR
MZERO
GC
XTAL1/MCLK
XTAL2
CLOCK
CIRCUITRY
DVAL
CONTROL
LOGIC
BIP
RESETO
RESET
STBY
GENERAL D ESCRIP TIO N
T his device is a 7th order sigma-delta modulator that converts
the analog input signal into a high speed 1-bit data stream. T he
part operates from a +5 V supply and accepts a differential input
range of 0 V to +2.5 V or ±1.25 V centered about a common-
mode bias. T he analog input is continuously sampled by the
analog modulator, eliminating the need for external sample and
hold circuitry. T he input information is contained in the output
stream as a density of ones. T he original information can be
reconstructed with an appropriate digital filter.
T he part provides an accurate on-chip 2.5 V reference. A refer-
ence input/output function is provided to allow either the inter-
nal reference or an external system reference to be used as the
reference source for the part.
T he device is offered in a 28-lead T SSOP package and designed
to operate from –40°C to +85°C.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
AD7720* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
REFERENCE MATERIALS
Technical Articles
• Delta-Sigma Rocks RF, As ADC Designers Jump On Jitter
DOCUMENTATION
Application Notes
• Part 1: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
• Part 2: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
• AN-202: An IC Amplifier User’s Guide to Decoupling,
Grounding, and Making Things Go Right for a Change
• AN-283: Sigma-Delta ADCs and DACs
DESIGN RESOURCES
• AD7720 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
• AN-311: How to Reliably Protect CMOS Circuits Against
Power Supply Overvoltaging
• AN-388: Using Sigma-Delta Converters-Part 1
• AN-389: Using Sigma-Delta Converters-Part 2
• AN-397: Electrically Induced Damage to Standard Linear
Integrated Circuits:
Data Sheet
DISCUSSIONS
• AD7720: CMOS Sigma-Delta Modulator with 90 dB
View all AD7720 EngineerZone Discussions.
Dynamic Range Data Sheet
SAMPLE AND BUY
Visit the product page to see pricing options.
TOOLS AND SIMULATIONS
• Sigma-Delta ADC Tutorial
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
MCLK = 12.5 MHz,
1 (AVDD = +5 V ؎ 5%; DVDD = +5 V ؎ 5%; AGND = DGND = 0 V, f
REF2 = +2.5 V; T = TMIN to T , unless otherwise noted)
AD7720–SPECIFICATIONS
A
MIN
P aram eter
B Version
Units
Test Conditions/Com m ents
ST AT IC PERFORMANCE
Resolution
When T ested with Ideal FIR Filter as in Figure 1
Guaranteed Monotonic
16
±1
±2
±6
±0.6
±1.5
±0.3
±1
Bits
LSB max
LSB typ
mV typ
% FSR typ
mV typ
Differential Nonlinearity
Integral Nonlinearity
Precalibration Offset Error
Precalibration Gain Error2
Postcalibration Offset Error3
Postcalibration Gain Error2, 3
Offset Error Drift
% FSR typ
LSB/°C typ
Gain Error Drift
REF2 Is an Ideal Reference, REF1 = AGND
Unipolar Mode
Bipolar Mode
±1
±0.5
LSB/°C typ
LSB/°C typ
ANALOG INPUT S
Signal Input Span (VIN(+) – VIN(–))
Bipolar Mode
Unipolar Mode
Maximum Input Voltage
Minimum Input Voltage
Input Sampling Capacitance
Input Sampling Rate
±VREF2/2
0 to VREF2
AVDD
0
V max
V max
V
BIP = VIH
BIP = VIL
V
2
pF typ
MHz
kΩ typ
2 fMCLK
Differential Input Impedance
109/(8 fMCLK
)
REFERENCE INPUT S
REF1 Output Voltage
2.32 to 2.62
60
3
V min/max
ppm/°C typ
kΩ typ
REF1 Output Voltage Drift
REF1 Output Impedance
Reference Buffer Offset Voltage
Using Internal Reference
REF2 Output Voltage
REF2 Output Voltage Drift
Using External Reference
REF2 Input Impedance
±12
mV max
Offset Between REF1 and REF2
2.32 to 2.62
60
V min/max
ppm/°C typ
REF1 = AGND
109/(16 fMCLK
2.32 to 2.62
)
kΩ typ
V min/max
External Reference Voltage Range
Applied to REF1 or REF2
DYNAMIC SPECIFICAT IONS4
Bipolar Mode
When T ested with Ideal FIR Filter as in Figure 1
BIP = VIH, VCM = 2.5 V, VIN(+) = VIN(–) = 1.25 V p-p
or VIN(–) = 1.25 V, VIN(+) = 0 V to 2.5 V
Input BW = 0 kHz–90.625 kHz
Signal to (Noise + Distortion)5
90
dB typ
86/84.5
–90/–88
–90
dB min
dB max
dB max
T otal Harmonic Distortion5
Spurious Free Dynamic Range
Unipolar Mode
Input BW = 0 kHz–90.625 kHz
Input BW = 0 kHz–90.625 kHz
BIP = VIL, VIN(–) = 0 V, VIN(+) = 0 V to 2.5 V
Input BW = 0 kHz–90.625 kHz
Signal to (Noise + Distortion)5
88
dB typ
dB min
dB max
dB max
dB typ
dB typ
84.5/83
–89/–87
–90
–93
96
T otal Harmonic Distortion5
Spurious Free Dynamic Range
Intermodulation Distortion
AC CMRR
Input BW = 0 kHz–97.65 kHz
Input BW = 0 kHz–97.65 kHz
VIN(+) = VIN(–) = 2.5 V p-p, VCM = 1.25 V to
3.75 V, 20 kHz
Overall Digital Filter Response
0 kHz–90.625 kHz
96.92 kHz
See Figure 1 for Characteristics of FIR Filter
±0.005
–3
90
dB max
dB min
dB typ
104.6875 kHz to 12.395 MHz
CLOCK
MCLK Duty Ratio
45 to 55
4
0.4
% max
V min
V max
For Specified Operation
MCLK Uses CMOS Logic
VMCLKH, MCLK High Voltage
VMCLKL, MCLK Low Voltage
–2–
REV. 0
AD7720
P aram eter
B Version
Units
Test Conditions/Com m ents
LOGIC INPUT S
VIH, Input High Voltage
VIL, Input Low Voltage
2
V min
0.8
10
10
V max
µA max
pF max
I
INH, Input Current
CIN, Input Capacitance
LOGIC OUT PUT S
V
OH, Output High Voltage
2.4
0.4
V min
V max
| IOUT | ≤ 200 µA
| IOUT | ≤ 1.6 mA
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
4.75/5.25
4.75/5.25
V min/V max
V min/V max
I
DD (T otal for AVDD, DVDD)
Digital Inputs Equal to 0 V or DVDD
Active Mode
Standby Mode
43
25
mA max
µA max
NOT ES
1Operating temperature range is as follows: B Version: –40 °C to +85°C.
2Gain Error excludes reference error. T he modulator gain is calibrated w.r.t. the voltage on the REF2 pin.
3Applies after calibration at temperature of interest.
4Measurement Bandwidth = 0.5 × fMCLK; Input Level = –0.05 dB.
5T A = +25°C to +85°C/T A = T MIN to T MAX
.
Specifications subject to change without notice.
90.625kHz
90.625kHz
FILTER 2
BIT STREAM
DECIMATE
BY 32
DECIMATE
BY 2
16-BIT
OUTPUT
120dB
90dB
FILTER 1
292.969kHz
104.687kHz
BANDWIDTH = 90.625 kHz
BANDWIDTH = 90.625 kHz
TRANSITION = 104.687kHz
ATTENUATION = 90dB
COEFFICIENTS = 151
TRANSITION = 292.969kHz
ATTENUATION = 120dB
COEFFICIENTS = 384
Figure 1. Digital Filter (Consists of 2 FIR Filters). This filter is im plem ented on the AD7722.
REV. 0
–3–
AD7720
(AVDD = +5 V ؎ 5%; DVDD = +5 V ؎ 5%; AGND = DGND = 0 V, REF2= +2.5 V unless otherwise noted)
TIMING CHARACTERISTICS
Lim it at TMIN, TMAX
(B Version)
P aram eter
Units
Conditions/Com m ents
fMCLK
100
15
67
0.45 × tMCLK
0.45 × tMCLK
15
10
kHz min
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Master Clock Frequency
12.5 MHz for Specified Performance
Master Clock Period
Master Clock Input High T ime
Master Clock Input Low T ime
Data Hold T ime After SCLK Rising Edge
RESET Pulsewidth
RESET Low T ime Before MCLK Rising
DVAL High Delay after RESET Low
t1
t2
t3
t4
t5
t6
t7
10
20 × tMCLK
NOT E
Guaranteed by design.
I
OL
1.6mA
TO
OUTPUT
PIN
+1.6V
C
L
50pF
I
OH
20
A
Figure 2. Load Circuit for Access Tim e and Bus Relinquish Tim e
t1
t2
SCLK (O)
t3
t4
DATA (O)
NOTE:
O SIGNIFIES AN OUTPUT
Figure 3. Data Tim ing
MCLK (I)
t6
t5
RESET (I)
DVAL (O)
t7
NOTE:
I SIGNIFIES AN INPUT
O SIGNIFIES AN OUTPUT
Figure 4. RESET Tim ing
–4–
REV. 0
AD7720
ABSO LUTE MAXIMUM RATINGS1
(T A = +25°C unless otherwise noted)
P IN CO NFIGURATIO N
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Input Voltage to DGND . . –0.3 V to DVDD + 0.3 V
Analog Input Voltage to AGND . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . ±10 mA
Operating T emperature Range
1
2
REF2
AGND
NC
28 AVDD
27
26
25
24
23
REF1
AGND
AVDD
3
STBY
DVAL
DGND
GC
4
5
AGND
VIN(+)
6
AD7720
TOP VIEW
(Not to Scale)
7
22 RESET
21 VIN(–)
8
BIP
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction T emperature . . . . . . . . . . . . . . . +150°C
T SSOP Package
MZERO
DATA
SCLK
RESETO
NC
9
20
AGND
10
11
12
13
14
19
18
DVDD
AGND
17 XTAL2
θ
JA T hermal Impedance . . . . . . . . . . . . . . . . . . . . 120°C/W
16 XTAL1/MCLK
15 DGND
Lead T emperature, Soldering
AGND
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NC = NO CONNECT
NOT ES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2T ransient currents of up to 100 mA will not cause SCR latchup.
O RD ERING GUID E
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
AD7720BRU
–40°C to +85°C
28-Lead T hin Shrink Small Outline
RU-28
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7720 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
AD7720
P IN FUNCTIO N D ESCRIP TIO NS
Function
P in No.
Mnem onic
1
REF2
Reference Input/Output. REF2 connects to the output of an internal buffer amplifier used
to drive the sigma-delta modulator. When REF2 is used as an input, REF1 must be con-
nected to AGND.
2, 14, 18, 20, 24, 26 AGND
Ground reference point for analog circuitry.
No Connect.
3, 13
4
NC
ST BY
Standby, Logic Input. When ST BY is high, the device is placed in a low power mode.
When ST BY is low, the device is powered up.
5
DVAL
Data Valid Logic Output. A logic high on DVAL indicates that the data bit stream from
the AD7720 is an accurate digital representation of the analog voltage at the input to the
sigma-delta modulator. T he DVAL pin is set low for 20 MCLK cycles if the analog input is
overranged.
6, 15
DGND
GC
Ground reference for the digital circuitry.
7
8
Digital Control Input. When GC is high, the gain error of the modulator can be calibrated.
BIP
Analog Input Range Select, Logic Input. A logic low on this input selects unipolar mode. A
logic high selects bipolar mode.
9
MZERO
Digital Control Input. When MZERO is high, the modulator inputs are internally grounded,
i.e., tied to AGND in unipolar mode and REF2 in bipolar mode. MZERO allows on-chip
offsets to be calibrated out. MZERO is low for normal operation.
10
11
12
16
DAT A
SCLK
Modulator Bit Stream. T he digital bit stream from the sigma-delta modulator is output at
DAT A.
Serial Clock, Logic Output. T he bit stream from the modulator is valid on the rising edge
of SCLK.
RESET O
Reset Logic Output. T he signal applied to the RESET pin is made available as an output at
RESET O.
XT AL1/MCLK CMOS Logic Clock Input. The XTAL1/MCLK pin interfaces the device’s internal oscillator
circuit to an external crystal or an external clock. A parallel resonant, fundamental-frequency,
microprocessor-grade crystal and a 1 MΩ resistor should be connected between the MCLK
and XT AL pins with two capacitors connected from each pin to ground. Alternatively, the
XT AL1/MCLK pin can be driven with an external CMOS-compatible clock. T he part is
specified with a 12.5 MHz master clock.
17
XT AL2
Oscillator Output. T he XT AL2 pin connects the internal oscillator output to an external
crystal. If an external clock is used, XT AL2 should be left unconnected.
19
DVDD
Digital Supply Voltage, +5 V ± 5%.
21, 23
VIN(–), VIN(+) Analog Input. In unipolar operation, the analog input range on VIN(+) is VIN(–) to
(VIN(–) + VREF); for bipolar operation, the analog input range on VIN+ is (VIN(–) ± VREF/2).
T he absolute analog input range must lie between 0 and AVDD. T he analog input is con-
tinuously sampled and processed by the analog modulator.
25, 28
22
AVDD
RESET
Analog Positive Supply Voltage, +5 V ± 5%.
Reset Logic Input. RESET is an asynchronous input. When RESET is taken high, the
sigma-delta modulator is reset by shorting the integrator capacitors in the modulator. DVAL
goes low for 20 MCLK cycles while the modulator is being reset.
27
REF1
Reference Input/Output. REF1 connects via a 3 kΩ resistor to the output of the internal
2.5 V reference, and to the input of a buffer amplifier that drives the sigma-delta modulator.
T his pin can also be overdriven with an external 2.5 V reference.
–6–
REV. 0
AD7720
TERMINOLOGY (IDEAL FIR FILTER USED WITH AD7720
[FIGURE 1])
Integr al Nonlinear ity
fundamental. Noise plus distortion is the rms sum of all of the
nonfundamental signals and harmonics to half the output word
rate (fMCLK/128), excluding dc. Signal-to-(Noise + Distortion) is
dependent on the number of quantization levels used in the
digitization process; the more levels, the smaller the quantiza-
tion noise. T he theoretical Signal-to-(Noise + Distortion) ratio
for a sine wave input is given by
T his is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. T he
endpoints of the transfer function are zero scale (not to be con-
fused with bipolar zero), a point 0.5 LSB below the first code
transition (100 . . . 00 to 100 . . . 01 in bipolar mode and
000 . . . 00 to 000 . . . 01 in unipolar mode) and full scale, a
point 0.5 LSB above the last code transition (011 . . . 10 to
011 . . . 11 in bipolar mode and 111 . . . 10 to 111 . . . 11 in
unipolar mode). T he error is expressed in LSBs.
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
where N is the number of bits.
Total H arm onic D istortion
T otal Harmonic Distortion (T HD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD7720, T H D is defined as
D iffer ential Nonlinear ity
T his is the difference between the measured and the ideal 1 LSB
change between two adjacent codes in the ADC.
(V22 +V32 +V42 +V52 +V6 )
2
Com m on-Mode Rejection Ratio
THD = 20 log
V1
T he ability of a device to reject the effect of a voltage applied to
both input terminals simultaneously—often through variation of
a ground level—is specified as a common-mode rejection ratio.
CMRR is the ratio of gain for the differential signal to the gain
for the common-mode signal.
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic.
Spur ious Fr ee D ynam ic Range
Unipolar O ffset Error
Spurious free dynamic range is the difference, in dB, between
the peak spurious or harmonic component in the ADC output
spectrum (up to fMCLK/128 and excluding dc) and the rms value
of the fundamental. Normally, the value of this specification will
be determined by the largest harmonic in the output spectrum
of the FFT . For input signals whose second harmonics occur in
the stop band region of the digital filter, a spur in the noise floor
limits the spurious free dynamic range.
Unipolar offset error is the deviation of the first code transition
from the ideal VIN(+) voltage which is (VIN(–) + 0.5 LSB)
when operating in the unipolar mode.
Bipolar O ffset Error
T his is the deviation of the midscale transition (111 . . . 11
to 000 . . . 00) from the ideal VIN(+) voltage which is (VIN(–)
–0.5 LSB) when operating in the bipolar mode.
Gain Error
Inter m odulation D istor tion
T he first code transition should occur at an analog value 1/2
LSB above minus full scale. T he last code transition should
occur for an analog value 3/2 LSB below the nominal full scale.
Gain error is the deviation of the actual difference between first
and last code transitions and the ideal difference between first
and last code transitions.
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m or n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
Signal-to-(Noise + D istortion)
Signal-to-(Noise + Distortion) is measured signal-to-noise at the
output of the ADC. T he signal is the rms magnitude of the
REV. 0
–7–
AD7720–Typical Characteristics
(AVDD = DVDD = 5.0 V, T = +25؇C; CLKIN = 12.5 MHz, AIN = 20 kHz, Bipolar Mode; V (+) = 0 V to 2.5 V, V (–) = 1.25 V unless otherwise
A
IN
IN
noted)
110
84
85
86
87
88
89
90
91
92
–85
–90
100
90
80
70
60
50
AIN = 1/5 · BW
SNR
–95
SFDR
–100
–105
–110
–115
S/ (N+D)
SFDR
THD
–40
–30
–20
–10
0
0
20
40
60
80
100
0
50
100
150
200
250
300
INPUT LEVEL – dB
OUTPUT DATA RATE – kSPS
INPUT FREQUENCY – kHz
Figure 5. S/(N+D) and SFDR vs.
Analog Input Level
Figure 6. S/(N+D) vs. Output Sam ple
Rate
Figure 7. SNR, THD, and SFDR vs.
Input Frequency
92.0
91.5
91.0
90.5
90.0
89.5
89.0
88.5
88.0
–85
84
85
–90
AIN = 1/5
·
IN
BW
SNR
V
(+) = V (–) = 1.25Vpk–pk
86
87
88
89
90
91
92
IN
V
V
(+) = V (–) = 1.25Vpk–pk
IN
IN
V
= 2.5V
CM
–95
–100
–105
–110
–115
= 2.5V
CM
THD
SFDR
0
20
40
60
80
100
0
50
100
150
200
250
300
–50
0
50
100
INPUT FREQUENCY – kHz
OUTPUT DATA RATE – kSPS
TEMPERATURE – °C
Figure 8. SNR, THD, and SFDR vs.
Input Frequency
Figure 9. S/(N+D) vs. Output Sam ple
Rate
Figure 10. SNR vs. Tem perature
1.0
0.8
–94
–96
5000
4500
THD
V
(+) = V (–)
IN IN
–98
0.6
4000
3500
3000
2500
2000
1500
1000
500
CLKIN = 12.5MHz
8k SAMPLES
–100
–102
0.4
0.2
3RD
–104
0
–106
–0.2
–0.4
–0.6
–0.8
–1.0
4TH
–108
–110
–112
–114
2ND
75 100
0
n–3
–116
0
20000
40000
CODE
65535
–50
–25
0
25
50
n–2
n–1
n
n+1
n+2
n+3
TEMPERATURE – °C
CODES
Figure 13. Differential Nonlinearity
Figure 11. THD vs. Tem perature
Figure 12. Histogram of Output Codes
with DC Input
REV. 0
–8–
AD7720
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
20000
40000
CODE
65535
Figure 14. Integral Nonlinearity Error
0
–10
0
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–100
–110
–120
–130
0
6.25
0
393.295 kHz
FREQUENCY – MHz
FREQUENCY – kHz
Figure 15. Modulator Output (0 Hz to MCLK/2)
Figure 18. Modulator Output (0 to 393.295 kHz)
0
0
–20
AIN = 90kHz
CLKIN = 12.5 MHz
SNR = 89.6dB
S/(N+D) = 89.6dB
SFDR = –108.0dB
CLKIN = 12.5MHz
SNR = 90.1dB
–20
–40
S/(N+D) = 89.2dB
SFDR = –99.5dB
THD = –96.6dB
2ND = –100.9dB
3RD = –106.0dB
4TH = –99.5dB
–40
–60
–60
–80
–80
–100
–120
–100
–120
–140
–154
–140
–154
98E+3
0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 90E+3
0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 90E+3 98E+3
Figure 16. 16K Point FFT
Figure 19. 16K Point FFT
0
0
XTAL = 12.288MHz
SNR = 89.0dB
AIN = 90kHz
XTAL = 12.288MHz
SNR = 88.1dB
S/(N+D) = 88.1dB
SFDR = –103.7dB
–20
–20
S/(N+D) = 87.8dB
SFDR = –94.3dB
THD = –93.8dB
2ND = –94.3dB
3RD = –108.5dB
4TH = –105.7dB
–40
–60
–40
–60
–80
–80
–100
–120
–100
–120
–140
–154
–140
–154
0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 90E+3 96E+3
0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 90E+3 96E+3
Figure 17. 16K Point FFT
Figure 20. 16K Point FFT
REV. 0
–9–
AD7720
CIRCUIT D ESCRIP TIO N
Sigm a-D elta AD C
T he AD7720 ADC employs a sigma-delta conversion technique
that converts the analog input into a digital pulse train. T he
analog input is continuously sampled by a switched capacitor
modulator at twice the rate of the clock input frequency (2 ×
A
B
A
B
50
50
VIN(+)
VIN(–)
2pF
2pF
AC
GROUND
fMCLK). T he digital data that represents the analog input is in
the one’s density of the bit stream at the output of the sigma-
delta modulator. T he modulator outputs the bit stream at a data
MCLK
A
A
B
B
rate equal to fMCLK
.
Figure 22. Analog Input Equivalent Circuit
Due to the high oversampling rate, which spreads the quantiza-
tion noise from 0 to fMCLK/2, the noise energy contained in the
band of interest is reduced (Figure 21a). T o reduce the quanti-
zation noise further, a high order modulator is employed to
shape the noise spectrum, so that most of the noise energy is
shifted out of the band of interest (Figure 21b).
Since the AD7720 samples the differential voltage across its
analog inputs, low noise performance is attained with an input
circuit that provides low differential mode noise at each input.
T he amplifiers used to drive the analog inputs play a critical
role in attaining the high performance available from the AD7720.
When a capacitive load is switched onto the output of an op
amp, the amplitude will momentarily drop. T he op amp will try
to correct the situation and, in the process, hits its slew rate
limit. T his nonlinear response, which can cause excessive ring-
ing, can lead to distortion. T o remedy the situation, a low pass
RC filter can be connected between the amplifier and the input
to the AD7720 as shown in Figure 23. T he external capacitor
at each input aids in supplying the current spikes created during
the sampling process. T he resistor in this diagram, as well as
creating the pole for the antialiasing, isolates the op amp from
the transient nature of the load.
QUANTIZATION NOISE
f
/2
MCLK
BAND OF INTEREST
a.
NOISE SHAPING
f
/2
MCLK
BAND OF INTEREST
b.
R
VIN(+)
Figure 21. Sigm a-Delta ADC
USING TH E AD 7720
AD C D iffer ential Inputs
C
ANALOG
INPUT
R
VIN(–)
T he AD7720 uses differential inputs to provide common-mode
noise rejection (i.e., the converted result will correspond to the
differential voltage between the two inputs). T he absolute volt-
age on both inputs must lie between AGND and AVDD.
C
Figure 23. Sim ple RC Antialiasing Circuit
In the unipolar mode, the full-scale input range (VIN(+) –
VIN(–)) is 0 V to VREF. In the bipolar mode configuration, the
full-scale analog input range is ±VREF2/2. T he bipolar mode
allows complementary input signals. Alternatively, VIN(–) can
be connected to a dc bias voltage to allow a single-ended input
on VIN(+) equal to VBIAS ± VREF2/2.
T he differential input impedance of the AD7720 switched
capacitor input varies as a function of the MCLK frequency,
given by the equation:
ZIN = 109/(8 fMCLK) kΩ
Even though the voltage on the input sampling capacitors may
not have enough time to settle to the accuracy indicated by the
resolution of the AD7720, as long as the sampling capacitor
charging follows the exponential curve of RC circuits, only the
gain accuracy suffers if the input capacitor is switched away too
early.
D iffer ential Inputs
T he analog input to the modulator is a switched capacitor de-
sign. T he analog input is converted into charge by highly linear
sampling capacitors. A simplified equivalent circuit diagram of
the analog input is shown in Figure 22. A signal source driving
the analog input must be able to provide the charge onto the
sampling capacitors every half MCLK cycle and settle to the
required accuracy within the next half cycle.
An alternative circuit configuration for driving the differential
inputs to the AD7720 is shown in Figure 24.
–10–
REV. 0
AD7720
The AD7720 can operate with its internal reference or an external
reference can be applied in two ways. An external reference can
be connected to REF1, overdriving the internal reference. How-
ever, there will be an error introduced due to the offset of the
internal buffer amplifier. For lowest system gain errors when
using an external reference, REF1 is grounded (disabling the
internal buffer) and the external reference is connected to REF2.
C
2.7nF
R
100⍀
VIN(+)
VIN(–)
C
2.7nF
R
100⍀
C
2.7nF
In all cases, since the REF2 voltage connects to the analog
modulator, a 220 nF capacitor must connect directly from
REF2 to AGND. T he external capacitor provides the charge
required for the dynamic load presented at the REF2 pin
(Figure 26).
Figure 24. Differential Input with Antialiasing
A capacitor between the two input pins sources or sinks charge
to allow most of the charge that is needed by one input to be
effectively supplied by the other input. T his minimizes undesir-
able charge transfer from the analog inputs to and from ground.
T he series resistor isolates the operational amplifier from the
current spikes created during the sampling process and provides
a pole for antialiasing. T he 3 dB cutoff frequency (f3 dB) of the
antialias filter is given by Equation 1, and the attenuation of the
filter is given by Equation 2.
⌽
A
⌽
B
4pF
REF2
220nF
4pF
⌽
A
⌽
B
SWITCHED-CAP
DAC REF
f3 dB = 1/(2 π REXT CEXT
)
(1)
2
⌽
⌽
A
⌽
⌽
B
MCLK
1/ 1+ f /f
A
B
(
)
3 dB
Attenuation = 20 log
(2)
Figure 26. REF2 Equivalent Circuit
The choice of the filter cutoff frequency will depend on the
amount of roll off that is acceptable in the passband of the
digital filter and the required attenuation at the first image
frequency.
T he AD780 is ideal to use as an external reference with the
AD7720. Figure 27 shows a suggested connection diagram.
T he capacitors used for the input antialiasing circuit must have
low dielectric absorption to avoid distortion. Film capacitors
such as Polypropylene, Polystyrene or Polycarbonate are suitable.
If ceramic capacitors are used, they must have NPO dielectric.
O/P
SELECT
1
2
3
4
NC
+V
8
7
6
5
+5V
REF2
REF1
NC
IN
220nF
22F
TEMP
GND
1F
V
OUT
22nF
TRIM
Applying the Refer ence
The reference circuitry used in the AD7720 includes an on-chip
+2.5 V bandgap reference and a reference buffer circuit. T he
block diagram of the reference circuit is shown in Figure 25.
T he internal reference voltage is connected to REF1 via a
3 kΩ resistor and is internally buffered to drive the analog
modulator’s switched capacitor DAC (REF2). When using the
internal reference, connect 100 nF between REF1 and AGND.
If the internal reference is required to bias external circuits, use
an external precision op amp to buffer REF1.
AD780
Figure 27. External Reference Circuit Connection
Input Cir cuits
Figures 28 and 29 show two simple circuits for bipolar mode
operation. Both circuits accept a single-ended bipolar signal
source and create the necessary differential signals at the input
to the ADC.
T he circuit in Figure 28 creates a 0 V to 2.5 V signal at the
VIN(+) pin to form a differential signal around an initial bias
voltage of 1.25 V. For single-ended applications, best T HD
performance is obtained with VIN(–) set to 1.25 V rather than
2.5 V. T he input to the AD7720 can also be driven differen-
tially with a complementary input as shown in Figure 29.
COMPARATOR
1V
REFERENCE
BUFFER
REF1
SWITCHED-CAP
DAC REF
In this case, the input common-mode voltage is set to 2.5 V.
T he 2.5 V p-p full-scale differential input is obtained with a
1.25 V p-p signal at each input in antiphase. T his configuration
minimizes the required output swing from the amplifier circuit
and is useful for single supply applications.
100nF
3k⍀
2.5V
REFERENCE
REF2
Figure 25. Reference Circuit Block Diagram
REV. 0
–11–
AD7720
12pF
1/2
1k⍀
1k⍀
AIN =
؎1.25V
XTAL
MCLK
1M⍀
VIN(+)
VIN(–)
OP275
1nF
1nF
1k⍀
DIFFERENTIAL
INPUT = 2.5V p-p
12pF
1/2
Figure 30. Crystal Oscillator Connection
VIN(–) BIAS
VOLTAGE = 1.25V
1k⍀
An external clock must be free of ringing and have a minimum
rise time of 5 ns. Degradation in performance can result as high
edge rates increase coupling that can generate noise in the sam-
pling process. T he connection diagram for an external clock
source (Figure 31) shows a series damping resistor connected
between the clock output and the clock input to the AD7720.
T he optimum resistor will depend on the board layout and the
impedance of the trace connecting to the clock input.
REF1
REF2
1k⍀
100nF
374k⍀
374k⍀
OP275
10nF
220nF
Figure 28. Single-Ended Analog Input for Bipolar Mode
Operation
25–150⍀
CLOCK
MCLK
CIRCUITRY
12pF
1k⍀
1k⍀
AIN =
Figure 31. External Clock Oscillator Connection
؎0.625V
A low phase noise clock should be used to generate the ADC
sampling clock because sampling clock jitter effectively modu-
lates the input signal and raises the noise floor. T he sampling
clock generator should be isolated from noisy digital circuits,
grounded and heavily decoupled to the analog ground plane.
1/2
OP275
VIN(–)
1nF
12pF
1/2
DIFFERENTIAL
INPUT = 2.5V p-p
1k⍀
1k⍀
COMMON MODE
VOLTAGE = 2.5V
T he sampling clock generator should be referenced to the ana-
log ground plane in a split ground system. However, this is not
always possible because of system constraints. In many cases,
the sampling clock must be derived from a higher frequency
multipurpose system clock that is generated on the digital
ground plane. If the clock signal is passed between its origin on
a digital plane to the AD7720 on the analog ground plane, the
ground noise between the two planes adds directly to the clock
and will produce excess jitter. T he jitter can cause unwanted
degradation in the signal-to-noise ratio and also produce un-
wanted harmonics.
VIN(+)
OP275
1nF
R
REF1
R
100nF
OP07
REF2
220nF
Figure 29. Single-Ended to Differential Analog Input
Circuit for Bipolar Mode Operation
T his can be somewhat remedied by transmitting the sampling
clock signal as a differential one, using either a small RF trans-
former or a high speed differential driver and receiver such as
PECL. In either case, the original master system clock should
be generated from a low phase noise crystal oscillator.
T he 1 nF capacitors at each ADC input store charge to aid the
amplifier settling as the input is continuously switched. A resis-
tor in series with the drive amplifier output and the 1 nF input
capacitor may also be used to create an antialias filter.
Clock Gener ation
T he AD7720 contains an oscillator circuit to allow a crystal or
an external clock signal to generate the master clock for the
ADC. T he connection diagram for use with the crystal is shown
in Figure 30. Consult the crystal manufacturer’s recommenda-
tion for the load capacitors.
–12–
REV. 0
AD7720
O ffset and Gain Calibr ation
common-mode rejection of the part will remove common-mode
noise on these inputs. T he analog and digital supplies to the
AD7720 are independent and separately pinned out to minimize
coupling between analog and digital sections of the device.
T he analog inputs of the AD7720 can be configured to measure
offset and gain errors. Pins MZERO and GC are used to config-
ure the part. Before calibrating the device, the part should be
reset so that the modulator is in a known state at calibration.
When MZERO is taken high, the analog inputs are tied to
AGND in unipolar mode and VREF in bipolar mode. After
taking MZERO high, 1000 MCLK cycles should be allowed for
the circuitry to settle before the bit stream is read from the
device. T he ideal ones density is 50% when bipolar operation is
selected and 37.5% when unipolar mode is selected.
T he printed circuit board that houses the AD7720 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. T his facilitates the
use of ground planes which can easily be separated. A minimum
etch technique is generally best for ground planes as it gives the
best shielding. Digital and analog ground planes should only
be joined in one place. If the AD7720 is the only device requir-
ing an AGND-to-DGND connection, the ground planes should
be connected at the AGND and DGND pins of the AD7720.
If the AD7720 is in a system where multiple devices require
AGND-to-DGND connections, the connection should still be
made at one point only, a star ground point that should be
established as close as possible to the AD7720.
When GC is taken high, VIN(–) is tied to ground while VIN(+)
is tied to VREF. Again, 1000 MCLK cycles should be allowed for
the circuitry to settle before the bit stream is read. T he ideal
ones density is 62.5%.
T he calibration results apply only for the particular analog input
mode (unipolar/bipolar) selected when performing the calibra-
tion cycle. On changing to a different analog input mode, a new
calibration must be performed.
Avoid running digital lines under the device as these will couple
noise onto the die. T he analog ground plane should be allowed
to run under the AD7720 to avoid noise coupling. T he power
supply lines to the AD7720 should use as large a trace as pos-
sible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals like
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board, and clock signals should
never be run near the analog inputs. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board should
run at right angles to each other. T his will reduce the effects of
feedthrough through the board. A microstrip technique is by far
the best, but is not always possible with a double-sided board.
In this technique, the component side of the board is dedi-
cated to ground planes while signals are placed on the other
side.
Before calibrating, ensure that the supplies have settled and that
the voltage on the analog input pins is between the supply
voltages.
Standby
T he part can be put into a low power standby mode by taking
ST BY high. During standby, the clock to the modulator is
turned off and bias is removed from all analog circuits.
Reset
T he RESET pin is used to reset the modulator to a known state.
When RESET is taken high, the integrator capacitors of the
modulator are shorted and DVAL goes low and remains low
until 20 MCLK cycles after RESET is deasserted. However, an
additional 1000 MCLK cycles should be allowed before reading
the modulator bit stream as the modulator circuitry needs to
settle after the reset.
Good decoupling is important when using high resolution ADCs.
All analog and digital supplies should be decoupled to AGND
and DGND respectively, with 100 nF ceramic capacitors in
parallel with 10 µF tantalum capacitors. T o achieve the best
from these decoupling capacitors, they should be placed as close
as possible to the device, ideally right up against the device. In
systems where a common supply voltage is used to drive both
the AVDD and DVDD of the AD7720, it is recommended that
the system’s AVDD supply is used. T his supply should have the
recommended analog supply decoupling between the AVDD
pin of the AD7720 and AGND and the recommended digital
supply decoupling capacitor between the DVDD pins and DGND.
D VAL
T he DVAL pin is used to indicate that an overrange input signal
has resulted in invalid data at the modulator output. As with all
single bit DAC high order sigma-delta modulators, large overloads
on the inputs can cause the modulator to go unstable. T he
modulator is designed to be stable with signals within the input
bandwidth that exceed full scale by 20%. When instability is
detected by internal circuits, the modulator is reset to a stable
state and DVAL is held low for 20 clock cycles.
Gr ounding and Layout
Since the analog inputs are differential, most of the voltages in
the analog modulator are common-mode voltages. T he excellent
REV. 0
–13–
AD7720
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
28-Lead Thin Shrink Sm all O utline
(RU-28)
0.386 (9.80)
0.378 (9.60)
15
28
1
14
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
–14–
REV. 0
–15–
–16–
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