AD7699BCPZRL7 [ADI]
16-Bit, 8-Channel, 500 kSPS PulSAR ADC; 16位， 8通道， 500 kSPS时的PulSAR ADC
| 型号： | AD7699BCPZRL7 |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 8-Channel, 500 kSPS PulSAR ADC |
| 文件： | 总28页 (文件大小：524K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, 8-Channel,
500 kSPS PulSAR ADC
AD7699
FEATURES
FUNCTIONAL BLOCK DIAGRAM
5V
0.5V TO 4.096V
0.1µF
0.5V TO VDD
10µF
16-bit resolution with no missing codes
8-channel multiplexer with choice of inputs
Unipolar single-ended
REFIN
REF
VDD
Differential (GND sense)
Pseudobipolar
Throughput: 500 kSPS
INL: 0.5 LSB typical, 1.5 LSB maximum ( 23 ppm or FSR)
Dynamic range: 93.3 dB
SINAD: 91.5 dB @ 20 kHz
THD: −97 dB @ 20 kHz
Analog input range: 0 V to VREF with VREF up to VDD
Multiple reference types
1.8V
TO
VDD
BAND GAP
REF
VIO
AD7699
TEMP
SENSOR
CNV
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
SCK
SDO
DIN
SPI SERIAL
INTERFACE
16-BIT SAR
ADC
MUX
ONE-POLE
LPF
SEQUENCER
COM
Internal 4.096 V
External buffered (up to 4.096 V)
External (up to VDD)
GND
Figure 1.
Internal temperature sensor
Channel sequencer, selectable 1-pole filter, busy indicator
No pipeline delay, SAR architecture
Single-supply 5 V operation with
1.8 V to 5 V logic interface
Table 1. Multichannel 14-/16-Bit PulSAR® ADC
Type
Channels 250 kSPS
500 kSPS ADC Driver
14-Bit
16-Bit
16-Bit
8
4
8
AD7949
AD7682
AD7689
ADA4841-x
ADA4841-x
ADA4841-x
Serial interface compatible with SPI, MICROWIRE,
QSPI, and DSP
AD7699
Power dissipation
26 mW @ 500 kSPS
GENERAL DESCRIPTION
The AD7699 is an 8-channel, 16-bit, charge redistribution
successive approximation register (SAR) analog-to-digital
converter (ADC) that operates from a single power supply, VDD.
5.2 μW @ 100 SPS
Standby current: 50 nA
20-lead 4 mm × 4 mm LFCSP package
The AD7699 contains all components for use in a multichannel,
low power data acquisition system, including a true 16-bit SAR
ADC with no missing codes; an 8-channel low crosstalk multip-
lexer useful for configuring the inputs as single-ended (with or
without ground sense), differential, or bipolar; an internal 4.096 V
low drift reference and buffer; a temperature sensor; a selectable
one-pole filter; and a sequencer that is useful when channels are
continuously scanned in order.
APPLICATIONS
Battery-powered equipment
Medical instruments: ECG/EKG
Mobile communications: GPS
Personal digital assistants
Power line monitoring
Data acquisition
Seismic data acquisition systems
Instrumentation
Process control
The AD7699 uses a simple serial port interface (SPI) for writing
to the configuration register and receiving conversion results.
The SPI interface uses a separate supply, VIO, which is set to the
host logic level. Power dissipation scales with throughput.
The AD7699 is housed in a tiny 20-lead LFCSP with operation
specified from −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD7699
TABLE OF CONTENTS
Features .............................................................................................. 1
Voltage Reference Output/Input .............................................. 18
Power Supply............................................................................... 19
Supplying the ADC from the Reference.................................. 19
Digital Interface.............................................................................. 20
Reading/Writing During Conversion, Fast Hosts.................. 20
Reading/Writing During Acquisition, Any Speed Hosts...... 20
Reading/Writing Spanning Conversion, Any Speed Host.... 20
Configuration Register, CFG.................................................... 20
General Timing Without a Busy Indicator ............................. 22
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
Overview...................................................................................... 13
Converter Operation.................................................................. 13
Transfer Functions...................................................................... 14
Typical Connection Diagrams.................................................. 15
Analog Inputs.............................................................................. 16
Driver Amplifier Choice............................................................ 18
Read/Write Spanning Conversion Without a Busy
Indicator ...................................................................................... 23
General Timing With a Busy Indicator................................... 24
Read/Write Spanning Conversion with a Busy Indicator..... 25
Application Hints ........................................................................... 26
Layout .......................................................................................... 26
Evaluating AD7699 Performance............................................. 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD7699
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VREF = 4.096 to VDD, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION
ANALOG INPUT
Voltage Range
16
Bits
Unipolar mode
Bipolar mode
Positive input, unipolar and bipolar modes
Negative or COM input, unipolar mode
Negative or COM input, bipolar mode
fIN = 250 kHz
0
+VREF
V
V
V
V
V
dB
nA
−VREF/2
−0.1
−0.1
+VREF/2
VREF + 0.1
+0.1
Absolute Input Voltage
Analog Input CMRR
Leakage Current at 25°C Input Acquisition phase
Impedance1
VREF/2 − 0.1 VREF/2 VREF/2 + 0.1
68
1
THROUGHPUT
Conversion Rate
Full Bandwidth2
¼ Bandwidth2
0
0
500
125
400
1600
kSPS
kSPS
ns
Transient Response
Full-scale step, full bandwidth
Full-scale step, ¼ bandwidth
ns
ACCURACY
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Transition Noise
16
−1.5
−1
Bits
0.5
+1.5
LSB3
LSB
0.25 +1.5
0.5
1
REF = VDD = 5 V
All modes
LSB
LSB
LSB
Gain Error4
−10
−3
+10
+3
Gain Error Match
1
Gain Error Temperature Drift
Offset Error4
Offset Error Match
Offset Error Temperature Drift
Power Supply Sensitivity
0.3
1
1
0.3
1.5
ppm/°C
LSB
LSB
ppm/°C
LSB
All modes
−10
−3
+10
+3
VDD = 5 V ± 5%
AC Accuracy
Dynamic Range
Signal-to-Noise
93.3
92.5
91.5
91.5
33.5
90.5
−97
112
dB5
dB
dB
dB
dB
dB
dB
dB
dB
fIN = 20 kHz, VREF = 5 V
fIN = 20 kHz, VREF = 4.096 V internal REF
fIN = 20 kHz, VREF = 5 V
fIN = 20 kHz, VREF = 5 V, −60 dB input
fIN = 20 kHz, VREF = 4.096 V internal REF
fIN = 20 kHz
92
89.5
90
SINAD
89
Total Harmonic Distortion
Spurious-Free Dynamic Range fIN = 20 kHz
Channel-to-Channel Crosstalk fIN = 100 kHz on adjacent channel(s)
SAMPLING DYNAMICS
−125
−3 dB Input Bandwidth
Full bandwidth
¼ bandwidth
VDD = 5 V
14
3.6
2.5
MHz
MHz
ns
Aperture Delay
Rev. 0 | Page 3 of 28
AD7699
Parameter
Conditions/Comments
Min
Typ
Max
Unit
INTERNAL REFERENCE
REF Output Voltage
REFIN Output Voltage6
REF Output Current
Temperature Drift
Line Regulation
@ 25°C
@ 25°C
4.086
4.096 4.106
V
V
µA
ppm/°C
ppm/V
ppm
ms
2.3
300
10
15
50
5
VDD = 5 V 5%
1000 hours
CREF = 10 µF
Long-Term Drift
Turn-On Settling Time
EXTERNAL REFERENCE
Voltage Range
REF input
REFIN input (buffered)
500 kSPS, REF = 5 V
0.5
0.5
VDD + 0.3
VDD − 0.2
V
V
µA
Current Drain
100
TEMPERATURE SENSOR
Output Voltage7
Temperature Sensitivity
@ 25°C
283
1
mV
mV/°C
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
−0.3
0.7 × VIO
−1
+0.3 × VIO
VIO + 0.3
+1
V
V
µA
µA
−1
+1
DIGITAL OUTPUTS
Data Format8
Pipeline Delay9
VOL
ISINK = +500 µA
ISOURCE = −500 µA
0.4
V
V
VOH
VIO − 0.3
POWER SUPPLIES
VDD
VIO
Standby Current10, 11
Power Dissipation
Specified performance
Specified performance
VDD and VIO = 5 V, @ 25°C
VDD = 5 V, 100 kSPS throughput
VDD = 5 V, 500 kSPS throughput
VDD = 5 V, 500 kSPS throughput with internal reference
4.5
1.8
5.5
VDD + 0.3
V
V
50
5.2
26
28
52
nA
µW
mW
mW
nJ
29
32
Energy per Conversion
TEMPERATURE RANGE12
Specified Performance
TMIN to TMAX
−40
+85
°C
1 See the Analog Inputs section.
2 The bandwidth is set with the configuration register.
3 LSB means least significant bit. With the 5 V input range, one LSB = 76.3 µV.
4 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the reference.
5 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
6 This is the output from the internal band gap.
7 The output voltage is internal and present on a dedicated multiplexer input.
8 Unipolar mode: serial 16-bit straight binary.
Bipolar mode: serial 16-bit twos complement.
9 Conversion results available immediately after completed conversion.
10 With all digital inputs forced to VIO or GND as required.
11 During acquisition phase.
12 Contact an Analog Devices, Inc., sales representative for the extended temperature range.
Rev. 0 | Page 4 of 28
AD7699
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VREF = 4.096 to VDD, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1
Symbol
tCONV
tACQ
Min
Typ
Max
Unit
µs
ns
µs
ns
µs
ns
ns
ns
ns
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width
Data Write/Read During Conversion
SCK Period
SCK Low Time
1.6
400
2
10
tCYC
tCNVH
tDATA
tSCK
1.2
tDSDO + 2
tSCKL
11
11
4
SCK High Time
tSCKH
tHSDO
tDSDO
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
16
17
18
21
28
ns
ns
ns
ns
ns
VIO Above 2.3 V
VIO Above 1.8 V
CNV Low to SDO D15 MSB Valid
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
tEN
15
17
18
22
25
32
ns
ns
ns
ns
ns
ns
ns
ns
ns
VIO Above 1.8 V
CNV High or Last SCK Falling Edge to SDO High Impedance
CNV Low to SCK Rising Edge
DIN Valid Setup Time from SCK Falling Edge
DIN Valid Hold Time from SCK Falling Edge
tDIS
tCLSCK
tSDIN
tHDIN
10
5
5
1 See Figure 2 and Figure 3 for load conditions.
I
500µA
OL
1.4V
TO SDO
C
L
50pF
500µA
I
OH
Figure 2. Load Circuit for Digital Interface Timing
70% VIO
30% VIO
tDELAY
tDELAY
1
1
2V OR VIO – 0.5V
2V OR VIO – 0.5V
2
2
0.8V OR 0.5V
0.8V OR 0.5V
1
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
2
Figure 3. Voltage Levels for Timing
Rev. 0 | Page 5 of 28
AD7699
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Analog Inputs
INx,1 COM1
Rating
GND − 0.3 V to VDD + 0.3 V
or VDD 130 mA
REF, REFIN
GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD, VIO to GND
VDD to VIO
−0.3 V to +7 V
7 V
ESD CAUTION
DIN, CNV, SCK to GND
SDO to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance (LFCSP)
θJC Thermal Impedance (LFCSP)
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
47.6°C/W
4.4°C/W
1 See the Analog Inputs section.
Rev. 0 | Page 6 of 28
AD7699
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
VDD
REF
REFIN
GND
1
2
3
4
5
15 VIO
14 SDO
13 SCK
12 DIN
11 CNV
AD7699
TOP VIEW
(Not to Scale)
GND
NOTES
1. THE EXPOSED PADDLE IS NOT CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS,
IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO
THE GND PLANE.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1, 20
2
Mnemonic Type1 Description
VDD
REF
P
AI/O
Power Supply. Nominally 4.5 to 5.5 V and should be decoupled with 10 μF and 100 nF capacitors.
Reference Input/Output. See the Voltage Reference Output/Input section.
When the internal reference is enabled, this pin produces 4.096 V. When the internal reference is disabled
and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin
(VDD – 0.5 V maximum) useful when using low cost, low power references.
For improved drift performance, connect a precision reference to REF (0.5 V to VDD).
For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as
close to REF as possible. See the Reference Decoupling section.
3
REFIN
AI/O
Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section.
When using the internal reference, the internal unbuffered reference voltage is present and needs
decoupling with a 0.1 μF capacitor.
When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is buffered to
the REF pin as previously described.
4, 5
GND
P
Power Supply Ground.
6 to 9
10
IN4 to IN7
COM
AI
AI
Analog Input Channel 4, Analog Input Channel 5, Analog Input Channel 6, and Analog Input Channel 7.
Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode point of 0 V
or VREF/2 V.
11
12
13
14
CNV
DIN
SCK
SDO
DI
Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held
high, the busy indictor is enabled.
Data Input. This input is used for writing to the 14-bit configuration register. The configuration register
can be written to during and after conversion.
Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an
MSB first fashion.
Serial Data Output. The conversion result is output on this pin and synchronized to SCK. In unipolar
modes, conversion results are straight binary; in bipolar modes, conversion results are twos
complement.
DI
DI
DO
15
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V,
3 V, or 5 V).
16 to 19
IN0 to IN3
AI
Analog Input Channel 0, Analog Input Channel 1, Analog Input Channel 2, and Analog Input Channel 3.
21 (EPAD)
Exposed
Paddle
(EPAD)
The exposed paddle is not connected internally. For increased reliability of the solder joints, it is
recommended that the pad be soldered to the GND plane.
1AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.
Rev. 0 | Page 7 of 28
AD7699
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 5V, VREF = 5V, VIO = VDD, unless otherwise noted
1.5
1.5
1.0
1.0
0.5
0
0.5
0
–0.5
–0.5
–1.0
–1.5
–1.0
0
16,384
32,768
49,152
65,536
0
16,384
32,768
49,152
65,536
CODES
CODES
Figure 5. Integral Nonlinearity vs. Code
Figure 8. Differential Nonlinearity vs. Code
250,000
200,000
250,000
200,000
σ = 0.51 LSB
σ = 0.78 LSB
V = 4.096V
REF
220,840
V
= 5V
REF
191,013
150,000
100,000
50,000
0
150,000
100,000
50,000
0
38,420
31,411
26,926
13,341
0
0
3
10
0
0
0
0
119
157
0
0
7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001
CODE IN HEX
7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001
CODE IN HEX
Figure 6. Histogram of a DC Input at Code Center
Figure 9. Histogram of a DC Input at Code Center
0
0
V
f
= 5V
= 500kSPS
= 19.94kHz
V
f
= 4.096V
= 500kSPS
= 19.94kHz
REF
REF
S
S
–20
–20
f
f
IN
IN
SNR = 92.3dB
SNR = 91.1dB
–40
–60
–80
–40
–60
–80
SINAD = 91.5dB
THD = –98dB
SFDR = 100dB
SECOND HARMONIC = –111dB
THIRD HARMONIC = –101dB
SINAD = 90.4dB
THD = –98dB
SFDR = 100dB
SECOND HARMONIC = –104dB
THIRD HARMONIC = –101dB
–100
–120
–140
–100
–120
–140
–160
–160
–180
0
–180
0
25
50
75
100 125 150 175 200 225 250
FREQUENCY (kHz)
25
50
75
100 125 150 175 200 225 250
FREQUENCY (kHz)
Figure 7. 20 kHz FFT, VREF = 5 V
Figure 10. 20 kHz FFT, VREF = 4.096 V
Rev. 0 | Page 8 of 28
AD7699
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
V
= 5V
V
= 5V
REF
REF
–10dB
–0.5dB
–10dB
–0.5dB
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY (kHz)
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY (kHz)
Figure 11. SNR vs. Frequency
Figure 14. SINAD vs. Frequency
16
15
14
13
12
11
10
–60
–65
–70
V
REF
= 5V
V
= 5V
REF
–10dB
–75
–80
–0.5dB
–10dB
–85
–90
–0.5dB
–95
–100
–105
–110
–115
–120
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY (kHz)
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY (kHz)
Figure 15. ENOB vs. Frequency
Figure 12. THD vs. Frequency
–80
115
96
94
92
fIN = 20kHz
SFDR, V
= 5V
REF
fIN = 20kHz
SNR, V
REF
= 5V
SINAD, V
= 5V
REF
SFDR,
–85
–90
110
105
100
95
V
= 4.096V
REF
90
88
86
SNR, V
REF
= 4.096V
THD, V
REF
= 5V
THD, V = 4.096V
REF
SINAD, V
REF
= 4.096V
–95
–100
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. THD, SFDR vs. Temperature
Figure 13. SNR, SINAD vs.Temperature
Rev. 0 | Page 9 of 28
AD7699
94
17
16
–80
–85
110
105
100
95
fIN = 20kHz
SNR
92
90
88
86
SFDR
THD
–90
–95
SINAD
ENOB
15
14
13
90
–100
–105
–110
85
80
4.0
4.5
5.0
5.5
4.0
4.5
5.0
5.5
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 17. SNR, SINAD, ENOB vs. Reference Voltage
Figure 20. THD, SFDR vs. Reference Voltage
95
94
93
92
91
90
89
88
87
86
85
15.6
15.5
15.4
15.3
15.2
15.1
15.0
14.9
14.8
14.7
14.6
5500
5250
5000
4750
4500
180
160
140
120
100
80
fIN = 20kHz
= 5V
fs = 500kSPS
V
, INT REF
V
DD
REF
SNR
SINAD
ENOB
V
, EXT REF
VIO
DD
60
40
20
125
–55
–35
–15
5
25
45
65
85
105
–10
–8
–6
–4
–2
0
TEMPERATURE (°C)
INPUT LEVEL (dB)
Figure 18. SNR, SINAD, and ENOB vs. Input Level
Figure 21. Operating Currents vs. Temperature
3
2
5750
5500
5250
5000
4750
4500
4250
4000
3750
100
90
80
70
60
50
40
30
20
fS = 500kSPS
4.096V INTERNAL REF
INTERNAL BUFFER, TEMP ON
INTERNAL BUFFER, TEMP OFF
UNIPOLAR GAIN
1
0
BIPOLAR GAIN
UNIPOLAR OFFSET
–1
BIPOLAR OFFSET
EXTERNAL REF, TEMP ON
EXTERNAL REF, TEMP OFF
–2
–3
VIO
–55
–35
–15
5
25
45
65
85
105
125
4.5
5.0
VDD SUPPLY (V)
5.5
TEMPERATURE (°C)
Figure 19. Offset and Gain Errors vs. Temperature, Not Normalized
Figure 22. Operating Currents vs. Supply
Rev. 0 | Page 10 of 28
AD7699
25
20
15
10
5
4.099
4.098
4.097
4.096
4.095
4.094
4.093
4.092
VDD = 5V, 85°C
VDD = 5V, 25°C
0
0
20
40
60
80
100
120
–55
–35
–15
5
25
45
65
85
105
125
SDO CAPACITIVE LOAD (pF)
TEMPERATURE (°C)
Figure 23. Internal Reference Output Voltage vs. Temperature, Three Devices
Figure 24. tDSDO Delay vs. SDO Capacitance Load and Supply
Rev. 0 | Page 11 of 28
AD7699
TERMINOLOGY
Signal-to-Noise Ratio (SNR)
Least Significant Bit (LSB)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
The LSB is the smallest increment that can be represented by a
converter. For an analog-to-digital converter with N bits of
resolution, the LSB expressed in volts is
VREF
LSB (V) =
2N
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 26).
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Differential Nonlinearity Error (DNL)
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the formula
Offset Error
For unipolar mode, the first transition should occur at a level
½ LSB above analog ground. The unipolar offset error is the
deviation of the actual transition from that point. For bipolar
mode, the first transition should occur at a level ½ LSB above
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
V
REF/2. The bipolar offset error is the deviation of the actual
Channel-to-Channel Crosstalk
transition from that point.
Channel-to-channel crosstalk is a measure of the level of crosstalk
between any two adjacent channels. It is measured by applying a
dc to the channel under test and applying a full-scale, 100 kHz
sine wave signal to the adjacent channel(s). The crosstalk is the
amount of signal that leaks into the test channel and is expressed
in decibels.
Gain Error
The last transition (from 111 … 10 to 111 … 11) should occur
for an analog voltage 1½ LSB below the nominal full scale. The
gain error is the deviation in LSB (or percentage of full-scale
range) of the actual level of the last transition from the ideal
level after the offset error is adjusted out. Closely related is the
full-scale error (also in LSB or percentage of full-scale range),
which includes the effects of the offset error.
Reference Voltage Temperature Coefficient
Reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at the
maximum and minimum reference output voltage (VREF) meas-
ured at TMIN, T (25°C), and TMAX. It is expressed in ppm/°C as
Aperture Delay
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and the
point at which the input signal is held for a conversion.
V
REF (Max)–VREF (Min)
TCVREF (ppm/°C) =
×106
V
REF (25°C) × (TMAX –TMIN )
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
where:
V
V
V
REF (Max) = maximum VREF at TMIN, T (25°C), or TMAX.
REF (Min) = minimum VREF at TMIN, T (25°C), or TMAX
REF (25°C) = VREF at 25°C.
.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels.
T
T
MAX = +85°C.
MIN = –40°C.
Rev. 0 | Page 12 of 28
AD7699
THEORY OF OPERATION
INx+
SWITCHES CONTROL
CONTROL
MSB
LSB
SW+
32,768C
16,384C
4C
4C
2C
2C
C
C
C
C
BUSY
REF
COMP
LOGIC
GND
OUTPUT CODE
32,768C
16,384C
MSB
LSB
SW–
CNV
INx– OR
COM
Figure 25. ADC Simplified Schematic
OVERVIEW
CONVERTER OPERATION
The AD7699 is an 8-channel, 16-bit, charge redistribution
successive approximation register (SAR) analog-to-digital
converter (ADC). It is capable of converting 500,000 samples
per second (500 kSPS) and power down between conversions.
For example, when operating with an external reference at
1 kSPS, it consumes 52 µW typically, ideal for battery-powered
applications.
The AD7699 is a successive approximation ADC based on a
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator input are connected to GND via SW+ and SW−. All
independent switches are connected to the analog inputs.
The AD7699 contains all of the components for use in a
multichannel, low power data acquisition system, including
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the INx+ and INx− (or COM)
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated. When the
conversion phase begins, SW+ and SW− are opened first. The
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the INx+ and INx− (or COM) inputs captured at the
end of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between GND and REF, the
comparator input varies by binary-weighted voltage steps
(VREF/2, VREF/4, ... VREF/32,768). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase, and the control logic
generates the ADC output code and a busy signal indicator.
•
•
•
•
•
•
16-bit SAR ADC with no missing codes
8-channel, low crosstalk multiplexer
Internal low drift reference and buffer
Temperature sensor
Selectable one-pole filter
Channel sequencer
These components are configured through an SPI-compatible,
14-bit register. Conversion results, also SPI compatible, can be
read after or during conversions with the option for reading
back the configuration.
The AD7699 provides the user with an on-chip track-and-hold
and does not exhibit pipeline delay or latency.
The AD7699 is specified from 4.5 V to 5.5 V and can be interfaced
to any 1.8 V to 5 V digital logic family. It is housed in a 20-lead,
4 mm × 4 mm LFCSP that combines space savings and allows
flexible configurations and is also pin-for-pin compatible with
the 16-bit AD7682 and AD7689, and the 14-bit AD7949.
Because the AD7699 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Rev. 0 | Page 13 of 28
AD7699
TRANSFER FUNCTIONS
TWOS
COMPLEMENT
STRAIGHT
BINARY
With the inputs configured for unipolar range (single ended,
COM with ground sense, or paired differentially with INx− as
ground sense), the data output is straight binary.
011...111 111...111
011...110 111...110
011...101 111...101
With the inputs configured for bipolar range (COM = VREF/2 or
paired differentially with INx− = VREF/2), the data outputs are
twos complement.
The ideal transfer characteristic for the AD7699 is shown in
Figure 26 and for both unipolar and bipolar ranges with the
internal 4.096 V reference.
100...010 000...010
100...001 000...001
100...000 000...000
–FSR
–FSR + 1LSB
+FSR – 1LSB
+FSR – 1.5LSB
–FSR + 0.5LSB
ANALOG INPUT
Figure 26. ADC Ideal Transfer Function
Table 6. Output Codes and Ideal Input Voltages
Unipolar Analog Input1
VREF = 4.096 V
Digital Output Code
(Straight Binary Hex)
0xFFFF3
0x8001
0x8000
Bipolar Analog Input2
VREF = 4.096 V
Digital Output Code
(Twos Complement Hex)
0x7FFF3
0x0001
0x0000
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
4.095938 V
2.048063 V
2.048 V
2.047938 V
62.5 μV
0 V
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
2.047938 V
62.5 μV
0 V
0x7FFF
0x0001
0x00003
−62.5 μV
−2.047938 V
−2.048 V
0xFFFF4
0x8001
0x8000
1 With COM or INx− = 0 V or all INx referenced to GND.
2 With COM or INx− = VREF/2.
3 This is also the code for an overranged analog input ((INx+) − (INx−), or COM, above VREF − VGND).
4 This is also the code for an underranged analog input ((INx+) − (INx−), or COM, below VGND).
Rev. 0 | Page 14 of 28
AD7699
TYPICAL CONNECTION DIAGRAMS
5V
1.8V TO VDD
100nF
100nF
100nF
2
10µF
V+
REFIN VDD
REF
VIO
0V TO V
REF
3
ADA4841-x
IN0
V–
V+
DIN
SCK
SDO
CNV
MOSI
SCK
IN[7:1]
AD7699
MISO
SS
0V TO V
REF
3
ADA4841-x
V–
0V OR
COM
V
/2
REF
GND
NOTES
1. INTERNAL REFERENCE SHOWN. SEE THE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR
REFERENCE SELECTION.
2. C
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
REF
3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.
4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.
Figure 27. Typical Application Diagram with Multiple Supplies
5V
1.8V TO VDD
100nF
100nF
100nF
2
10µF
V+
REFIN VDD
REF
VIO
3
ADA4841-x
IN0
V+
DIN
SCK
SDO
CNV
MOSI
SCK
IN[7:1]
AD7699
MISO
SS
3
ADA4841-x
V
p-p
REF
COM
GND
V
/2
REF
NOTES
1. INTERNAL REFERENCE SHOWN. SEE THE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR
REFERENCE SELECTION.
2. C
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
REF
3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.
4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.
Figure 28. Typical Application Diagram Using Bipolar Input
Rev. 0 | Page 15 of 28
AD7699
70
65
60
55
50
45
40
35
30
Unipolar or Bipolar
Figure 27 shows an example of the recommended connection
diagram for the AD7699 when multiple supplies are available.
Bipolar Single Supply
Figure 28 shows an example of a system with a bipolar input
using single supplies with the internal reference (optional
different VIO supply). This circuit is also useful when the
amplifier/signal conditioning circuit is remotely located with
some common mode present. Note that for any input config-
uration, the inputs, INx, are unipolar and always referenced to
GND (no negative voltages even in bipolar range).
1
10
100
1k
10k
For this circuit, a rail-to-rail input/output amplifier can be used;
however, the offset voltage vs. input common-mode range should
be noted and taken into consideration (1 LSB = 62.5 μV with
FREQUENCY (kHz)
Figure 30. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog inputs
can be modeled as a parallel combination of the capacitor, CPIN
V
REF = 4.096 V). Note that the conversion results are in twos
,
complement format when using the bipolar input configuration.
Refer to the AN-581 Application Note, Biasing and Decoupling
Op Amps in Single Supply Applications, at www.analog.com for
additional details about using single-supply amplifiers.
and the network formed by the series connection of RIN and CIN.
PIN is primarily the pin capacitance. RIN is typically 400 Ω (8.8 kΩ
C
when the one-pole filter is active) and is a lumped component
made up of serial resistors and the on resistance of the switches.
ANALOG INPUTS
Input Structure
C
IN is typically 27 pF and is mainly the ADC sampling capacitor.
Selectable Low-Pass Filter
Figure 29 shows an equivalent circuit of the input structure of
the AD7699. The two diodes, D1 and D2, provide ESD
protection for the analog inputs, IN[7:0] and COM. Care must
be taken to ensure that the analog input signal does not exceed
the supply rails by more than 0.3 V because this causes the
diodes to become forward-biased and to start conducting
current.
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. While the AD7699 is
acquiring, RIN and CIN make a one-pole, low-pass filter that
reduces undesirable aliasing effects and limits the noise from
the driving circuitry. The low-pass filter can be programmed
for the full bandwidth or ¼ of the bandwidth with CFG[6], as
shown in Table 8. Note that the converter throughput must also be
reduced by ¼ when using the filter. If the maximum throughput
is used with the BW set to ¼, the acquisition time of the
converter, tACQ, is violated, resulting in poor THD.
These diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions may eventually occur
when the input buffer supplies are different from VDD. In such
a case, for example, an input buffer with a short circuit, the
current limitation can be used to protect the part.
VDD
Input Configurations
Figure 31 shows the different methods for configuring the analog
inputs with the configuration register (CFG[12:10]). Refer to
the Configuration Register, CFG section for more details.
D1
D2
INx+
OR INx–
OR COM
C
IN
R
IN
C
PIN
GND
Figure 29. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the true
differential signal between INx+ and COM or INx+ and INx−.
(COM or INx− = GND 0.1 V or VREF 0.1 V). By using these
differential inputs, signals common to both inputs are rejected,
as shown in Figure 30.
Rev. 0 | Page 16 of 28
AD7699
Sequencer
CH0+
CH1+
CH2+
CH0+
CH1+
CH2+
IN0
IN1
IN2
IN3
IN0
IN1
IN2
IN3
The AD7699 includes a channel sequencer useful for scanning
channels in a IN0 to IN[7:0] fashion. Channels are scanned as
singles or pairs, with or without the temperature sensor, after
the last channel is sequenced.
CH3+
CH4+
CH5+
CH6+
CH7+
CH3+
CH4+
CH5+
CH6+
CH7+
COM–
IN4
IN5
IN4
IN5
The sequencer starts with IN0 and finishes with IN[7:0] set in
CFG[9:7]. For paired channels, the channels are paired
depending on the last channel set in CFG[9:7]. Note that the
channel pairs are always paired as IN (even) = INx+ and IN
(odd) = INx− regardless of CFG[7].
IN6
IN6
IN7
IN7
COM
GND
COM
GND
B—8 CHANNELS,
COMMON REFERENCE
A—8 CHANNELS,
SINGLE ENDED
To enable the sequencer, CFG[2:1] are written to for initializing
the sequencer. After CFG[13:0] are updated, DIN must be held
low while reading data out (at least for Bit 13), or the CFG register
begins updating again.
CH0+ (–)
CH0– (+)
CH1+ (–)
CH1– (+)
CH0+ (–)
IN0
IN1
IN2
IN3
IN0
IN1
IN2
IN3
CH0– (+)
CH1+ (–)
CH1– (+)
While operating in a sequence, the CFG register can be changed
by writing 012 to CFG[2:1]. However, if changing CFG11 (paired
or single channel) or CFG[9:7] (last channel in sequence), the
sequence reinitializes and converts IN0 (or IN1) after CFG is
updated.
CH2+ (–)
CH2– (+)
CH2+
CH3+
CH4+
CH5+
COM–
IN4
IN5
IN4
IN5
IN6
IN7
CH3+ (–)
CH3– (+)
IN6
IN7
Examples
COM
GND
COM
GND
Bit[13], Bits[6:3], and Bit 0 are configured for the input and
sequencer.
C—4 CHANNELS,
DIFFERENTIAL
D—COMBINATION
As a first example, scan all IN[7:0] referenced to COM = GND
with the temperature sensor.
Figure 31. Multiplexed Analog Input Configurations
13
12 11 10
9
8
INx
1
7
6
5
4
3
2
1
0
The analog inputs can be configured as
CFG
INCC
BW
REF
SEQ
RB
•
Figure 31A, single-ended referenced to system ground;
CFG[12:10] = 1112.
1
1
0
1
1
1
0
As a second example, scan three paired channels without the
temperature sensor and referenced to VREF/2.
•
Figure 31B, bipolar differential with a common reference
point; COM = VREF/2; CFG[12:10] = 0102.
Unipolar differential with COM connected to a ground
sense; CFG[12:10] = 1102.
13
12 11 10
9
8
7
6
5
4
3
2
1
0
CFG
INCC
INx
0
BW
REF
SEQ
RB
0
0
X1
1
X1
1
1
•
•
Figure 31C, bipolar differential pairs with INx− referenced
to VREF/2; CFG[12:10] = 00X2.
Unipolar differential pairs with INx− referenced to a
ground sense; CFG[12:10] = 10X2.
In this configuration, the INx+ is identified by the channel
in CFG[9:7]. For example, for IN0 = IN1+ and IN1 =
IN1−, CFG[9:7] = 0002; for IN1 = IN1+ and IN0 = IN1−,
CFG[9:7] = 0012.
Figure 31D, inputs configured in any of the above
combinations (showing that the AD7699 can be configured
dynamically).
1 X = don’t care.
Source Resistance
When the source impedance of the driving circuit is low, the
AD7699 can be driven directly. Large source impedances signifi-
cantly affect the ac performance, especially total harmonic
distortion (THD). The dc performances are less sensitive to the
input impedance. The maximum source impedance depends on
the amount of THD that can be tolerated. The THD degrades as a
function of the source impedance and the maximum input
frequency.
Rev. 0 | Page 17 of 28
AD7699
described in Table 8 with more details in each of the following
sections.
DRIVER AMPLIFIER CHOICE
Although the AD7699 is easy to drive, the driver amplifier must
meet the following requirements:
Internal Reference/Temperature Sensor
The internal reference can be set for a 4.096 V output as
detailed in Table 8. With the internal reference enabled, the
band gap voltage is also present on the REFIN pin, which
requires an external 0.1 μF capacitor. Because the current
output of REFIN is limited, it can be used as a source if followed
by a suitable buffer, such as the AD8605.
•
The noise generated by the driver amplifier must be kept
as low as possible to preserve the SNR and transition noise
performance of the AD7699. Note that the AD7699 has a
noise much lower than most of the other 16-bit ADCs and,
therefore, can be driven by a noisier amplifier to meet a given
system noise specification. The noise from the amplifier is
filtered by the AD7699 analog input circuit low-pass filter
made by RIN and CIN or by an external filter, if one is used.
Because the typical noise of the AD7699 is 35 µV rms (with
Enabling the reference also enables the internal temperature
sensor, which measures the internal temperature of the AD7699
and is thus useful for performing a system calibration. Note
that, when using the temperature sensor, the output is straight
binary referenced from the AD7699 GND pin.
V
REF = 5 V), the SNR degradation due to the amplifier is
The internal reference is temperature-compensated to within
15 m V. The reference is trimmed to provide a typical drift of
3 ppm/°C.
35
SNRLOSS = 20log
π
2
352 + f−3dB (NeN )2
External Reference and Internal Buffer
where:
−3dB is the input bandwidth in megahertz of the AD7699
For improved drift performance, an external reference can be
used with the internal buffer. The external reference is connected
to REFIN, and the output is produced on the REF pin. An
external reference can be used with the internal buffer with or
without the temperature sensor enabled. Refer to Table 8 for
register details. With the buffer enabled, the gain is unity and is
limited to an input/output of 4.096 V.
f
(14.7 MHz in full BW or 670 kHz in ¼ BW) or the cutoff
frequency of an input filter, if one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.
The internal reference buffer is useful in multiconverter applica-
tions because a buffer is typically required in these applications. In
addition, a low power reference can be used because the internal
buffer provides the necessary performance to drive the SAR
architecture of the AD7699.
•
•
For ac applications, the driver should have a THD perfor-
mance commensurate with the AD7699. Figure 12 shows
THD vs. frequency for the AD7699.
For multichannel, multiplexed applications on each input
or input pair, the driver amplifier and the AD7699 analog
input circuit must settle a full-scale step onto the capacitor
array at a 16-bit level (0.0015%). In amplifier data sheets,
settling at 0.1% to 0.01% is more commonly specified. This
may differ significantly from the settling time at a 16-bit
level and should be verified prior to driver selection.
External Reference
In any of the five voltage reference schemes, an external refer-
ence can be connected directly on the REF pin because the output
impedance of REF is >5 kΩ. To reduce power consumption, the
reference and buffer can be powered down independently or
together for the lowest power consumption. However, for applica-
tions requiring the use of the temperature sensor, the reference
must be active. Refer to Table 8 for register details. For improved
drift performance, an external reference such as the ADR43x or
ADR44x is recommended.
Table 7. Recommended Driver Amplifiers
Amplifier
ADA4841-x
AD8655
AD8021
AD8022
OP184
Typical Application
Very low noise, small, and low power
5 V single supply, low noise
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
Reference Decoupling
Whether using an internal or external reference, the AD7699
voltage reference output/input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins. This decoupling depends on the choice of the voltage
reference but usually consists of a low ESR capacitor connected
to REF and GND with minimum parasitic inductance. A 10 µF
(X5R, 1206 size) ceramic chip capacitor is appropriate when
using the internal reference, the ADR43x/ADR44x external
AD8605, AD8615 5 V single supply, low power
VOLTAGE REFERENCE OUTPUT/INPUT
The AD7699 allows the choice of a very low temperature drift
internal voltage reference, an external reference, or an external
buffered reference.
The internal reference of the AD7699 provides excellent
performance and can be used in almost all applications. There
are five possible choices of voltage reference schemes briefly
Rev. 0 | Page 18 of 28
AD7699
reference, or a low impedance buffer such as the AD8031 or the
AD8605.
The AD7699 powers down automatically at the end of each
conversion phase; therefore, the operating currents and power
scale linearly with the sampling rate. This makes the part ideal
for low sampling rates (even of a few hertz) and low battery-
powered applications.
The placement of the reference decoupling capacitor is also
important to the performance of the AD7699, as explained in the
Layout section. Mount the decoupling capacitor on the same side
as the ADC at the REF pin with a thick PCB trace. The GND
should also connect to the reference decoupling capacitor with
the shortest distance and to the analog ground plane with
several vias.
10,000
1000
100
10
VDD = 5V, INTERNAL REF
VDD = 5V, EXTERNAL REF
If desired, smaller reference decoupling capacitor values down
to 2.2 µF can be used with a minimal impact on performance,
especially on DNL.
1
VIO
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
0.1
0.010
0.001
For applications that use multiple AD7699s or other PulSAR
devices, it is more effective to use the internal reference buffer
to buffer the external reference voltage, thus reducing SAR
conversion crosstalk.
10
100
1k
10k
100k
1M
SAMPLING RATE (sps)
Figure 33. Operating Currents vs. Sampling Rate
SUPPLYING THE ADC FROM THE REFERENCE
The voltage reference temperature coefficient (TC) directly
impacts full scale; therefore, in applications where full-scale
accuracy matters, care must be taken with the TC. For instance,
For simplified applications, the AD7699, with its low operating
current, can be supplied directly using the reference circuit, as
shown in Figure 34. The reference line can be driven by
a
15 ppm/°C TC of the reference changes full scale by 1 LSB/°C.
•
•
The system power supply directly
A reference voltage with enough current output capability,
such as the ADR43x/ADR44x
A reference buffer, such as the AD8605, which can also
filter the system power supply, as shown in Figure 34
POWER SUPPLY
The AD7699 uses two power supply pins: an analog and digital
core supply (VDD) and a digital input/output interface supply
(VIO). VIO allows direct interface with any logic between 1.8 V
and VDD. To reduce the supplies needed, the VIO and VDD
pins can be tied together. The AD7699 is independent of power
supply sequencing between VIO and VDD. The only restriction
is that CNV must be low when powering up the AD7699.
Additionally, it is very insensitive to power supply variations
over a wide frequency range, as shown in Figure 32.
75
•
5V
5V
10Ω
5V 10kΩ
1µF
1µF
0.1µF
0.1µF
10µF
AD8605
1
REF
VDD
VIO
70
65
60
55
50
45
40
35
30
AD7699
1
OPTIONAL REFERENCE BUFFER AND FILTER.
Figure 34. Example of an Application Circuit
1
10
100
1k
10k
FREQUENCY (kHz)
Figure 32. PSRR vs. Frequency
Rev. 0 | Page 19 of 28
AD7699
DIGITAL INTERFACE
The AD7699 uses a simple 4-wire interface and is compatible
with SPI, MICROWIRE™, QSPI™, digital hosts, and DSPs, for
example, Blackfin® ADSP-BF53x, SHARC®, ADSP-219x, and
ADSP-218x.
The SCK frequency required is calculated by
Number _SCK _ Edges
f
SCK
t
DATA
The time between tDATA and tCONV is a safe time when digital
activity should not occur, or sensitive bit decisions may be
corrupt.
The interface uses the CNV, DIN, SCK, and SDO signals and
allows CNV, which initiates the conversion, to be independent
of the readback timing. This is useful in low jitter sampling or
simultaneous sampling applications.
READING/WRITING DURING ACQUISITION, ANY
SPEED HOSTS
A 14-bit register, CFG[13:0], is used to configure the ADC for
the channel to be converted, the reference selection, and other
components, which are detailed in the Configuration Register,
CFG section.
When reading/writing after conversion, or during acquisition
(n), conversion results are for the previous (n − 1) conversion,
and writing is for the (n + 1) acquisition.
When CNV is low, reading/writing can occur during conversion,
acquisition, and spanning conversion (acquisition plus conver-
sion), as detailed in the following sections. The CFG word is
updated on the first 14 SCK rising edges, and conversion results
are output on the first 15 (or 16 if busy mode is selected) SCK
falling edges. If the CFG readback is enabled, an additional
14 SCK falling edges are required to output the CFG word
associated with the conversion results, with the CFG MSB
following the LSB of the conversion result.
For the maximum throughput, the only time restriction is that
the reading/writing take place during the tACQ (min) time. For
slow throughputs, the time restriction is dictated by throughput
required by the user, and the host is free to run at any speed.
Thus for slow hosts, data access must take place during the
acquisition phase.
READING/WRITING SPANNING CONVERSION, ANY
SPEED HOST
When reading/writing spanning conversion, the data access starts
at the current acquisition (n) and spans into the conversion (n).
Conversion results are for the previous (n − 1) conversion, and
writing the CFG register is for the next (n + 1) acquisition and
conversion.
A discontinuous SCK is recommended because the part is
selected with CNV low, and SCK activity begins to write a new
configuration word and clock out data.
Note that in the following sections, the timing diagrams indicate
digital activity (SCK, CNV, DIN, SDO) during the conversion.
However, due to the possibility of performance degradation,
digital activity should occur only prior to the safe data reading/
writing time, tDATA, because the AD7699 provides error correction
circuitry that can correct for an incorrect bit during this time.
From tDATA to tCONV, there is no error correction and conversion
results may be corrupted. The user should configure the AD7699
and initiate the busy indicator (if desired) prior to tDATA. It is also
possible to corrupt the sample by having SCK or DIN transitions
near the sampling instant. Therefore, it is recommended to keep
the digital pins quiet for approximately 30 ns before and 10 ns
after the rising edge of CNV, using a discontinuous SCK whenever
possible to avoid any potential performance degradation.
Similar to reading/writing during conversion, reading/writing
should only occur up to tDATA. For the maximum throughput,
the only time restriction is that reading/writing take place
during the tACQ (min) + tDATA time.
For slow throughputs, the time restriction is dictated by the
user’s required throughput, and the host is free to run at any
speed. Similar to reading/writing during acquisition, for slow
hosts, the data access must take place during the acquisition
phase with additional time into the conversion.
Note that data access spanning conversion requires the CNV to
be driven high to initiate a new conversion, and data access is
not allowed when CNV is high. Thus, the host must perform
two bursts of data access when using this method.
READING/WRITING DURING CONVERSION, FAST
HOSTS
CONFIGURATION REGISTER, CFG
When reading/writing during conversion (n), conversion
results are for the previous (n − 1) conversion, and writing the
CFG is for the next (n + 1) acquisition and conversion.
The AD7699 uses a 14-bit configuration register (CFG[13:0]) as
detailed in Table 8 for configuring the inputs, the channel to be
converted, one-pole filter bandwidth, the reference, and the
channel sequencer. The CFG register is latched (MSB first) on
DIN with 14 SCK rising edges. CFG update is edge dependent,
allowing for asynchronous or synchronous hosts.
After the CNV is brought high to initiate conversion, it must be
brought low again to allow reading/writing during conversion.
Reading/writing should only occur up to tDATA and, because this
time is limited, the host must use a fast SCK.
Rev. 0 | Page 20 of 28
AD7699
The register can be written to during conversion, during acquisi-
tion, or spanning acquisition/conversion and is updated at the
end of conversion, tCONV (maximum). There is always a one deep
delay when writing the CFG register. Note that at power-up, the
CFG register is undefined and two dummy conversions are
required to update the register. To preload the CFG register
with a factory setting, hold DIN high for two conversions. Thus
CFG[13:0] = 0x3FFF. This sets the AD7699 for the following:
•
•
•
IN[7:0] unipolar referenced to GND, sequenced in order
Full bandwidth for a one-pole filter
Internal reference/temperature sensor disabled, buffer
enabled
Enables the sequencer
No readback of the CFG register
•
•
Table 8 summarizes the configuration register bit details. See
the Theory of Operation section for more details.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CFG
INCC
INCC
INCC
INx
INx
INx
BW
REF
REF
REF
SEQ
SEQ
RB
Table 8. Configuration Register Description
Bit(s)
[13]
Name Description
CFG Configuration update.
0 = Keep current configuration settings.
1 = Overwrite contents of register.
[12:10] INCC
Input channel configuration. Selection of pseudobipolar, pseudodifferential, pairs, single-ended, or temperature sensor. Refer to
the Input Configurations section.
Bit 12
Bit 11
Bit 10
Function
0
0
0
1
1
1
0
1
1
0
1
1
X1
0
Bipolar differential pairs; INx− referenced to VREF/2 0.1 V.
Bipolar; INx referenced to COM = VREF/2 0.1 V.
Temperature sensor.
Unipolar differential pairs; INx− referenced to GND 0.1 V.
Unipolar, IN0 to IN7 referenced to COM = GND 0.1 V (GND sense).
Unipolar, IN0 to IN7 referenced to GND.
1
X1
0
1
[9:7]
INx
Input channel selection in binary fashion.
Bit 9
0
Bit 8
0
Bit 7
0
Channel
IN0
0
0
1
IN1
…
1
…
1
…
1
…
IN7
[6]
BW
REF
Select bandwidth for low-pass filter. Refer to the Selectable Low-Pass Filter section.
0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughput must also be reduced to ¼.
1 = Full BW.
[5:3]
Reference/buffer selection. Selection of internal, external, and external buffered references, and enabling of the on-chip
temperature sensor. Refer to the Voltage Reference Output/Input section.
Bit 5
Bit 4
Bit 3
Function
0
0
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
Not used
Internal reference, REF = 4.096 V output.
External reference, temperature enabled.
External reference, internal buffer, temperature enabled.
External reference, temperature disabled.
External reference, internal buffer, temperature disabled.
[2:1]
SEQ
Channel sequencer. Allows for scanning channels in an IN0 to IN[7:0] fashion. Refer to the Sequencer section.
Bit 2
Bit 1
Function
0
0
1
1
0
1
0
1
Disable sequencer.
Update configuration during sequence.
Scan IN0 to IN[7:0] (set in CFG[9:7]), then temperature.
Scan IN0 to IN[7:0] (set in CFG[9:7]).
0
RB
Read back the CFG register.
0 = Read back current configuration at end of data.
1 = Do not read back contents of configuration.
1 X = don’t care.
Rev. 0 | Page 21 of 28
AD7699
MSB of the current conversion. For detailed timing, refer to
Figure 36 and Figure 37, which depict reading/writing spanning
conversion with all timing details, including setup, hold, and SCK.
GENERAL TIMING WITHOUT A BUSY INDICATOR
Figure 35 details the timing for all three modes: reading/writing
during conversion, after conversion, and spanning conversion.
Note that the gating item for both CFG and data readback is at
the end of conversion (EOC). At the end of conversions (EOC),
if CNV is high, the busy indicator is disabled.
When CNV is brought low after EOC, SDO is driven from high
impedance to the MSB. Falling SCK edges clock out bits starting
with MSB − 1.
The SCK can idle high or low depending on the clock polarity
(CPOL) and clock phase (CPHA) settings if SPI is used. A simple
solution is to use CPOL = CPHA = 0 as shown in Figure 35 with
SCK idling low.
As detailed previously, the data access should occur up to safe
data reading/writing time, tDATA. If the full CFG word was not
written to prior to EOC, it is discarded and the current
configuration remains. If the conversion result is not read out
fully prior to EOC, it is lost as the ADC updates SDO with the
START OF CONVERSION
tCYC
tCONV
END OF CONVERSION (EOC)
EOC
EOC
POWER
UP
tDATA
ACQUISITION
(n – 1)
ACQUISITION
(n)
ACQUISITION
(n + 1)
ACQUISITION
(n + 2)
CONVERSION (n – 2)
CONVERSION (n – 1)
CONVERSION (n)
CONVERSION (n + 1)
PHASE
CNV
DIN
XXX
XXX
CFG (n)
CFG (n + 1)
CFG (n + 2)
DATA (n)
MSB
(n + 1)
MSB
(n – 2)
MSB
(n – 1)
MSB
(n)
DATA (n – 2)
DATA (n – 1)
SDO
SCK
1
16/30
1
16/30
1
16/30
1
16/30
CNV
CFG (n)
CFG (n + 1)
CFG (n + 2)
CFG (n + 3)
DIN
SDO
SCK
DATA
(n – 2)
DATA
(n – 1)
DATA (n)
16/30
DATA (n + 1)
1
16/30
1
16/30
1
1
CNV
CFG (n)
CFG (n + 1)
CFG (n + 2)
CFG (n + 3)
DIN
SDO
SCK
DATA
(n – 2)
DATA
DATA
(n – 1)
DATA
(n – 1)
DATA
(n + 1)
DATA (n)
DATA (n)
16/30
(n – 2)
1
1
16/30
1
16/30
1
NOTES
1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.
A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK
IS ENABLED, A TOTAL OF 30 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.
Figure 35. General Interface Timing for the AD7699 Without a Busy Indicator
Rev. 0 | Page 22 of 28
AD7699
the CFG update. While CNV is low, both a CFG update and a
data readback take place. The first 14 SCK rising edges are used
to update the CFG, and the first 15 SCK falling edges clock out
the conversion results starting with MSB − 1. The restriction
for both configuring and reading is that they both must occur
before the tDATA time of the next conversion elapses. All 14 bits
of CFG[13:0] must be written, or they are ignored. In addition,
if the 16-bit conversion result is not read back before tDATA elapses,
it is lost.
READ/WRITE SPANNING CONVERSION WITHOUT
A BUSY INDICATOR
This mode is used when the AD7699 is connected to any host
using an SPI, serial port, or FPGA. The connection diagram is
shown in Figure 36, and the corresponding timing is given in
Figure 37. For SPI, the host should use CPHA = CPOL = 0.
Reading/writing spanning conversion is shown, which covers
all three modes detailed in the Digital Interface section. For this
mode, the host must generate the data transfer based on the
conversion time. For an interrupt driven transfer, refer to the
next section, which uses a busy indicator.
The SDO data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the 16th (or 30th) SCK falling edge, or
when CNV goes high (whichever occurs first), SDO returns to
high impedance.
A rising edge on CNV initiates a conversion, forces SDO to
high impedance, and ignores data present on DIN. After a
conversion is initiated, it continues until completion irrespective
of the state of CNV. CNV must be returned high before the safe
data transfer time, tDATA, and then held high beyond the conver-
sion time, tCONV, to avoid generation of the busy signal indicator.
If CFG readback is enabled, the CFG associated with the conver-
sion result is read back MSB first following the LSB of the
conversion result. A total of 30 SCK falling edges is required to
return SDO to high impedance if this is enabled.
After the conversion is complete, the AD7699 enters the acquisi-
tion phase and powers down. When the host brings CNV low
after tCONV (max), the MSB is enabled on SDO. The host also
must enable the MSB of CFG at this time (if necessary) to begin
DIGITAL HOST
AD7699
CNV
SDO
SS
MISO
MOSI
SCK
DIN
SCK
FOR SPI USE CPHA = 0, CPOL = 0.
Figure 36. Connection Diagram for the AD7699 Without a Busy Indicator
tCYC
>
tCONV
tCONV
tDATA
tCONV
tDATA
tCNVH
RETURN CNV HIGH
FOR NO BUSY
RETURN CNV HIGH
FOR NO BUSY
CNV
tACQ
(QUIET
TIME)
(QUIET
TIME)
ACQUISITION
(n + 1)
ACQUISITION
(n – 1)
CONVERSION (n)
ACQUISITION (n)
CONVERSION (n – 1)
tSCK
UPDATE (n + 1)
CFG/SDO
UPDATE (n)
tSCKH
SEE NOTE
CFG/SDO
tCLSCK
16/
30
16/
30
SCK
DIN
1
14
15
2
14
15
X
tSCKL
tSDIN
tHDIN
CFG
MSB – 1
CFG
LSB
CFG
LSB
CFG
MSB
X
X
X
tHSDO
tDSDO
tEN
END CFG (n + 1)
tEN
tEN
END CFG (n)
BEGIN CFG (n + 1)
SEE NOTE
tDIS
SDO
LSB
MSB MSB – 1
BEGIN DATA (n – 1)
LSB + 1 LSB
END DATA (n – 1)
LSB + 1
tDIS
tDIS
tDIS
NOTES
END DATA (n – 2)
1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF.
15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
Figure 37. Serial Interface Timing for the AD7699 Without a Busy Indicator
Rev. 0 | Page 23 of 28
AD7699
fully prior to EOC, the last bit clocked out remains. If this bit is
low, the busy signal indicator cannot be generated because the
digital output requires a high impedance, or a bit remaining high,
to low transition for the interrupt input of the host. A good
example of this occurs when an SPI host sends 16 SCKs because
these are usually limited to 8-bit or 16-bit bursts, thus the LSB
remains. Because the transition noise of the AD7699 is 4 LSBs
peak to peak (or greater), the LSB is low 50% of the time. For
this interface, the SPI host needs to burst 24 SCKs, or a QSPI
interface can be used and programmed for 17 SCKs.
GENERAL TIMING WITH A BUSY INDICATOR
Figure 38 details the timing for all three modes: reading/writing
during conversion, after conversion, and spanning conversion.
Note that the gating item for both CFG and data readback is at
the end of conversion (EOC). As detailed previously, the data
access should occur up to safe data reading/writing time, tDATA
If the full CFG word is not written to prior to EOC, it is
discarded and the current configuration remains.
.
At the EOC, if CNV is low, the busy indicator is enabled. In
addition, to generate the busy indicator properly, the host must
assert a minimum of 17 SCK falling edges to return SDO to
high impedance because the last bit of data on SDO remains
active. Unlike the case detailed in the General Timing Without
a Busy Indicator section, if the conversion result is not read out
The SCK can idle high or low depending on the CPOL and
CPHA settings if SPI is used. A simple solution is to use CPOL
= CPHA = 1 (not shown) with SCK idling high.
START OF CONVERSION
tCYC
tCONV
END OF CONVERSION (EOC)
EOC
EOC
POWER
UP
tDATA
ACQUISITION
(n –1)
ACQUISITION
(n)
ACQUISITION
ACQUISITION
PHASE
CONVERSION (n – 2)
CONVERSION (n – 1)
CONVERSION (n)
CONVERSION (n + 1)
(n + 1)
(n + 2)
CNV
DIN
XXX
XXX
CFG (n)
CFG (n + 2)
DATA (n)
CFG (n + 1)
DATA
(n – 2)
DATA
(n – 1)
SDO
SCK
1
17/31
1
17/31
1
17/31
1
17/31
CNV
CFG (n)
CFG (n + 1)
CFG (n + 2)
DATA (n)
CFG (n + 3)
DIN
DATA
(n – 2)
DATA
(n – 1)
SDO
DATA (n + 1)
1
17/31
1
17/31
1
17/31
1
SCK
CNV
CFG (n + 2)
CFG (n + 1)
CFG (n)
CFG (n + 3)
DIN
DATA
(n – 2)
DATA
(n – 1)
DATA
(n – 1)
SDO
DATA (n)
DATA (n + 1)
DATA (n – 2)
DATA (n)
1
17/31
1
17/31
1
17/31
1
SCK
NOTES
1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.
A TOTAL OF 17 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK
IS ENABLED, A TOTAL OF 31 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.
Figure 38. General Interface Timing for the AD7699 With a Busy Indicator
Rev. 0 | Page 24 of 28
AD7699
update. While CNV is low, both a CFG update and a data
READ/WRITE SPANNING CONVERSION WITH A
BUSY INDICATOR
readback take place. The first 14 SCK rising edges are used to
update the CFG register, and the first 16 SCK falling edges clock
out the conversion results starting with the MSB. The restriction
for both configuring and reading is that they both occur before
the tDATA time elapses for the next conversion. All 14 bits of
CFG[13:0] must be written or they are ignored. Also, if the 16-bit
conversion result is not read back before tDATA elapses, it is lost.
This mode is used when the AD7699 is connected to any host
using an SPI, serial port, or FPGA with an interrupt input. The
connection diagram is shown in Figure 39, and the corresponding
timing is given in Figure 40. For SPI, the host should use CPHA
= CPOL = 1. Reading/writing spanning conversion is shown,
which covers all three modes detailed in the Digital Interface
section.
The SDO data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 17th SCK falling edge,
SDO returns to high impedance. Note that, if the optional SCK
falling edge is not used, the busy feature cannot be detected if
the LSB for the conversion is low.
A rising edge on CNV initiates a conversion, forces SDO to
high impedance, and ignores data present on DIN. After a
conversion is initiated, it continues until completion irrespec-
tive of the state of CNV. CNV must be returned low before the
safe data transfer time, tDATA, and then held low beyond the
conversion time, tCONV, to generate the busy signal indicator.
When the conversion is complete, SDO transitions from high
impedance to low with a pull-up to VIO, which can be used to
interrupt the host to begin data transfer.
If CFG readback is enabled, the CFG register associated with
the conversion result (n − 1) is read back MSB first following
the LSB of the conversion result. A total of 31 SCK falling edges
is required to return SDO to high impedance if this is enabled.
After the conversion is complete, the AD7699 enters the
acquisition phase and power-down. The host must enable the
MSB of CFG at this time (if necessary) to begin the CFG
VIO
DIGITAL HOST
AD7699
SDO
MISO
IRQ
SS
CNV
MOSI
SCK
DIN
SCK
FOR SPI USE CPHA = 1, CPOL = 1.
Figure 39. Connection Diagram for the AD7699 with a Busy Indicator
tCYC
tCONV
tACQ
tDATA
tDATA
tCNVH
CNV
CONVERSION
(n – 1)
(QUIET
TIME)
(QUIET
ACQUISITION
(n + 1)
CONVERSION (n – 1)
tSCK
ACQUISITION (n)
TIME)
CONVERSION (n)
UPDATE (n + 1)
CFG/SDO
UPDATE (n)
CFG/SDO
tSCKH
SEE NOTE
17/
17/
31
16
15
SCK
DIN
1
2
16
15
X
31
tHDIN
tSDIN
tSCKL
CFG
CFG
X
X
X
X
X
MSB MSB –1
tHSDO
tDSDO
tDIS
BEIGN CFG (n + 1)
tEN
tDIS
END CFG (n)
END CFG (n + 1)
MSB
MSB
LSB
+ 1
LSB
+ 1
SDO
LSB
LSB
– 1
SEE NOTE
BEGIN DATA (n – 1)
END DATA (n – 1)
END DATA (n – 2)
tEN
tDIS
tEN
NOTES
1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF.
16 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
30 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW.
Figure 40. Serial Interface Timing for the AD7699 with a Busy Indicator
Rev. 0 | Page 25 of 28
AD7699
APPLICATION HINTS
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.
LAYOUT
The printed circuit board that houses the AD7699 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7699, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.
Finally, the power supplies, VDD and VIO, of the AD7699
should be decoupled with ceramic capacitors, typically 100 nF,
placed close to the AD7699 and connected using short, wide
traces to provide low impedance paths and to reduce the effect
of glitches on the power supply lines.
Avoid running digital lines under the device because these
couple noise onto the die unless a ground plane under the
AD7699 is used as a shield. Fast switching signals, such as CNV
or clocks, should not run near analog signal paths. Crossover of
digital and analog signals should be avoided.
EVALUATING AD7699 PERFORMANCE
Other recommended layouts for the AD7699 are outlined in the
documentation of the evaluation board for the AD7699 (EVAL-
AD76MUXCBZ). The evaluation board package includes a fully
assembled and tested evaluation board, documentation, and
software for controlling the board from a PC via the evaluation
controller board, EVAL-CONTROL BRD3.
At least one ground plane should be used. It can be common or
split between the digital and analog sections. In the latter case,
the planes should be joined underneath the AD7699.
The AD7699 voltage reference input, REF, has a dynamic input
impedance and should be decoupled with minimal parasitic
Rev. 0 | Page 26 of 28
AD7699
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
15
16
20
1
5
0.50
BSC
2.65
2.50 SQ
2.35
PIN 1
INDICATOR
3.75
BSC SQ
EXPOSED
PAD
(BOTTOM VIEW)
10
11
6
0.50
0.40
0.30
0.25 MIN
TOP VIEW
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SECTION OF THIS DATA SHEET.
0.30
0.23
0.18
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 41. 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
4 mm × 4 mm Body, Very Thin Quad
(CP-20-4)
Dimensions shown in millimeters
ORDERING GUIDE
Integral
Nonlinearity
No Missing
Code
Temperature
Range
Package
Option
Ordering
Quantity
Model
AD7699BCPZ1
AD7699BCPZRL71
EVAL-AD7699CBZ1
EVAL-CONTROL BRD3Z1, 2
Package Description
20-Lead LFCSP_VQ
20-Lead LFCSP_VQ
Evaluation Board
Controller Board
1.5 LSB max
1.5 LSB max
16 bits
16 bits
−40°C to +85°C
−40°C to +85°C
CP-20-4
CP-20-4
Tray, 490
Reel, 1500
1 RoHS Compliant Part.
2 This controller board allows a PC to control and communicate with all Analog Devices evaluation boards whose model numbers end in CB.
Rev. 0 | Page 27 of 28
AD7699
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07354-0-10/08(0)
Rev. 0 | Page 28 of 28
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