AD7658-1YSTZ-500RL7 [ADI]
IC 6-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQFP64, LEAD FREE, MS-026BCD, LQFP-64, Analog to Digital Converter;
| 型号： | AD7658-1YSTZ-500RL7 |
| 厂家： | 
ADI |
| 描述： | IC 6-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQFP64, LEAD FREE, MS-026BCD, LQFP-64, Analog to Digital Converter CD 转换器 |
| 文件： | 总32页 (文件大小：1368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
250 kSPS, 6-Channel, Simultaneous
Sampling, Bipolar 16-/14-/12-Bit ADC
Preliminary Technical Data
AD7656-1/AD7657-1/AD7658-1
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AV
DV
Six independent ADCs
CC
CC
CONVSTB
V
CONVSTC
CONVSTA
DD
True bipolar analog inputs
CS
SER/PAR
Pin-/software-selectable ranges: ±10 V, ±± V
Fast throughput rate: 2±0 kSPS
iCMOSTM process technology
Low power
TBD mW at 2±0 kSPS with ± V supplies
Wide input bandwidth
TBD dB SNR at ±0 kHz input frequency
On-chip reference and reference buffers
Parallel, serial, and daisy-chain interface modes
High speed serial interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Standby mode: 100 µW max
CLK
OSC
CONTROL
LOGIC
V
DRIVE
STBY
REF
BUF
OUTPUT
DRIVERS
D
OUT
A
V
V
T/H
T/H
16/14/12-BIT SAR
16/14/12-BIT SAR
1
SCLK
2
3
OUTPUT
DRIVERS
D
OUT
B
BUF
V
T/H
T/H
16/14/12-BIT SAR
16/14/12-BIT SAR
OUTPUT
DRIVERS
D
OUT
C
V
4
DATA/
CONTROL
LINES
OUTPUT
DRIVERS
BUF
64-lead LQFP
16/14/12-BIT SAR
V
V
T/H
5
RD
WR
APPLICATIONS
16/14/12-BIT SAR
T/H
V
6
Power line monitoring systems
Instrumentation and control systems
Multi-axis positioning systems
AD7656-1/AD7657-1/AD7658-1
AGND
SS
DGND
Figure 1.
GENERAL DESCRIPTION
CONVST pins allow independent, simultaneous sampling of
the three ADC pairs. The AD7656-1/AD7657-1/AD7658-1 all
have a high speed parallel and serial interface, allowing the
devices to interface with microprocessors or DSPs. In serial
interface mode, the parts have a daisy-chain feature that allows
multiple ADCs to connect to a single serial interface. The
AD7656-1/ AD7657-1/AD7658-1 can accommodate true
bipolar input signals in the 4 × VREF range and 2 × VREF range.
The AD7656-1/ AD7657-1/AD7658-1 also contain an on-chip
2.5 V reference.
The AD7656-1/AD7657-1/AD7658-11 contain six 16-/14-/12-
bit, fast, low power, successive approximation ADCs all in the
one package that is designed on the iCMOS process (industrial
CMOS). iCMOS is a process combining high voltage silicon
with submicron CMOS and complementary bipolar
technologies. It enables the development of a wide range of high
performance analog ICs, capable of 33 V operation in a
footprint that no previous generation of high voltage parts
could achieve. Unlike analog ICs using conventional CMOS
processes, iCMOS components can accept bipolar input signals
while providing increased performance, which dramatically
reduces power consumption and package size.
PRODUCT HIGHLIGHTS
1. Six 16-/14-/12-bit, 250 kSPS ADCs on board.
2. Six true bipolar, high impedance analog inputs.
3. Parallel and high speed serial interfaces.
The AD7656-1/AD7657-1/AD7658-1 feature throughput rates
up to 250 kSPS. The parts contain low noise, wide bandwidth,
track-and-hold amplifiers that can handle input frequencies
up to 12 MHz.
The conversion process and data acquisition are controlled
using CONVST signals and an internal oscillator. Three
1 Protected by U.S. Patent No. 6,731,232.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD7656-1/AD7657-1/AD7658-1
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 14
Terminology.................................................................................... 18
Theory of Operation ...................................................................... 20
Converter Details ....................................................................... 20
ADC Transfer Function............................................................. 21
Reference Section ....................................................................... 21
Typical Connection Diagram ................................................... 21
Driving the Analog Inputs ........................................................ 22
Interface Section......................................................................... 22
Application Hints ........................................................................... 29
Layout .......................................................................................... 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD7656.......................................................................................... 3
AD7657.......................................................................................... 5
AD7658.......................................................................................... 7
Timing Specifications .................................................................. 9
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
REVISION HISTORY
Rev. PrC| Page 2 of 32
Preliminary Technical Data
AD7656-1/AD7657-1/AD7658-1
SPECIFICATIONS
AD76±6-1
VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V;
For 4 × VREF range: VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; For 2 × VREF range: VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V;
f
SAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted.1
Table 1.
Parameter
B Version1 Y Version1 Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
fIN = 50 kHz sine wave
84
85.5
85
86.5
−90
−92
−100
−100
84
85.5
85
86.5
−90
−92
−100
−100
dB min
dB typ
dB min
dB typ
dB max
dB typ
dB typ
dB typ
Signal-to-Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
VDD/VSS
VDD/VSS
=
=
5 V to 10 V
12 V to 16.5 V
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Aperture Delay
fa = 50 kHz, fb = 49 kHz
−112
−107
10
4
35
−112
−107
10
4
35
dB typ
dB typ
ns max
ns max
ps typ
Aperture Delay Matching
Aperture Jitter
Channel-to-Channel Isolation2
Full Power Bandwidth
−100
12
2
−100
12
2
dB typ
MHz typ
MHz typ
fIN on unselected channels up to 100 kHz
@ −3 dB
@ −0.1 dB
DC ACCURACY
Resolution
16
16
Bits
No Missing Codes
15
16
3
1
14
16
4.5
1
Bits min
Bits min
LSB max
LSB typ
@ 25°C
Integral Nonlinearity2
Positive Full-Scale Error2
Positive Full-Scale Error Matching2
Bipolar Zero-Scale Error2
Bipolar Zero-Scale Error Matching2
Negative Full-Scale Error2
Negative Full-Scale Error Matching2
ANALOG INPUT
0.75
0.35
0.023
0.038
0.75
0.35
0.75
0.35
0.023
0.038
0.75
0.35
% FS max
% FS max
% FS max
% FS max
% FS max
% FS max
0.22% FSR typical
0.004% FSR typical
0.22% FSR typical
See Table 8 for min VDD/VSS for each range
RNG bit/RANGE pin = 0
Input Voltage Ranges
4 ꢀ VREF
4 ꢀ VREF
V
2 ꢀ VREF
2 ꢀ VREF
V
RNG bit/RANGE pin = 1
DC Leakage Current
Input Capacitance3
1
10
14
1
10
14
µA max
pF typ
pF typ
4 ꢀ VREF range when in track
2 ꢀ VREF range when in track
REFERENCE INPUT/OUTPUT
Reference Input Voltage Range
DC Leakage Current
2.5
1
18.5
2.5
1
18.5
V min/max
µA max
pF typ
Input Capacitance3
REFEN/DIS = 1
1,000 hours
Reference Output Voltage
Long-Term Stability
Reference Temperature Coefficient
2.49/2.51
2.49/2.51
V min/max
ppm typ
ppm/°C max
ppm/°C typ
150
25
6
150
25
6
Rev. PrC | Page 3 of 32
AD7656-1/AD7657-1/AD7658-1
Preliminary Technical Data
Parameter
B Version1 Y Version1 Unit
Test Conditions/Comments
LOGIC INPUTS
Input High Voltage (VINH
)
0.7 ꢀ VDRIVE 0.7 ꢀ VDRIVE V min
0.3 ꢀ VDRIVE 0.3 ꢀ VDRIVE V max
Input Low Voltage (VINL
)
Input Current (IIN)
1
10
1
10
µA max
pF max
Typically 10 nA, VIN = 0 V or VDRIVE
Input Capacitance (CIN)3
LOGIC OUTPUTS
Output High Voltage (VOH
Output Low Voltage (VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
)
VDRIVE − 0.2 VDRIVE − 0.2 V min
ISOURCE = 200 µA
ISINK = 200 µA
)
0.2
1
10
0.2
1
10
V max
µA max
pF max
Twos complement
CONVERSION RATE
Conversion Time
3.1
550
250
3.1
550
250
µs max
ns max
kSPS
Track-and-Hold Acquisition Time2, 3
Throughput Rate
Parallel interface mode only
POWER REQUIREMENTS
VDD
5/15
5/15
V nom min/max For 4 x VREF range, VDD = 10 V to 16.5 V
VSS
−5/−15
−5/−15
V nom min/max For 4 x VREF range, VDD = −10 V to −16.5 V
AVCC
5
5
V nom
DVCC
5
5
V nom
VDRIVE
ITOTAL
3/5
3/5
V nom min/max
Digital I/PS = 0 V or VDRIVE
Normal Mode (Static)
(Includes IAVCC, IVDD, IVSS, IVDRIVE, IDVCC
Normal Mode (Operational)
(Includes IAVCC, IVDD, IVSS, IVDRIVE, IDVCC
ISS (Operational)
28
28
mA max
AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,
VSS = −16.5 V
fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = 5.25 V,
VDD = 16.5 V, VSS = −16.5 V
VSS = −16.5 V, fSAMPLE = 250 kSPS
VDD = 16.5 V, fSAMPLE = 250 kSPS
AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,
)
)
TBD
TBD
mA max
0.25
0.25
7
0.25
0.25
7
mA max
mA max
mA max
IDD (Operational)
Partial Power-Down Mode
V
SS = −16.5 V
Full Power-Down Mode (STBY Pin)
Power Dissipation
80
80
µA max
SCLK on or off, AVCC = DVCC = VDRIVE = 5.25 V,
VDD = 16.5 V, VSS = −16.5 V
AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,
VSS = −16.5 V
Normal Mode (Static)
143
TBD
35
143
TBD
35
mW max
mW max
mW max
µW max
Normal Mode (Operational)
Partial Power-Down Mode
Full Power-Down Mode (STBY Pin)
fSAMPLE = 250 kSPS
100
100
1 Temperature ranges are as follows: B version is −40°C to +85°C, Y version is −40°C to +125°C.
2 See the Terminology section.
3 Sample tested during initial release to ensure compliance.
Rev. PrC| Page 4 of 32
Preliminary Technical Data
AD7656-1/AD7657-1/AD7658-1
AD76±7-1
VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V;
For 4 × VREF range: VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; For 2 × VREF range: VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V;
f
SAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter
B Version1 Y Version1 Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
Signal-to-Noise Ratio (SNR)2
fIN = 50 kHz sine wave
81.5
82.5
83.5
−90
−92
−100
81.5
82.5
83.5
−89
−92
−100
dB min
dB min
dB typ
dB max
dB typ
dB typ
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Delay Matching
Aperture Jitter
Channel-to-Channel Isolation2
fa = 50 kHz, fb = 49 kHz
−109
−104
10
4
35
−100
12
2
−109
−104
10
4
35
−100
12
2
dB typ
dB typ
ns max
ns max
ps typ
dB typ
MHz typ
MHz typ
fIN on unselected channels up to 100 kHz
@ −3 dB
@ −0.1 dB
Full Power Bandwidth
DC ACCURACY
Resolution
14
14
Bits
No Missing Codes
Integral Nonlinearity2
14
1.5
1
14
1.5
1
Bits min
LSB max
LSB typ
Positive Full-Scale Error2
Positive Full-Scale Error Matching2
Bipolar Zero-Scale Error2
Bipolar Zero-Scale Error Matching2
Negative Full-Scale Error2
Negative Full-Scale Error Matching2
ANALOG INPUT
0.61
0.3
0.0305
0.0427
0.61
0.3
0.61
0.3
0.0305
0.0427
0.61
0.3
% FS max
% FS max
% FS max
% FS max
% FS max
% FS max
0.183% FSR typical
0.015 % FSR typical
0.183% FSR typical
See Table 8 for min VDD/VSS for each range
RNG bit/RANGE pin = 0
RNG bit/RANGE pin = 1
Input Voltage Ranges
4 ꢀ VREF
2 ꢀ VREF
1
10
14
4 ꢀ VREF
2 ꢀ VREF
1
10
14
V
V
DC Leakage Current
Input Capacitance3
µA max
pF typ
pF typ
4 ꢀ VREF range when in track
2 ꢀ VREF range when in track
REFERENCE INPUT/OUTPUT
Reference Input Voltage Range
DC Leakage Current
2.5
1
18.5
2.5
1
18.5
V min/max
µA max
pF typ
Input Capacitance3
REFEN/DIS = 1
1,000 hours
Reference Output Voltage
Long-Term Stability
Reference Temperature Coefficient
2.49/2.51
2.49/2.51
V min/max
ppm typ
ppm/°C max
ppm/°C typ
150
25
6
150
25
6
LOGIC INPUTS
Input High Voltage (VINH
)
0.7 ꢀ VDRIVE 0.7 ꢀ VDRIVE V min
0.3 ꢀ VDRIVE 0.3 ꢀ VDRIVE V max
Input Low Voltage (VINL
)
Input Current (IIN)
Input Capacitance (CIN)3
1
10
1
10
µA max
pF max
Typically 10 nA, VIN = 0 V or VDRIVE
Rev. PrC | Page 5 of 32
AD7656-1/AD7657-1/AD7658-1
Preliminary Technical Data
Parameter
B Version1 Y Version1 Unit
Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage (VOH
Output Low Voltage (VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
)
VDRIVE − 0.2 VDRIVE − 0.2 V min
ISOURCE = 200 µA
ISINK = 200 µA
)
0.2
1
10
0.2
1
10
V max
µA max
pF max
Twos complement
CONVERSION RATE
Conversion Time
3.1
550
250
3.1
550
250
µs max
ns max
kSPS
Track-and-Hold Acquisition Time2, 3
Throughput Rate
Parallel interface mode only
POWER REQUIREMENTS
VDD
5/15
5/15
V nom min/max For 4 x VREF range, VDD = 10 V to 16.5 V
VSS
−5/−15
−5/−15
V nom min/max For 4 x VREF range, VDD = −10 V to −16.5 V
AVCC
5
5
V nom
DVCC
5
5
V nom
VDRIVE
ITOTAL
3/5
3/5
V nom min/max
Digital I/PS = 0 V or VDRIVE
Normal Mode (Static)
(Includes IAVCC, IVDD, IVSS, IVDRIVE, IDVCC
Normal Mode (Operational)
(Includes IAVCC, IVDD, IVSS, IVDRIVE, IDVCC
ISS (Operational)
28
28
mA max
AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,
VSS = −16.5 V
fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = 5.25 V,
VDD = 16.5 V, VSS = −16.5 V
VSS = −16.5 V, fSAMPLE = 250 kSPS
VDD = 16.5 V, fSAMPLE = 250 kSPS
AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,
VSS = −16.5 V
)
)
TBD
TBD
mA max
0.25
0.25
7
0.25
0.25
7
mA max
mA max
mA max
IDD (Operational)
Partial Power-Down Mode
Full Power-Down Mode (STBY Pin)
Power Dissipation
80
80
µA max
SCLK on or off, AVCC = DVCC = VDRIVE = 5.25 V,
VDD = 16.5 V, VSS = −16.5 V
AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,
V
SS = −16.5 V
Normal Mode (Static)
143
TBD
35
143
TBD
35
mW max
mW max
mW max
µW max
Normal Mode (Operational)
Partial Power-Down Mode
Full Power-Down Mode (STBY Pin)
fSAMPLE = 250 kSPS
100
100
1 Temperature ranges are as follows: B version is −40°C to +85°C, Y version is −40°C to +125°C.
2 See the Terminology section.
3 Sample tested during initial release to ensure compliance.
Rev. PrC| Page 6 of 32
Preliminary Technical Data
AD7656-1/AD7657-1/AD7658-1
AD76±8-1
VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V;
For 4 × VREF range: VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; For 2 × VREF range: VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V;
f
SAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted.1
Table 3.
Parameter
B Version1 Y Version1 Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
fIN = 50 kHz sine wave
73
73
dB min
dB typ
dB max
dB typ
dB typ
73.5
−88
−92
−97
73.5
−88
−92
−97
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Aperture Delay
fa = 50 kHz, fb = 49 kHz
−106
−101
10
4
35
−106
−101
10
4
35
dB typ
dB typ
ns max
ns max
ps typ
Aperture Delay Matching
Aperture Jitter
Channel-to-Channel Isolation2
Full Power Bandwidth
−100
12
2
−100
12
2
dB typ
MHz typ
MHz typ
fIN on unselected channels up to 100 kHz
@ −3 dB
@ −0.1 dB
DC ACCURACY
Resolution
No Missing Codes
12
12
0.7
1
0.6104
0.366
3
12
12
0.7
1
0.6104
0.366
3
Bits
Bits min
LSB max
LSB max
% FS max
% FS max
LSB max
LSB max
% FS max
% FS max
Differential Nonlinearity
Integral Nonlinearity2
Positive Full-Scale Error2
Positive Full-Scale Error Matching2
Bipolar Zero-Scale Error2
Bipolar Zero-Scale Error Matching2
Negative Full-Scale Error2
Negative Full-Scale Error Matching2
ANALOG INPUT
0.244% FSR typical
0.0488% FSR typical
0.244% FSR typical
3
3
0.6104
0.366
0.6104
0.366
See Table 8 for min VDD/VSS for each range
RNG bit/RANGE pin = 0
RNG bit/RANGE pin = 1
Input Voltage Ranges
4 ꢀ VREF
2 ꢀ VREF
1
10
14
4 ꢀ VREF
2 ꢀ VREF
1
10
14
V
V
DC Leakage Current
Input Capacitance3
µA max
pF typ
pF typ
4 ꢀ VREF range when in track
2 ꢀ VREF range when in track
REFERENCE INPUT/OUTPUT
Reference Input Voltage Range
DC Leakage Current
2.5
1
18.5
2.5
1
18.5
V min/max
µA max
pF typ
Input Capacitance3
REFEN/DIS = 1
1,000 hours
Reference Output Voltage
Long-Term Stability
Reference Temperature Coefficient
2.49/2.51
2.49/2.51
V min/max
ppm typ
ppm/°C max
ppm/°C typ
150
25
6
150
25
6
LOGIC INPUTS
Input High Voltage (VINH
)
0.7 ꢀ VDRIVE 0.7 ꢀ VDRIVE V min
0.3 ꢀ VDRIVE 0.3 ꢀ VDRIVE V max
Input Low Voltage (VINL
)
Input Current (IIN)
Input Capacitance (CIN)3
1
10
1
10
µA max
pF max
Typically 10 nA, VIN = 0 V or VDRIVE
Rev. PrC | Page 7 of 32
AD7656-1/AD7657-1/AD7658-1
Preliminary Technical Data
Parameter
B Version1 Y Version1 Unit
Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage (VOH
Output Low Voltage (VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
)
VDRIVE − 0.2 VDRIVE − 0.2 V min
ISOURCE = 200 µA
ISINK = 200 µA
)
0.2
1
10
0.2
1
10
V max
µA max
pF max
Twos complement
CONVERSION RATE
Conversion Time
3.1
550
250
3.1
550
250
µs max
ns max
kSPS
Track-and-Hold Acquisition Time2, 3
Throughput Rate
Parallel interface mode only
POWER REQUIREMENTS
VDD
5/15
5/15
V nom min/max For 4 x VREF range, VDD = 10 V to 16.5 V
VSS
−5/−15
−5/−15
V nom min/max For 4 x VREF range, VDD = −10 V to −16.5 V
AVCC
5
5
V nom
DVCC
5
5
V nom
VDRIVE
ITOTAL
3/5
3/5
V nom min/max
Digital I/PS = 0 V or VDRIVE
Normal Mode (Static)
(Includes IAVCC, IVDD, IVSS, IVDRIVE, IDVCC
Normal Mode (Operational)
(Includes IAVCC, IVDD, IVSS, IVDRIVE, IDVCC
ISS (Operational)
28
28
mA max
AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,
VSS = −16.5 V
fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = 5.25 V,
VDD = 16.5 V, VSS = −16.5 V
VSS = −16.5 V, fSAMPLE = 250 kSPS
VDD = 16.5 V, fSAMPLE = 250 kSPS
AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,
VSS = −16.5 V
)
)
TBD
TBD
mA max
0.25
0.25
7
0.25
0.25
7
mA max
mA max
mA max
IDD (Operational)
Partial Power-Down Mode
Full Power-Down Mode (STBY Pin)
Power Dissipation
80
80
µA max
SCLK on or off, AVCC = DVCC = VDRIVE = 5.25 V,
VDD = 16.5 V, VSS = −16.5 V
AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,
V
SS = −16.5 V
Normal Mode (Static)
143
TBD
35
143
TBD
35
mW max
mW max
mW max
µW max
Normal Mode (Operational)
Partial Power-Down Mode
Full Power-Down Mode (STBY Pin)
fSAMPLE = 250 kSPS
100
100
1 Temperature ranges are as follows: B version is −40°C to +85°C, Y version is −40°C to +125°C
2 See the Terminology section.
3 Sample tested during initial release to ensure compliance.
Rev. PrC| Page 8 of 32
Preliminary Technical Data
AD7656-1/AD7657-1/AD7658-1
TIMING SPECIFICATIONS
AVCC/DVCC = 4.75 V to 5.25 V, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external,
TA = TMIN to TMAX, unless otherwise noted.1
Table 4.
Limit at TMIN, TMAX
Parameter
PARALLEL MODE
tCONVERT
Unit
Description
VDRIVE < 4.7± V
VDRIVE = 4.7± V to ±.2± V
3
150
3
150
µs typ
ns min
Conversion time, internal clock
Minimum quiet time required between bus relinquish
and start of next conversion
tQUIET
tACQ
t10
t1
550
25
60
2
550
25
60
2
ns min
ns min
ns min
ms max
µs max
Acquisition time
Minimum CONVST low pulse
CONVST high to BUSY high
STBY rising edge to CONVST rising edge
Partial power-down mode
tWAKE-UP
25
25
PARALLEL WRITE OPERATION
t11
t12
t13
t14
t15
15
0
15
0
ns min
ns min
ns min
ns min
ns min
WR pulse width
CS to WR setup time
5
5
CS to WR hold time
5
5
Data setup time before WR rising edge
Data hold after WR rising edge
5
5
PARALLEL READ OPERATION
t2
0
0
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
BUSY to RD delay
t3
0
0
CS to RD setup time
t4
0
0
CS to RD hold time
t5
45
45
10
12
6
36
36
10
12
6
RD pulse width
t6
Data access time after RD falling edge
Data hold time after RD rising edge
Bus relinquish time after RD rising edge
Minimum time between reads
t7
t8
t9
SERIAL INTERFACE
fSCLK
t16
18
12
18
12
MHz max Frequency of serial read clock
ns max
ns max
ns min
ns min
ns min
ns max
Delay from CS until SDATA three-state disabled
2
t17
22
22
Data access time after SCLK rising edge/CS falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time after SCLK falling edge
CS rising edge to SDATA high impedance
t18
t19
t20
t21
0.4 tSCLK
0.4 tSCLK
10
0.4 tSCLK
0.4 tSCLK
10
18
18
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 A buffer is used on the data output pins for this measurement.
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
25pF
200µA
I
OH
Figure 2. Load Circuit for Digital Output Timing Specification
Rev. PrC | Page 9 of 32
AD7656-1/AD7657-1/AD7658-1
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to AGND, DGND
VSS to AGND, DGND
VDD to AVCC
AVCC to AGND, DGND
DVCC to AVCC
−0.3 V to +16.5 V
+0.3 V to −16.5 V
VCC − 0.3 V to 16.5 V
−0.3 V to +7 V
−0.3 V to AVCC + 0.3 V
−0.3 V to +7 V
DVCC to DGND, AGND
AGND to DGND
−0.3 V to +0.3 V
VDRIVE to DGND
−0.3 V to +DVCC + 0.3 V
VSS − 0.3 V to VDD + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to AVCC + 0.3 V
Analog Input Voltage to AGND1
Digital Input Voltage to DGND
Digital Output Voltage to GND
REFIN to AGND
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. These
specifications apply to a four-layer board.
Input Current to Any Pin Except
Supplies2
10 mA
Table 6. Thermal Resistance
Package Type
Operating Temperature Range
B Version
Y Version
Storage Temperature Range
Junction Temperature
Pb/SN Temperature, Soldering
Reflow (10 sec to 30 sec)
θJA
θJC
Unit
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
150°C
64-Lead LQFP
45
11
°C/W
240(+0)°C
Pb-Free Temperature, Soldering Reflow 260(+0)°C
1 If the analog inputs are being driven from alternative VDD and VSS supply
circuitry, a 240 Ω series resistor should be placed on the analog inputs.
2 Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrC| Page 10 of 32
Preliminary Technical Data
AD7656-1/AD7657-1/AD7658-1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48
DB14/REFBUF
V6
EN/DIS
DB13
PIN 1
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AV
AV
V5
CC
CC
3
DB12
DB11
4
5
DB10/DOUT C
DB9/DOUT B
DB8/DOUT A
DGND
AGND
AGND
V4
6
AD7656-1/AD7657-1/AD7658-1
7
TOP VIEW
8
(Not to Scale)
AV
AV
V3
CC
CC
9
V
DRIVE
10
11
12
13
14
15
16
DB7/HBEN/DCEN
DB6/SCLK
AGND
AGND
V2
DB5/DCIN A
DB4/DCIN B
DB3/DCIN C
DB2/SEL C
AV
AV
V1
CC
CC
DB1/SEL B
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
54, 56, 58
REFCAPA, REFCAPB,
REFCAPC
Decoupling capacitors are connected to these pins. This decouples the reference buffer for each
ADC pair. Each REFCAP pin should be decoupled to AGND using a 1 µF.
33, 36, 39,
42, 45, 48
V1 to V6
Analog Input 1 to 6. These are six single-ended analog inputs. In hardware mode, the analog input
range on these channels is determined by the RANGE pin. In software mode, it is determined by bits
RNGC to RNGA of the control register (see Table 10).
32, 37, 38, 43, AGND
44, 49, 52, 53,
Analog Ground. Ground reference point for all analog circuitry on the AD7656-1/AD7657-1/AD7658-
1.
55, 57, 59
All analog input signals and any external reference signal should be referred to this AGND voltage.
All 11 of these AGND pins should be connected to the AGND plane of a system. The AGND and
DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart,
even on a transient basis.
26
DVCC
Digital Power, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis. This supply should be decoupled
to DGND, and 10 µF and 100 nF decoupling capacitors should be placed on the DVCC pin.
9
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage of the
interface. Nominally at the same supply as the supply of the host interface.
8, 25
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7656-1/AD7657-
1/AD7658-1. Both DGND pins should connect to the DGND plane of a system. The DGND and AGND
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
34, 35, 40,
41, 46, 47,
50, 60
AVCC
Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AVCC and
DVCC voltages should ideally be at the same potential and must not be more than 0.3 V apart, even
on a transient basis.
23, 22, 21
CONVST A,
Conversion Start Input A, B, C. These logic inputs are used to initiate conversions on the ADC pairs.
CONVST B, CONVST C CONVST A is used to initiate simultaneous conversions on V1 and V2. CONVST B is used to initiate
simultaneous conversions on V3 and V4. CONVST C is used to initiate simultaneous conversions on
V5 and V6. When CONVSTx switches from low to high, the track-and-hold switch on the selected
ADC pair switches from track to hold and the conversion is initiated. These inputs can also be used
to place the ADC pairs into partial power-down mode.
Rev. PrC | Page 11 of 32
AD7656-1/AD7657-1/AD7658-1
Preliminary Technical Data
Pin No.
Mnemonic
Description
19
CS
Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low
in parallel mode, the output bus is enabled and the conversion result is output on the parallel data
bus lines. When both CS and WR are logic low in parallel mode, DB[15:8] are used to write data to
the on-chip control register. In serial mode, the CS is used to frame the serial read transfer and clock
out the MSB of the serial output data.
20
63
RD
Read Data. When both CS and RD are logic low in parallel mode, the output bus is enabled. In serial
mode, the RD line should be held low.
Write Data/Reference Enable/Disable. When H/S SEL pin is high and both CS and WR are logic low,
DB[15:8] are used to write data to the internal control register. When the H/S SEL pin is low, this pin
is used to enable or disable the internal reference. When H/S SEL = 0 and REF EN/DIS = 0, the
internal reference is disabled and an external reference should be applied to the REFIN/REFOUT pin.
When H/S SEL = 0 and REF EN/DIS = 1, the internal reference is enabled and the REFIN/REFOUT pin
should be decoupled. See the Reference Section.
WR/REFEN/DIS
18
51
61
17
BUSY
BUSY Output. This pin transitions high when a conversion is started and remains high until the
conversion is complete and the conversion data is latched into the output data registers. A new
conversion should not be initiated on the AD7656-1/AD7657-1/AD7658-1 when the BUSY signal is
high.
REFIN/REFOUT
SER/PAR/SEL
DB0/SEL A
Reference Input/Output. The on-chip reference is available on this pin for use external to the
AD7656-1/AD7657-1/AD7658-1. Alternatively, the internal reference can be disabled and an
external reference can be applied to this input. See the Reference Section. When the internal
reference is enabled, this pin should be decoupled using at least a 10 µF decoupling cap.
Serial/Parallel Selection Input. When this pin is low, the parallel interface is selected. When this
pin is high, the serial interface mode is selected. In serial mode, DB[10:8] take on their DOUT[C:A]
function, DB[0:2] take on their DOUT select function, DB7 takes on its DCEN function. In serial mode,
DB15 and DB[13:11] should be tied to DGND.
Data Bit 0/Select DOUT A. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin.
When SER/PAR = 1, this pin takes on its SEL A function; it is used to configure the serial interface. If
this pin is 1, the serial interface operates with one/two/three DOUT output pins and enables DOUT A
as a serial output. When operating in serial mode, this pin should always be = 1.
16
15
DB1/SEL B
DB2/SEL C
Data Bit 1/Select DOUT B. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin.
When SER/PAR = 1, this pin takes on its SEL B function; it is used to configure the serial interface. If
this pin is 1, the serial interface operates with two/three DOUT output pins and enables DOUT B as a
serial output. If this pin is 0, the DOUT B is not enabled to operate as a serial data output pin and
only one DOUT output pin, DOUT A, is used. Unused serial DOUT pins should be left unconnected.
Data Bit 2/Select DOUT C. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin.
When SER/PAR = 1, this pin takes on its SEL C function; it is used to configure the serial interface. If
this pin is 1, the serial interface operates with three DOUT output pins and enables DOUT C as a
serial output. If this pin is 0, the DOUT C is not enabled to operate as a serial data output pin.
Unused serial DOUT pins should be left unconnected.
14
13
12
DB3/DCIN C
DB4/DCIN B
DB5/DCIN A
Data Bit 3/Daisy-Chain Input C. When SER/PAR = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR = 1 and DCEN = 1, this pin acts as Daisy-Chain Input C. When operating
in serial mode but not in daisy-chain mode, this pin should be tied to DGND.
Data Bit 4/Daisy-Chain Input B. When SER/PAR = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR = 1 and DCEN = 1, this pin acts as Daisy-Chain Input B. When operating
in serial mode but not in daisy-chain mode, this pin should be tied to DGND.
Data Bit 5/Daisy-Chain Input A. When SER/PAR is low, this pin acts as a three-state parallel digital
output pin. When SER/PAR = 1 and DCEN = 1, this pin acts as Daisy-Chain Input A. When operating
in serial mode but not in daisy-chain mode, this pin should be tied to DGND.
11
10
DB6/SCLK
Data Bit 6/Serial Clock. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When
SER/PAR = 1, this pin takes on its SCLK input function; it is the read serial clock for the serial transfer.
DB7/HBEN/DCEN
Data Bit 7/High Byte Enable/Daisy-Chain Enable. When operating in parallel word mode
(SER/PAR = 0 and W/B = 0), this pin takes on its Data Bit 7 function. When operating in parallel
byte mode (SER/PAR = 0 and W/B = 1), this pin takes on its HBEN function. When in this mode and
the HBEN pin is logic high, the data is output MSB byte first on DB[15:8]. When the HBEN pin is
logic low, the data is output LSB byte first on DB[15:8]. When operating in serial mode (SER/PAR = 1),
this pin takes on its DCEN function. When the DCEN pin is logic high, the parts operate in daisy-
chain mode with DB[5:3] taking on their DCIN[A:C] function. When operating in serial mode but
not in daisy-chain mode, this pin should be tied to DGND.
Rev. PrC| Page 12 of 32
Preliminary Technical Data
AD7656-1/AD7657-1/AD7658-1
Pin No.
Mnemonic
Description
7
DB8/DOUT A
Data Bit 8/Serial Data Output A. When SER/PAR = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR = 1 and SEL A = 1, this pin takes on its DOUT A function and outputs
serial conversion data.
6
5
DB9/DOUT B
Data Bit 9/Serial Data Output B. When SER/PAR = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR = 1 and SEL B = 1, this pin takes on its DOUT B function and outputs
serial conversion data. This configures the serial interface to have two DOUT output lines.
DB10/DOUT C
Data Bit 10/Serial Data Output C. When SER/PAR = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR = 1 and SEL C = 1, this pin takes on its DOUT C function and outputs
serial conversion data. This configures the serial interface to have three DOUT output lines.
4
DB11
Data Bit 11/Digital Ground. When SER/PAR = 0, this pin acts as a three-state parallel digital output
pin. When SER/PAR = 1, this pin should be tied to DGND.
3, 2, 64
DB12, DB13, DB15
Data Bit 12, 13, 15. When SER/PAR = 0, these pins act as three-state parallel digital input/output
pins. When CS and RD are low, these pins are used to output the conversion result. When CS and WR
are low, these pins are used to write to the control register. When SER/PAR = 1, these pins should be
tied to DGND. For the AD7657, DB15 contains a leading zero. For the AD7658, DB15, DB13, and
DB12 contain leading zeros.
1
Data Bit 14/REFBUF Enable/Disable. When SER/PAR =0, this pin acts as a three-state digital input/
output pin. For the AD7657/AD7658, DB14 contains a leading zero. When SER/PAR = 1, this pin can be
used to enable or disable the internal reference buffers.
DB14/REFBUFEN
/DIS
28
RESET
Reset Input. When set to logic high, this pin resets the AD7656-1/AD7657-1/AD7658-1. The current
conversion, if any, is aborted. The internal register is set to all 0s. In hardware mode, the AD7656-
1/AD7657-1/AD7658-1 are configured depending on the logic levels on the hardware select pins. In
all modes, the parts should receive a RESET pulse after power-up. The reset high pulse should be
typically 100 ns wide. After the RESET pulse, the AD7656-1/AD7657-1/AD7658-1 needs to see a valid
CONVST pulse in order to initiate a conversion; this should consist of a high-to-low CONVST edge
followed by a low-to-high CONVST edge. The CONVST signal should be high during the RESET pulse.
27
RANGE
Analog Input Range Selection. Logic input. The logic level on this pin determines the input range of
the analog input channels. When this pin is Logic 1 at the falling edge of BUSY, the range for the
next conversion is 2 ꢀ VREF. When this pin is Logic 0 at the falling edge of BUSY, the range for the
next conversion is 4 ꢀ VREF. In hardware select mode, the RANGE pin is checked on the falling edge
of BUSY. In software mode (H/S SEL = 1), the RANGE pin can be tied to DGND and the input range is
determined by the RNGA, RNGB, and RNGC bits in the control register.
31
30
24
VDD
Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.
Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.
VSS
STBY
Standby Mode Input. This pin is used to put all six on-chip ADCs into standby mode. The STBY pin is
high for normal operation and low for standby operation.
62
H/S SEL
W/B
Hardware/Software Select Input. Logic input. When H/S SEL = 0, the AD7656-1/AD7657-1/AD7658-1
operate in hardware select mode, and the ADC pairs to be simultaneously sampled are selected
by the CONVST pins. When H/S SEL = 1, the ADC pairs to be sampled simultaneously are selected by
writing to the control register. In serial mode, CONVST A is used to initiate conversions on the
selected ADC pairs.
29
Word/Byte Input. When this pin is logic low, data can be transferred to and from the AD7656-
1/AD7657-1/ AD7658-1 using the parallel data lines DB[15:0]. When this pin is logic high, byte mode is
enabled. In this mode, data is transferred using data lines DB[15:8] and DB[7] takes on its HBEN
function. To obtain the 16-bit conversion result, 2-byte reads are required. In serial mode, this pin
should be tied to DGND.
Rev. PrC | Page 13 of 32
AD7656-1/AD7657-1/AD7658-1
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
1.5
0
V
/V = ±15V
DD SS
AV /DV /V
INTERNAL REFERENCE
±10V RANGE
= +5V
CC CC DRIVE
–20
–40
T
= 25°C
A
1.0
f
f
= 250kSPS
= 50kHz
S
IN
0.5
–60
SNR = +87.33dB
SINAD = +87.251dB
THD = –104.32dB
SFDR = –104.13dB
0
–80
–0.5
–1.0
–1.5
–2.0
–100
–120
–140
–160
AV /DV /V
CC CC DRIVE
= +5V
V
/V = ±12V
DD SS
f
= 250kSPS
RANGE
SAMPLE
2 × V
REF
DNL WCP = 0.81LSB
DNL WCN = –0.57LSB
0
10k
20k
30k
CODE
40k
50k
60k 65535
0
0
0
25
50
75
100
125
FREQUENCY (kHz)
Figure 7. AD7656-1 Typical DNL
Figure 4. AD7656-1 FFT for 10 V Range
0
–20
2.0
1.6
V
/V = ±12V
DD SS
AV /DV /V
CC CC DRIVE
= +5V
AV /DV /V
= +5V
V
/V = ±12V
CC CC DRIVE
DD SS
INTERNAL REFERENCE
±5V RANGE
f
= 250kSPS
RANGE
SAMPLE
2 × V
1.2
REF
T
= 25°C
A
–40
f
f
= 250kSPS
= 50kHz
S
0.8
IN
–60
SNR = +86.252dB
SINAD = +86.196dB
THD = –105.11dB
SFDR = –98.189dB
0.4
–80
0
–0.4
–0.8
–1.2
–1.6
–2.0
–100
–120
–140
–160
0
2000
4000
6000
8000 10000 12000 14000 16383
CODE
25
50
75
100
125
FREQUENCY (kHz)
Figure 8. AD7657-1 Typical INL
Figure 5. AD7656-1 FFT for 5 V Range
2.0
1.6
2.0
1.5
AV /DV /V
CC CC DRIVE
= +5V
AV /DV /V
= +5V
CC
CC DRIVE
V
/V = ±12V
V
f
/V = ±12V
DD SS
DD SS
= 250kSPS
RANGE
SAMPLE
2 × V
1.2
REF
INL WCP = 0.64LSB
INL WCN = –0.76LSB
1.0
0.8
0.5
0.4
0
0
–0.4
–0.8
–1.2
–1.6
–2.0
–0.5
–1.0
–1.5
–2.0
0
2000
4000
6000
8000 10000 12000 14000 16383
CODE
10k
20k
30k
CODE
40k
50k
60k 65535
Figure 9. AD7657-1 Typical DNL
Figure 6. AD7656-1 Typical INL
Rev. PrC| Page 14 of 32
Preliminary Technical Data
AD7656-1/AD7657-1/AD7658-1
1.0
–60
–70
f
= 250kSPS
SAMPLE
INTERNAL REFERENCE
= 25°C
AV /DV /V
= +5V
0.8
0.6
CC
CC DRIVE
T
V
f
/V = ±12V
A
DD SS
AV /DV /V
CC CC DRIVE
= +5V
= 250kSPS
RANGE
SAMPLE
V
/V = ±5.25V
DD SS
2 × V
REF
±5V RANGE
0.4
AV /DV
CC
/
CC
= +4.75V
–80
V
DRIVE
/V = ±10V
0.2
V
DD SS
±10V RANGE
AV /DV
CC
/
CC
= +5V
0
–90
V
DRIVE
/V = ±12V
V
DD SS
–0.2
–0.4
–0.6
–0.8
–1.0
±5V RANGE
–100
–110
–120
AV /DV
/
CC
CC
= +5.25V
V
V
DRIVE
/V = ±16.5V
±10V RANGE
DD SS
0
500
1000
1500 2000
CODE
2500
3000 3500
4095
10
100
1000
ANALOG INPUT FREQUENCY (kHz)
Figure 13. AD7656 THD vs. Input Frequency
Figure 10. AD7658 Typical INL
1.0
0.8
–60
–70
V
/V = ±16.5V
DD SS
AV /DV /V
= +5.25V
AV /DV /V
= +5V
CC
CC DRIVE
CC
CC DRIVE
T
= 25°C
V
f
/V = ±12V
A
DD SS
= 250kSPS
RANGE
INTERNAL REFERENCE
±4 × V RANGE
SAMPLE
0.6
2 × V
REF
REF
0.4
–80
0.2
R
= 1000Ω
SOURCE
0
–90
R
= 100Ω
SOURCE
–0.2
–0.4
–0.6
–0.8
–1.0
R
= 220Ω
SOURCE
–100
–110
–120
R
= 10Ω
SOURCE
R
= 50Ω
SOURCE
0
500
1000
1500 2000
CODE
2500
3000 3500
4095
10
100
ANALOG INPUT FREQUENCY (kHz)
Figure 11. AD7658 Typical DNL
Figure 14. AD7656 THD vs. Input Frequency for Various Source Impedances,
4 ꢀ VREF Range
90
85
80
75
70
65
60
–40
AV /DV /V
CC CC DRIVE
= +5.25V
V
/V = ±12V
DD SS
V
/V = ±16.5V
DD SS
AV /DV /V
= +5V
CC
CC DRIVE
±10V RANGE
–50
–60
T
= 25°C
A
INTERNAL REFERENCE
±2 × V RANGE
AV /DV
/
CC
CC
= +5V
V
V
REF
DRIVE
AV /DV
CC CC
/
/V = ±12V
DD SS
V
= +4.75 V
DRIVE
/V = ±10V
±5V RANGE
–70
V
DD SS
±10V RANGE
–80
R
= 1000Ω
SOURCE
AV /DV
CC
/
CC
= +5V
–90
V
V
DRIVE
/V = ±5.25V
R
= 220Ω
SOURCE
DD SS
±5V RANGE
R
= 100Ω
SOURCE
–100
–110
–120
f
= 250kSPS
INTERNAL REFERENCE
SAMPLE
R
= 50Ω
R
SOURCE
= 10Ω
SOURCE
T
= 25°C
A
10
100
ANALOG INPUT FREQUENCY (kHz)
1000
10
100
ANALOG INPUT FREQUENCY (kHz)
Figure 12. AD7656-1 SINAD vs. Input Frequency
Figure 15. AD7656-1 THD vs. Input Frequency for Various Source
Impedances,
2 ꢀ VREF Range
Rev. PrC | Page 15 of 32
AD7656-1/AD7657-1/AD7658-1
Preliminary Technical Data
2.510
100
90
80
70
60
50
40
f
= 250kSPS
RANGE
AV /DV /V
CC CC DRIVE
= +5V
SAMPLE
±2 × V
V
/V = ±12V
REF
DD SS
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
INTERNAL REFERENCE
T
f
= 25°C
= 10kHz
A
IN
100nF ON V AND V
DD
SS
V
SS
V
DD
–55
–35
–15
5
25
45
65
85
105
125
30
80
130 180 230 280 330 380 430 480 530
SUPPLY RIPPLE FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 16. Reference Voltage vs. Temperature
Figure 19. PSRR vs. Supply Ripple Frequency
3.20
3.15
3.10
3.05
3.00
2.95
2.90
2.85
2.80
2.75
2.70
87.0
86.5
86.0
85.5
85.0
84.5
84.0
83.5
83.0
AV /DV /V
CC CC DRIVE
= +5V
V
/V = ±12V
DD SS
±5V RANGE,
AV /DV /V
= +5V
CC CC DRIVE
/V = ±12V
DD SS
±10V RANGE,
V
AV /DV /V
= +5.25V
CC CC DRIVE
V
/V = ±16.5V
DD SS
f
f
= 250kSPS
SAMPLE
= 50kHz
IN
INTERNAL REFERENCE
–40 –20 20
TEMPERATURE (°C)
–55
–35
–15
5
25
45
65
85
105
125
0
40
60
80
100
120
140
TEMPERATURE (°C)
Figure 17. Conversion Time vs. Temperature
Figure 20.AD7656 SNR vs. Temperature
–100
–101
–102
–103
–104
–105
–106
–107
3500
3000
2500
2000
1500
1000
500
f
f
= 250kSPS
SAMPLE
= 50kHz
3212
IN
V
/V = ±15V
DD SS
INTERNAL REFERENCE
AV /DV /V
INTERNAL REFERENCE
8192 SAMPLES
= +5V
CC CC DRIVE
2806
±10V RANGE,
AV /DV /V
= +5.25V
CC CC DRIVE
V
/V = ±16.5V
DD SS
1532
±5V RANGE,
AV /DV /V
= +5V
CC CC DRIVE
V
/V = ±12V
DD SS
392
–3
168
25
57
–4
0
0
3
0
–5
–40
–20
0
20
40
60
80
100
120
140
–2
–1
0
1
2
TEMPERATURE (°C)
CODE
Figure 21. AD7656-1 THD vs. Temperature
Figure 18. AD7656 Histogram of Codes
Rev. PrC| Page 16 of 32
Preliminary Technical Data
AD7656-1/AD7657-1/AD7658-1
30
25
20
15
10
5
120
110
100
90
±10V RANGE
±5V RANGE
80
AV /DV /V
CC CC DRIVE
= 5V
V
/V = ±12V
DD SS
= 25°C
AV /DV /V
= +5V
T
CC
CC DRIVE
= 250kSPS
A
70
60
f
INTERNAL REFERENCE
SAMPLE
FOR ±5V RANGE V /V = ±12V
±2 × V RANGE
DD SS
REF
30kHz ON SELECTED CHANNEL
FOR ±10V RANGE V /V = ±16.5V
DD SS
0
–40
–20
0
20
40
60
80
100
0
20 40 60 80
100
120
140
TEMPERATURE (°C)
FREQUENCY OF INPUT NOISE (kHz)
Figure 22. Channel-to-Channel Isolation
Figure 23. Dynamic Current vs. Temperature
Rev. PrC | Page 17 of 32
AD7656-1/AD7657-1/AD7658-1
TERMINOLOGY
Preliminary Technical Data
The ratio depends on the number of quantization levels in the
digitization process: the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by
Integral Nonlinearity
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of
the transfer function are zero scale, a ½ LSB below the first code
transition and full scale at ½ LSB above the last code transition.
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, this is 98 dB for a 16-bit converter, 86.04 dB for a 14-bit
converter, and 74 dB for a 12-bit converter.
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the harmonics to the fundamental.
For the AD7656-1/AD7657-1/AD7658-1, it is defined as
Bipolar Zero Code Error
The deviation of the midscale transition (all 1s to all 0s) from
the ideal VIN voltage, that is, AGND − 1 LSB.
2
2
2
2
2
V2 +V3 +V4 +V5 +V6
THD(dB) = 20log
V1
Bipolar Zero Code Error Match
The difference in bipolar zero code error between any two input
channels.
where:
V1 is the rms amplitude of the fundamental.
Positive Full-Scale Error
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
The deviation of the last code transition (011…110) to (011…111)
from the ideal (+4 × VREF − 1 LSB, +2 × VREF − 1 LSB) after
adjusting for the bipolar zero code error.
through sixth harmonics.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2, excluding dc) to the rms value
of the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is
determined by a noise peak.
Positive Full-Scale Error Match
The difference in positive full-scale error between any two input
channels.
Negative Full-Scale Error
The deviation of the first code transition (10…000) to (10…001)
from the ideal (−4 × VREF + 1 LSB, −2 × VREF + 1 LSB) after
adjusting for the bipolar zero code error.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities create distortion
products at sum and difference frequencies of mfa nfb, where
m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for
which neither m nor n are equal to 0. For example, the second-
order terms include (fa + fb) and (fa − fb), and the third-order
terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
Negative Full-Scale Error Match
The difference in negative full-scale error between any two
input channels.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of the conversion. The track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within 1 LSB, after the end of the conversion.
See the Track-and-Hold Section for more details.
The AD7656-1/AD7657-1/AD7658-1 are tested using the CCIF
standard in which two input frequencies near the top end of the
input bandwidth are used. In this case, the second-order terms
are usually distanced in frequency from the original sine waves,
and the third-order terms are usually at a frequency close to the
input frequencies. As a result, the second- and third-order terms
are specified separately. The calculation of the intermodulation
distortion is per the THD specification, where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in decibels.
Signal-to-(Noise + Distortion) Ratio
The measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2, excluding dc).
Rev. PrC| Page 18 of 32
Preliminary Technical Data
AD7656-1/AD7657-1/AD7658-1
where:
Power Supply Rejection (PSR)
Variations in power supply affect the full-scale transition but
not the converter’s linearity. Power supply rejection is the
maximum change in full-scale transition point due to a change
in power supply voltage from the nominal value. See the Typical
Performance Characteristics section.
Pf is equal to the power at frequency f in the ADC output.
PfS is equal to the power at frequency fS coupled onto the VDD
and VSS supplies.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between any two channels. It is measured by applying a full-scale,
100 kHz sine wave signal to all unselected input channels and
determining the degree to which the signal attenuates in the
selected channel with a 30 kHz signal.
Figure 19 shows the power supply rejection ratio vs. supply
ripple frequency for the AD7656-1/AD7657-1/AD7658-1. The
power supply rejection ratio is defined as the ratio of the power
in the ADC output at full-scale frequency, f, to the power of a
200 mV p-p sine wave applied to the ADC’s VDD and VSS
supplies of frequency fS
PSRR (dB) = 10 log (Pf/PfS)
Rev. PrC | Page 19 of 32
AD7656-1/AD7657-1/AD7658-1
Preliminary Technical Data
THEORY OF OPERATION
CONVERTER DETAILS
Analog Input Section
The AD7656-1/AD7657-1/AD7658-1 can handle true bipolar
input voltages. The logic level on the RANGE pin or the value
written to the RNGx bits in the control register determines the
analog input range on the AD7656-1/AD7657-1/AD7658-1 for
the next conversion. When the RANGE pin/RNGx bit is 1, the
analog input range for the next conversion is 2 × VREF. When
the RANGE pin/RNGx bit is 0, the analog input range for the
The AD7656-1/AD7657-1/AD7658-1 are high speed, low
power converters that allow the simultaneous sampling of six
on-chip ADCs. The analog inputs on the AD7656-1/AD7657-
1/AD7658-1 can accept true bipolar input signals. The RANGE
pin/RNG bits are used to select either 4 × VREF or 2 × VREF as
the input range for the next conversion.
Each AD7656-1/AD7657-1/AD7658-1 contains six SAR ADCs,
six track-and-hold amplifiers, an on-chip 2.5 V reference,
reference buffers, and high speed parallel and serial interfaces.
The parts allow the simultaneous sampling of all six ADCs
when all three CONVST signals are tied together. Alternatively,
the six ADCs can be grouped into three pairs. Each pair has an
associated CONVST signal used to initiate simultaneous
sampling on each ADC pair, on four ADCs, or on all six ADCs.
CONVST A is used to initiate simultaneous sampling on V1 and
V2, CONVST B is used to initiate simultaneous sampling on V3
and V4, and CONVST C is used to initiate simultaneous
sampling on V5 and V6.
next conversion is 4 × VREF
.
V
DD
D1
D2
C2
R1
V1
C1
V
SS
Figure 24. Equivalent Analog Input Structure
Figure 24 shows an equivalent circuit of the analog input structure
of the AD7656-1/AD7657-1/AD7658-1. The two diodes, D1
and D2, provide ESD protection for the analog inputs. Care
must be taken to ensure that the analog input signal never
exceeds the VDD and VSS supply rails by more than 300 mV.
Signals exceeding this value cause these diodes to become
forward-biased and to start conducting current into the
substrate. The maximum current these diodes can conduct
without causing irreversible damage to the parts is 10 mA.
Capacitor C1 in Figure 24 is typically about 4 pF and can be
attributed primarily to pin capacitance. Resistor R1 is a lumped
component made up of the on resistance of a switch (track-and-
hold switch). This resistor is typically about 25 Ω. Capacitor C2
is the ADC sampling capacitor and has a capacitance of 10 pF
typically.
A conversion is initiated on the AD7656-1/AD7657-1/AD7658-
1 by pulsing the CONVSTx input. On the rising edge of
CONVSTx, the track-and-hold of the selected ADC pair is
placed into hold mode and the conversions are started. After
the rising edge of CONVSTx, the BUSY signal goes high to
indicate that the conversion is taking place. The conversion
clock for the AD7656-1/AD7657-1/AD7658-1 is internally
generated, and the conversion time for the parts is 3 µs. The
BUSY signal returns low to indicate the end of conversion. On
the falling edge of BUSY, the track-and-hold returns to track
mode. Data can be read from the output register via the parallel
or serial interface.
The AD7656-1/AD7657-1/AD7658-1 require VDD and VSS dual
supplies for the high voltage analog input structures. These
supplies must be equal to or greater than the analog input range
(see Table 8 for the requirements on these supplies for each
analog input range). The AD7656-1/AD7657-1/AD7658-1
require a low voltage AVCC supply of 4.75 V to 5.25 V to power
the ADC core, a DVCC supply of 4.75 V to 5.25 V for the digital
power, and a VDRIVE supply of 2.7 V to 5.25 V for the interface
power.
Track-and-Hold Section
The track-and-hold amplifiers on the AD7656-1/AD7657-
1/AD7658-1 allow the ADCs to accurately convert an input sine
wave of full-scale amplitude to 16-/14-/12-bit resolution
respectively. The input bandwidth of the track-and-hold
amplifiers is greater than the Nyquist rate of the ADC, even
when the AD7656-1/ AD7657-1/AD7658-1 are operating at its
maximum throughput rate. The parts can handle input
frequencies of up to 12 MHz.
To meet the specified performance when using the minimum
supply voltage for the selected analog input range, it can be
necessary to reduce the throughput rate from the maximum
throughput rate.
The track-and-hold amplifiers sample their respective inputs
simultaneously on the rising edge of CONVSTx. The aperture time
for the track-and-hold (that is, the delay time between the external
CONVSTx signal actually going into hold) is 10 ns. This is well
matched across all six track-and-holds on one device and from
device to device. This allows more than six ADCs to be sampled
simultaneously. The end of the conversion is signaled by the falling
edge of BUSY, and it is at this point that the track-and-holds return
to track mode and the acquisition time begins.
Table 8. Minimum VDD/VSS Supply Voltage Requirements
Analog Input
Range (V)
Reference
Voltage (V)
Full Scale
Input (V)
Minimum
VDD/VSS (V)
4 ꢀ VREF
4 ꢀ VREF
+2.5
+3.0
10
12
10
12
Rev. PrC | Page 20 of 32
Preliminary Technical Data
AD7656-1/AD7657-1/AD7658-1
2 ꢀ VREF
2 ꢀ VREF
+2.5
+3.0
5
6
5
6
the REFIN/REFOUT pin should be decoupled using a 1 µF
capacitor.
ADC TRANSFER FUNCTION
The AD7656-1/AD7657-1/AD7658-1 contain three on-chip
reference buffers. Each of the three ADC pairs has an associated
reference buffer. These reference buffers require external
decoupling capacitors on REFCAPA, REFCAPB, and REFCAPC
pins, and 1 µF decoupling capacitors should be placed on these
REFCAP pins. The internal reference buffers can be disabled in
software mode by writing to Bit DB8 in the internal control
register. If operating the devices in serial mode,
The output coding of the AD7656-1/AD7657-1/AD7658-1 is
twos complement. The designed code transitions occur midway
between successive integer LSB values, that is, 1/2 LSB, 3/2 LSB.
The LSB size is FSR/65,536 for the AD7656-1, FSR/16384 for
the AD7657-1, and FSR/4096 for the AD7658-1. The ideal
transfer characteristic is shown in Figure 25.
011...111
011...110
the internal reference buffers can be disabled in hardware mode
by setting the DB14/REFBUF/ DIS pin high. If the internal
EN
reference and its buffers are disabled, an external buffered
reference should be applied to the REFCAP pins.
000...001
000...000
111...111
TYPICAL CONNECTION DIAGRAM
100...010
Figure 26 shows the typical connection diagram for the
AD7656-1/AD7657-1/AD7658-1. There are eight AVCC supply
pins on the parts. The AVCC supply is the supply that is used for
the AD7656-1/AD7657-1/AD7658-1 conversion process,
therefore, it should be well decoupled. The AVCC supply pins
should be decoupled using a 1 µF capacitor. The AD7656-
1/AD7657-1/ AD7658-1 can operate with the internal reference
or an externally applied reference. In this configuration, the
parts are configured to operate with the external reference. The
REFIN/REFOUT pin is decoupled with a 1 µF cap . The three
internal reference buffers are enabled. Each of the REFCAP pins
are decoupled with a 1 µF capacitor.
100...001
100...000
AGND – 1LSB
–FSR/2 + 1/2LSB
+FSR/2 – 3/2LSB
ANALOG INPUT
Figure 25. AD7656-1/AD7657-1/AD7658-1 Transfer Characteristic
The LSB size is dependent on the analog input range selected
(see Table 9).
REFERENCE SECTION
The RFIN/REFOUT pin either allows access to the AD7656-1/
AD7657-1/AD7658-1’s 2.5 V reference or it allows an external
reference to be connected, providing the reference source for
each part’s conversions. The AD7656-1/AD7657-1/AD7658-1
can accommodate a 2.5 V to 3 V external reference range.
When using an external reference, the internal reference needs
to be disabled. After a reset, the AD7656-1/AD7657-1/AD7658-
1 default to operating in external reference mode with the
internal reference buffers enabled. The internal reference can be
enabled in either hardware or software mode. To enable the
If the same supply is being used for the AVCC supply and DVCC
supply, a ferrite or small RC filter should be placed between the
supply pins.
AGND pins are connected to the AGND plane of the system.
The DGND pins are connected to the digital ground plane in
the system. The AGND and DGND planes should be connected
together at one place in the system. This connection should be
made as close as possible to the AD7656-1/AD7657-1/AD7658-
1 in the system.
H
internal reference in hardware mode, the /S SEL pin = 0 and the
DIS
REF EN/
H
pin = 1. To enable the internal reference in software
mode, /S SEL = 1 and a write to the control register is necessary
to make DB9 of the register = 1. For the internal reference mode,
Table 9. LSB Size for Each Analog Input Range
Range
AD76±6-1
AD76±7-1
AD76±8-1
Input Range
LSB Size
FS Range
10 V
0.305 mV
20 V/65,536
5 V
0.152 mV
10 V/65,536
10 V
1.22 mV
20 V/16384
5 V
0.610 mV
10 V/16384
10 V
4.88 mV
20 V/4096
5 V
2.44mV
10 V/4096
Rev. PrC | Page 21 of 32
AD7656-1/AD7657-1/AD7658-1
Preliminary Technical Data
DV
CC
+
DIGITAL SUPPLY
VOLTAGE +3V OR +5V
ANALOG SUPPLY
1
VOLTAGE 5V
+
+
1µF
1µF
1µF
AGND AV
DD
DV
DGND
V DGND
DRIVE
CC
CC
+9.5V TO +16.5V
SUPPLY
V
+
+
+
1µF
1µF
PARALLEL
D0 TO D15
INTERFACE
µP/µC/DSP
AGND
CONVST A, B, C
REFCAPA, B, C
AGND
CS
RD
BUSY
RESET
2.5V
REF
REFIN/OUT
AGND
AD7656-1/
AD7657-1/
AD7658-1
1µF
SER/PAR
H/S
W/B
RANGE
SIX ANALOG
INPUTS
–9.5V TO –16.5V
SUPPLY
V
SS
V
STBY
DRIVE
1µF
+
AGND
Figure 26. Typical Connection Diagram
Parallel Interface (SER/
PAR
= 0)
The VDRIVE supply is connected to the same supply as the
processor. The voltage on VDRIVE controls the voltage value of
the output logic signals.
The AD7656-1/AD7657-1/AD7658-1 consist of six 16-/14-/12-
bit ADCs respectively. A simultaneous sample of all six ADCs
can be performed by connecting all three CONVST pins
together, CONVST A, CONVST B, and CONVST C. The
AD7656-1/AD7657-1/ AD7658-1 need to see a CONVST pulse
in order to initiate a conversion; this should consist of a falling
CONVST edge followed by a rising CONVST edge. The rising
edge of CONVSTx initiates simultaneous conversions on the
selected ADCs. The AD7656-1/AD7657-1/AD7658-1 contain
an on-chip oscillator that is used to perform the conversions.
The conversion time, tCONV, is 3 µs. The BUSY signal goes low to
indicate the end of conversion. The falling edge of the BUSY
signal is used to place the track-and-hold into track mode. The
AD7656-1/AD7657-1/AD7658-1 also allow the six ADCs to be
converted simultaneously in pairs by pulsing the three
The VDD and VSS signals should be decoupled with a minimum
1 µF decoupling capacitor. These supplies are used for the high
voltage analog input structures on the AD7656-1/AD7657-
1/AD7658-1 analog inputs.
DRIVING THE ANALOG INPUTS
Together, the driver amplifier and the analog input circuit used
for the AD7656-1 must settle for a full-scale step input to a 16-
bit level (0.0015%), which is within the specified 550 ns
acquisition time of the AD7656-1. The noise generated by the
driver amplifier needs to be kept as low as possible in order to
preserve the SNR and transition noise performance of the
AD7656-1.
CONVST pins independently. CONVST A is used to initiate
simultaneous conversions on V1 and V2, CONVST B is used to
initiate simultaneous conversions on V3 and V4, and
The driver also needs to have a THD performance suitable to
that of the AD7656-1. The AD8021 meets all these
requirements. The AD8021 needs an external compensation
capacitor of 10 pF. If a dual version of the AD8021 is required,
the AD8022 can be used. The AD8610 and the AD797 can also
be used to drive the AD7656-1/AD7657-1/AD7658-1.
CONVST C is used to initiate simultaneous conversions on V5
and V6. The conversion results from the simultaneously
sampled ADCs are stored in the output data registers.
Data can be read from the AD7656-1/AD7657-1/AD7658-1 via
INTERFACE SECTION
CS
RD
W
the parallel data bus with standard
0). To read the data over the parallel bus, SER/
CS RD
and
signals ( /B =
PAR
should be
input signals are internally gated to
enable the conversion result onto the data bus. The data lines
CS
The AD7656-1/AD7657-1/AD7658-1 provide two interface
options, a parallel interface and a high speed serial interface. The
required interface mode is selected via the SER/
parallel interface can operate in word ( /B = 0) or byte ( /B =
1) mode. The interface modes are discussed in the following
sections.
tied low. The
and
PAR
pin. The
DB0 to DB15 leave their high impedance state when both
RD
W
W
and
are logic low.
Rev. PrC| Page 22 of 32
Preliminary Technical Data
AD7656-1/AD7657-1/AD7658-1
CS
The signal can be permanently tied low, and the
RD
can affect the performance of the conversion. For the specified
performance, it is recommended to perform the read after the
conversion. For unused input channel pairs, the associated
signal
can be used to access the conversion results. A read operation
can take place after the BUSY signal goes low. The number of
required read operations depends on the number of ADCs that
are simultaneously sampled (see Figure 27). If CONVST A
and CONVST B are simultaneously brought low, four read
operations are required to obtain the conversion results from
V1, V2, V3, and V4. If CONVST A and CONVST C are
simultaneously brought low, four read operations are required
to obtain the conversion results from V1, V2, V5, and V6.
The conversion results are output in ascending order. For
the AD7657, DB15 and DB14 contain two leading zeros and
DB[13:0] output the 14-bit conversion result. For the AD7658,
DB[15:12] contain four leading zeros and DB[11:0] output the
12-bit conversion result.
CONVSTx pin should be tied to VDRIVE
.
If there is only an 8-bit bus available, the AD7656-1/AD7657-1/
AD7658-1 interface can be configured to operate in byte mode
W
(
/B = 1). In this configuration, the DB7/HBEN/DCEN pin
takes on its HBEN function. Each channel conversion result
from the AD7656-1/AD7657-1/AD7658-1 can be accessed in
two read operations, with 8-bits of data provided on DB15 to
DB8 for each of the read operations (see Figure 28). The HBEN
pin determines whether the read operation first accesses the
high byte or the low byte of the 16-bit conversion result. To
always access the low byte first on DB15 to DB8, the HBEN pin
should be tied low. To always access the high byte first on DB15
to DB8, the HBEN pin should be tied high. In byte mode when
all three CONVST pins are pulsed together to initiate
When using the three CONVST signals to independently
initiate conversions on the three ADC pairs, care should be
taken to ensure that a conversion is not initiated on a channel
pair when the BUSY signal is high. It is also recommended not
to initiate a conversion during a read sequence because doing so
simultaneous conversions on all six ADCs, 12 read operations
are necessary to read back the six 16-/14-/12-bit conversion
results. DB[6:0] should be left unconnected in byte mode.
t10
CONVST A,
CONVST B,
CONVST C
tCONV
tACQ
BUSY
t4
CS
t3
t2
t5
t9
RD
t7
t6
t8
tQUIET
DATA
V1
V2
V3
V4
V5
V6
W
Figure 27. Parallel Interface Timing Diagram ( /B = 0)
CS
t4
t3
t9
t5
RD
t8
t7
t6
LOW BYTE
HIGH BYTE
DB15 TO DB8
W
Figure 28. Parallel Interface—Read Cycle for Byte Mode of Operation. ( /B = 1, HBEN = 0)
Rev. PrC | Page 23 of 32
Preliminary Technical Data
AD7656-1/AD7657-1/AD7658-1
Table 11.
Bit
Software Selection of ADCs
Mnemonic
Comment
H
The /S SEL pin determines the source of the combination of
DB15 VC
This bit is used to select Analog Inputs V5
and V6 for the next conversion.
When this bit = 1, V5 and V6 are
simultaneously converted on the
next CONVST A rising edge.
H
ADCs that are to be simultaneously sampled. When the /S SEL
pin is logic low, the combination of channels to be simultaneously
sampled is determined by the CONVST A, CONVST B, and
H
CONVST C pins. When the /S SEL pin is logic high, the
DB14 VB
DB13 VA
DB12 RNGC
This bit is used to select Analog Inputs
V3 and V4 for the next conversion.
When this bit = 1, V3 and V4 are
simultaneously converted on the
next CONVST A rising edge.
combination of channels selected for simultaneous sampling is
determined by the contents of the Control Register DB15 to
Control Register DB13. In this mode, a write to the control
register is necessary.
This bit is used to select Analog Inputs
V1 and V2 for the next conversion.
When this bit = 1, V1 and V2 are
simultaneously converted on the
next CONVST A rising edge.
The control register is an 8-bit write only register. Data is written
CS
WR
to this register using the
and
pins and the DB[15:8] data
pins (see Figure 29). The control register is shown in Table 10.
To select an ADC pair to be simultaneously sampled, set the
corresponding data line high during the write operation.
This bit is used to select the analog input
range for Analog Inputs V5 and V6.
When this bit = 1, the 2 ꢀ VREF mode is
selected for the next conversion.
When this bit = 0, the 4 ꢀ VREF mode is
selected for the next conversion.
The AD7656-1/AD7657-1/AD7658-1 control register allows
individual ranges to be programmed on each ADC pair. DB12
to DB10 in the control register are used to program the range
on each ADC pair.
DB11 RNGB
DB10 RNGA
This bit is used to select the analog input
range for Analog Inputs V3 and V4.
When this bit = 1, the 2 ꢀ VREF mode is
selected for the next conversion.
When this bit = 0, the 4 ꢀ VREF mode is
selected for the next conversion.
After a reset occurs on the AD7656-1/AD7657-1/AD7658-1,
the control register contains all zeros.
The CONVST A signal is used to initiate a simultaneous
conversion on the combination of channels selected via the
control register. The CONVST B and CONVST C signals can be
This bit is used to select the analog input
range for Analog Inputs V1 and V2.
When this bit = 1, the 2 ꢀ VREF mode is
selected for the next conversion.
When this bit = 0, the 4 ꢀ VREF mode is
selected for the next conversion.
H
tied low when operating in software mode ( /S SEL = 1). The
number of read pulses required depends on the number of
ADCs selected in the control register and on whether the
devices are operating in word or byte mode. The conversion
results are output in ascending order.
DB9
DB8
REFEN
This bit is used to select the internal
reference or an external reference.
When this bit = 0, the external reference
mode is selected. When this bit = 1, the
internal reference is selected.
During the write operation, Data Bus Bit DB15 to Bit DB8 are
bidirectional and become inputs to the control register when
RD
CS
WR
is logic high and
on DB15 through DB8 is latched into the control register when
WR
and
are logic low. The logic state
REFBUF
This bit is used to select between using the
internal reference buffers and choosing
to bypass these reference buffers.
When this bit = 0, the internal reference
buffers are enabled and decoupling is
required on the REFCAP pins. When this
bit = 1, the internal reference buffers are
disabled and a buffered reference should
be applied to the REFCAP pins.
goes logic high.
Table 10. Control Register Bit Function Descriptions
(Default All 0s)
DB1± DB14 DB13 DB12 DB11 DB10 DB9
DB8
VC
VB
VA
RNGC RNGB RNGA REFEN REFBUF
CS
WR
t13
t12
t11
t15
t14
DATA
DB15 TO DB8
W
Figure 29. Parallel Interface—Write Cycle for Word Mode ( /B= 0)
Rev. PrC | Page 24 of 32
AD7656-1/AD7657-1/AD7658-1
Preliminary Technical Data
If it is required to clock conversion data out on two data out
lines, DOUT A and DOUT B should be used. To enable DOUT A
and DOUT B, DB0/SEL A and DB1/SEL B should be tied to
VDRIVE and DB2/SEL C should be tied low. When six simultaneous
conversions are performed and only two DOUT lines are used,
a 48 SCLK transfer can be used to access the data from the
AD7656-1/AD7657-1/AD7658-1. The read sequence is shown
in Figure 31 for a simultaneous conversion on all six ADCs
using two DOUT lines. If a simultaneous conversion occurred
on all six ADCs, and only two DOUT lines are used to read the
results from the AD7656-1/AD7657-1/AD7658-1. DOUT A
clocks out the result from V1, V2, and V5, while DOUT B
clocks out the results from V3, V4, and V6.
Changing the Analog Input Range ( /S SEL = 0)
H
The AD7656-1/AD7657-1/AD7658-1 RANGE pin allows the
user to select either 2 × VREF or 4 × VREF as the analog input
H
range for the six analog inputs. When the /S SEL pin is low,
the logic state of the RANGE pin is sampled on the falling edge
of the BUSY signal to determine the range for the next
simultaneous conversion. When the RANGE pin is logic high at
the falling edge of the BUSY signal, the range for the next
conversion is
2 × VREF. When the RANGE pin is logic low at the falling
edge of the BUSY signal, the range for the next conversion is
4 × VREF. After a RESET pulse, the range is updated on the first
falling BUSY edge after the RESET pulse.
Data can also be clocked out using just one DOUT line, in
which case DOUT A should be used to access the conversion
data. To configure the AD7656-1/AD7657-1/AD7658-1 to
operate in this mode, DB0/SEL A should be tied to VDRIVE and
DB1/SEL B and DB2/SEL C should be tied low. The
Changing the Analog Input Range ( /S SEL = 1)
H
H
When the /S SEL pin is high, the range can be changed by
writing to the control register. DB[12:10] in the control register
are used to select the analog input ranges for the next conversion.
Each analog input pair has an associated range bit, allowing
independent ranges to be programmed on each ADC pair.
When the RNGx bit = 1, the range for the next conversion
is 2 × VREF. When the RNGx bit = 0, the range for the next
disadvantage of using just one DOUT line is that the
throughput rate is reduced. Data can be accessed from the
AD7656-1/AD7657-1/AD7658-1 using one 96 SCLK transfer,
three 32 SCLK individually framed transfers, or six 16 SCLK
RD
individually framed transfers. In serial mode, the
signal
conversion is 4 × VREF
.
should be tied low. The unused DOUT line(s) should be left
unconnected in serial mode.
Serial Interface (SER/
= 1)
PAR
By pulsing one, two, or all three CONVSTx signals, the
AD7656-1/AD7657-1/AD7658-1 use their on-chip trimmed
oscillator to simultaneously convert the selected channel pairs
on the rising edge of CONVSTx. After the rising edge of
CONVSTx, the BUSY signal goes high to indicate that the
conversion has started. It returns low when the conversion is
complete 3 µs later. The output register is loaded with the new
conversion results, and data can be read from the AD7656-
1/AD7657-1/AD7658-1. To read the data back from the parts
PAR
Serial Read Operation
Figure 32 shows the timing diagram for reading data from the
AD7656-1/AD7657-1/AD7658-1 in serial mode. The SCLK input
CS
signal provides the clock source for the serial interface. The
signal goes low to access data from the AD7656-1/AD7657-
CS
1/AD7658-1. The falling edge of
takes the bus out of three-
state and clocks out the MSB of the 16-bit conversion result.
The ADCs output 16 bits for each conversion result; the data
stream of the AD7656-1 consists of 16 bits of conversion data
provided MSB first. The data stream for the AD7657-1 consists
of two leading zeros followed by 14 bits of conversion data MSB
first. The data stream for the AD7658-1 consists of four leading
zeros and 12 bits of conversion data provided MSB first.
over the serial interface, SER/
should be tied high. The
CS
and SCLK signals are used to transfer data from the AD7656-
1/AD7657-1/AD7658-1. The parts have three DOUT pins,
DOUT A, DOUT B, and DOUT C. Data can be read back from
the each part using one, two, or all three DOUT lines.
The first bit of the conversion result is valid on the first SCLK
Figure 30 shows six simultaneous conversions and the read
sequence using three DOUT lines. Also in Figure 30, 32 SCLK
transfers are used to access data from the AD7656-1/AD7657-1/
AD7658-1; however, two 16 SCLK individually framed transfers
CS
falling edge after the
falling edge. The subsequent 15 data
bits are clocked out on the rising edge of the SCLK signal. Data
is valid on the SCLK falling edge. To access each conversion
result, 16 clock pulses must be provided to the AD7656-
1/AD7657-1/ AD7658-1. Figure 32 shows how a 16 SCLK read
is used to access the conversion results.
CS
with the
signal can also be used to access the data on the
three DOUT lines. When operating the AD7656-1/AD7657-
1/AD7658-1 in serial mode with conversion data clocking out on
all three DOUT lines, DB0/SEL A, DB1/SEL B, and DB2/SEL C
should be tied to VDRIVE. These pins are used to enable the
DOUT A to DOUT C lines, respectively.
Rev. PrC | Page 25 of 32
Preliminary Technical Data
AD7656-1/AD7657-1/AD7658-1
CONVST A,
CONVST B,
CONVST C
tCONV
tACQ
BUSY
CS
16
32
SCLK
tQUIET
DOUT A
V1
V3
V5
V2
V4
V6
DOUT B
DOUT C
Figure 30. Serial Interface with Three DOUT Lines
CS
48
SCLK
DOUT A
DOUT B
V5
V6
V1
V3
V2
V4
Figure 31. Serial Interface with Two DOUT Lines
t1
CONVST A,
t10
CONVST B,
tACQ
tCONV
CONVST C
t2
BUSY
ACQUISITION
CONVERSION
ACQUISITION
CS
tQUIET
t19
t18
SCLK
t16
t17
t20
DB1
t21
DB15
DB14
DB13
DB0
DOUT A, B, C
Figure 32. Serial Read Operation
Rev. PrC | Page 26 of 32
AD7656-1/AD7657-1/AD7658-1
Preliminary Technical Data
Figure 35 shows the timing if two AD7656-1/AD7657-
1/AD7658-1 devices are configured in daisy-chain mode and
are operating with three DOUT lines. Assuming a simultaneous
Daisy-Chain Mode (DCEN = 1, SER/
PAR
= 1)
When reading conversion data back from the AD7656-
1/AD7657-1/ AD7658-1 using their three/two/one DOUT pins,
it is possible to configure the parts to operate in daisy-chain
mode, using the DCEN pin. This daisy-chain feature allows
multiple AD7656-1/ AD7657-1/AD7658-1 devices to be cascaded
together and is useful for reducing component count and wiring
connections. An example connection of two devices is shown in
Figure 33. This configuration shows two DOUT lines being
used. Simultaneous sampling of the 12 analog inputs is possible
by using a common CONVSTx signal. The DB5, DB4, and DB3
data pins are used as data input pins DCIN [A:C] for the daisy-
chain mode.
CS
sampling of all 12 inputs occurs, the
frames a 64 SCLK
transfer during the read operation. During the first 32 SCLKs of
this transfer, the conversion results from Device 1 are clocked
into the digital host and the conversion results from Device 2
are clocked into Device 1. During the last 32 SCLKs of the
transfer, the conversion results from Device 2 are clocked out of
Device 1 and into the digital host. Device 2 clocks out zeros.
Standby/Partial Power-Down Modes of Operation
Each ADC pair can be individually placed into partial power-
down mode by bringing the CONVSTx signal low before the
falling edge of BUSY. To power the ADC pair back up, the
CONVSTx signal should be brought high to tell the ADC pair
to power up and place the track-and-hold into track mode.
After the power-up time from partial power-down has elapsed,
the CONVSTx signal should receive a rising edge to initiate a
valid conversion. In partial power-down mode, the reference
buffers remain powered up. While an ADC pair is in partial power-
down mode, conversions can still occur on the other ADCs.
The rising edge of CONVST is used to initiate a conversion on
the AD7656-1/AD7657-1/AD7658-1. After the BUSY signal has
gone low to indicate that the conversion is complete, the user
can begin to read the data from the two devices. Figure 34 shows
the serial timing diagram when operating two AD7656-
1/AD7657-1/ AD7658-1 devices in daisy-chain mode.
CS
The
falling edge is used to frame the serial transfer from the
AD7656-1/AD7657-1/AD7658-1 devices, to take the bus out of
three-state, and to clock out the MSB of the first conversion
result. In the example shown in Figure 34, all 12 ADC channels
are simultaneously sampled. Two DOUT lines are used to read
The AD7656-1/AD7657-1/AD7658-1 have a standby mode
whereby the devices can be placed into a low power
consumption mode (100 µW max). The AD7656-1/AD7657-
1/AD7658-1 are placed into standby mode by bringing the logic
CS
the conversion results in this example. frames a 96 SCLK
STBY
operation by bringing
input
low and can be powered up again for normal
STBY
transfer. During the first 48 SCLKs, the conversion data is
transferred from Device 2 to Device 1. DOUT A on Device 2
transfers conversion data from V1, V2, and V5 into DCIN A in
Device 1. DOUT B on Device 2 transfers conversion results from
V3, V4, and V6 to DCIN B in Device 1. During the first 48
SCLKs, Device 1 transfers data into the digital host. DOUT A on
Device 1 transfers conversion data from V1, V2, and V5.
DOUT B on Device 1 transfers conversion data from V3, V4,
and V6. During the last 48 SCLKs, Device 2 clocks out zeros
and Device 1 shifts the data clocked in from Device 2 during
the first 48 SCLKs into the digital host. This example can
also be implemented using six 16 SCLK individually framed
transfers if DCEN remains high during the transfers.
logic high. The output data buffers
are still operational when the AD7656-1/AD7657-1/AD7658-1
are in standby mode, meaning the user can continue to access
the conversion results of the parts. This standby feature can be
used to reduce the average power consumed by the AD7656-
1/AD7657-1/AD7658-1 when operating at lower throughput
rates. The parts can be placed into standby at the end of each
conversion when BUSY goes low and taken out of standby again
prior to the next conversion. The time for the AD7656-
1/AD7657-1/AD7658-1 to come out of standby is called the
wake-up time. The wake-up time limits the maximum
throughput rate at which the AD7656-1/AD7657-1/AD7658-1
can operate when powering down between conversions. See the
Specifications section.
Rev. PrC | Page 27 of 32
AD7656-1/AD7657-1/AD7658-1
Preliminary Technical Data
CONVERT
DIGITAL HOST
CONVST
CONVST
DCIN A
DCIN B
DOUT A
DOUT B
DATA IN1
DATA IN2
DOUT A
AD7656-1/
AD7657-1/
AD7658-1
AD7656-1/
DOUT B
AD7657-1/
AD7658-1
SCLK
CS
SCLK
CS
CS
SCLK
DCEN = 0
DCEN = 1
DEVICE 1
DEVICE 2
Figure 33. Daisy-Chain Configuration
CONVST A,
CONVST B,
CONVST C
BUSY
CS
1
2
3
15
16
17
31
32
33
47
48
49
63
64
65
94
95
96
SCLK
DEVICE 1, DOUT A
DEVICE 1, DOUT B
DEVICE 2, DOUT A
DEVICE 2, DOUT B
MSB V1
MSB V3
MSB V1
MSB V3
LSB V1 MSB V2
LSB V3 MSB V4
LSB V1 MSB V2
LSB V3 MSB V4
LSB V2 MSB V5
LSB V4 MSB V6
LSB V2 MSB V5
LSB V4 MSB V6
LSB V5 MSB V1
LSB V6 MSB V3
LSB V5
LSB V1 MSB V2
LSB V3 MSB V4
LSB V5
LSB V6
LSB V6
Figure 34. Daisy-Chain Serial Interface Timing with Two DOUT Lines
CONVST A,
CONVST B,
CONVST C
BUSY
CS
1
2
3
15
16
17
31
32
33
47
48
49
63
64
SCLK
DEVICE 1, DOUT A
DEVICE 1, DOUT B
DEVICE 1, DOUT C
DEVICE 2, DOUT A
DEVICE 2, DOUT B
DEVICE 2, DOUT C
MSB V1
MSB V3
MSB V5
MSB V1
MSB V3
MSB V5
LSB V1 MSB V2
LSB V3 MSB V4
LSB V5 MSB V6
LSB V1 MSB V2
LSB V3 MSB V4
LSB V5 MSB V6
LSB V2 MSB V1
LSB V4 MSB V3
LSB V6 MSB V5
LSB V2
LSB V1 MSB V2
LSB V3 MSB V4
LSB V5 MSB V6
LSB V2
LSB V4
LSB V6
LSB V4
LSB V6
Figure 35. Daisy-Chain Serial Interface Timing with Three DOUT Lines
Rev. PrC| Page 28 of 32
AD7656-1/AD7657-1/AD7658-1
Preliminary Technical Data
APPLICATION HINTS
near analog signal paths. Crossover of digital and analog signals
should be avoided. Traces on different but close layers of the
board should run at right angles to each other to reduce the
effect of feedthrough through the board.
LAYOUT
The printed circuit board that houses the AD7656-1/AD7657-
1/ AD7658-1 should be designed so that the analog and digital
sections are separated and confined to certain areas of the board.
The power supply lines to the AVCC, DVCC, VDRIVE, VDD, and VSS
pins on the AD7656-1/AD7657-1/AD7658-1 should use as large
a trace as possible to provide low impedance paths and reduce
the effect of glitches on the power supply lines. Good
connections should be made between the AD7656-1/AD7657-
1/AD7658-1 supply pins and the power tracks on the board;
this should involve the use of a single via or multiple vias for
each supply pin.
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In the case of
the split plane, the digital and analog ground planes should be
joined in only one place, preferably underneath the AD7656-1/
AD7657-1/AD7658-1, or at least as close as possible to each
part.
If the AD7656-1/AD7657-1/AD7658-1 are in a system where
multiple devices require analog-to-digital ground connections,
the connection should still be made at only one point, a star
ground point, which should be established as close as possible to
the AD7656-1/AD7657-1/AD7658-1. Good connections should
be made to the ground plane. Avoid sharing one connection for
multiple ground pins. Individual vias or multiple vias to the
ground plane should be used for each ground pin.
Good decoupling is also important to lower the supply
impedance presented to the AD7656-1/AD7657-1/AD7658-1
and to reduce the magnitude of the supply spikes. The
decoupling capacitors should be placed close to, ideally right up
against, these pins and their corresponding ground pins.
Additionally, low ESR 1 μF capacitors should be placed on each
of the supply pins, REFINOUT and each REFCAP pin. Avoid
sharing these capacitors between pins. Use big vias to connect
the capacitors to the power and ground planes. Use wide, short
traces between the via and the capacitor pad, or place the via
adjacent to the capacitor pad to minimize parasitic inductances.
Recommended decoupling is outlined in Figure 26.
Avoid running digital lines under the devices because doing so
couples noise onto the die. The analog ground plane should be
allowed to run under the AD7656-1/AD7657-1/AD7658-1 to
avoid noise coupling. Fast-switching signals like CONVST or
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board, and they should never run
Rev. PrC | Page 29 of 32
AD7656-1/AD7657-1/AD7658-1
OUTLINE DIMENSIONS
Preliminary Technical Data
0.75
0.60
0.45
12.00
BSC SQ
1.60
MAX
64
49
48
1
PIN 1
10.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
16
33
32
0.15
0.05
SEATING
PLANE
17
VIEW A
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 36. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7656-1BST
AD7656-1BST-500RL7
AD7656-1BSTZ1
AD7656-1BSTZ-REEL1
AD7656-1BSTZ-500RL71
AD7656-1YSTZ1
AD7656-1YSTZ-REEL1
AD7656-1YSTZ-500RL71
AD7657-1BSTZ1
AD7657-1BSTZ-REEL1
AD7657-1BSTZ-500RL71
AD7657-1YSTZ1
AD7657-1YSTZ-REEL1
AD7657-1YSTZ-500RL71
AD7658-1BSTZ1
AD7658-1BSTZ-REEL1
AD7658-1BSTZ-500RL71
AD7658-1YSTZ1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
AD7658-1YSTZ-REEL1
AD7658-1YSTZ-500RL71
1 Z = Pb-free part.
Rev. PrC| Page 30 of 32
Preliminary Technical Data
NOTES
AD7656-1/AD7657-1/AD7658-1
Rev. PrC | Page 31 of 32
AD7656-1/AD7657-1/AD7658-1
NOTES
Preliminary Technical Data
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PR07017-0-8/06(PrC)
Rev. PrC| Page 32 of 32
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