AD7654ACPZ [ADI]
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16-Bit, ꢀ1 LSB INL,
500 kSPS, Differential ADC
a
AD7676
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Throughput: 500 kSPS
AVDD AGND REF REFGND
DVDD DGND
INL: ꢀ1 LSB Max (ꢀ0.0015% of Full Scale)
16-Bit Resolution with No Missing Codes
S/(N+D): 94 dB Typ @ 45 kHz
OVDD
OGND
AD7676
THD: –110 dB Typ @ 45 kHz
Differential Input Range: ꢀ2.5 V
Both AC and DC Specifications
SERIAL
PORT
IN+
IN–
SWITCHED
CAP DAC
SER/PAR
BUSY
D[15:0]
CS
No Pipeline Delay
16
Parallel (8 Bits/16 Bits) and Serial 5 V/3 V Interface
SPI™/QSPI™/MICROWIRE™/DSP Compatible
Single 5 V Supply Operation
67 mW Typical Power Dissipation, 15 ꢁW @ 100 SPS
Power-Down Mode: 7 ꢁW Max
PARALLEL
INTERFACE
CLOCK
PD
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
RD
RESET
OB/2C
BYTESWAP
Packages: 48-Lead Quad Flatpack (LQFP)
48-Lead Frame Chip Scale (LFCSP)
Pin-to-Pin Compatible with the AD7675
CNVST
Table I. PulSAR Selection
APPLICATIONS
CT Scanners
Type/kSPS
100–250
500–570
800–1000
Data Acquisition
Instrumentation
Spectrum Analysis
Medical Instruments
Battery-Powered Systems
Process Control
Pseudo Differential
AD7660
AD7650
AD7664
True Bipolar
True Differential
18-Bit
AD7663
AD7675
AD7678
AD7665
AD7676
AD7679
AD7654
AD7671
AD7677
AD7674
Simultaneous/
Multichannel
GENERAL DESCRIPTION
The AD7676 is a 16-bit, 500 kSPS, charge redistribution SAR,
fully differential analog-to-digital converter (ADC) that oper-
ates from a single 5 V power supply. The part contains a high
speed 16-bit sampling ADC, an internal conversion clock,
error correction circuits, and both serial and parallel system
interface ports.
PRODUCT HIGHLIGHTS
1. Excellent INL
The AD7676 has a maximum integral nonlinearity of 1.0 LSB
with no missing 16-bit code.
The AD7676 is hardware factory-calibrated and is comprehen-
sively tested to ensure such ac parameters as signal-to-noise ratio
(SNR) and total harmonic distortion (THD), in addition to the
more traditional dc parameters of gain, offset, and linearity.
2. Superior AC Performances
The AD7676 has a minimum dynamic of 92 dB, 94 dB typical.
3. Fast Throughput
The AD7676 is a 500 kSPS, charge redistribution, 16-bit
It is fabricated using Analog Devices’ high performance, 0.6 micron
CMOS process and is available in a 48-lead LQFP or a tiny
48-lead LFCSP with operation specified from –40°C to +85°C.
SAR ADC with internal error correction circuitry.
4. Single-Supply Operation
The AD7676 operates from a single 5 V supply and typically
dissipates only 67 mW. It consumes 7 µW maximum when in
power-down.
5. Serial or Parallel Interface
Versatile parallel (8 bits or 16 bits) or 2-wire serial interface
arrangement compatible with either 3 V or 5 V logic.
SPI and QSPI are trademarks of Motorola, Inc.
MIRCOWIRE is a trademark of National Semiconductor Corporation.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
AD7676–SPECIFICATIONS (–40ꢂC to +85ꢂC, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUT
Voltage Range
VIN+ – VIN–
–VREF
–0.1
+VREF
+3
V
Operating Input Voltage
Analog Input CMRR
Input Current
V
IN+, VIN– to AGND
V
f
IN = 10 kHz
79
5
dB
µA
500 kSPS Throughput
Input Impedance
See Analog Inputs Section
0
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
2
500
µs
kSPS
DC ACCURACY
Integral Linearity Error
No Missing Codes
Transition Noise
–1
16
+1
LSB1
Bits
LSB
LSB
LSB
LSB
LSB
0.35
0.7
+Full-Scale Error2
–Full-Scale Error2
Zero Error2
–22
–22
–8
+22
+22
+8
Power Supply Sensitivity
AVDD = 5 V 5%
AC ACCURACY
Signal-to-Noise
f
IN = 20 kHz
92
94
dB3
dB3
dB3
dB3
dB3
dB3
dB3
dB3
dB3
MHz
fIN = 45 kHz
94
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
fIN = 20 kHz
104.5
110
110
–110
–110
94
fIN = 45 kHz
fIN = 20 kHz
–103.5
fIN = 45 kHz
fIN = 20 kHz
92
fIN = 45 kHz
94
fIN = 45 kHz, –60 dB Input
34
–3 dB Input Bandwidth
3.9
SAMPLING DYNAMICS
Aperture Delay
2
5
ns
ps rms
ns
Aperture Jitter
Transient Response
Full-Scale Step
750
REFERENCE
External Reference Voltage Range
External Reference Current Drain
2.3
2.5
170
AVDD – 1.85
V
µA
500 kSPS Throughput
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
–0.3
+2.0
–1
+0.8
V
OVDD + 0.3
V
+1
+1
µA
IIH
–1
µA
DIGITAL OUTPUTS
Data Format
Pipeline Delay
VOL
Parallel or Serial 16-Bit Conversion Results Available
Immediately after Completed Conversion
ISINK = 1.6 mA
ISOURCE = –100 µA
0.4
V
V
VOH
OVDD – 0.6
POWER SUPPLIES
Specified Performance
AVDD
4.75
4.75
2.7
5
5
5.25
5.25
5.254
V
V
V
DVDD
OVDD
Operating Current
AVDD
500 kSPS Throughput
9.5
3.9
37
67
15
mA
mA
µA
DVDD5
OVDD5
Power Dissipation5
500 kSPS Throughput
100 SPS Throughput
74
7
mW
µW
µW
In Power-Down Mode6
TEMPERATURE RANGE7
Specified Performance
TMIN to TMAX
–40
+85
°C
NOTES
1LSB means Least Significant Bit. Within the 2.5 V input range, one LSB is 76.3 µV.
2See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4The maximum should be the minimum of 5.25 V and DVDD + 0.3 V.
5Tested in Parallel Reading Mode.
6With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively.
7Contact factory for extended temperature range.
Specifications subject to change without notice.
–2–
REV. B
AD7676
TIMING SPECIFICATIONS (–40ꢂC to +85ꢂC, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figures 11 and 12
Convert Pulsewidth
Time between Conversions
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes except in Master Serial Read
Convert Mode
t1
t2
t3
t4
5
2
ns
µs
ns
µs
30
1.25
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth
t5
t6
t7
t8
t9
2
ns
ns
µs
ns
ns
10
1.25
750
10
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
t10
t11
t12
t13
1.25
ns
ns
ns
ns
45
5
40
15
Refer to Figures 16 and 17 (Master Serial Interface Modes)1
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CNVST LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay2
Internal SCLK Period2
525
3
25
12
7
4
2
40
Internal SCLK HIGH2
Internal SCLK LOW2
SDOUT Valid Setup Time2
SDOUT Valid Hold Time2
SCLK Last Edge to SYNC Delay2
CS HIGH to SYNC HI-Z
3
10
10
10
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert2
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
See Table I
1.25
25
µs
ns
Refer to Figures 18 and 19 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
t31
t32
t33
t34
t35
t36
t37
5
3
5
5
25
10
10
ns
ns
ns
ns
ns
ns
ns
18
External SCLK HIGH
External SCLK LOW
NOTES
1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2In Serial Master Read during Convert Mode, see Table II.
Specifications subject to change without notice.
–3–
REV. B
AD7676
Table II. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
0
0
0
1
1
0
1
1
Unit
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum
t18
t19
t19
t20
t21
t22
t23
t24
t28
3
17
50
70
22
21
18
4
17
17
ns
ns
ns
ns
ns
ns
ns
ns
µs
25
40
12
7
4
2
100
140
50
49
18
30
140
3.5
200
280
100
99
18
89
3
2
60
2.5
300
5.75
ABSOLUTE MAXIMUM RATINGS1
I
1.6mA
OL
Analog Inputs
IN+2, IN–2, REF, REFGND
. . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . 0.3 V
Supply Voltages
TO OUTPUT
PIN
1.4V
C
*
L
60pF
I
500ꢁA
OH
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . 7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Inputs . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Internal Power Dissipation3 . . . . . . . . . . . . . . . . . . . . 700 mW
Internal Power Dissipation4 . . . . . . . . . . . . . . . . . . . . . . 2.5 W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range
*
IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD
L
C
OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing
2V
0.8V
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
tDELAY
tDELAY
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2V
2V
0.8V
0.8V
Figure 2. Voltage Reference Levels for Timings
2 See Analog Inputs section.
3 Specification is for device in free air: 48-Lead LQFP: JA = 91°C/W, JC = 30°C/W.
4 Specification is for device in free air: 48-Lead LFCSP: JA = 26°C/W.
ORDERING GUIDE
Package
Option
Model
Temperature Range
Package Description
AD7676AST
AD7676ASTRL
AD7676ACP
AD7676ACPRL
EVAL-AD7676CB1
EVAL-CONTROL BRD22
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Quad Flatpack (LQFP)
Quad Flatpack (LQFP)
Chip Scale (LFCSP)
Chip Scale (LFCSP)
Evaluation Board
ST-48
ST-48
CP-48
CP-48
Controller Board
NOTES
1This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for
evaluation/demonstration purposes.
2This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7676 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
AD7676
PIN FUNCTION DESCRIPTIONS
Description
Pin No. Mnemonic
Type
1
2
AGND
AVDD
P
P
Analog Power Ground Pin
Input Analog Power Pins. Nominally 5 V.
No Connect
3, 6, 7, NC
40–42,
44–48
4
5
BYTESWAP
DI
DI
Parallel Mode Selection (8-Bit/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB is
output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
OB/2C
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight
binary. When LOW, the MSB is inverted resulting in a twos complement output from its internal
shift register.
8
SER/PAR
D[0:1]
DI
Serial/Parallel Selection Input. When LOW, the Parallel Port is selected. When HIGH, the
Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port.
9, 10
11, 12
DO
DI/O
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in
high impedance.
D[2:3] or
When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data
Output Bus.
DIVSCLK[0:1]
When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the Serial Master
Read after Convert Mode. These inputs, part of the Serial Port, are used to slow down, if desired,
the internal serial clock that clocks the data output. In the other serial modes, these pins are high
impedance outputs.
13
D[4]
or EXT/INT
DI/O
When SER/PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for
choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is
selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to
an external clock signal connected to the SCLK input.
14
15
16
D[5]
or INVSYNC
DI/O
DI/O
DI/O
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of
the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
D[6]
or INVSCLK
When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal.
It is active in both Master and Slave Modes.
D[7]
or RDC/SDIN
When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data
input or a Read Mode selection input depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion
results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is
output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When
EXT/INT is LOW, RDC/SDIN is used to select the Read Mode. When RDC/SDIN is HIGH,
the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data is output
on SDOUT only when the conversion is complete.
17
18
OGND
OVDD
P
P
Input/Output Interface, Digital Power Ground
Input/Output Interface, Digital Power. Nominally at the same supply as the supply of the host
interface (5 V or 3 V).
19
20
DVDD
DGND
P
P
Digital Power. Nominally at 5 V.
Digital Power Ground
REV. B
–5–
AD7676
PIN FUNCTION DESCRIPTIONS (continued)
Description
Pin No. Mnemonic
Type
21
D[8]
or SDOUT
DO
When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. When
SER/PAR is HIGH, this output, part of the Serial Port, is used as a serial data output synchronized
to SCLK. Conversion results are stored in an on-chip register. The AD7676 provides the conversion
result, MSB first, from its internal shift register. The DATA format is determined by the logic level
of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK.
In Serial Mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge.
22
23
D[9]
or SCLK
DI/O
DO
When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input or
output, depending on the logic state of the EXT/INT pin. The active edge where the data SDOUT
is updated depends on the logic state of the INVSCLK pin.
D[10]
or SYNC
When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this output, part of the Serial Port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read
sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while
SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is
driven LOW and remains LOW while SDOUT output is valid.
24
D[11]
or RDERROR
DO
When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is used as
an incomplete read error flag. In Slave Mode, when a data read is started and not complete when
the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH.
25–28
29
D[12:15]
BUSY
DO
DO
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless
of the state of SER/PAR.
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could
be used as a data-ready clock signal.
30
31
32
DGND
RD
P
Must Be Tied to Digital Ground
DI
DI
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
CS
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
CS is also used to gate the external serial clock.
33
34
RESET
PD
DI
DI
Reset Input. When set to a logic HIGH, resets the AD7676. Current conversion if any is aborted.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions
are inhibited after the current one is completed.
35
CNVST
DI
Start Conversion. If CNVST is HIGH when the acquisition phase (t8) is complete, the next falling
edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion.
This mode is the most appropriate if low sampling jitter is desired. If CNVST is LOW when the
acquisition phase (t8) is complete, the internal sample-and-hold is put into the hold state and a
conversion is started immediately.
36
AGND
REF
P
Must Be Tied to Analog Ground
Reference Input Voltage
37
AI
AI
AI
AI
38
REFGND
IN–
Reference Input Analog Ground
Differential Negative Analog Input
Differential Positive Analog Input
39
43
IN+
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
–6–
REV. B
AD7676
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
1
AGND
AVDD
36
35
34
33
32
31
30
29
28
27
26
25
AGND
PIN 1
IDENTIFIER
2
CNVST
PD
3
4
5
NC
BYTESWAP
RESET
OB/2C
NC
CS
AD7676
6
RD
TOP VIEW
7
NC
DGND
BUSY
D15
D14
D13
D12
(Not to Scale)
8
SER/PAR
D0
9
10
D1
11
12
D2/DIVSCLK[0]
D3/DIVSCLK[1]
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
DEFINITION OF SPECIFICATIONS
Integral Nonlinearity Error (INL)
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
Integral nonlinearity is the maximum deviation of a straight line
drawn through the transfer function of the actual ADC. The
deviation is measured from the middle of each code.
input. It is related to S/(N+D) by the following formula:
ENOB = S / N + D
–1.76 / 6.02
(
[
]
)
dB
Differential Nonlinearity Error (DNL)
and is expressed in bits.
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It is
often specified in terms of resolution for which no missing codes
are guaranteed.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
+Full-Scale Error
Signal-to-Noise Ratio (SNR)
The last transition (from 011 . . . 10 to 011 . . . 11 in twos comple-
ment coding) should occur for an analog voltage 1 1/2 LSB below
the nominal +full scale (+2.499886 V for the 2.5 V range). The
+full-scale error is the deviation of the actual level of the last
transition from the ideal level.
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels (dB).
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
–Full-Scale Error
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels (dB).
The first transition (from 100 . . . 00 to 100 . . . 01 in twos comple-
ment coding) should occur for an analog voltage 1/2 LSB above
the nominal –full scale (–2.499962 V for the 2.5 V range). The
–full-scale error is the deviation of the actual level of the last
transition from the ideal level.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Bipolar Zero Error
The bipolar zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the midscale
output code.
Transient Response
The time required for the AD7676 to achieve its rated accuracy
after a full-scale step function is applied to its input.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
REV. B
–7–
AD7676
–Typical Performance Characteristics
1.00
0.75
0.50
0.25
0
16000
14000
12000
10000
8000
14640
–0.25
–0.50
–0.75
6000
4000
2000
880
863
0
0
0
0
0
0
0
0
–1.00
0
0000
16384
32768
CODE
49152
65536
7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004
CODE IN HEXA
TPC 4. Histogram of 16,384 Conversions of a DC Input at
the Code Center
TPC 1. Integral Nonlinearity vs. Code
9000
8000
7000
6000
5000
4000
3000
2000
1000
0000
20
16
12
8
8271
8094
4
0
0
0
8
11
0
0
0
0
7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004
CODE IN HEXA
–1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0.0
NEGATIVE INL – LSB
TPC 5. Typical Negative INL Distribution (199 Units)
TPC 2. Histogram of 16,384 Conversions of a DC Input at
the Code Transition
0
20
16
12
8
fS = 500kSPS
fIN = 45.01kHz
SNR = 94dB
THD = –110dB
SFDR = 110dB
SINAD = 93.9dB
–20
–40
–60
–80
–100
–120
–140
–160
–180
4
0
0
50
100
150
200
250
0
0.1
0.2
0.3 0.4
0.5
0.6 0.7
0.8
0.9
1.0
FREQUENCY – kHz
POSITIVE INL – LSB
TPC 3. Typical Positive INL Distribution (199 Units)
TPC 6. FFT Plot
–8–
REV. B
AD7676
100
95
90
85
80
75
70
16.0
15.5
15.0
14.5
14.0
13.5
13.0
50
40
30
20
10
0
OVDD = 2.7V @ 85ꢂC
OVDD = 2.7V @ 25ꢂC
SNR
S/(NꢃD)
OVDD = 5.0V @ 85ꢂC
ENOB
OVDD = 5.0V @ 25ꢂC
1
10
100
1000
0
50
100
– pF
150
200
FREQUENCY – kHz
C
L
TPC 7. SNR, S/(N+D), and ENOB vs. Frequency
TPC 10. Typical Delay vs. Load Capacitance CL
100k
96
10k
1k
SNR
S/(NꢃD)
93
100
10
AVDD
DVDD
90
87
83
1
OVDD
0.1
0.01
0.001
–60
–50
–40
–30
–20
–10
0
10
100
1k
10k
100k
1M
INPUT LEVEL – dB
SAMPLING RATE – SPS
TPC 8. SNR and S/(N+D) vs. Input Level
TPC 11. Operating Currents vs. Sample Rate
96
93
90
87
84
–104
250
DVDD
SNR
200
150
100
50
–106
–108
–110
–112
THD
AVDD
OVDD
0
–55
–35
–15
0
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
TEMPERATURE – ꢂC
TEMPERATURE – ꢂC
TPC 9. SNR, THD vs. Temperature
TPC 12. Power-Down Operating Currents vs. Temperature
–9–
REV. B
AD7676
5
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW–.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire both analog signals.
4
3
2
–FS
1
0
When the acquisition phase is complete and the CNVST input
goes or is low, a conversion phase is initiated. When the conversion
phase begins, SW+ and SW– are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the REFGND input. Therefore, the differential voltage between
the output of IN+ and IN– captured at the end of the acquisition
phase is applied to the comparator inputs, causing the comparator
to become unbalanced.
–1
–2
OFFSET
+FS
–3
–4
–5
–55 –35 –15
–5
15
35
55
75
95 115 135
By switching each element of the capacitor array between
REFGND or REF, the comparator input varies by binary
weighted voltage steps (VREF/2, VREF/4 . . . VREF/65536). The
control logic toggles these switches, starting with the MSB first,
in order to bring the comparator back into a balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings BUSY output LOW.
TEMPERATURE – ꢂC
TPC 13. Drift vs. Temperature
CIRCUIT INFORMATION
Transfer Functions
The AD7676 is a fast, low power, single-supply, precise 16-bit
analog-to-digital converter (ADC). The AD7676 is capable of
converting 500,000 samples per second (500 kSPS) and allows
power saving between conversions. When operating at 100 SPS,
for example, it typically consumes only 15 µW. This feature
makes the AD7676 ideal for battery-powered applications.
Using the OB/2C digital input, the AD7676 offers two output
codings: straight binary and twos complement. The ideal transfer
characteristic for the AD7676 is shown in Figure 4.
The AD7676 provides the user with an on-chip track-and-hold,
successive-approximation ADC that does not exhibit any pipeline
or latency, making it ideal for multiple multiplexed channel
applications.
111...111
111...110
111...101
The AD7676 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP package or a 48-lead LFCSP package that combines
space savings and allows flexible configurations as either serial
or parallel interface. The AD7676 is pin-to-pin compatible with
the AD7675.
000...010
000...001
000...000
–FS
–FS + 1 LSB
+FS – 1 LSB
+FS – 1.5 LSB
–FS + 0.5 LSB
CONVERTER OPERATION
The AD7676 is a successive-approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC consists
of two identical arrays of 16 binary weighted capacitors.
ANALOG INPUT
Figure 4. ADC Ideal Transfer Function
IN+
SWITCHES
CONTROL
MSB
LSB
SW
+
32,768C 16,384C
4C
2C
C
C
BUSY
REF
CONTROL
LOGIC
COMP
OUTPUT
CODE
REFGND
4C
2C
C
C
32,768C 16,384C
MSB
SW
LSB
–
CNVST
IN–
Figure 3. ADC Simplified Schematic
–10–
REV. B
AD7676
DVDD
ANALOG
SUPPLY
(5V)
100ꢄ
DIGITAL SUPPLY
(3.3V OR 5V)
NOTE 6
+
+
+
100nF
10ꢁF
10ꢁF
100nF
100nF
10ꢁF
ADR421
AVDD
REF
AGND
DGND
OVDD
OGND
DVDD
SERIAL PORT
2.5V REF
NOTE 1
SCLK
1Mꢄ
100nF
NOTE 3
50ꢄ
C
+
REF
50kꢄ
1ꢁF
SDOUT
NOTE 2
REFGND
BUSY
ꢁC/ꢁP/DSP
50ꢄ
–
U1
15ꢄ
CNVST
D
NOTE 4
IN+
+
ANALOG INPUT+
NOTE 7
C
2.7nF
C
AD8021
AD7676
NOTE 5
OB/2C
SER/PAR
DVDD
50ꢄ
–
U2
+
CLOCK
CS
RD
15ꢄ
NOTE 4
IN–
ANALOG INPUT–
BYTESWAP
RESET
PD
C
2.7nF
C
AD8021
NOTE 5
NOTES
1. SEEVOLTAGE REFERENCE INPUT SECTION.
2. WITHTHE RECOMMENDEDVOLTAGE REFERENCES, C
IS 47ꢁF. SEEVOLTAGE REFERENCE INPUT SECTION.
REF
3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.
4. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
5. SEE ANALOG INPUTS SECTION.
6. OPTION, SEE POWER SUPPLY SECTION.
7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.
Figure 5. Typical Connection Diagram ( 2.5 V Range Shown)
TYPICAL CONNECTION DIAGRAM
current. These diodes can handle a forward-biased current of
120 mA maximum. This condition could eventually occur when
the input buffer’s (U1) or (U2) supplies are different from
AVDD. In such a case, an input buffer with a short-circuit
current limitation can be used to protect the part.
Figure 5 shows a typical connection diagram for the AD7676.
Different circuitry shown on this diagram is optional and is
discussed below.
Analog Inputs
The AD7676 is specified to operate with a differential 2.5 V
range. The typical input impedance for each analog input range
is also shown. Figure 6 shows a simplified analog input section
of the AD7676.
This analog input structure is a true differential structure. By
using these differential inputs, signals common to both inputs
are rejected as shown in Figure 7, which represents the typical
CMRR over frequency.
AVDD
85
80
75
70
65
60
55
50
45
40
R+ = 684ꢄ
IN+
C
S
C
S
IN–
R– = 684ꢄ
AGND
Figure 6. Simplified Analog Input
The diodes shown in Figure 6 provide ESD protection for the
inputs. Care must be taken to ensure that the analog input signal
never exceeds the absolute ratings on these inputs. This will
cause these diodes to become forward-biased and start conducting
1k
10k
100k
1M
10M
FREQUENCY – Hz
Figure 7. Analog Input CMRR vs. Frequency
REV. B
–11–
AD7676
During the acquisition phase for ac signals, the AD7676 behaves
like a one-pole RC filter consisting of the equivalent resistance
R+, R–, and CS. The resistors R+ and R– are typically 684 Ω and
are lumped components made up of some serial resistors and the
on resistance of the switches. The capacitor CS is typically 60 pF
and is mainly the ADC sampling capacitor. This one-pole filter
with a typical –3 dB cutoff frequency of 3.88 MHz reduces unde-
sirable aliasing effects and limits the noise coming from the inputs.
performance of the AD7676. The noise coming from the driver is
filtered by the AD7676 analog input circuit one-pole, low-pass
filter made by R+, R–, and CS. The SNR degradation due to
the amplifier is:
28
SNRLOSS = 20LOG
2
784 + π f−3 dB (N eN
)
where:
–3 dB is the –3 dB input bandwidth of the AD7676 (3.9 MHz)
or the cutoff frequency of the input filter if any is used.
Because the input impedance of the AD7676 is very high, the
AD7676 can be driven directly by a low impedance source without
gain error. That allows users to put, as shown in Figure 5, an
external one-pole RC filter between the output of the amplifier
output and the ADC analog inputs to even further improve the
noise filtering done by the AD7676 analog input circuit. However,
the source impedance has to be kept low because it affects the
ac performances, especially the total harmonic distortion (THD).
The maximum source impedance depends on the amount of
THD that can be tolerated. The THD degrades proportionally
to the source impedance.
f
N is the noise factor of the amplifier (1 if in buffer
configuration).
eN is the equivalent input noise voltage of the op amp in nV/√Hz.
For instance, a driver with an equivalent input noise of
2 nV/√Hz like the AD8021 and configured as a buffer, thus
with a noise gain of +1, will degrade the SNR by only 0.26 dB.
The AD8021 meets these requirements and is usually appropriate
for almost all applications. The AD8021 needs an external
compensation capacitor of 10 pF. This capacitor should have
good linearity as an NPO ceramic or mica type.
Single-to-Differential Driver
For applications using unipolar analog signals, a single-ended-to-
differential driver will allow for a differential input into the part.
The schematic is shown in Figure 8.
The AD8022 could also be used where a dual version is needed
and a gain of 1 is used.
The AD8132 or the AD8138 could also be used to generate
a differential signal from a single-ended signal.
U1
ANALOG INPUT
AD8021
(UNIPOLAR)
C
C
The AD829 is another alternative where high frequency (above
500 kHz) performance is not required. In a gain of 1, it requires
an 82 pF compensation capacitor.
590ꢄ
IN+
IN–
590ꢄ
AD7676
The AD8610 is also another option where low bias current is
needed in low frequency applications.
U2
590ꢄ
590ꢄ
REF
2.5V REF
AD8021
Voltage Reference Input
The AD7676 uses an external 2.5 V voltage reference.
C
C
2.5V REF
The voltage reference input REF of the AD7676 has a dynamic
input impedance. Therefore, it should be driven by a low imped-
ance source with an efficient decoupling between the REF and
REFGND inputs. This decoupling depends on the choice of the
voltage reference but usually consists of a low ESR tantalum
capacitor connected to the REF and REFGND inputs with
minimum parasitic inductance. 47 µF is an appropriate value for
the tantalum capacitor when used with one of the recommended
reference voltages:
Figure 8. Single-Ended-to-Differential Driver Circuit
This configuration, when provided an input signal of 0 to VREF
will produce a differential 2.5 V with a common mode at 1.25 V.
If the application can tolerate more noise, the AD8138 can be used.
,
Driver Amplifier Choice
Although the AD7676 is easy to drive, the driver amplifier needs
to meet the following requirements:
• The driver amplifier and the AD7676 analog input circuit have
to be able, together, to settle for a full-scale step of the capaci-
tor array at a 16-bit level (0.0015%). In the amplifier’s data
sheet, the settling at 0.1% or 0.01% is more commonly
specified. It could significantly differ from the settling time
at the 16-bit level and, therefore, it should be verified prior to
the driver selection. The tiny op amp AD8021, which com-
bines ultralow noise and a high gain bandwidth, meets this
settling time requirement even when used with a high gain
up to 13.
•
The low noise, low temperature drift ADR421 and AD780
voltage references
•
•
The low power ADR291 voltage reference
The low cost AD1582 voltage reference
For applications using multiple AD7676s, it is more effective to
buffer the reference voltage with a low noise, very stable op amp
like the AD8031.
Care should also be taken with the reference temperature coeffi-
cient of the voltage reference, which directly affects the full-scale
accuracy if this parameter matters. For instance, a 15 ppm/°C
tempco of the reference changes the full scale by 1 LSB/°C.
• The driver needs to have a THD performance suitable to
that of the AD7676.
• The noise generated by the driver amplifier needs to be kept
as low as possible to preserve the SNR and transition noise
–12–
REV. B
AD7676
1M
100k
10k
1k
VREF , as mentioned in the specification table, could be increased
to AVDD – 1.85 V. The benefit here is the increased SNR obtained
as a result of this increase. Since the input range is defined in
terms of VREF, this would essentially increase the range to make
it a 3 V input range with an AVDD above 4.85 V. The theo-
retical improvement as a result of this increase in reference is
1.58 dB (20 log [3/2.5]). Due to the theoretical quantization noise,
however, the observed improvement is approximately 1 dB. The
AD780 can be selected with a 3 V reference voltage.
100
10
Power Supply
The AD7676 uses three sets of power supply pins: an analog 5 V
supply AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. The OVDD supply allows
direct interface with any logic working between 2.7 V and
DVDD + 0.3 V. To reduce the number of supplies needed, the
digital core (DVDD) can be supplied through a simple RC filter
from the analog supply as shown in Figure 5. The AD7676 is
independent of power supply sequencing once OVDD does not
exceed DVDD by more than 0.3 V and thus free from supply
voltage-induced latch-up. Additionally, it is very insensitive to
power supply variations over a wide frequency range, as shown in
Figure 9.
1
0.1
10
100
1k
10k
100k
1M
SAMPLING RATE – SPS
Figure 10. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7676 is controlled by the signal CNVST, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. The CNVST signal operates independently of CS
and RD signals.
75
70
65
60
55
50
45
40
35
t2
t1
CNVST
BUSY
t4
t3
t6
t5
ACQUIRE
CONVERT
t7
MODE
CONVERT
ACQUIRE
t8
1k
10k
100k
1M
10M
Figure 11. Basic Conversion Timing
FREQUENCY – Hz
For true sampling applications, the recommended operation of
the CNVST signal is the following:
Figure 9. PSRR vs. Frequency
POWER DISSIPATION
The AD7676 automatically reduces its power consumption at
the end of each conversion phase. During the acquisition phase,
the operating currents are very low, which allows a significant
power savings when the conversion rate is reduced, as shown in
Figure 10. This feature makes the AD7676 ideal for very low
power battery-operated applications.
CNVST must be held HIGH from the previous falling edge of
BUSY, and during a minimum delay corresponding to the acqui-
sition time t8; then, when CNVST is brought LOW, a conversion
is initiated and the BUSY signal goes HIGH until the comple-
tion of the conversion. Although CNVST is a digital signal, it
should be designed with this special care with fast, clean edges,
and levels, with minimum overshoot and undershoot or ringing.
For applications where the SNR is critical, the CNVST signal
should have a very low jitter. To achieve this, some use a dedicated
oscillator for CNVST generation or, at least, to clock it with a
high frequency low jitter clock as shown in Figure 5.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be driven
close to the power rails (i.e., DVDD and DGND) and OVDD
should not exceed DVDD by more than 0.3 V.
REV. B
–13–
AD7676
t9
PARALLEL INTERFACE
The AD7676 is configured to use the parallel interface (Figure 13)
when the SER/PAR is held LOW. The data can be read either
after each conversion, which is during the next acquisition phase,
or during the following conversion as shown, respectively, in
Figures 14 and 15. When the data is read during the conversion,
however, it is recommended that it be read-only during the first
half of the conversion phase. That avoids any potential feedthrough
between voltage transients on the digital interface and the most
critical analog conversion circuitry.
RESET
BUSY
DATABUS
t8
CS
CNVST
RD
Figure 12. RESET Timing
For other applications, conversions can be automatically initiated.
If CNVST is held LOW when BUSY is LOW, the AD7676
controls the acquisition phase and then automatically initiates a
new conversion. By keeping CNVST LOW, the AD7676 keeps
the conversion process running by itself. It should be noted that
the analog input has to be settled when BUSY goes LOW. Also,
at power-up, CNVST should be brought LOW once to initiate the
conversion process. In this mode, the AD7676 could sometimes
run slightly faster than the guaranteed limit of 500 kSPS.
BUSY
CURRENT
DATABUS
CONVERSION
t12
t13
Figure 14. Slave Parallel Data Timing for Reading
(Read after Conversion)
CS = 0
t1
CNVST,
DIGITAL INTERFACE
RD
The AD7676 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel databus. The
AD7676 digital interface also accommodates both 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7676
to the host system interface digital supply. Finally, by using the
OB/2C input pin, either twos complement or straight binary
coding can be used.
BUSY
t4
t3
PREVIOUS
DATABUS
CONVERSION
t12
t13
The two signals CS and RD control the interface. When at least
one of these signals is HIGH, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7676 in
multicircuit applications and is held LOW in a single AD7676
design. RD is generally used to enable the conversion result on
the databus.
Figure 15. Slave Parallel Data Timing for Reading (Read
during Conversion)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 16, the LSB byte is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is LOW. When
BYTESWAP is HIGH, the LSB and MSB bytes are swapped and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].
CS = RD = 0
t1
CNVST
t10
CS
RD
t4
BUSY
t3
t11
PREVIOUS CONVERSION DATA
NEW DATA
DATABUS
BYTE
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)
HI-Z
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
PINS D[15:8]
PINS D[7:0]
t12
t12
t13
HI-Z
LOW BYTE
HIGH BYTE
Figure 16. 8-Bit Parallel Interface
–14–
REV. B
AD7676
SERIAL INTERFACE
data is valid. The serial clock SCLK and the SYNC signal can be
inverted if desired. The output data is valid on both the rising
and falling edges of the data clock. Depending on RDC/SDIN
input, the data can be read after each conversion or during the
following conversion. Figures 17 and 18 show the detailed timing
diagrams of these two modes.
The AD7676 is configured to use the serial interface when the
SER/PAR is held HIGH. The AD7676 outputs 16 bits of data
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin.
MASTER SERIAL INTERFACE
Internal Clock
The AD7676 is configured to generate and provide the serial data
clock SCLK when the EXT/INT pin is held LOW. The AD7676 also
generates a SYNC signal to indicate to the host when the serial
Usually, because the AD7676 has a longer acquisition phase
than the conversion phase, the data is read immediately after
conversion. That makes the mode master, read after conversion,
the most recommended serial mode when it can be used.
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
EXT/INT = 0
CS, RD
t3
CNVST
t28
BUSY
t30
t29
t25
SYNC
t14
t18
t19
t24
t20
t21
2
t26
1
3
14
15
16
SCLK
t15
t27
X
D15
D14
t23
D2
D1
D0
SDOUT
t16
t22
Figure 17. Master Serial Data Timing for Reading (Read after Conversion)
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
EXT/INT = 0
CS, RD
t1
CNVST
t3
BUSY
t17
t25
SYNC
t14
t19
t20 t21
t24
t26
t15
SCLK
1
2
3
14
15
16
t18
t27
X
D15
D14
t23
D2
D1
D0
SDOUT
t16
t22
Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Conversion)
REV. B
–15–
AD7676
In Read-after-Conversion Mode, unlike in other modes, it should
be noted that the signal BUSY returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
an external clock is being provided, it is a discontinuous clock
that is toggling only when BUSY is LOW or, more importantly,
that it does not transition during the latter half of BUSY HIGH.
External Discontinuous Clock Data Read after Conversion
This mode is the most recommended of the serial slave modes.
Figure 19 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
LOW, the result of this conversion can be read while both CS and
RD are LOW. The data is shifted out, MSB first, with 16 clock
pulses and is valid on both the rising and falling edges of the clock.
In Read-during-Conversion Mode, the serial clock and data
toggle at appropriate instances, which minimizes potential feed-
through between digital activity and the critical conversion decisions.
SLAVE SERIAL INTERFACE
External Clock
The AD7676 is configured to accept an externally supplied serial
data clock on the SCLK pin when the EXT/INT pin is held HIGH.
In this mode, several methods can be used to read the data. The
external serial clock is gated by CS and the data are output when
both CS and RD are LOW. Thus, depending on CS, the data can
be read after each conversion or during the following conversion.
The external clock can be either a continuous or discontinuous
clock. A discontinuous clock can be either normally HIGH or
normally LOW when inactive. Figures 19 and 20 show the detailed
timing diagrams of these methods. Usually, because the AD7676
has a longer acquisition phase than the conversion phase, the
data are read immediately after conversion.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients
on the digital interface during the conversion process.
Another advantage is to be able to read the data at any speed up to
40 MHz, which accommodates both slow digital host interface
and the fastest serial reading.
Finally, in this mode only, the AD7676 provides a “daisy chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing component
count and wiring connections when it is desired as it is, for
instance, in isolated multiconverter applications.
While the AD7676 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is particu-
larly important during the second half of the conversion phase
because the AD7676 provides error correction circuitry that can
correct for an improper bit decision made during the first half of
the conversion phase. For this reason, it is recommended that when
An example of the concatenation of two devices is shown in
Figure 21. Simultaneous sampling is possible by using a common
CNVST signal. It should be noted that the RDC/SDIN input is
latched on the opposite edge of SCLK of the one used to shift
out the data on SDOUT. Thus, the MSB of the “upstream”
converter just follows the LSB of the “downstream” converter
on the next SCLK cycle.
INVSCLK = 0
EXT/INT = 1
RD = 0
CS
BUSY
t35
t36
t37
SCLK
1
2
3
14
15
16
17
18
t31
t32
SDOUT
X
D15
D14
D13
X13
D1
X1
D0
X15
Y15
X14
Y14
t16
t34
SDIN
X15
X14
X0
t33
Figure 19. Slave Serial Data Timing for Reading (Read after Conversion)
–16–
REV. B
AD7676
External Clock Data Read During Conversion
interface or with a general-purpose Serial Port or I/O Ports on a
microcontroller. A variety of external buffers can be used with
the AD7676 to prevent digital noise from coupling into the ADC.
The following sections illustrate the use of the AD7676 with
an SPI-equipped microcontroller, and the ADSP-21065L and
ADSP-218x signal processors.
Figure 20 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are LOW, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 16 clock pulses, and is valid on both rising and
falling edges of the clock. The 16 bits have to be read before the
current conversion is complete. If that is not done, RDERROR is
pulsed HIGH and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy chain feature
in this mode, and RDC/SDIN input should always be tied either
HIGH or LOW.
SPI Interface (MC68HC11)
Figure 22 shows an interface diagram between the AD7676 and an
SPI-equipped microcontroller, such as the MC68HC11. To accom-
modate the slower speed of the microcontroller, the AD7676 acts
as a slave device and data must be read after conversion. This mode
also allows the daisy chain feature. The convert command could
be initiated in response to an internal timer interrupt. The reading
of output data, one byte at a time if necessary, could be initiated
in response to the end-of-conversion signal (BUSY going LOW)
using an interrupt line of the microcontroller. The serial periph-
eral interface (SPI) on the MC68HC11 is configured for Master
Mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase
Bit (CPHA) = 1, and SPI interrupt enable (SPIE) = 1 by writing
to the SPI Control Register (SPCR). The IRQ is configured for
edge-sensitive-only operation (IRQE = 1 in OPTION register).
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 18 MHz is recommended to ensure
that all the bits are read during the first half of the conversion
phase. For this reason, this mode is more difficult to use.
MICROPROCESSOR INTERFACING
The AD7676 is ideally suited for traditional dc measurement
applications supporting a microprocessor and ac signal processing
applications interfacing to a digital signal processor. The AD7676
is designed to interface either with a parallel 8-bit or 16-bit wide
INVSCLK = 0
EXT/INT = 1
RD = 0
CS
CNVST
BUSY
t3
t35
t36 t37
SCLK
1
2
3
14
15
16
t31
t32
SDOUT
X
D15
D14
D13
D1
D0
t16
Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion during Conversion)
BUSY
OUT
BUSY
BUSY
AD7676 NO. 2
(UPSTREAM)
AD7676 NO. 1
(DOWNSTREAM)
DATA
OUT
RDC/SDIN
SDOUT
RDC/SDIN
SDOUT
CNVST
CS
CNVST
CS
SCLK
SCLK
SCLK IN
CS IN
CNVST IN
Figure 21. Two AD7676s in a Daisy Chain Configuration
–17–
REV. B
AD7676
DVDD
ground planes that can be easily separated. Digital and analog
ground planes should be joined in only one place, preferably
underneath the AD7676, or, at least, as close as possible to the
AD7676. If the AD7676 is in a system where multiple devices
require analog to digital ground connections, the connection
should still be made at one point only, a star ground point
that should be established as close as possible to the AD7676.
MC68HC11*
AD7676*
SER/PAR
EXT/INT
CS
BUSY
SDOUT
SCLK
IRQ
RD
MISO/SDI
SCK
INVSCLK
CNVST
I/O PORT
It is recommended to avoid running digital lines under the device
as these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7676 to avoid noise
coupling. Fast switching signals like CNVST or clocks should be
shielded with digital ground to avoid radiating noise to other sec-
tions of the board and should never run near analog signal paths.
Crossover of digital and analog signals should be avoided. Traces
on different but close layers of the board should run at right
angles to each other. This will reduce the effect of feedthrough
through the board.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. Interfacing the AD7676 to SPI Interface
ADSP-21065L in Master Serial Interface
As shown in Figure 23, the AD7676 can be interfaced to the
ADSP-21065L using the serial interface in Master Mode without
any glue logic required. This mode combines the advantages of
reducing the wire connections and the ability to read the data during
or after conversion maximum speed transfer (DIVSCLK[0:1]
both LOW).
The power supply lines to the AD7676 should use as large a
trace as possible to provide low impedance paths and reduce the
effect of glitches on the power supply lines. Good decoupling is
also important to lower the supply’s impedance presented to
the AD7676 and reduce the magnitude of the supply spikes.
Decoupling ceramic capacitors, typically 100 nF, should be
placed on each power supply’s pins, AVDD, DVDD, and OVDD,
close to and ideally right up against these pins and their corre-
sponding ground pins. Additionally, low ESR 10 µF capacitors
should be located in the vicinity of the ADC to further reduce
low frequency ripple.
The AD7676 is configured for the Internal Clock Mode (EXT/INT
LOW) and acts, therefore, as the master device. The convert
command can be generated by either an external low jitter oscil-
lator or, as shown, by a FLAG output of the ADSP-21065L or by
a frame output TFS of one serial port of the ADSP-21065L that
can be used like a timer. The Serial Port on the ADSP-21065L
is configured for external clock (IRFS = 0), rising edge active
(CKRE = 1), external late framed sync signals (IRFS = 0,
LAFS = 1, RFSR = 1), and active HIGH (LRFS = 0). The Serial
Port of the ADSP-21065L is configured by writing to its receive
control register (SRCTL)—see the ADSP-2106x SHARC User’s
Manual. Because the Serial Port within the ADSP-21065L will
be seeing a discontinuous clock, an initial word reading has to
be done after the ADSP-21065L has been reset to ensure that
the Serial Port is properly synchronized to this clock during each
following data read operation.
The DVDD supply of the AD7676 can be either a separate
supply or come from the analog supply, AVDD, or from the
digital interface supply, OVDD. When the system digital supply
is noisy, or fast switching digital signals are present, it is recom-
mended if no separate supply is available, to connect the DVDD
digital supply to the analog supply AVDD through an RC filter as
shown in Figure 5 and to connect the system supply to the inter-
face digital supply OVDD and the remaining digital circuitry.
When DVDD is powered from the system supply, it is useful to
insert a bead to further reduce high frequency spikes.
DVDD
ADSP-21065L*
AD7676*
SHARC
SER/PAR
The AD7676 has four different ground pins: REFGND, AGND,
DGND, and OGND. REFGND senses the reference voltage and
should be a low impedance return to the reference because it
carries pulsed currents. AGND is the ground to which most inter-
nal ADC analog signals are referenced. This ground must be
connected with the least resistance to the analog ground plane.
DGND must be tied to the analog or digital ground plane,
depending on the configuration. OGND is connected to the
digital system ground.
RDC/SDIN
RD
SYNC
SDOUT
SCLK
RFS
EXT/INT
DR
CS
RCLK
INVSYNC
INVSCLK
CNVST
FLAG OR TFS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. Interfacing to the ADSP-21065L Using
the Serial Master Mode
The layout of the decoupling of the reference voltage is important.
The decoupling capacitor should be close to the ADC and
connected with short and large traces to minimize parasitic
inductances.
APPLICATION HINTS
Layout
Evaluating the AD7676 Performance
The AD7676 has very good immunity to noise on the power
supplies as can be seen in Figure 21. However, care should still
be taken with regard to grounding layout.
A recommended layout for the AD7676 is outlined in the
evaluation board for the AD7676. The evaluation board package
includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from a
PC via the Eval-Control BRD2.
The printed circuit board that houses the AD7676 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use of
–18–
REV. B
AD7676
OUTLINE DIMENSIONS
48-Lead Plastic Quad Flatpack [LQFP]
1.4 mm Thick
(ST-48)
Dimensions shown in millimeters
1.60 MAX
PIN 1
INDICATOR
0.75
0.60
0.45
9.00 BSC
37
48
36
1
SEATING
PLANE
1.45
1.40
1.35
0.20
0.09
7.00
BSC
TOP VIEW
(PINS DOWN)
VIEW A
7ꢀ
3.5ꢀ
0ꢀ
0.15
0.05
25
12
SEATING
PLANE
24
0.08 MAX
13
COPLANARITY
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90ꢀ CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
48-Lead Frame Chip Scale Package [LFCSP]
(CP-48)
Dimensions shown in millimeters
0.30
7.00
BSC SQ
0.23
0.18
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
37
48
36
1
PIN 1
INDICATOR
5.25
4.70
2.25
6.75
BSC SQ
BOTTOM
VIEW
TOP
VIEW
0.50
0.40
0.30
12
25
24
13
5.50
REF
0.70 MAX
0.65 NOM
1.00
0.90
0.80
12ꢀ MAX
0.05 MAX
0.02 NOM
0.25
REF
0.50 BSC
COPLANARITY
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
REV. B
–19–
Revision History
Location
Page
10/02—Data Sheet changed from REV. A to REV. B.
Added 48-Lead LFCSP to FEATURES and GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Added PulSAR Selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Edit to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Additions to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Edits to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Edit to Transfer Functions section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Changes to Power Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Added 48-Lead Frame Chip Scale Package (LFCSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
–20–
REV. B
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