AD7477ART-REEL7 [ADI]
1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23; 1 MSPS ， 12位/ 10位/ 8位ADC，采用6引脚SOT -23
| 型号： | AD7477ART-REEL7 |
| 厂家： | 
ADI |
| 描述： | 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 |
| 文件： | 总20页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 MSPS, 12-/10-/8-Bit ADCs
in 6-Lead SOT-23
AD7476/AD7477/AD7478*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fast Throughput Rate: 1 MSPS
Specified for VDD of 2.35 V to 5.25 V
Low Power:
V
DD
3.6 mW Typ at 1 MSPS with 3 V Supplies
15 mW Typ at 1 MSPS with 5 V Supplies
Wide Input Bandwidth:
8-/10-/12-BIT
SUCCESSIVE-
APPROXIMATION
ADC
V
T/H
IN
70 dB SNR at 100 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPI®/QSPI™/MICROWIRE™/DSP Compatible
Standby Mode: 1 A Max
SCLK
SDATA
CS
CONTROL
LOGIC
6-Lead SOT-23 Package
AD7476/AD7477/AD7478
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
GND
Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High Speed Modems
Optical Sensors
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit,
and 8-bit, high speed, low power, successive-approximation
ADCs. The parts operate from a single 2.35 V to 5.25 V power
supply and feature throughput rates up to 1 MSPS. The parts
contain a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 6 MHz.
1. First 12-/10-/8-Bit ADCs in a SOT-23 Package.
2. High Throughput with Low Power Consumption.
3. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced while not converting. The part also features a
shutdown mode to maximize power efficiency at lower
throughput rates. Current consumption is 1 µA maximum
when in shutdown.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
4. Reference Derived from the Power Supply.
The AD7476/AD7477/AD7478 use advanced design techniques
to achieve very low power dissipation at high throughput rates.
5. No Pipeline Delay.
The parts feature a standard successive-approximation ADC
with accurate control of the sampling instant via a CS input
and once-off conversion control.
The reference for the part is taken internally from VDD. This
allows the widest dynamic input range to the ADC. Thus the
analog input range for the part is 0 V to VDD. The conversion
rate is determined by the SCLK.
*Protected by U.S.Patent No. 6,681,332.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
(A Version: VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, unless otherwise
noted; S and B Versions: VDD = 2.35 V to 5.25 V, fSCLK = 12 MHz, fSAMPLE = 600 kSPS,
AD7476–SPECIFICATIONS1unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted.)
Parameter
A Version1, 2 B Version1, 2
S Version1, 2 Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fIN = 100 kHz Sine Wave
B Version, VDD = 2.4 V to 5.25 V
TA = 25°C
Signal-to-(Noise + Distortion) (SINAD)3 69
70
70
69
70
dB min
dB min
dB typ
dB min
dB typ
dB typ
dB typ
71.5
71
72.5
–78
–80
Signal-to-Noise Ratio (SNR)3
70
70
B Version, VDD = 2.4 V to 5.25 V
Total Harmonic Distortion (THD)3
–80
–78
–80
Peak Harmonic or Spurious Noise (SFDR)3 –82
Intermodulation Distortion (IMD)3
Second-Order Terms
Third-Order Terms
Aperture Delay
–78
–78
10
–78
–78
10
–78
–78
10
dB typ
dB typ
ns typ
fa = 103.5 kHz, fb = 113.5 kHz
fa = 103.5 kHz, fb = 113.5 kHz
Aperture Jitter
30
30
30
ps typ
Full Power Bandwidth
6.5
6.5
6.5
MHz typ
@ 3 dB
DC ACCURACY
S, B Versions, VDD = (2.35 V to 3.6 V)4;
A Version, VDD = (2.7 V to 3.6 V)
Resolution
12
1
12
1.5
0.6
–0.9/+1.5
0.75
1.5
12
1.5
0.6
–0.9/+1.5
0.75
Bits
Integral Nonlinearity3
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
Differential Nonlinearity3
Offset Error3
Guaranteed No Missed Codes to 12 Bits
0.75
2
0.5
0.5
Gain Error3
1.5
2
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to VDD
1
30
0 to VDD
1
30
0 to VDD
1
30
V
µA max
pF typ
LOGIC INPUTS
Input High Voltage, VINH
2.4
1.8
0.4
0.8
1
2.4
1.8
0.4
0.8
1
2.4
1.8
0.4
0.8
1
V min
V min
V max
V max
µA max
µA typ
pF max
VDD = 2.35 V
VDD = 3 V
VDD = 5 V
Typically 10 nA, VIN = 0 V or VDD
Input Low Voltage, VINL
Input Current, IIN, SCLK Pin
Input Current, IIN, CS Pin
1
10
1
10
1
10
5
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance5
Output Coding
VDD – 0.2
VDD – 0.2
VDD – 0.2
V min
ISOURCE = 200 µA; VDD = 2.35 V to 5.25 V
ISINK = 200 µA
0.4
10
10
0.4
10
10
0.4
10
10
V max
µA max
pF max
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
0.8
1.33
500
400
600
1.33
500
400
600
µs max
16 SCLK Cycles
500
350
1000
ns max
Full-Scale Step Input
Sine Wave Input ≤100 kHz
See Serial Interface Section
ns max
kSPS max
Throughput Rate
POWER REQUIREMENTS
VDD
2.35/5.25
2.35/5.25
2.35/5.25
V min/max
IDD
Digital I/Ps = 0 V or VDD
Normal Mode (Static)
2
1
3.5
1.6
1
2
1
3
1.4
1
2
1
3
1.4
1
mA typ
mA typ
mA max
mA max
µA max
µA max
VDD = 4.75 V to 5.25 V. SCLK On or Off
VDD = 2.35 V to 3.6 V. SCLK On or Off
VDD = 4.75 V to 5.25 V; fSAMPLE = fSAMPLEMAX6
VDD = 2.35 V to 3.6 V; fSAMPLE = fSAMPLEMAX6
SCLK Off
Normal Mode (Operational)
Full Power-Down Mode
80
80
80
SCLK On
Power Dissipation7
Normal Mode (Operational)
17.5
4.8
5
15
4.2
5
15
4.2
5
mW max
mW max
µW max
µW max
VDD = 5 V; fSAMPLE = fSAMPLEMAX6
VDD = 3 V; fSAMPLE = fSAMPLEMAX6
VDD = 5 V; SCLK Off
Full Power-Down
3
3
3
VDD = 3 V; SCLK Off
NOTES
1Temperature ranges as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.
2Operational from VDD = 2.0 V.
5Guaranteed by characterization.
6A Version: fSAMPLEMAX = 1 MSPS; B, S Versions: fSAMPLEMAX = 600 kSPS.
3See Terminology section.
7See Power vs. Throughput Rate section.
Specifications subject to change without notice.
4Maximum B, S version specifications apply as typical figures when VDD = 5.25 V.
–2–
REV. D
AD7477–SPECIFICATIONS1
(VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.)
Parameter
A Version1, 2
S Version1, 2
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Second-Order Terms
fIN = 100 kHz Sine Wave, fSAMPLE = 1 MSPS
61
–73
–74
61
–73
–74
dB min
dB max
dB max
–78
–78
10
–78
–78
10
dB typ
dB typ
ns typ
fa = 103.5 kHz, fb = 113.5 kHz
fa = 103.5 kHz, fb = 113.5 kHz
Third-Order Terms
Aperture Delay
Aperture Jitter
30
30
ps typ
Full Power Bandwidth
6.5
6.5
MHz typ
@ 3 dB
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
10
1
0.9
1
1
10
1
0.9
1
Bits
LSB max
LSB max
LSB max
LSB max
Guaranteed No Missed Codes to 10 Bits
Gain Error
1
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to VDD
1
30
0 to VDD
1
30
V
µA max
pF typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
2.4
0.8
0.4
1
1
10
2.4
0.8
0.4
1
1
10
V min
V max
V max
µA max
µA typ
pF max
VDD = 5 V
VDD = 3 V
Typically 10 nA, VIN = 0 V or VDD
Input Current, IIN, SCLK Pin
Input Current, IIN, CS Pin
4
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
VDD – 0.2
VDD – 0.2
V min
ISOURCE = 200 µA; VDD = 2.7 V to 5.25 V
ISINK = 200 µA
0.4
10
10
0.4
10
10
V max
µA max
pF max
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
800
400
1
800
400
1
ns max
ns max
16 SCLK Cycles with SCLK at 20 MHz
MSPS max See Serial Interface Section
POWER REQUIREMENTS
VDD
2.7/5.25
2.7/5.25
V min/max
IDD
Digital I/Ps = 0 V or VDD
Normal Mode (Static)
2
1
3.5
1.6
1
2
1
3.5
1.6
1
mA typ
mA typ
mA max
mA max
µA max
µA max
VDD = 4.75 V to 5.25 V; SCLK On or Off
VDD = 2.7 V to 3.6 V; SCLK On or Off
VDD = 4.75 V to 5.25 V; fSAMPLE = 1 MSPS
Normal Mode (Operational)
Full Power-Down Mode
V
DD = 2.7 V to 3.6 V; fSAMPLE = 1 MSPS
SCLK Off
SCLK On
80
80
Power Dissipation5
Normal Mode (Operational)
17.5
4.8
5
17.5
4.8
5
mW max
mW max
µW max
VDD = 5 V; fSAMPLE = 1 MSPS
VDD = 3 V; fSAMPLE = 1 MSPS
VDD = 5 V; SCLK Off
Full Power-Down
NOTES
1Temperature ranges as follows: A Version: –40°C to +85°C; S Version: –55°C to +125°C.
2Operational from VDD = 2.0 V, with input high voltage, VINH = 1.8 V min.
3See Terminology section.
4Guaranteed by characterization.
5See Power vs. Throughput Rate section.
Specifications subject to change without notice.
REV. D
–3–
AD74786–SPECIFICATIONS1
(VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.)
Parameter
A Version1, 2
S Version1, 2
Unit
Test Conditions/Comments
fIN = 100 kHz Sine Wave, fSAMPLE = 1 MSPS
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Second-Order Terms
49
–65
–65
49
–65
–65
dB min
dB max
dB max
–68
–68
10
–68
–68
10
dB typ
dB typ
ns typ
fa = 498.7 kHz, fb = 508.7 kHz
fa = 498.7 kHz, fb = 508.7 kHz
Third-Order Terms
Aperture Delay
Aperture Jitter
30
30
ps typ
Full Power Bandwidth
6.5
6.5
MHz typ
@ 3 dB
DC ACCURACY
Resolution
8
8
Bits
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Total Unadjusted Error (TUE)
0.5
0.5
0.5
0.5
0.5
0.5
LSB max
LSB max
LSB max
LSB max
LSB max
0.5
0.5
0.5
0.5
Guaranteed No Missed Codes to Eight Bits
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to VDD
1
30
0 to VDD
1
30
V
µA max
pF typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
2.4
0.8
0.4
1
1
10
2.4
0.8
0.4
1
1
10
V min
V max
V max
µA max
µA typ
pF max
VDD = 5 V
V
DD = 3 V
Input Current, IIN, SCLK Pin
Typically 10 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
4
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
VDD – 0.2
VDD – 0.2
V min
ISOURCE = 200 µA; VDD = 2.7 V to 5.25 V
ISINK = 200 µA
0.4
10
10
0.4
10
10
V max
µA max
pF max
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
800
400
1
800
400
1
ns max
ns max
16 SCLK Cycles with SCLK at 20 MHz
MSPS max See Serial Interface Section
POWER REQUIREMENTS
VDD
2.7/5.25
2.7/5.25
V min/max
IDD
Digital I/Ps = 0 V or VDD
Normal Mode (Static)
2
1
3.5
1.6
1
2
1
3.5
1.6
1
mA typ
mA typ
mA max
mA max
µA max
µA max
VDD = 4.75 V to 5.25 V; SCLK On or Off
V
V
V
DD = 2.7 V to 3.6 V; SCLK On or Off
DD = 4.75 V to 5.25 V; fSAMPLE = 1 MSPS
DD = 2.7 V to 3.6 V; fSAMPLE = 1 MSPS
Normal Mode (Operational)
Full Power-Down Mode
SCLK Off
SCLK On
80
80
Power Dissipation5
Normal Mode (Operational)
17.5
4.8
5
17.5
4.8
5
mW max
mW max
µW max
VDD = 5 V; fSAMPLE = 1 MSPS
V
DD = 3 V; fSAMPLE = 1 MSPS
Full Power-Down
NOTES
VDD = 5 V; SCLK Off
1Temperature ranges as follows: A Version: –40°C to +85°C; S Version: –55°C to +125°C.
2Operational from VDD = 2.0 V, with input high voltage, VINH = 1.8 V min.
3See Terminology section.
4Guaranteed by characterization.
5See Power vs. Throughput Rate section.
Specifications subject to change without notice.
–4–
REV. D
AD7476/AD7477/AD7478
TIMING SPECIFICATIONS1, 2 (VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)
Limit at TMIN, TMAX
AD7476/AD7477/AD7478
5 V3
Parameter
3 V3
Unit
Description
4
fSCLK
10
20
12
10
20
12
kHz min
MHz max
MHz max
A Version
B Version
tCONVERT
tQUIET
16 × tSCLK
16 × tSCLK
50
50
ns min
Minimum Quiet Time Required between Bus Relinquish and
Start of Next Conversion
Minimum CS Pulsewidth
CS to SCLK Setup Time
Delay from CS until SDATA Three-State Disabled
Data Access Time after SCLK Falling Edge, A Version
Data Access Time after SCLK Falling Edge, B Version
SCLK Low Pulsewidth
SCLK High Pulsewidth
SCLK to Data Valid Hold Time
t1
10
10
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs typ
t25
t35
t4
10
10
20
20
40
20
70
20
t5
t6
0.4 × tSCLK
0.4 × tSCLK
0.4 × tSCLK
0.4 × tSCLK
t76
10
10
25
1
10
10
25
1
t8
SCLK Falling Edge to SDATA High Impedance
SCLK Falling Edge to SDATA High Impedance
Power-Up Time from Full Power-Down
7
tPOWER-UP
NOTES
1Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2A Version timing specifications apply to the AD7477 S Version and AD7478 S Version; B Version timing specifications apply to the AD7476 S Version.
33 V specifications apply from VDD = 2.7 V to 3.6 V for A Version; 3 V specifications apply from VDD = 2.35 V to 3.6 V for B Version; 5 V specifications apply from
VDD = 4.75 V to 5.25 V.
4Mark/Space ratio for the SCLK input is 40/60 to 60/40.
5Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
6t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish time
of the part and is independent of the bus loading.
7See Power-Up Time section.
Specifications subject to change without notice.
200A
200A
I
I
OL
TO OUTPUT
PIN
1.6V
C
50pF
L
OH
Figure 1. Load Circuit for Digital Output Timing
Specifications
REV. D
–5–
AD7476/AD7477/AD7478
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C, unless otherwise noted.)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
SOT-23 Package
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 230°C/W
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to GND . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Output Voltage to GND . . . . . . –0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . 10 mA
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Military (S Version) . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
θ
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 92°C/W
Lead Temperature, Soldering
Reflow (10 sec to 30 sec) . . . . . . . . . . . . . . . . 235 (0/+5)°C
Pb-Free Temperature Soldering
Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 (0/+5)°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kV
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2 Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Temperature
Range
Linearity
Package
Option2
Branding
Information
Model
Error (LSB)1
AD7476ART-500RL7
AD7476ART-REEL
AD7476ART-REEL7
AD7476ARTZ-500RL73
AD7476ARTZ-REEL3
AD7476ARTZ-REEL73
AD7476BRT-REEL
AD7476BRT-REEL7
AD7476BRTZ-REEL3
AD7476BRTZ-REEL73
AD7476SRT-500RL7
AD7476SRT-R2
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
1 typ
RT-6
CEA
CEA
CEA
CEA
CEA
CEA
CEB
CEB
CEB
CEB
CES
CES
CES
CES
CES
CES
CES
CES
CFA
CFA
CFA
CFS
CFS
CFS
CFS
CJA
1 typ
RT-6
1 typ
RT-6
1 typ
RT-6
1 typ
RT-6
1 typ
RT-6
1.5 max
1.5 max
1.5 max
1.5 max
1.5 max
1.5 max
1.5 max
1.5 max
1.5 max
1.5 max
1.5 max
1.5 max
1 max
RT-6
RT-6
RT-6
RT-6
RT-6
RT-6
AD7476SRT-REEL
AD7476SRT-REEL7
AD7476SRTZ-500RL73
AD7476SRTZ-R23
RT-6
RT-6
RT-6
RT-6
AD7476SRTZ-REEL3
AD7476SRTZ-REEL73
AD7477ART-500RL7
AD7477ART-REEL
AD7477ART-REEL7
AD7477SRT-500RL7
AD7477SRT-R2
RT-6
RT-6
RT-6
1 max
RT-6
1 max
RT-6
1 max
RT-6
1 max
RT-6
AD7477SRT-REEL
AD7477SRT-REEL7
AD7478ART-500RL7
AD7478ART-REEL
AD7478ART-REEL7
AD7478SRT-500RL7
AD7478SRT-R2
1 max
RT-6
1 max
RT-6
0.5 max
0.5 max
0.5 max
0.5 max
0.5 max
0.5 max
RT-6
RT-6
CJA
RT-6
CJA
RT-6
CJS
RT-6
CJS
AD7478SRT-REEL7
EVAL-AD7476CB4
EVAL-AD7477CB4
RT-6
CJS
Evaluation Board
Evaluation Board
EVAL-CONTROL BRD25
NOTES
Control Board
1Linearity Error here refers to integral linearity error.
2RT = SOT-23.
3Z = Pb free.
4This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.
5This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete
evaluation kit, you need to order the particular ADC evaluation board, e.g., EVAL-AD7476CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See relevant
evaluation board application note for more information.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7476/AD7477/AD7478 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
–6–
REV. D
AD7476/AD7477/AD7478
PIN CONFIGURATION
V
1
2
3
6
5
4
CS
DD
AD7476/
AD7477/
GND
SDATA
V
AD7478
SCLK
IN
TOP VIEW
(Not to Scale)
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
2
VDD
GND
Power Supply Input. The VDD range for the AD7476/AD7477/AD7478 is from 2.35 V to 5.25 V.
Analog Ground. Ground reference point for all circuitry on the AD7476/AD7477/AD7478. All analog
input signals should be referred to this GND voltage.
3
4
VIN
SCLK
Analog Input. Single-ended analog input channel. The input range is 0 V to VDD.
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock
input is also used as the clock source for the AD7476/AD7477/AD7478’s conversion process.
5
SDATA
Data Out. Logic output. The conversion result from the AD7476/AD7477/AD7478 is provided on
this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The
data stream from the AD7476 consists of four leading zeros followed by the 12 bits of conversion data,
which is provided MSB first; the data stream from the AD7477 consists of four leading zeros followed
by the 10 bits of conversion data, followed by two trailing zeros, which is also provided MSB first; the
data stream from the AD7478 consists of four leading zeros followed by the eight bits of conversion
data, followed by four trailing zeros, which is provided MSB first.
6
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7476/AD7477/AD7478 and framing the serial data transfer.
REV. D
–7–
AD7476/AD7477/AD7478
TERMINOLOGY
Total Unadjusted Error
Integral Nonlinearity
This is a comprehensive specification that includes gain error,
linearity error, and offset error.
This is the maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. For the AD7476/
AD7477, the endpoints of the transfer function are zero scale, a
point 1/2 LSB below the first code transition, and full scale, a
point 1/2 LSB above the last code transition. For the AD7478, the
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB above
the last code transition.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of harmon-
ics to the fundamental. For the AD7476/AD7477/AD7478, it is
defined as:
(V22 +V32 +V42 +V52 +V6 )
2
THD(dB) = 20 log
V1
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Offset Error
This is the deviation of the first code transition (00 . . . 000)
to (00 . . . 001) from the ideal (i.e., AGND + 0.5 LSB). For
the AD7478, this is the deviation of the first code transition
(00 . . . 000) to (00 . . . 001) from the ideal (i.e., AGND + 1 LSB).
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Gain Error
For the AD7476/AD7477, this is the deviation of the last code
transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e.,
VREF – 1.5 LSB) after the offset error has been adjusted out. For
the AD7478, this is the deviation of the last code transition
(111 . . . 110) to (111 . . . 111) from the ideal (i.e., VREF – 1 LSB)
after the offset error has been adjusted.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n is equal to zero. For example,
the second-order terms include (fa + fb) and (fa – fb), while the
third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and
(fa – 2fb).
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode after the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within 0.5 LSB, after the end of conversion. See
the Serial Interface Timing section for more detail.
The AD7476/AD7477/AD7478 are tested using the CCIF
standard where two input frequencies are used, fa = 498.7 kHz and
fb = 508.7 kHz. In this case, the second-order terms are usually
distanced in frequency from the original sine waves while the
third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals, expressed in dB.
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the quanti-
zation noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB; for a 10-bit converter
it is 62 dB; and for an 8-bit converter it is 50 dB.
–8–
REV. D
Typical Performance Characteristics–AD7476/AD7477/AD7478
0
0
8192 POINT FFT
SAMPLE
8192 POINT FFT
f
= 1MSPS
–10
–20
–30
f
f
= 1MSPS
–15
SAMPLE
f
= 100kHz
IN
= 100kHz
IN
SINAD = 49.82dB
THD = –75.22dB
SFDR = –67.78dB
SINAD = 71.67dB
THD = –81.00dB
SFDR = –81.63dB
–35
–55
–40
–50
–60
–70
–80
–90
–75
–95
–115
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY – kHz
50
100 150 200 250 300 350 400 450 500
FREQUENCY – kHz
0
TPC 4. AD7478 Dynamic Performance at 1 MSPS
TPC 1. AD7476 Dynamic Performance at 1 MSPS
–66
–15
V
= 2.35V
SCLK = 20MHz
DD
8192 POINT FFT
–67
–68
–69
–70
–71
–72
–73
f
f
= 600kSPS
–15
–35
–55
–75
SAMPLE
= 100kHz
IN
SINAD = 71.71dB
THD = –80.88dB
SFDR = –83.23dB
V
= 2.7V
DD
V
= 5.25V
DD
V
= 4.75V
DD
–95
V
= 3.6V
DD
–115
10k
100k
INPUT FREQUENCY – Hz
1M
50
100
150
200
250
300
0
FREQUENCY – kHz
TPC 5. AD7476 SINAD vs. Input Frequency at 993 kSPS
TPC 2. AD7476 Dynamic Performance at 600 kSPS
–69.0
0
8192 POINT FFT
–10
f
f
= 1MSPS
SAMPLE
SCLK = 12MHz
–69.5
–70.0
–70.5
–71.0
–71.5
–72.0
–72.5
V
= 2.35V
= 2.7V
DD
= 100kHz
IN
–20
–30
–40
–50
–60
–70
–80
–90
SINAD = 61.66dB
THD = –80.64dB
SFDR = –85.75dB
V
DD
V
V
= 5.25V
= 4.75V
= 3.6V
DD
DD
V
DD
–100
10k
100k
INPUT FREQUENCY – Hz
1M
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY – kHz
TPC 6. AD7476 SINAD vs. Input Frequency at 605 kSPS
TPC 3. AD7477 Dynamic Performance at 1 MSPS
REV. D
–9–
AD7476/AD7477/AD7478
CIRCUIT INFORMATION
ADC TRANSFER FUNCTION
The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit,
and 8-bit, fast, micropower, single-supply ADCs. The parts can be
operated from a 2.35 V to 5.25 V supply. When operated from
either a 5 V supply or a 3 V supply, the AD7476/AD7477/AD7478
are capable of throughput rates of 1 MSPS when provided with
a 20 MHz clock.
The output coding of the AD7476/AD7477/AD7478 is straight
binary. For the AD7476/AD7477, designed code transitions
occur midway between successive integer LSB values (i.e.,
1/2 LSB, 3/2 LSB, and so on). The LSB size for the AD7476
is VDD/4096 and the LSB size for the AD7477 is VDD/1024. The
ideal transfer characteristic for the AD7476/AD7477 is shown
in Figure 4.
The AD7476/AD7477/AD7478 provide the user with an on-chip,
track-and-hold ADC, and a serial interface housed in a tiny
6-lead SOT-23 package, which offers the user considerable
space saving advantages over alternative solutions. The serial
clock input accesses data from the part and also provides the
clock source for the successive-approximation ADC. The analog
input range is 0 V to VDD. An external reference is not required
for the ADC, nor is there a reference on-chip. The reference for
the AD7476/AD7477/AD7478 is derived from the power supply
and thus gives the widest dynamic input range.
For the AD7478, designed code transitions occur midway between
successive integer LSB values (i.e., 1 LSB, 2 LSB, and so on).
The LSB size for the AD7478 is VDD/256. The ideal transfer
characteristic for the AD7478 is shown in Figure 5.
111 ... 111
111 ... 110
The AD7476/AD7477/AD7478 also feature a power-down option
to save power between conversions. The power-down feature is
implemented across the standard serial interface as described in
the Modes of Operation section.
111 ... 000
1LSB = V /4096 (AD7476)
DD
1LSB = V /1024 (AD7477)
011 ... 111
DD
CONVERTER OPERATION
The AD7476/AD7477/AD7478 are successive-approximation
analog-to-digital converters based around a charge redistribution
DAC. Figures 2 and 3 show simplified schematics of the ADC.
Figure 2 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in position A, the comparator is held in a
balanced condition, and the sampling capacitor acquires the
000 ... 010
000 ... 001
000 ... 000
0.5LSB
؉V –1.5LSB
DD
0V
ANALOG INPUT
Figure 4. Transfer Characteristic for the AD7476/AD7477
signal on VIN
.
CHARGE
REDISTRIBUTION
DAC
SAMPLING
CAPACITOR
COMPARATOR
V
111 ... 111
111 ... 110
A
B
IN
SW1
CONTROL
LOGIC
ACQUISITION
PHASE
SW2
AGND
111 ... 000
V
/2
DD
1LSB = V /256 (AD7478)
DD
011 ... 111
Figure 2. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 3), SW2 will open
and SW1 will move to Position B, causing the comparator to
become unbalanced. The Control Logic and the Charge Redistri-
bution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the ADC
output code. Figures 4 and 5 show the ADC transfer function.
000 ... 010
000 ... 001
000 ... 000
1LSB
؉V –1LSB
DD
0V
ANALOG INPUT
Figure 5. Transfer Characteristic for AD7478
TYPICAL CONNECTION DIAGRAM
Figure 6 shows a typical connection diagram for the AD7476/
AD7477/AD7478. VREF is taken internally from VDD and as
such, VDD should be well decoupled. This provides an analog
input range of 0 V to VDD. The conversion result is output in a
16-bit word with four leading zeros followed by the MSB of the
12-bit, 10-bit, or 8-bit result. The 10-bit result from the AD7477
will be followed by two trailing zeros. The 8-bit result from
the AD7478 will be followed by four trailing zeros.
CHARGE
REDISTRIBUTION
DAC
SAMPLING
COMPARATOR
V
A
B
IN
CAPACITOR
SW1
CONTROL
LOGIC
CONVERSION
PHASE
SW2
AGND
V
/2
DD
Figure 3. ADC Conversion Phase
–10–
REV. D
AD7476/AD7477/AD7478
Alternatively, because the supply current required by the
AD7476/AD7477/AD7478 is so low, a precision reference can be
used as the supply source to the AD7476/AD7477/AD7478. A
REF19x voltage reference (REF195 for 5 V, or REF193 for 3 V)
can be used to supply the required voltage to the ADC (see
Figure 6). This configuration is especially useful if the power
supply is quite noisy or if the system supply voltages are at some
value other than 5 V or 3 V (e.g., 15 V). The REF19x will output
a steady voltage to the AD7476/AD7477/AD7478. If the low
dropout REF193 is used, the current it typically needs to supply
to the AD7476/AD7477/AD7478 is 1 mA. When the ADC is
converting at a rate of 1 MSPS, the REF193 will need to supply a
maximum of 1.6 mA to the AD7476/AD7477/AD7478. The load
regulation of the REF193 is typically 10 ppm/mA (REF193, VS =
5 V), which results in an error of 16 ppm (48 µV) for the 1.6 mA
drawn from it. This corresponds to a 0.065 LSB error for the
AD7476 with VDD = 3 V from the REF193, a 0.016 LSB error for
the AD7477, and a 0.004 LSB error for the AD7478. For applica-
tions where power consumption is of concern, the Power-Down
mode of the ADC and the Sleep mode of the REF19x reference
should be used to improve power performance. See the Modes of
Operation section.
the substrate. These diodes can conduct a maximum of 10 mA
without causing irreversible damage to the part. The capacitor
C1 in Figure 7 is typically about 4 pF and can primarily be
attributed to pin capacitance. The resistor R1 is a lumped
component made up of the on resistance of a switch. This
resistor is typically about 100 Ω. The capacitor C2 is the ADC
sampling capacitor and typically has a capacitance of 30 pF. For
ac applications, removing high frequency components from the
analog input signal is recommended by use of a band-pass filter
on the relevant analog input pin. In applications where harmonic
distortion and signal-to-noise ratio are critical, the analog input
should be driven from a low impedance source. Large source
impedances will significantly affect the ac performance of the
ADC. This may necessitate the use of an input buffer amplifier.
The choice of the op amp will be a function of the particular
application.
V
DD
C2
30pF
D1
D2
R1
V
IN
C1
4pF
3V
CONVERSION PHASE - SWITCH OPEN
TRACK PHASE - SWITCH CLOSED
5V
SUPPLY
REF193
1mA
1F
TANT
0.1F
10F
0.1F
680nF
Figure 7. Equivalent Analog Input Circuit
V
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance will depend on the amount of total harmonic distortion
(THD) that can be tolerated. The THD will increase as the source
impedance increases and performance will degrade. Figure 8
shows a graph of the total harmonic distortion versus source
impedance for different analog input frequencies when using
a supply voltage of 2.7 V and sampling at a rate of 605 kSPS.
Figures 9 and 10 each show a graph of the total harmonic
distortion versus analog input signal frequency for various supply
voltages while sampling at 993 kSPS with an SCLK frequency of
20 MHz and 605 kSPS with an SCLK frequency of 12 MHz,
respectively.
DD
SCLK
0V TO V
DD
V
IN
INPUT
AD7476/
AD7477/
AD7478
SDATA
C/P
GND
CS
SERIAL
INTERFACE
Figure 6. REF193 as Power Supply to AD7476/AD7477/
AD7478
Table I provides some typical performance data with various
references used as a VDD source with a low frequency analog
input. Under the same setup conditions, the references were
compared and the AD780 proved the optimum reference.
0
V
= 2.7V
DD
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Table I.
fS = 605kSPS
Reference Tied
to VDD
AD7476 SNR Performance
1 kHz Input (dB)
fIN = 200kHz
AD780 @ 3 V
REF193
71.17
70.4
fIN = 300kHz
AD780 @ 2.5 V
REF192
AD1582
71.35
70.93
70.05
fIN = 100kHz
Analog Input
fIN = 10kHz
Figure 7 shows an equivalent circuit of the analog input structure
of the AD7476/AD7477/AD7478. The two diodes D1 and D2
provide ESD protection for the analog inputs. Care must be
taken to ensure that the analog input signal never exceeds the
supply rails by more than 300 mV. This will cause these diodes
to become forward-biased and start conducting current into
1
10
100
1k
10k
SOURCE IMPEDANCE – ⍀
Figure 8. THD vs. Source Impedance for Various Analog
Input Frequencies
REV. D
–11–
AD7476/AD7477/AD7478
restricted by the VDD + 0.3 V limit as on the analog inputs. For
example, if the AD7476/AD7477/AD7478 were operated with a
VDD of 3 V, then 5 V logic levels could be used on the digital
inputs. However, it is important to note that the data output on
SDATA will still have 3 V logic levels when VDD = 3 V. Another
–50
–55
–60
–65
advantage of SCLK and CS not being restricted by the VDD
+
V
DD
= 2.35V
= 2.7V
0.3 V limit is the fact that power supply sequencing issues are
avoided. If CS or SCLK is applied before VDD, there is no risk of
latch-up as there would be on the analog inputs if a signal greater
V
= 5.25V
–70
–75
–80
DD
V
DD
than 0.3 V was applied prior to VDD
.
V
DD
= 4.75V
MODES OF OPERATION
–85
–90
The mode of operation of the AD7476/AD7477/AD7478 is
selected by controlling the (logic) state of the CS signal during a
conversion. There are two possible modes of operation, Normal
mode and Power-Down mode. The point at which CS is pulled
high after the conversion has been initiated will determine whether
or not the AD7476/AD7477/AD7478 will enter Power-Down
mode. Similarly, if already in power-down, CS can control
whether the device will return to normal operation or remain in
power-down. These modes of operation are designed to provide
flexible power management options. These options can be chosen
to optimize the power dissipation/throughput rate ratio for different
application requirements.
V
= 3.6V
DD
10k
100k
1M
INPUT FREQUENCY – Hz
Figure 9. THD vs. Analog Input Frequency, fS = 993 kSPS
–72
V
= 2.35V
DD
–74
–76
–78
–80
–82
–84
V
= 2.7V
Normal Mode
DD
This mode is intended for fastest throughput rate performance,
as the user does not have to worry about any power-up times
with the AD7476/AD7477/AD7478 remaining fully powered all
the time. Figure 11 shows the general diagram of the operation
of the AD7476/AD7477/AD7478 in this mode.
V
= 4.75V
= 5.25V
DD
V
DD
V
= 3.6V
DD
The conversion is initiated on the falling edge of CS as described
in the Serial Interface section. To ensure the part remains fully
powered up at all times, CS must remain low until at least 10
SCLK falling edges have elapsed after the falling edge of CS. If
CS is brought high any time after the tenth SCLK falling edge,
but before the sixteenth SCLK falling edge, the part will remain
powered up but the conversion will be terminated and SDATA
will go back into three-state. Sixteen serial clock cycles are
required to complete the conversion and access the complete
10k
100k
1M
INPUT FREQUENCY – Hz
Figure 10. THD vs. Analog Input Frequency, fS = 605 kSPS
Digital Inputs
The digital inputs applied to the AD7476/AD7477/AD7478 are
not limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs applied can go to 7 V and are not
CS
1
10
16
SCLK
SDATA
4 LEADING ZEROS + CONVERSION RESULT
Figure 11. Normal Mode Operation
CS
SCLK
1
2
10
16
THREE-STATE
SDATA
Figure 12. Entering Power-Down Mode
–12–
REV. D
AD7476/AD7477/AD7478
THE PART BEGINS
TO POWER UP
THE PART IS FULLY POWERED
UP WITH V FULLY ACQUIRED
IN
CS
A
1
10
16
1
16
SCLK
SDATA
INVALID DATA
VALID DATA
Figure 13. Exiting Power-Down Mode
conversion result. CS may idle high until the next conversion or
may idle low until CS returns high sometime prior to the next
conversion (effectively idling CS low).
conversion, to the next falling edge of CS. When running at
1 MSPS throughput rate, the AD7476/AD7477/AD7478 will
power up and acquire a signal within 0.5 LSB in one dummy
cycle, i.e., 1 s.
Once a data transfer is complete (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
When powering up from the Power-Down mode with a dummy
cycle, as in Figure 13, the track-and-hold that was in Hold
mode while the part was powered down returns to Track mode
after the first SCLK edge the part receives after the falling edge of
CS. This is shown as Point A in Figure 13. Although at any
SCLK frequency one dummy cycle is sufficient to power up the
device and acquire VIN, it does not necessarily mean that a full
dummy cycle of 16 SCLKs must always elapse to power up the
device and fully acquire VIN; 1 µs will be sufficient to power up the
device and acquire the input signal. If, for example, a 5 MHz
SCLK frequency were applied to the ADC, the cycle time would
be 3.2 µs. In one dummy cycle, 3.2 µs, the part would be powered
up and VIN fully acquired. However, after 1 µs with a 5 MHz
SCLK, only five SCLK cycles would have elapsed. At this stage,
the ADC would be fully powered up and the signal acquired. So,
in this case, the CS can be brought high after the tenth SCLK
falling edge and brought low again after a time tQUIET to initiate
the conversion.
t
QUIET, has elapsed by again bringing CS low.
Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then powered
down for a relatively long duration between these bursts of several
conversions. When the AD7476/AD7477/AD7478 is in power-
down, all analog circuitry is powered down.
To enter power-down, the conversion process must be interrupted
by bringing CS high any time after the second falling edge of
SCLK and before the tenth falling edge of SCLK, as shown in
Figure 12. Once CS has been brought high in this window of
SCLKs, the part will enter power-down and the conversion that
was initiated by the falling edge of CS will be terminated and
SDATA will go back into three-state. If CS is brought high before
the second SCLK falling edge, the part will remain in Normal mode
and will not power down. This will avoid accidental power-down
due to glitches on the CS line.
When power supplies are first applied to the AD7476/AD7477/
AD7478, the ADC may power up in either Power-Down mode
or Normal mode. Because of this, it is best to allow a dummy
cycle to elapse to ensure the part is fully powered up before
attempting a valid conversion. Likewise, if it is intended to keep
the part in the Power-Down mode while not in use and the user
wants the part to power up in Power-Down mode, the dummy
cycle may be used to ensure the device is in power-down by
executing a cycle such as that shown in Figure 12. Once supplies
are applied to the AD7476/AD7477/AD7478, the power-up
time is the same as that when powering up from the Power-Down
mode. It takes approximately 1 µs to fully power up if the part
powers up in Normal mode. It is not necessary to wait 1 µs before
executing a dummy cycle to ensure the desired mode of operation.
Instead, the dummy cycle can occur directly after power is supplied
to the ADC. If the first valid conversion is then performed directly
after the dummy conversion, care must be taken to ensure that
adequate acquisition time has been allowed. As mentioned earlier,
when powering up from the Power-Down mode, the part will
return to track upon the first SCLK edge applied after the falling
edge of CS. However, when the ADC powers up initially after
supplies are applied, the track-and-hold will already be in track.
This means that if the ADC powers up in the desired mode of
operation, and a dummy cycle is not required to change mode, then
a dummy cycle is not required to place the track-and-hold
into track.
To exit this mode of operation and power up the AD7476/
AD7477/AD7478 again, a dummy conversion is performed. On
the falling edge of CS, the device will begin to power up, and
will continue to power up as long as CS is held low until after the
falling edge of the tenth SCLK. The device will be fully powered
up once 16 SCLKs have elapsed and, as shown in Figure 13,
valid data will result from the next conversion. If CS is brought
high before the tenth falling edge of SCLK, the AD7476/
AD7477/AD7478 will again go back into power-down. This
avoids accidental power-up due to glitches on the CS line or an
inadvertent burst of eight SCLK cycles while CS is low. So
although the device may begin to power up on the falling edge
of CS, it will again power down on the rising edge of CS as long
as it occurs before the tenth SCLK falling edge.
Power-Up Time
The power-up time of the AD7476/AD7477/AD7478 is typically
1 s, which means that with any frequency of SCLK up to
20 MHz, one dummy cycle will always be sufficient to allow the
device to power up. Once the dummy cycle is complete, the ADC
will be fully powered up and the input signal will be acquired
properly. The quiet time (tQUIET) must still be allowed from the
point at which the bus goes back into three-state after the dummy
REV. D
–13–
AD7476/AD7477/AD7478
POWER VS. THROUGHPUT RATE
The Power-Down mode is intended for use with throughput
rates of approximately 333 kSPS and under, because at higher
sampling rates power is not saved by using the Power-Down mode.
By using the Power-Down mode on the AD7476/AD7477/AD7478
when not converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 14 shows how as the
throughput rate is reduced, the device remains in its power-down
state longer, and the average power consumption over time
drops accordingly.
SERIAL INTERFACE
Figures 15, 16, and 17 show the detailed timing diagrams for
serial interfacing to the AD7476, AD7477, and AD7478,
respectively. The serial clock provides the conversion clock
and also controls the transfer of information from the AD7476/
AD7477/AD7478 during conversion.
For example, if the AD7476/AD7477/AD7478 is operated in a
continuous sampling mode with a throughput rate of 100 kSPS
and a SCLK of 20 MHz (VDD = 5 V), and the device is placed
in the Power-Down mode between conversions, then the power
consumption is calculated as follows. The power dissipation
during normal operation is 17.5 mW (VDD = 5 V). If the
power-up time is one dummy cycle, i.e., 1 µs, and the remaining
conversion time is another cycle, i.e., 1 µs, then the AD7476/
AD7477/AD7478 can be said to dissipate 17.5 mW for 2 µs
during each conversion cycle. If the throughput rate is 100 kSPS,
the cycle time is 10 µs and the average power dissipated
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into Hold mode,
takes the bus out of three-state, and the analog input is sampled
at this point. The conversion is also initiated at this point and
will require sixteenth SCLK cycles to complete. Once 13 SCLK
falling edges have elapsed, the track-and-hold will go back into
track on the next SCLK rising edge as shown in Figures 15, 16,
and 17 at Point B. On the sixteenth SCLK falling edge, the
SDATA line will go back into three-state. If the rising edge of
CS occurs before 16 SCLKs have elapsed, the conversion will be
terminated and the SDATA line will go back into three-state;
otherwise, SDATA returns to three-state on the sixteenth SCLK
falling edge as shown in Figures 15, 16, and 17. Sixteen serial
clock cycles are required to perform the conversion process
and to access data from the AD7476/AD7477/AD7478. CS
going low provides the first leading zero to be read in by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges, beginning with the second
leading zero. Thus the first falling clock edge on the serial clock
has the first leading zero provided and also clocks out the second
leading zero. The final bit in the data transfer is valid on the
sixteenth falling edge, having been clocked out on the previous
(fifteenth) falling edge. In applications with a slower SCLK, it
is possible to read in data on each SCLK rising edge, i.e., al-
though the first leading zero will have to be read on the first
SCLK falling edge after the CS falling edge. Therefore, the first
rising edge of SCLK after the CS falling edge will provide the
second leading zero and the fifteenth rising SCLK edge will have
DB0 provided or the final zero for the AD7477 and AD7478.
This may not work with most microcontrollers/DSPs, but could
possibly be used with FPGAs and ASICs.
during each cycle is (2/10) × (17.5 mW) = 3.5 mW. If VDD
=
3 V, SCLK = 20 MHz, and the device is again in Power-Down
mode between conversions, the power dissipation during normal
operation is 4.8 mW. The AD7476/AD7477/AD7478 can now
be said to dissipate 4.8 mW for 2 µs during each conversion
cycle. With a throughput rate of 100 kSPS, the average power
dissipated during each cycle is (2/10) × (4.8 mW) = 0.96 mW.
Figure 14 shows the power versus throughput rate when using
the Power-Down mode between conversions with both 5 V
and 3 V supplies.
100
V
= 5V, SCLK = 20MHz
DD
10
1
V
= 3V, SCLK = 20MHz
DD
0.1
0.01
0
50
100
150
200
250
300
350
THROUGHPUT RATE – kSPS
Figure 14. Power vs. Throughput Rate
–14–
REV. D
AD7476/AD7477/AD7478
t1
CS
tCONVERT
t2
t6
B
SCLK
1
2
3
4
5
13
14
t5
15
16
t8
t7
t3
t4
tQUIET
THREE-
STATE
THREE-STATE
Z
ZERO
ZERO
ZERO
DB11
DB10
DB2
DB1
DB0
SDATA
4 LEADING ZEROS
Figure 15. AD7476 Serial Interface Timing Diagram
t1
CS
tCONVERT
t2
t6
B
SCLK
1
2
3
4
5
13
14
t5
15
16
t8
t3
t7
t4
tQUIET
THREE-
STATE
THREE-STATE
Z
ZERO
ZERO
ZERO
DB9
DB8
DB0
ZERO
ZERO
SDATA
4 LEADING ZEROS
2 TRAILING
ZEROS
Figure 16. AD7477 Serial Interface Timing Diagram
t1
CS
tCONVERT
t2
t6
B
SCLK
1
2
3
4
12
13
14
t5
15
16
t8
t7
t4
t3
tQUIET
THREE-
STATE
THREE-STATE
Z
ZERO
ZERO
ZERO
DB7
ZERO
ZERO
ZERO
ZERO
SDATA
4 TRAILING ZEROS
8 BITS OF DATA
4 LEADING ZEROS
Figure 17. AD7478 Serial Interface Timing Diagram
REV. D
–15–
AD7476/AD7477/AD7478
MICROPROCESSOR INTERFACING
To implement the Power-Down mode, SLEN should be set
to 0111 to issue an 8-bit SCLK burst. The connection diagram
is shown in Figure 19. The ADSP-21xx has the TFS and RFS of
the SPORT tied together, with TFS set as an output and RFS
set as an input. The DSP operates in Alternate Framing mode
and the SPORT control register is set up as described. The
frame synchronization signal generated on the TFS is tied to
CS and as with all signal processing applications, equidistant
sampling is necessary. However, in this example, the timer
interrupt is used to control the sampling rate of the ADC and, under
certain conditions, equidistant sampling may not be achieved.
The serial interface on the AD7476/AD7477/AD7478 allows
the part to be directly connected to a range of many different
microprocessors. This section explains how to interface the
AD7476/AD7477/AD7478 with some of the more common
microcontroller and DSP serial interface protocols.
AD7476/AD7477/AD7478 to TMS320C5x/C54x Interface
The serial interface on the TMS320C5x uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices like the AD7476/
AD7477/AD7478. The CS input allows easy interfacing between
the TMS320C5x/C54x and the AD7476/AD7477/AD7478 without
any glue logic required. The serial port of the TMS320C5x/C54x
is set up to operate in burst mode with internal CLKX (Tx serial
clock) and FSX (Tx frame sync). The serial port control register
(SPC) must have the following setup: FO = 0, FSM = 1,
MCM = 1, and TXM = 1. The format bit, FO, may be set to 1
to set the word length to eight bits, in order to implement the
Power-Down mode on the AD7476/AD7477/AD7478. The
connection diagram is shown in Figure 18. It should be noted that
for signal processing applications, it is imperative that the frame
synchronization signal from the TMS320C5x/C54x provides
equidistant sampling.
The timer registers, for example, are loaded with a value that will
provide an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and therefore
the reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given (i.e., TX0 = AX0), the state of the SCLK is checked.
The DSP will wait until the SCLK has gone high, low, and high
before transmission will start. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, the data may be transmitted, or it may
wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3,
a SCLK of 2 MHz is obtained, and eight master clock periods
will elapse for every one SCLK period. If the timer registers
are loaded with the value 803, 100.5 SCLKs will occur between
interrupts and subsequently between transmit instructions. This
situation will result in nonequidistant sampling as the transmit
instruction is occurring on an SCLK edge. If the number of
SCLKs between interrupts is a whole integer figure of N, equidis-
tant sampling will be implemented by the DSP.
TMS320C5x/
AD7476/
TMS320C54x*
AD7477/
AD7478*
SCLK
CLKX
CLKR
DR
SDATA
FSX
FSR
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7476/
Figure 18. Interfacing to the TMS320C5x/C54x
ADSP-21xx*
SCLK
AD7477/
AD7478*
AD7476/AD7477/AD7478 to ADSP-21xx Interface
SCLK
The ADSP-21xx family of DSPs are interfaced directly to the
AD7476/AD7477/AD7478 without any glue logic required. The
SPORT control register should be set up as follows:
DR
SDATA
RFS
TFS
CS
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data-Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. Interfacing to the ADSP-21xx
ITFS = 1
–16–
REV. D
AD7476/AD7477/AD7478
AD7476/AD7477/AD7478 to DSP56xxx Interface
AD7476/AD7477/AD7478 to MC68HC16 Interface
The connection diagram in Figure 20 shows how the AD7476/
AD7477/AD7478 can be connected to the SSI (Synchronous
Serial Interface) of the DSP56xxx family of DSPs from Motorola.
The SSI is operated in Synchronous Mode (SYN bit in
CRB =1) with internally generated word frame sync for both
Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in CRB). Set the word
length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. To
implement the Power-Down mode on the AD7476/AD7477/
AD7478, the word length can be changed to eight bits by setting
bits WL1 = 0 and WL0 = 0 in CRA. It should be noted that
for signal processing applications, it is imperative that the
frame synchronization signal from the DSP56xxx provides
equidistant sampling.
The Serial Peripheral Interface (SPI) on the MC68HC16 is
configured for Master Mode (MSTR = 1), the Clock Polarity
Bit (CPOL) = 1, and the Clock Phase Bit (CPHA) = 0. The SPI
is configured by writing to the SPI Control Register (SPCR)—see
the 68HC16 User Manual. The serial transfer will take place as
a 16-bit operation when the SIZE bit in the SPCR register is set
to SIZE = 1. To implement the Power-Down mode with an
8-bit transfer, set SIZE = 0. A connection diagram is shown
in Figure 21.
AD7476/
MC68HC16*
SCLK/PMC2
MISO/PMC0
AD7477/
AD7478*
SCLK
SDATA
AD7476/
AD7477/
DSP56xxx*
SCK
AD7478*
SS/PMC3
CS
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
SRD
SC2
SDATA
Figure 21. Interfacing to the MC68HC16
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. Interfacing to the DSP56xxx
REV. D
–17–
AD7476/AD7477/AD7478
OUTLINE DIMENSIONS
6-Lead Plastic Surface-Mount Package [SOT-23]
(RT-6)
Dimensions shown in millimeters
2.90 BSC
6
1
5
2
4
3
2.80 BSC
1.60 BSC
PIN 1
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
0.60
0.45
0.30
10؇
0؇
0.50
0.30
0.15 MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178AB
–18–
REV. D
AD7476/AD7477/AD7478
Revision History
Location
Page
3/04—Data Sheet changed from REV. C to REV. D.
Added U.S. Patent number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to AD7476/AD7477/AD7478 to ADSP-21xx Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/03—Data Sheet changed from REV. B to REV. C.
Change to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Change to TYPICAL CONNECTION DIAGRAM SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Change to Figure 8 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Change to Figure 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Change to Figure 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
OUTLINE DIMENSIONS updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REV. D
–19–
–20–
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