AD7456BRM [ADI]
IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, MICRO, SOIC-8, Analog to Digital Converter;
| 型号： | AD7456BRM |
| 厂家： | 
ADI |
| 描述： | IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, MICRO, SOIC-8, Analog to Digital Converter 光电二极管 转换器 |
| 文件： | 总8页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
Differential Input, 100kSPS,
a
PreliminaryTechnicalData
12-BitADCin8-leadSOT-23
AD7456
FEATU RES
F U NC T IO NAL B LO C K D IAG RAM
Specified for VDD of 3 V and 5 V
Ve ry Lo w Po w e r:
TBD m W t yp a t 100kS PS w it h 3 V S u p p lie s
TBD m W t yp a t 100kS PS w it h 5 V S u p p lie s
Fu lly Diffe re n t ia l An a lo g In p u t
Wid e In p u t Ba n d w id t h :
V
DD
V
V
12-BIT SUCCESSIVE
IN+
70d B S INAD a t 20kHz In p u t Fre q u e n cy
No Pip e lin e De la ys
APPROXIMATION
T/H
ADC
IN-
S e ria l In t e rfa ce - S PITM/ QS PITM/ MICROWIRETM
DS P Co m p a t ib le
/
V
REF
Au t o m a t ic Po w e r-Do w n Mo d e
8 Pin S OT-23 a n d µS OIC Pa cka g e
SCLK
AP P LICATIO N S
Tra n s d u c e r In t e rfa c e
Battery Pow ered System s
Data Acquisition System s
Portable Instrum entation
Motor Control
SDATA
CONTROL
LOGIC
AD7456
CS
Co m m u n ic a t io n s
GND
G E NE R AL D E S C R IP T IO N
powered up on the falling edge of CS and a conversion is
initiated on the rising edge of CS, where the analog input
is sampled. Once a conversion is complete, the device
automatically enters a power down mode to reduce power
dissipation between conversions.
T he AD7456 is a 12-bit, low power, successive-approxi-
mation (SAR) analog-to-digital converter that features a
fully differential analog input. T his part operates from a
single 3 V or 5 V power supply and features throughput
rates up to 100kSPS.
T he SAR architecture of this part ensures that there are
no pipeline delays.
T he part contains a low-noise, wide bandwidth, differen-
tial track and hold amplifier (T /H) which can handle
input frequencies in excess of 1MHz with the -3dB point
being 20MH z typically. T he reference voltage is applied
externally to the VREF pin and can be varied from 100 mV
to 3.5 V depending on the power supply and what suits the
application. T he value of the reference voltage determines
the common mode voltage range of the part. With this
truly differential input structure and variable reference
input, the user can select a variety of input ranges and bias
points.
P R O D U C T H IG H LIG H T S
1.Operation with either 3 V or 5 V power supplies.
2.Low Power Consumption.
With a 3V supply, the AD7456 offer T BDmW
typ power consumption for 100kSPS throughput.
3.Fully D ifferential Analog Input.
4.Variable Voltage Reference Input.
5.N o Pipeline D elay.
6.Accurate control of the sampling instant via a CS input
and once off conversion control.
7.8-lead SOT -23 package.
T he conversion process and data acquisition are controlled
using CS and the serial clock allowing the device to inter-
face with Microprocessors or DSPs. T he device is
8. ENOB > 8 bits typically with 100mV reference.
MICROWIRE is a trademark of National Semiconductor Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
REV. PrA 24/05/02
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
w w w .analog.com
© Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
( V = 2.7V to 3.6V, fSCLK = 12MHz, fS = 100kHz, V = 2.0 V; F = 20kHz;
DD
REF
IN
1
V = 4.75V to 5.25V, fSCLK = 12MHz, fS = 100kHz, V = 2.5 V; F = 20kHz;
V
CM
DD
REF
IN
AD7456-SPECIFICATIONS
3 = V ; T = TMIN to T , unless otherwise noted.)
REF A MAX
P ar am eter
Test Conditions/Com m ents
B Version1
U n it
D YN AM IC PERF O RM AN C E
Signal to (Noise + Distortion)
(SIN AD )2
VDD = 5V
VDD = 3V
70
68
-75
-73
-75
-73
dB min
dB min
dB max
dB max
dB max
dB max
T otal H armonic D istortion (T H D )2 VDD = 5V, -80dB typ
VDD = 3V, -78dB typ
Peak H armonic or Spurious Noise2
VDD = 5V, -82dB typ
VDD = 3V, -80dB typ
Intermodulation D istortion (IM D )2
Second Order T erms
T hird Order T erms
-85
-85
10
50
20
dB typ
dB typ
ns typ
ps typ
M H z typ
M H z typ
Aperture D elay2
Aperture Jitter2
Full Power Bandwidth2
@ -3 dB
@ -0.1 dB
2.5
D C AC C U RAC Y
Resolution
12
± 1
Bits
LSB max
Integral N onlinearity (IN L)2
D ifferential N onlinearity (D N L)2
Guaranteed No Missed Codes
to 12 Bits.
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
± 1
± 3
± 6
± 3
± 6
± 3
± 6
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Zero Code Error2
Positive Gain Error2
N egative Gain Error2
AN ALO G IN PU T
Full Scale Input Span
Absolute Input Voltage
VIN +
4
2 x VREF
VIN+ - VIN -
V
3
VCM = VREF
VCM = VREF
VCM ± VREF/2
V
V
3
VIN -
VCM ± VREF/2
D C Leakage Current
Input Capacitance
± 1
20
6
µA max
pF typ
pF typ
When in T rack
When in Hold
REF EREN C E IN PU T
VREF Input Voltage
VDD = 5 V (±1% tolerance
for specified performance)
VDD = 3 V (±1% tolerance
for specified performance)
2.55
V
2.06
± 1
V
D C Leakage Current
µA max
pF typ
VREF Input Capacitance
15
LO G IC IN PU T S
Input H igh Voltage, VIN H
Input Low Voltage, VIN L
Input Current, IIN
2.4
0.8
± 1
10
V min
V max
µA max
pF max
T ypically 10nA, VIN = 0VorVD D
7
Input Capacitance, CIN
LO G IC O U T P U T S
Output H igh Voltage, VOH
VDD = 5V; ISOURCE = 200µA
VDD = 3V; ISOURCE = 200µA
ISIN K = 200µA
2.8
2.4
0.4
± 1
10
T wo’s
V min
V min
V max
µA max
pF max
Output Low Voltage, VOL
Floating-State Leakage C urrent
Floating-State Output Capacitance7
Output Coding
C omplement
–2 –
REV. PrA
PRELIMINARY TECHNICAL DATA
AD7456 - SPECIFICATIONS
AD7456
P a r a m eter
Test Conditions/Com m ents
B Ver sion1
Units
C O N VERSIO N RAT E
Conversion T ime
1.33µs with a 12MHz SCLK
Sine Wave Input
Step Input
16
SC LK cycles
ns max
ns max
T rack/H old Acquisition T ime2
T BD
T BD
100
T hroughput Rate9
kSPS max
P O WER REQ U IREM EN T S
VD D
Range: 3 V+20%/-10%;
5 V ± 5%
3/5
Vm in /m ax
1 0
I D D
Static
O perational
VDD =3 V/5 V. SCLK On or Off
VDD = 5 V.
VDD = 3 V.
0.5
T BD
T BD
mA typ
mA max
mA max
Power D issipation
Operational
VDD =5 V.
VDD =3 V.
T BD
T BD
mW max
mW max
N O T E S
1T emperature ranges as follows: A,
2See ‘T erm inology’ section.
B Versions: –40°C to + 85°C .
3C ommon M ode Voltage. T he input signal can be centered on any choice of dc C ommon M ode Voltage as long as this value is in the range
specified in F igures T BD .
4Because the input spans of VIN+ and VIN- are both VREF
, and they are 180° out of phase, the differential voltage is 2 x VREF.
5T he AD 7456 is functional with
6T he AD 7456 is functional with
a
a
reference input from100mV and for VDD
reference input from100mV and for VDD
=
=
5V, the reference can range up to 3.5V (see ‘Reference Section’).
3V, the reference range up to 2.2V (see ‘Reference Section’).
7Sample tested
@
+ 25°C to ensure compliance.
9See ‘Serial Interface Section’.
10M easured with
midscale D C input.
a
Specifications subject to change without notice.
–3 –
REV. PrA
PRELIMINARY TECHNICAL DATA
AD7456
( V = 2.7V to 3.6V, fSCLK = 12MHz, fS = 100kHz, V = 2.0 V;
DD
REF
TIMINGSPECIFICATIONS1,2
V = 4.75V to 5.25V, fSCLK = 12MHz, fS = 100kHz, V = 2.5 V;
DD
REF
V
CM
3 = V ; T = TMIN to T , unless otherwise noted.)
REF A MAX
Lim it at T MIN, TMAX
P ar am eter
+3V
+5V
Units
D escription
4
fSC LK
10
10
kH z min
12
12
M H z max
tC O N VE RT
tP O WE RU P
16 x tSCLK
1.33
1.4
16 x tSCLK
1.33
1.4
1.4
10
20
40
0.4 tSCLK
0.4 tSCLK
10
tSCLK = 1/fSCLK
12M H z fSC LK
Power-U p T ime
Acquisition T ime
µs max
µs min
µs min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns min
tAC Q U ISIT IO N 1.4
t2
10
20
40
0.4 tSCLK
CS Rising Edge to SCLK Falling Edge Setup T ime
5
t35
Delay from CS Rising Edge Until SDAT A 3-State Disabled
Data Access T ime After SCLK Falling Edge
SCLK H igh Pulse Width
t4
t5
t6
0.4 tSCLK
SCLK Low Pulse Width
t76
10
10
35
20
SCLK Edge to Data Valid Hold T ime
SCLK Falling Edge to SDAT A 3-State Enabled
SCLK Falling Edge to SDAT A 3-State Enabled
T ime spent in Power Down
t8
10
35
20
tSLEEP
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts.
2See Figure 1, Figure
2 and the ‘Serial Interface’ section.
3C om m on M od e Voltage.
4M ark/Space ratio for the SC LK input is 40/60 to 60/40.
5Measured with the load circuit of Figure
3
and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD
V.
6t8 is derived from the measured time taken by the data outputs to change 0.5
= 5 V and time for
an output to cross 0.4 V or 2.0 V for VDD
= 3
V
when loaded with the circuit of Figure 2. T he measured num-
ber is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. T his means that the time, t8, quoted in the
timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
Specifications subject to change without notice.
POWER
UP
CONVERT
START
TRACK
HOLD
TRACK
T
POWERUP
T
T
POWERUP
T
ACQ UIS ITION
ACQ UISITION
C S
AUTO MATIC
POWER DOWN
t
2
t
5
SCLK
t
t
4
0
t
7
t
6
t
8
3
0
T
SLEEP
DB11
SDATA
0
0
DB10
DB2 DB1 DB0
THREE-STATE
THREE-STATE
4 LEADING ZERO’S
Figure 1. AD7456 Serial Interface Tim ing Diagram
–4 –
REV. PrA
PRELIMINARY TECHNICAL DATA
AD7456
AB SO LU T E M AXIM U M RAT ING S1
(T A = +25°C unless otherwise noted)
I
OL
200µA
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V
VIN+ to GND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
VIN- to GND . . . . . . . . . . . . . . .
–0.3 V to VDD + 0.3 V
Digital Input Voltage to GND . . . . . . . . -0.3 V to +7 V
Digital Output Voltage to GND . -0.3 V to VDD + 0.3 V
VREF to GND . . . . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V
Input Current to Any Pin Except Supplies2 . . . . ± 10m A
Operating T emperature Range
TO
OUTP UT
PIN
+1.6V
C
L
50 pF
Commercial (A, B Version) . . . . . . . . . -40oC to +85oC
Storage T emperature Range . . . . . . . . . -65oC to +150oC
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . + 150oC
200µA
I
OH
T hermal Impedance . . . . . . . . . . 205.9°C /W (µSOIC )
211.5°C/W (SOT -23)
JA
T hermal Impedance . . . . . . . .
43.74°C/W (µSOIC)
91.99°C/W (SOT -23)
JC
Figure 3. Load Circuit for Digital Output Tim ing
Specifications
Lead T emperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . + 215oC
Infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . + 220oC
E S D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kV
N O T E S
1Stressesabove those listed under “Absolute Maximum Ratings” maycause permanent
damage to the device. Thisisa stressratingonlyand functionaloperation ofthe device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods mayaffect device reliability.
2T ransient currents of up to 100 mA will not cause SC R latch up.
O R D E R ING G U ID E
Linearity
P ackage
Model
Ran ge
Error (LSB)1 O p tion 4
Br anding Infor m ation
AD 7456BRT
-40°C to +85°C
-40°C to +85°C
Evaluation Board
C ontroller Board
± 1 LSB
± 1 LSB
RT -8
RM -8
T BD
T BD
AD 7456BRM
T BD
EVAL-C O N T RO L BRD 23
NOTES
1Linearity error here refers to Integral N on-linearity Error.
2T his can be used as a stand-alone evaluation board or in conjunction with the EVALUAT ION BOARD CONT ROLLER for evaluation/demonstration purposes.
3EVALU AT ION BOARD C ON T ROLLER. T his board is
evaluation boards ending in the C B designators. T o order
a
complete unit allowing
complete Evaluation Kit, you will need to order the AD C evaluation board i.e.
a PC to control and communicate with all Analog D evices
a
T BD , the EVAL-C ON T ROL BRD 2 and
a 12V AC transformer. See the T BD technote for more information.
4S0 = SOIC; RM = µSOIC
C A U T I O N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V
readily accumulate on the human body and test equipment and can discharge without
d et ect ion . Alt h ou gh t h e AD 7456 feat u res p rop riet ary E SD p rot ect ion circu it ry,
p erm an en t d am age m ay occu r on d evices su b ject ed t o h igh -en ergy elect rost at ic
discharges. T herefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–5 –
REV. PrA
PRELIMINARY TECHNICAL DATA
AD7456
P IN F U NC T IO N D E SC R IP T IO N
P in Mnem onic
Function
VREF
Reference Input for the AD7456. An external reference must be applied to this input. For a 5 V power
supply, the reference is 2.5 V (±1%) and for a 3 V power supply, the reference is 2V (±1%)
for specified performance. T his pin should be decoupled to GND with a capacitor of at least 0.1µF.
See the ‘Reference Section’ for more details.
VIN +
VIN -
Positive T erminal for Differential Analog Input.
Negative T erminal for Differential Analog Input.
G N D
Analog Ground. Ground reference point for all circuitry on the AD7456. All analog input
signals and any external reference signal should be referred to this GND voltage.
C S
Chip Select. T his input provides the dual function of powering up the device and initiating a
conversion on the AD7456.
SD AT A
Serial Data. Logic Output. T he conversion result from the AD7456 is provided on this output
as a serial data stream. T he bits are clocked out on the falling edge of the SCLK input. T he data
stream of the AD7456 consists of four leading zeros followed by the 12 bits of conversion data which
is provided MSB first. T he output coding is two’s complement.
SC L K
V D D
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. T his clock
input is also used as the clock source for the conversion process.
Power Supply Input. VDD is 3 V (+20%/-10%) or 5 V (±5%). T his supply should be decoupled to
GND with a 0.1µF Capacitor and a 10µF T antalum Capacitor.
P IN C O NFIGURATIO N 8-LE AD SO T-23
V
V
1
2
3
4
V
8
7
6
5
REF
DD
AD7456
SOT-23
TOP VIEW
(Not to Scale)
SCLK
SDATA
CS
IN+
V
IN -
GND
P IN C O NF IG URAT IO N µSO IC
V
V
REF
1
2
3
4
8
7
6
5
DD
AD7456
µSOIC
TOP VIEW
(Not to Scale)
V
IN +
SCLK
SDATA
CS
V
IN-
GND
–6 –
REV. PrA
PRELIMINARY TECHNICAL DATA
AD7456
T E R M I N O L O G Y
Ap er tu r e Jitter
T his is the sample to sample variation in the effective
point in time at which the actual sample is taken.
Signal to (Noise + D istor tion) Ratio
T his is the measured ratio of signal to (noise + distortion)
at the output of the ADC. T he signal is the rms amplitude
of the fundamental. Noise is the sum of all
nonfundamental signals up to half the sampling frequency
(fS/2), excluding dc. T he ratio is dependent on the number
of quantization levels in the digitization process; the more
levels, the smaller the quantization noise. T he theoretical
signal to (noise + distortion) ratio for an ideal N-bit con-
verter with a sine wave input is given by:
F u ll P ower Ban dwidth
T he full power bandwidth of an ADC is that input fre-
quency at which the amplitude of the reconstructed
fundamental is reduced by 0.1dB or 3dB for a full scale
input.
C om m on Mode Rejection Ratio (C MRR)
T he Common Mode Rejection Ratio is defined as the
ratio of the power in the ADC output at full-scale fre-
quency, f, to the power of a 200mV p-p sine wave applied
to the Common Mode Voltage of VIN+ and VIN- of fre-
quency fs:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
T hus for a 12-bit converter, this is 74 dB,
T ota l H a r m on ic D istor tion
CMRR ( dB) = 10log( Pf/Pfs)
T otal harmonic distortion (T HD) is the ratio of the rms
sum of harmonics to the fundamental. For the AD7450, it
is defined as:
Pf is the power at the frequncy f in the ADC output; Pfs is
the power at frequency fs in the ADC output.
In tegr a l Non lin ea r ity (INL)
T his is the maximum deviation from a straight line pass-
ing through the endpoints of the ADC transfer function.
2
2
2
2
2
V2
V
V
V
V
+
6
+
+
+
3
4
5
THD (d B ) 20 lo g
=
V1
D iffer en tia l Non lin ea r ity (D NL)
T his is the difference between the measured and the ideal 1
LSB change between any two adjacent codes in the ADC.
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, V5 and V6 are the rms amplitudes of the second to
the sixth harmonics.
Zer o C ode E r r or
T his is the deviation of the midscale code transition (111...111
P eak H ar m onic or Spur ious Noise
to 000...000) from the ideal VIN+-VIN (i.e., 0LSB).
-
Peak harmonic or spurious noise is defined as the ratio of
the rms value of the next largest component in the ADC
output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried
in the noise floor, it will be a noise peak.
P ositive Gain E r r or
T his is the deviation of the last code transition (011...110 to
011...111) from the ideal VIN+-VIN- (i.e., +VREF - 1LSB), after
the Zero Code Error has been adjusted out.
Nega tive G a in E r r or
T his is the deviation of the first code transition (100...000 to
100...001) from the ideal VIN+-VIN - (i.e., -VREF + 1LSB), after
the Zero Code Error has been adjusted out.
In t er m od u la t ion D ist or t ion
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities will create
distortion products at sum and difference frequencies of
mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation
distortion terms are those for which neither m nor n are
equal to zero. For example, the second order terms in-
clude (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
T r a ck/H old Acqu isition T im e
T he track/hold amplifier returns into track mode on the
13th SCLK rising edge (see the “Serial Interface Sec-
tion”). T he track/hold acquisition time is the minimum
time required for the track and hold amplifier to remain in
track mode for its output to reach and settle to within 0.5
LSB of the applied input signal.
T he AD7456 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth
are used. In this case, the second order terms are usually
distanced in frequency from the original sine waves while
the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third
order terms are specified separately. T he calculation of the
intermodulation distortion is as per the T H D specification
where it is the ratio of the rms sum of the individual dis-
tortion products to the rms amplitude of the sum of the
fundamentals expressed in dBs.
P ower Supply Rejection Ratio (P SRR)
T he power supply rejection ratio is defined as the ratio of
the power in the ADC output at full-scale frequency, f, to
the power of a 200mV p-p sine wave applied to the ADC
VDD supply of frequency fs. T he frequency of this input
varies from 1kHz to 1MHz.
PSRR (dB) = 10 log (Pf/Pfs)
Pf is the power at frequency f in the ADC output; Pfs is
the power at frequency fs in the ADC output.
Ap er tu r e D ela y
T his is the amount of time from the leading edge of the
sampling clock until the ADC actually takes the sample.
–7 –
REV. PrA
PRELIMINARY TECHNICAL DATA
AD7456
SE R IAL INT E R F AC E
Figure 1 shows a detailed timing diagram for the serial
interface of the AD7456. T he serial clock provides the
conversion clock and also controls the transfer of data
from the AD7456 during conversion.
T he falling edge of CS powers the part up and also puts
the track and hold into track. T he power up time is
1.4µsec minimum and in this time, the device also ac-
quires the analog input signal. CS must remain low for
the duration of power up. T he rising edge of CS initiates
the conversion process, puts the track and hold into hold
mode and takes the serial data bus out of three-state. T he
conversion will require 16 SCLK cycles to complete.
On the 16th SCLK falling edge, after the time t8, the
serial data bus will go back into three-state, and the device
will automatically enter full power down. It will remain
powered down until the next falling edge of CS.
If the falling edge of CS occurs before the 16 bits of con-
version data have been clocked out of the device, the
conversion will be aborted, SDAT A will go back into
three-state and the track and hold will go back into track;
thus the part will sample the analog input. On the next
rising edge of CS, a normal conversion will be initiated
and the device will automatically powerdown at the end of
the conversion as before.
T he conversion result from the AD7456 is provided on
the SDAT A output as a serial data stream. T he bits are
clocked out on the falling edge of the SCLK input. T he
data stream of the AD7456 consists of four leading zeros
followed by the 12 bits of conversion data which is pro-
vided MSB first. T he output coding is two’s complement.
16 serial clock cycles are therefore required to perform a
conversion and to access data from the AD7456. A rising
edge on CS provides the first leading zero to be read in by
the micro-controller or DSP. T he remaining data is then
clocked out on the subsequent SCLK falling edges begin-
ning with the second leading zero. T hus the first falling
clock edge on the serial clock after CS has gone high
provides the second leading zero. T he final bit in the data
transfer is valid on the 16th falling edge, having been
clocked out on the previous (15th) falling edge.
–8 –
REV. PrA
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