AD7399BR-REEL7 [ADI]
Quad, Serial-Input 12-Bit/10-Bit DACs; 四，串行输入，12位/ 10位DAC
| 型号： | AD7399BR-REEL7 |
| 厂家： | 
ADI |
| 描述： | Quad, Serial-Input 12-Bit/10-Bit DACs |
| 文件： | 总16页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad, Serial-Input
12-Bit/10-Bit DACs
a
AD7398/AD7399
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AD7398—12-Bit Resolution
AD7399—10-Bit Resolution
V
V
B
V
A
DD
REF
REF
Programmable Power Shutdown
Single (3 V to 5 V) or Dual (؎5 V) Supply Operation
3-Wire Serial SPI-Compatible Interface
Internal Power ON Reset
Double Buffered Registers for Simultaneous
Multichannel DAC Update
Four Separate Rail-to-Rail Reference Inputs
Thin Profile TSSOP-16 Package Available
Low Tempco 1.5 ppm/؇C
DAC A
INPUT
REG A
V
A
B
DAC A
DAC B
OUT
OUT
REGISTER
SERIAL
REGISTER
DAC B
REGISTER
CS
INPUT
REG B
V
SDI
APPLICATIONS
DAC C
INPUT
REG C
V
V
C
DAC C
DAC D
Automotive Output Voltage Span
Portable Communications
Digitally Controlled Calibration
PC Peripherals
REGISTER
OUT
CLK
DAC D
REGISTER
12/10
INPUT
REG D
D
OUT
GENERAL DESCRIPTION
POWER
ON RESET
The AD7398/AD7399 family of quad, 12-bit/10-bit, voltage-
output digital-to-analog converters is designed to operate from a
single 3 V to 5 V or a dual 5 V supply. Built with Analog’s robust
CBCMOS process, this monolithic DAC offers the user low
cost, and ease-of-use in single or dual-supply systems.
V
V
C
V
D
GND
RS
LDAC
SS
REF
REF
The applied external reference VREF determines the full-scale
output voltage. Valid VREF values include VSS < VREF < VDD that
result in a wide selection of full-scale outputs. For multiplying
applications ac inputs can be as large as 5 VP.
0.50
0.40
0.30
0.20
0.10
A doubled-buffered serial-data interface offers high-speed,
3-wire, SPI and microcontroller-compatible inputs using serial-
data-in (SDI), clock (CLK), and a chip-select (CS). A common
level-sensitive load-DAC strobe (LDAC) input allows simulta-
neous update of all DAC outputs from previously loaded Input
Registers. Additionally, an internal power ON reset forces the
output voltage to zero at system turn ON. An external asynchro-
nous reset (RS) also forces all registers to the zero code state. A
programmable power-shutdown feature reduces power dissipa-
tion on unused DACs.
V
DD
= +5V
= –5V
= +2.5V
V
SS
REF
V
T
= 25؇C
A
0
–0.10
–0.20
–0.30
–0.40
–0.50
Both parts are offered in the same pinout to enable users to
select the appropriate resolution for their application without
redesigning the layout. For 8-bit resolution applications see the
pin compatible AD7304 product.
512
4096
1024
1536
CODE – Decimal
2560
3072 3584
2048
0
The AD7398/AD7399 is specified over the extended industrial
(–40°C to +125°C) temperature range. Parts are available in
wide body SOIC-16 and ultracompact thin 1.1 mm TSSOP-
16 packages.
Figure 1. AD7398 DNL vs. Code (TA = 25°C)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
AD7398/AD7399–SPECIFICATIONS
(@ VDD = 5 V, VSS = 0 V; or VDD = +5 V, VSS = –5 V, VREF = +2.5 V, –40؇C < TA
< +125؇C, unless otherwise noted.)
AD7398 12-BIT VOLTAGE OUTPUT DAC
P
arameter
Symbol
Condition
3 V–5 V ؎ 10%
؎5 V ؎ 10%
Unit
STATIC PERFORMANCE
Resolution1
N
12
1.5
1
7
2.5
1.5
12
1.5
1
2.5
2.5
1.5
Bits
Relative Accuracy2
INL
DNL
VZSE
VFSE
TCVFS
LSB max
LSB max
mV max
mV max
ppm/°C typ
Differential Nonlinearity2
Zero-Scale Error
Monotonic
Data = 000H
Data = FFFH
Full-Scale Voltage Error
Full-Scale Tempco3
REFERENCE INPUT
V
REFIN Range4
VREF
RREF
CREF
0/VDD
35
5
VSS/VDD
35
5
V min/max
kΩ typ6
pF typ
Input Resistance5
Data = 555H, Worst-Case
Input Capacitance3
ANALOG OUTPUT
Output Current
IOUT
CL
Data = 800H, ∆VOUT = 4 LSB
No Oscillation
5
200
5
400
mA typ
pF max
Capacitive Load3
LOGIC INPUTS
Logic Input Low Voltage
VIL
VIH
VDD = 3 V
VDD = 5 V
CLK Only
0.5
0.8
80% VDD
2.1–2.4
1
V max
V max
V min
V min
µA max
pF max
0.8
4.0
2.4
1
Logic Input High Voltage
Input Leakage Current
Input Capacitance3
IIL
CIL
10
10
INTERFACE TIMING3, 7
Clock Frequency
Clock Width High
Clock Width Low
CS to Clock Set Up
Clock to CS Hold
Load DAC Pulsewidth
Data Setup
fCLK
tCH
tCL
tCSS
tCSH
tLDAC
tDS
tDH
tLDS
tLDH
11
45
45
10
20
45
15
10
0
16.6
30
30
5
15
30
10
5
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Data Hold
Load Setup to CS
Load Hold to CS
0
15
20
AC CHARACTERISTICS
Output Slew Rate
Settling Time8
Shutdown Recovery
DAC Glitch
SR
tS
tSDR
Q
Data = 000H to FFFH to 000H
To 0.1% of Full Scale
2
6
6
150
15
–63
2
6
6
150
15
–63
V/µs typ
µs typ
µs typ
Code 7FFH to 800H to 7FFH
nVs typ
nVs typ
dB typ
Digital Feedthrough
Feedthrough
QDF
V
OUT/VREF
VREF = 1.5 VDC + 1 V p-p,
Data = 000H, f = 100 kHz
SUPPLY CHARACTERISTICS
Shutdown Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation
IDD_SD
IDD
ISS
PDISS
PSS
No Load
30/60
1.5/2.5
1.5/2.5
5
30/60
1.6/2.7
1.6/2.7
16
µA typ/max
mA typ/max
mA typ/max
mW typ
VIL = 0 V, No Load
VIL = 0 V, No Load
VIL = 0 V, No Load
Power Supply Sensitivity
∆VDD
=
5%
0.006
0.006
%/% max
NOTES
1One LSB = VREF/4096 V for the 12-bit AD7398.
2The first eight codes (000H, 007H) are excluded from the linearity error measurement in single supply operation.
3These parameters are guaranteed by design and not subject to production testing.
4When VREF is connected to either the VDD or the VSS power supply the corresponding VOUT voltage will program between ground and the supply voltage minus the
offset voltage of the output buffer, which is the same as the VZSE error specification. See additional discussion in the Operation section of the data sheet.
5Input resistance is code-dependent.
6Typicals represent average readings measured at 25°C.
7All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
8The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
–2–
REV. 0
AD7398/AD7399
(@ VDD = 5 V, VSS = 0 V; or VDD = +5 V, VSS = –5 V, VREF = +2.5 V, –40؇C < TA
< +125؇C, unless otherwise noted.)
AD7399 10-BIT VOLTAGE OUTPUT DAC
P
arameter
Symbol
Condition
3 V–5 V ؎ 10%
؎5 V ؎ 10%
Unit
STATIC PERFORMANCE
Resolution1
N
10
1
1
7
15
1.5
10
1
1
4
15
1.5
Bits
Relative Accuracy2
INL
DNL
VZSE
VFSE
TCVFS
LSB max
LSB max
mV max
mV max
ppm/°C typ
Differential Nonlinearity2
Zero-Scale Error
Monotonic
Data = 000H
Data = 3FFH
Full-Scale Voltage Error
Full-Scale Tempco3
REFERENCE INPUT
VREFIN Range4
VREF
RREF
CREF
0/VDD
40
5
VSS/VDD
40
5
V min/max
kΩ typ6
pF typ
Input Resistance5
Input Capacitance3
Data = 155H, Worst-Case
ANALOG OUTPUT
Output Current
IOUT
CL
Data = 200H, ∆VOUT = 1 LSB
No Oscillation
5
400
mA typ
pF max
Capacitive Load3
200
LOGIC INPUTS
Logic Input Low Voltage
VIL
VIH
VDD = 3 V
0.5
0.8
80% VDD
2.1–2.4
1
V max
V max
V min
V min
µA max
pF max
V
DD = 5 V
0.8
4.0
2.4
1
Logic Input High Voltage
CLK Only
Input Leakage Current
Input Capacitance3
IIL
CIL
10
10
INTERFACE TIMING3, 7
Clock Frequency
Clock Width High
Clock Width Low
CS to Clock Set Up
Clock to CS Hold
Load DAC Pulsewidth
Data Setup
fCLK
tCH
tCL
tCSS
tCSH
tLDAC
tDS
tDH
tLDS
tLDH
11
45
45
10
20
45
15
10
0
16.6
30
30
5
15
30
10
5
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Data Hold
Load Setup to CS
Load Hold to CS
0
15
20
AC CHARACTERISTICS
Output Slew Rate
Settling Time8
Shutdown Recovery
DAC Glitch
SR
tS
tSDR
Q
QDF
VOUT/VREF
Data = 000H to 3FFH to 000H
To 0.1% of Full Scale
2
6
6
150
15
–63
2
6
6
150
15
–63
V/µs typ
µs typ
µs typ
Code 1FFH to 200H to 1FFH
nVs typ
nVs typ
dB typ
Digital Feedthrough
Feedthrough
VREF = 1.5 VDC + 1 V p-p,
Data = 000H, f = 100 kHz
SUPPLY CHARACTERISTICS
Shutdown Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation
IDD_SD
IDD
ISS
PDISS
PSS
No Load
30/60
1.5/2.5
1.5/2.5
5
30/60
1.6/2.7
1.6/2.7
16
µA typ/max
mA typ/max
mA typ/max
mW typ
VIL = 0 V, No Load
VIL = 0 V, No Load
VIL = 0 V, No Load
Power Supply Sensitivity
∆VDD
=
5%
0.006
0.006
%/% max
NOTES
1One LSB = VREF/1024 V for the 10-bit AD7399.
2The first two codes (000H, 001H) are excluded from the linearity error measurement in single supply operation.
3These parameters are guaranteed by design and not subject to production testing.
4When VREF is connected to either the VDD or the VSS power supply the corresponding VOUT voltage will program between ground and the supply voltage minus the
offset voltage of the output buffer, which is the same as the VZSE error specification. See additional discussion in the Operation section of the data sheet.
5Input resistance is code-dependent.
6Typicals represent average readings measured at 25°C.
7All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
8The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
–3–
REV. 0
AD7398/AD7399
ABSOLUTE MAXIMUM RATINGS*
Operating Temperature Range . . . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature
R-16 (Vapor Phase, 60 secs) . . . . . . . . . . . . . . . . . . 215°C
RU-16 (Infrared, 15 secs) . . . . . . . . . . . . . . . . . . . . 224°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VOUT to GND . . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA
Thermal Resistance θJA
16-Lead SOIC Package (R-16) . . . . . . . . . . . . . . 158°C/W
16-Lead Thin Shrink Surface Mount (RU-16) . . . 180°C/W
Maximum Junction Temperature (TJ Max) . . . . . . . . 150°C
Package Power Dissipation . . . . . . . . . . . . . (TJ Max–TA)/θJA
ORDERING GUIDE
Resolution
(Bits)
Temperature
Range
Package
Description
Package
Option
Container
Quantity
Model
AD7398BR
12
12
12
10
10
10
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
SOL-16
SOL-16
TSSOP-16
SOL-16
SOL-16
R-16
R-16
RU-16
R-16
R-16
48
AD7398BR-REEL7
AD7398BRU-REEL7
AD7399BR
AD7399BR-REEL7
AD7399BRU-REEL7
1,000
1,000
48
1,000
1,000
TSSOP-16
RU-16
The AD7398 contains 3254 transistors. The die size measures 108 mil × 144 millimeters.
SDI
SA
D1
D0
SD
A1
D9
D8
D7
D6
D5
D4
D3
D2
A0
D11
D10
IN
REG
LD
CLK
t
DH
t
CH
t
t
CL
DS
t
t
CSH
CSS
CS
t
LDH
LDAC
t
LDS
t
LDAC
Figure 2. AD7398 Timing Diagram (AD7399 with SDI = 14 Bits Only)
CLK
1/f
t
t
CLK
CL
CH
t
LDAC
LDH
t
t
LDS
LDS
t
LDAC
t
t
CSH
CSS
CS
t
CSS
Figure 3. Continuous Clock Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7398/AD7399 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD7398/AD7399
PIN CONFIGURATION
V
B
A
16 V
C
D
1
2
3
4
5
6
7
8
OUT
OUT
V
V
15
14
13
12
11
10
9
OUT
DD
OUT
AD7398/
AD7399
V
V
SS
V
A
V
V
C
D
REF
REF
TOP VIEW
(Not to Scale)
V
B
REF
REF
GND
SDI
CLK
CS
LDAC
RS
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
VOUT
OUTA
VSS
Function
1
2
3
4
B
DAC B Voltage Output.
DAC A Voltage Output.
Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can
be tied to VDD or VSS pin.
V
V
REFA
5
V
REFB
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can
be tied to VDD or VSS pin.
6
7
GND
LDAC
Ground Pin.
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all Input Register data to
DAC registers. Asynchronous active low input. See Control Logic Truth Table for operation.
8
9
RS
CS
Resets Input and DAC Registers to All Zero Codes. Shift Register contents unchanged.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers Serial Regis-
ter Data to the Input Register when CS returns High. Does not effect LDAC operation.
10
11
12
CLK
SDI
Schmitt Triggered Clock Input, Positive Edge Clocks Data into Shift Register.
Serial Data Input. Input data loads directly into the shift register.
DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can
be tied to VDD or VSS pin.
V
REFD
13
V
REFC
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can
be tied to VDD or VSS pin.
14
15
16
VDD
Positive Power Supply Input. Specified range of operation 3 V to 5 V 10%.
DAC D Voltage Output.
DAC C Voltage Output.
V
OUTD
VOUT
C
REV. 0
–5–
AD7398/AD7399
Table I. Control Logic Truth Table
Serial Shift Register Function
CS
CLK
LDAC
Input Register Function
DAC Register
H
L
L
L
X
L
H
H
H
H
H
L
No Effect
No Effect
Shift-Register-Data Advanced One Bit
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
Latched
Latched
Updated with SR Contents
Latched
Latched
No Effect
No Effect
Latched
Latched
Latched
Transparent
Latched
↑
+
H
↑
+
L/H
X
X
H
H
↑
+
NOTES
1. ↑+ Positive logic transition; ↓– Negative logic transition; X Don’t Care; SR shift register.
2. At power ON, both the Input Register and the DAC Register are loaded with all zeros.
3. During Power Shutdown, reprogramming of any internal registers can take place, but the output amplifiers will not produce the new values until the part is taken
out of Shutdown mode.
4. LDAC input is a level-sensitive input that controls the four DAC registers.
Table II. AD7398 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
Bit Position B15
LSB
B0
D0
B14
SD
B13
A1
B12
A0
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
AD7398
SA
NOTE
Bit positions B14 and B15 are power shutdown control Bits SD and SA. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to
Logic 1, the address decoded by Bits B12 and B13 (A0 and A1) determine the DAC channel that will be placed in the power shutdown state.
Table III. AD7399 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
Bit Position B13
LSB
B0
D0
B12
SD
B11
A1
B10
A0
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
AD7399
SA
NOTE
Bit positions B12 and B13 are power shutdown control Bits SD and SA. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to
Logic 1, the address decoded by Bits B10 and B11 (A0 and A1) determine the DAC channel that will be placed in the power shutdown state.
Table IV. AD7398/AD7399 Address Decode Control
SA
SD
A1
A0
DAC Channel Affected
1
0
0
0
0
0
0
0
0
X
1
1
1
1
0
0
0
0
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
All DACs Shutdown
DAC A Shutdown
DAC B Shutdown
DAC C Shutdown
DAC D Shutdown
DAC A Input Register Decoded
DAC B Input Register Decoded
DAC C Input Register Decoded
DAC D Input Register Decoded
–6–
REV. 0
AD7398/AD7399
TERMINOLOGY
Relative Accuracy, INL
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL versus code plot can be seen in TPC 1.
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by 1 LSB
at the major carry transition (midscale transition). A plot of the
glitch impulse is shown in TPC 10.
Digital Feedthrough, QDF
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC, but
is measured when the DAC output is not updated. CS is held
high, while the CLK and SDI signals are toggled. It is speci-
fied in nV-s and is measured with a full-scale code change on
the data bus, i.e., from all 0s to all 1s and vice versa. A typi-
cal plot of digital feedthrough is shown in TPC 11.
Differential Nonlinearity, DNL
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maxi-
mum ensures monotonicity. TPC 3 illustrates a typical DNL
versus code plot.
Zero-Scale Error, VZSE
Zero-scale error is a measure of the output voltage error from
zero voltage when zero code is loaded to the DAC register.
Power Supply Sensitivity, PSS
This specification indicates how the output of the DAC is
affected by changes in the power supply voltage. Power supply
sensitivity is quoted in terms of % change in output per %
change in VDD for full-scale output of the DAC. VDD is varied
by 10%.
Full-Scale Error, VFSE
Full-scale error is a measure of the output voltage error from full-
scale voltage when full-scale code is loaded to the DAC register.
Reference Feedthrough, VOUT/VREF
Full-Scale Temperature Coefficient, TCVFS
This is a measure of the feedthrough from the VREF input to
the DAC output when the DAC is loaded with all 0s. A 100 kHz,
1 V p-p is applied to VREF. Reference feedthrough is expressed
in dB or mV p-p.
This is a measure of the change in full-scale error with a change
in temperature. It is expressed in ppm/°C or mV/°C.
DAC Glitch Impulse, Q
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
REV. 0
–7–
–Typical Performance Characteristics
AD7398/AD7399
0.50
1.50
1.25
1.00
0.75
0.50
0.25
AD7398
AD7398
0.40
V
V
V
T
= +5V
= –5V
V
V
V
T
= +5V
= –5V
DD
SS
DD
SS
0.30
0.20
= +2.5V
= +2.5V
= 25؇C
A
REF
REF
= 25؇C
A
0.10
0
–0.10
–0.20
–0.30
–0.40
–0.50
0
–0.25
–0.50
–0.75
–1.00
2560
CODE – Decimal
0
1536
2048
2560
3072
3584
4096
1536
2048
3072
3584
4096
512
1024
512
1024
0
CODE – Decimal
TPC 1. AD7398 INL vs. Code (TA = 25°C)
TPC 3. AD7398 DNL vs. Code (TA = 25°C)
0.50
0.25
0
0.50
0.25
0
T
V
= 25؇C, V = +5V
DD
A
DAC–D
DAC–D
= –5V, V
= +2.5V
SS
REF
T
= 25؇C
A
V
V
V
= +5V
DD
SS
= –5V
–0.25
–0.50
–0.25
–0.50
= +2.5V
REF
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
CODE – Decimal
CODE – Decimal
0.50
0.25
0
0.50
0.25
T
V
= 25؇C, V = +5V
DD
A
DAC–C
DAC–C
= –5V, V
= +2.5V
SS
REF
T
= 25؇C
0
–0.25
–0.50
A
V
V
V
= +5V
DD
SS
–0.25
–0.50
= –5V
= +2.5V
REF
0
128
256
384
512
640
768
896
0
128
256
384
512
640
768
896
1024
1024
CODE – Decimal
CODE – Decimal
0.50
0.25
0
0.50
0.25
0
T
V
= 25؇C, V = +5V
DD
T
V
= 25؇C, V = +5V
DD
A
A
DAC–B
DAC–B
= –5V, V
= +2.5V
= –5V, V = +2.5V
SS
SS
REF
REF
–0.25
–0.50
–0.25
–0.50
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
CODE – Decimal
CODE – Decimal
0.50
0.25
0
0.50
0.25
T
V
= 25؇C, V = +5V
DD
A
DAC–A
DAC–A
= –5V, V
= +2.5V
SS
REF
0
–0.25
–0.50
T
V
= 25؇C, V = +5V
DD
–0.25
–0.50
A
= –5V, V
= +2.5V
SS
REF
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
CODE – Decimal
CODE – Decimal
TPC 2. AD7399 INL vs. Code (TA = 25°C)
TPC 4. AD7399 DNL vs. Code (TA = 25°C)
–8–
REV. 0
AD7398/AD7399
10.0
8.0
6.0
4.0
1.00
0.75
AD7398/AD7399
AD7398
= 25؇C
T
= 25؇C
SINKING CURRENT INTO V
T
A
OUT
A
V
V
= +5V
= –5V
DD
SS
V
= +3V, V = 0V
SS
DD
DNL
0.50
0.25
0
V
= +5V, V = –5V
DD
SS
2.0
0
INL
V
= +5V, V = 0V
SS
DD
FSE
–2.0
–4.0
–6.0
–8.0
–10.0
–0.25
SOURCING CURRENT FROM V
OUT
–0.50
–0.75
–1.00
V
V
V
= +5V, V = –5V
SS
DD
DD
DD
= +5V, V = 0V
SS
= +3V, V = 0V
SS
–20
–15
–10
–5
0
5
10
15
– mA
20
–4
–3
–2
–1
0
1
4
5
–5
2
3
SOURCE OR SINK CURRENT FROM V
REFERENCE VOLTAGE – Volts
OUT
TPC 5. AD7398 INL, DNL, FSE vs. Reference Voltage
TPC 8. ∆VOUT vs. Load Current
25
20
15
10
5
100.00
AD7398
AD7398
90.00
SAMPLE SIZE = 125
T
= 25؇C
A
–40؇C TO +125؇C
V
V
V
= +5V
= –5V
DD
SS
80.00
70.00
60.00
50.00
40.00
30.00
20.00
= +2.5V
REF
10.00
0
0
512
3072
4096
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6
1024
1536
2048
2560
3584
0
CODE – Decimal
FULL SCALE ERROR TEMPCO – ppm/؇C
TPC 6. AD7398 Reference Input Current vs. Code
TPC 9. AD7398 Full-Scale Error Tempco
1000
AD7398
V
V
T
= +5V
= –5V
= 25؇C
DD
SS
A
100
90
100
CS (5V/DIV)
10
V
(0.2V/DIV)
OUT
0%
TIME – 2s/DIV
10
512
1024
1536
2048
2560
3072
3584 4096
0
CODE – Decimal
TPC 7. AD7398 Reference Input Resistance vs. Code
TPC 10. AD7398 Midscale Glitch
REV. 0
–9–
AD7398/AD7399
FFFH
800H
400H
200H
100H
080H
040H
020H
010H
008H
004H
002H
001H
0
–12
–24
–36
–48
–60
–72
100
90
V
(50mV/DIV)
OUT
–84
10
CLOCK (5V/DIV)
0%
V
V
V
T
= +5V
= –5V
DD
–96
000H
SS
= 100mV rms
REF
–108
= 25؇C
A
TIME – 100ns/DIV
1k
10k
100k
1M
100
FREQUENCY – Hz
TPC 11. AD7398 Digital Feedthrough
TPC 14. AD7398 Multiplying Gain vs. Frequency
5
V
= 5V, V = –5V, V
= 5V
REF
DD
SS
T
= 25؇C
A
2
4
1. V = +5V, V = –5V, CODE = 000 , FFF
2. V = +5V, V = –5V, CODE = 555
3. V = +5V, V = 0V, CODE = 000 , FFF
4. V = +5V, V = 0V, CODE = 555
5. V = +3V, V = 0V, CODE = 000 , FFF
6. V = +3V, V = 0V, CODE = 555
DD
SS
H
H
H
DD
SS
4
3
2
1
DD
SS
H
H
H
100
V
(2V/DIV)
OUT
90
DD
SS
H
DD
SS
H
H
DD
SS
1
3
6
5
10
0%
CS (5V/DIV)
TIME – 5s/DIV
0
1.E+03
1.E+04
1.E+08
1.E+06
1.E+07
1.E+05
CLOCK FREQUENCY – Hz
TPC 12. AD7398 Large Signal Settling Time
TPC 15. AD7398 Supply Current vs. Clock Frequency
2.0
V
= 5V, V = –5V, V
= 5V
REF
DD
SS
AD7398
؎5V
T
V
= 25؇C
A
DUAL SUPPLIES
= 2.5V
REF
100
V
(2V/DIV)
1.75
1.5
OUT
90
؎3V
SINGLE SUPPLY
10
CS (5V/DIV)
0%
1.25
1.0
TIME – 2s/DIV
4
2
3
5
6
POWER SUPPLY VOLTAGE – V
TPC 13. AD7398 Shutdown Recovery
TPC 16. AD7398 Supply Current vs. Supply Voltage
–10–
REV. 0
AD7398/AD7399
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
AD7398
SAMPLE SIZE = 135
AD7398/AD7399
V
V
= +5V
= –5V
DD
SS
V
= 2.5V
REF
0.75
CODE = FFF
H
0.5
0.25
0
CODE = 000
H
100
150
0
50
–50
100
200
400
500
600
0
300
TEMPERATURE – ؇C
HOURS OF OPERATION AT 150؇C
TPC 17. Supply Current vs. Temperature
TPC 19. AD7398 Long-Term Drift
36
AD7398/AD7399
V
V
= +5V
= –5V
DD
SS
35
34
33
32
31
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE – ؇C
TPC 18. Shutdown Current vs. Temperature
REV. 0
–11–
AD7398/AD7399
V
V
REF
C
D
A B
DD
AD7398/AD7399
DAC
INPUT
V
V
A
B
DAC A
DAC B
CS
OUT
REGISTER
REGISTER
CLK
ADDRESS
DECODE
4
SDI
DAC
REGISTER
INPUT
REGISTER
OUT
SERIAL
REGISTER
INPUT
DAC
DAC C
DAC D
V
C
D
OUT
REGISTER
REGISTER
12/10
DAC
REGISTER
INPUT
REGISTER
V
OUT
POWER
ON RESET
GND
V
RS
LDAC
SS
Figure 4. Simplified Block Diagram
CIRCUIT OPERATION
The nominal DAC output voltage is determined by the exter-
nally applied VREF and the digital data (D) as:
The AD7398 and AD7399 contain four, 12-bit and 10-bit,
voltage-output, digital-to-analog converters respectively. Each
DAC has its own independent multiplying reference input. Both
AD7398/AD7399 use 3-wire SPI-compatible serial data interface,
with an asynchronous RS pin for zero-scale reset. In addition, a
LDAC strobe enables four channel simultaneous updates for
hardware synchronized output voltage changes.
D
VOUT =VREF
×
×
(For AD7398)
(1)
4096
D
1024
VOUT =VREF
(For AD7399)
(2)
Where D is the 12-bit or 10-bit decimal equivalent of the data
word. VREF is the externally applied reference voltage.
D/A Converter Section
V
DD
In order to maintain good analog performance, bypass power
supplies with 0.01 µF ceramic capacitors (mount them close to
the supply pins) and 1 µF–10 µF Tantalum capacitors in paral-
lel. In additions, clean power supplies with low ripple voltage
capability should be used. Switching power supplies may be
used for this application but beware of its higher ripple voltage
and PSS frequency-dependent characteristics. It is also best to
supply the AD7398/AD7399’s power from the system’s analog
supply voltages. (Don’t use the digital 5 V supply).
AD7398/AD7399
V
REF
V
A
OUT
R
R
The reference input resistance is code dependent exhibiting
worst case 35 kΩ for AD7398 when the DAC is loaded with
alternating codes 010101010101. Similarly, the reference input
resistance is 40 kΩ for AD7399 when the DAC is loaded with
0101010101.
GND
V
SS
Figure 5. Simplified DAC Channel
DAC OPERATION
The internal R-2R ladder of the AD7398 and AD7399 operate
in the voltage switching mode maintaining an output voltage
that is the same polarity as the input reference voltage. A propri-
etary scaling technique is used to attenuate the input reference
voltage in the DAC. The output buffer amplifies the internal
DAC output to achieve a VREF to VOUT gain of unity.
OPERATION WITH VREF EQUAL TO THE SUPPLY
The AD7398/AD7399 is designed to approach the full output
voltage swing from ground to VDD or VSS. The maximum output
swing is achieved when the corresponding VREF input pin is tied
to the same power supply. This power supply should be low
noise and low ripple, preferably operated by a suitable reference
voltage source such as ADR292 and REF02. The output swing
–12–
REV. 0
AD7398/AD7399
is limited by the internal buffer offset voltage and the output
drive current capability of the output stage. One should at least
budget the VZSE offset voltage as the closest the output voltage
can get to either supply voltage under a no load condition. Under
a loaded output, degrade the headroom by a factor of 2 mV per
1 mA of load current. Also note that the internal op amp has an
offset voltage so that the first eight codes of AD7398 may not
respond at either the supply voltage or at ground until the internal
DAC voltage exceeds the output buffers offset voltage. Simi-
larly, the first two codes of AD7399 should not be used.
serial data is in 8-bit bytes, two right-justified data bytes can be
written to the AD7398 and AD7399. Keeping the CS line low
between the first and second bytes transfer will result in a suc-
cessful serial register update.
Once the data is properly aligned in the shift register, the posi-
tive edge of the CS initiates the transfer of new data to the target
DAC register, determined by the decoding of address Bits A1
and A0. For the AD7398, Tables I, II, IV, and Figures 2 and
3 define the characteristics of the software serial interface. For
the AD7399, Tables I, III, IV, and Figure 3 (with 14-bits excep-
tion) define the characteristics of the software serial interface.
Figures 6 and 7 show the equivalent logic interface for the key
digital control pins for AD7398 and AD7399.
POWER SUPPLY SEQUENCING
VDD/VSS of AD7398/AD7399 should be powered from the system
analog supplies. In addition, VIN of the external reference should
also be coming from the same supply. Such practice will avoid
a possible latch-up when the reference is powered on prior to
VDD/VSS, or powered off subsequent to VDD/VSS. If VDD/VSS
and VREF are separate power sources, then ensure VDD/VSS is
powered on before VREF and powered off after VREF. In addition,
An asynchronous RS provides hardware control reset to zero-
code state over the preset function and DAC Register loading. If
this function is not needed, the RS pin can be tied to logic high.
TO INPUT REGISTER
V
REF pins of the unused DACs should also be connected to GND
A
ADDRESS
B
or some power sources to ensure similar power-up/-down sequence.
DECODER
C
D
CS
PROGRAMMABLE POWER SHUTDOWN
EN
The two MSBs of the serial input register, SA and SD, are used
to program various shutdown modes. If SA is set to Logic 1, all
DACs will be in shutdown mode. If SA = 0 and SD = 1, a cor-
responding DAC will be shut down addressed by Bits A0 and
A1, See Tables II–IV.
SHIFT REGISTER
CLK
SDI
Figure 6. Equivalent Logic Interface
POWER-ON RESET
WORST CASE ACCURACY
Assuming a perfect reference, the worst-case output voltage may
be calculated from the following equation.
When the VDD power supply is turned ON, an internal reset
strobe forces all the Input and DAC registers to the zero-code
state. The VDD power supply should have a smooth positive
ramp without drooping in order to have consistent results,
especially in the region of VDD = 1.5 V to 2.2 V. The VSS sup-
ply has no effect on the power-on reset performance. The
DAC register data will stay at zero until a valid serial register
data load takes place.
D
2N
VOUT
where
=
×(VREF +VFSE )+VZSE + INL
(3)
D = Decimal Code Loaded to DAC Ranges 0 ≤ D ≤ 2N–1
N = Number of Bits
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND) and VDD as shown in Figure 7.
VREF = Applied Reference Voltage
VFSE = Full-Scale Error in Volts
VZSE = Zero-Scale Error in Volts
INL = Integral Nonlinearity in Volts INL is 0 at Full Scale
V
DD
or Zero Scale
DIGITAL INPUTS
SERIAL DATA INTERFACE
5k⍀
The AD7398/AD7399 uses a 3-wire (CS, SDI, CLK) SPI-
GND
compatible serial data interface. Serial data of the AD7398 and
AD7399 is clocked into the serial input register in a 16-bit and
14-bit data-word format respectively. MSB bits are loaded first.
Table II defines the 16 data-word bits for AD7398. Table III
defines the 14 data-word bits for the AD7399. Data is placed on
the SDI pin, and clocked into the register on the positive clock
edge of CLK subject to the data setup and data hold time
requirements specified in the Interface Timing specifications.
Data can only be clocked in while the CS chip select pin is
active low. For the AD7398, only the last 16 bits which are
clocked into the serial register, will be interrogated when the CS
pin returns to the logic high state, extra data bits are ignored.
For the AD7399, only the last 14 bits, which are clocked into
the serial register, will be interrogated when the CS pin returns
to the logic high state. Since most microcontrollers’ output
Figure 7. Equivalent ESD Protection Circuits
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD7398/AD7399 is via a
serial bus that uses standard protocol compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire interface consisting of a clock signal, a data signal
and a synchronization signal. The AD7398/AD7399 requires a
16-bit/14-bit data word with data valid on the rising edge of CLK.
The DAC update may be done automatically when all the data
is clocked in, or it may be done under control of LDAC.
REV. 0
–13–
AD7398/AD7399
80C51/80L51 to AD7398/AD7399 Interface
ADSP-2101/ADSP-2103 to AD7398/AD7399 Interface
A serial interface between the AD7398/AD7399 and the 80C51/
80L51 microcontroller is shown in Figure 11. TxD of the micro-
controller drives the CLK of the AD7398/AD7399, while RxD
drives the serial data line of the DAC. P3.3 is a bit program-
mable pin on the serial port which is used to drive CS.
Figure 8 shows a serial interface between the AD7398/AD7399
and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103
is set to operate in the SPORT (Serial Port) transmit alternate
framing mode. The ADSP-2101/ADSP-2103 is programmed
through the SPORT control register and should be configured
as follows: Internal Clock Operation, Active Low Framing,
16-Bit-Word Length. For the AD7398, transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled. For the AD7399, the first two bits are don’t care as the
AD7399 will keep the last 14 bits. Similarly, transmission is
initiated by writing a word to the Tx register after the SPORT
has been enabled. Because of the edge-triggered difference, an
inverter is required at the SCLKs between the DSP and the DAC.
P3.4
P3.3
LDAC
CS
AD7398/
AD7399
80C51/
80L51*
RX
D
D
SDI
CLK
TX
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. 80C51/80L51 to AD7398/AD7399 Interface
Note that the 80C51/80L51 provides the LSB first, while the
AD7398/AD7399 expect the MSB of the 16-bit/14-bit word
first. Care should be taken to ensure the transmit routine takes
this into account. It can usually be done through software by
shifting out and accumulating the bits in the correct order
before inputting to the DAC. In addition, 80C51 outputs two
byte words/16 bits data, thus for AD7399, the first two bits,
after rearrangement, should be Don’t Care as they will be
dropped from the AD7399’s 14-bit word.
FO
TFS
DT
LDAC
CS
AD7398/
AD7399
ADSP-2101/
ADSP-2103*
SDI
CLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 8. ADSP-2101/ADSP-2103 to AD7398/AD7399
Interface
68HC11 to AD7398/AD7399 Interface
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is valid on the falling edge of TxD, so the clock
must be inverted as the DAC clocks data into the input shift
register on the rising edge of the serial clock. The 80C51/80L51
transmits its data in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. As AD7399 requires a 14-bit
word, P3.3 (or any one of the other programmable bits) is the CS
input signal to the DAC, so P3.3 should be brought low at the
beginning of the 16-bit write cycle 2 × 8 bit words, and held low
until the 16-bit 2 × 8 cycle is completed. After that, P3.3 is
brought high again and the new data loads to the DAC. Again,
the first two bits, after rearranging, should be don’t care. LDAC
on the AD7398/AD7399 may also be controlled by the 80C51/
80L51 serial port output by using another bit-programmable
pin, P3.4.
Figure 9 shows a serial interface between the AD7398/AD7399
and the 68HC11 microcontroller. SCK of the 68HC11 drives
the CLK of the DAC, while the MOSI output drives the serial
data lines SDI. CS signal is driven from one of the port lines.
The 68HC11 is configured for master mode; MSTR = 1, CPOL = 0,
and CPHA = 0. Data appearing on the MOSI output is valid on
the rising edge of SCK.
PC6
PC7
LDAC
CS
68HC11/
68L11*
AD7398/
AD7399
MOS1
SDI
CLK
SCK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. 68HC11/68L11 to AD7398/AD7399 Interface
MICROWIRE to AD7398/AD7399 Interface
Figure 10 shows an interface between the AD7398/AD7399 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and into the AD7398/
AD7399 on the rising edge of the serial clock. No glue logic is
required as the DAC clocks data into the input shift register on
the rising edge.
CS
SO
CS
SDI
CLK
AD7398/
AD7399
MICROWIRE*
SCK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 10. MICROWIRE to AD7398/AD7399 Interface
–14–
REV. 0
AD7398/AD7399
APPLICATIONS
V
REF
STAIRCASE WINDOWS COMPARATOR
WINDOW 1
WINDOW 2
V
V
B
OUT
OUT
Many applications need to determine whether voltage levels are
within predetermined limits. Some requirements are for non-
overlapping windows and others for overlapping windows. Both
circuit configurations are shown in Figures 12 and 13 respectively.
A
D
C
V
OUT
WINDOW 3
V
OUT
GND
V
TEST
Figure 15. Overlapping Windows Range
V+
AD8564
10k⍀
The nonoverlapping circuit employs one AD7398/AD7399 and
ten comparators to achieve five voltage windows. These windows
range between VREF and analog ground as shown in Figure 13.
Similarly, the overlapping circuit employs six comparators to
achieve three overlapping windows, Figure 15.
V
REF
WINDOW 1
V
DD
V+
10k⍀
V
A
V
A
REF
OUT
WINDOW 2
AD7398/
AD7399
PROGRAMMABLE DAC REFERENCE VOLTAGE
With AD7398/AD7399’s flexibility, one of the internal DACs
can be used to control a common programmable VREFX for the
rest of the DACs.
V+
10k⍀
WINDOW 3
AD8564
V
B
C
V
V
B
OUT
REF
The circuit configuration is shown in Figure 16. The relation-
ship of VREFX to VREF is dependent upon the digital code and
the ratio of R1 and R2, and is given by:
V+
10k⍀
C
V
REF
OUT
WINDOW 4
R2
R1
D
R2
VREFX =VREF × 1+
–VREFX
×
×
(5)
2N R1
V+
10k⍀
1/2 AD8564
V
D
V D
OUT
REF
WINDOW 5
GND
D
R2
R1
VREF × 1+
VREFX
=
(6)
R2
1+
×
2N R1
Figure 12. Nonoverlapping Windows Comparator
V
Where D = Decimal Equivalent of Input Code
N = Number of Bits
REF
WINDOW 1
V
V
A
B
OUT
OUT
WINDOW 2
WINDOW 3
V
REF = Applied External Reference
REFX = Reference Voltage for DAC A to D
V
V
C
OUT
WINDOW 4
WINDOW 5
Table V. VREFX vs. R1 and R2
V
D
OUT
GND
R1, R2
Digital Code
VREFX
R1 = R2
R1 = R2
R1 = R2
R1 = 3R2
R1 = 3R2
R1 = 3R2
0000 0000 0000
1000 0000 0000
1111 1111 1111
0000 0000 0000
1000 0000 0000
1111 1111 1111
2 VREF
1.3 VREF
VREF
4 VREF
1.6 VREF
VREF
Figure 13. Nonoverlapping Windows Range
V
TEST
V+
AD8564
10k⍀
V
REF
WINDOW 1
V
V
DD
A
B
V
V
A
B
V+
OUT
REF
10k⍀
V
The accuracy of VREFX will be affected by the quality of R1 and
R2 and therefore, tight tolerance low tempco thin film resistors
should be used.
OUT
REF
WINDOW 2
AD7398/
AD7399
V
C
V
V
C
OUT
REF
V+
10k⍀
1/2 AD8564
D
V
D
REF
OUT
WINDOW 3
Figure 14. Overlapping Windows Comparator
REV. 0
–15–
AD7398/AD7399
R2؎0.1%
V
A
REF
V
V
A
R1؎0.1%
OUT
V
REF
DAC A
VIN
ADR293
V
B
REF
B
OUT
DAC B
V
C
REF
V
C
OUT
TO OTHER
COMPONENTS
DAC C
V
D
REF
V
D
OUT
DAC D
AD7398/AD7399
Figure 16. Programmable DAC Reference
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Wide SOIC
16-Lead TSSOP
(RU-16)
(R-16)
0.4133 (10.50)
0.3977 (10.00)
0.201 (5.10)
0.193 (4.90)
16
1
9
8
16
9
0.2992 (7.60)
0.2914 (7.40)
0.177 (4.50)
0.169 (4.30)
0.4193 (10.65)
0.3937 (10.00)
0.256 (6.50)
0.246 (6.25)
1
8
PIN 1
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
0.050 (1.27)
BSC
0.006 (0.15)
0.002 (0.05)
؋
45؇ 0.0433 (1.10)
MAX
8؇
0؇
8؇
0؇
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
0.028 (0.70)
0.020 (0.50)
SEATING
PLANE
0.0500 (1.27)
0.0157 (0.40)
0.0079 (0.20)
0.0035 (0.090)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
BSC
–16–
REV. 0
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