AD7398BRUZ-REEL7_技术文档

Quad, Serial-Input

12-Bit/10-Bit DACs

AD7398/AD7399

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AD7398—12-bit resolution

V

B

V

A

DD

REF

AD7399—10-bit resolution

AD7398/AD7399

Programmable power shutdown

Single (3 V to 5 V) or dual ( 5 V) supply operation

3-wire, serial SPI®-compatible interface

Internal power-on reset

Double buffered registers for simultaneous

multichannel DAC update

Four separate rail-to-rail reference inputs

Thin profile, TSSOP-16 package available

Low tempco: 1.5 ppm/°C

DAC A

REGISTER

INPUT

REG A

DAC A

DAC B

V

A

B

OUT

SERIAL

REGISTER

CS

SDI

DAC B

REGISTER

INPUT

REG B

V

DAC C

REGISTER

INPUT

REG C

V

C

D

DAC C

DAC D

OUT

CLK

Qualified for automotive applications

12/10

DAC D

REGISTER

APPLICATIONS

INPUT

REG D

OUT

Automotive output voltage span

Portable communications

Digitally controlled calibration

PC peripherals

POWER

ON RESET

V

RS

LDAC

V

C

V

D

GND

SS

REF

Figure 1.

GENERAL DESCRIPTION

The AD7398/AD7399 family of quad, 12-bit/10-bit, voltage

output digital-to-analog converters (DACs) is designed to

operate from a single 3 V to 5 V supply or a dual 5 V supply.

Built with the Analog Devices, Inc. robust CBCMOS process,

these monolithic DACs offer the user low cost with ease-of-use

in single or dual-supply systems.

Both parts are offered in the same pinout, enabling users to

select the appropriate resolution for their application without

redesigning the layout. For 8-bit resolution applications, see the

pin-compatible AD7304 product.

The AD7398/AD7399 are specified over the extended industrial

(−40°C to +125°C) temperature range. Parts are available in

16-lead, wide body SOIC and ultracompact, thin, 1.1 mm

TSSOP packages.

The applied external reference, V_REF, determines the full-scale

output voltage. Valid V_REFvalues include V_SS< V_REF< V_DDthat

result in a wide selection of full-scale outputs. For multiplying

applications, ac inputs can be as large as 5 V_P.

0.5

V

= +5V

= –5V

DD

SS

0.4

0.3

= +2.5V

REF

T

= 25°C

A

A doubled-buffered serial-data interface offers high speed, 3-wire,

SPI- and microcontroller-compatible inputs using serial data-in

0.2

CS

(SDI), clock (CLK), and a chip-select ( ). A common level-

0.1

LDAC

sensitive, load-DAC strobe ( ) input allows simultaneous

0

update of all DAC outputs from previously loaded input registers.

Additionally, an internal power-on reset forces the output voltage to

–0.1

–0.2

–0.3

–0.4

–0.5

RS

zero at system turn on. An external asynchronous reset ( ) also

forces all registers to the zero code state. A programmable power-

shutdown feature reduces power dissipation on unused DACs.

0

512

1024

1536

2048

2560

3072

3584

4096

CODE (Decimal)

Figure 2. AD7398 DNL vs. Code (T_A= 25°C)

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

AD7398/AD7399

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AD7398 12-Bit Voltage Output DAC ........................................ 3

AD7399 10-Bit Voltage Output DAC ........................................ 4

Timing Diagrams.......................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration And Function Descriptions............................ 7

Input Registers .................................................................................. 8

AD7398 Serial Input Register Data Format.............................. 8

AD7399 Serial Input Register Data Format.............................. 8

Terminology ...................................................................................... 9

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 14

DAC Operation .......................................................................... 14

Operation with V_REFEqual to the Supply................................ 15

Power Supply Sequencing ......................................................... 15

Programmable Power Shutdown.............................................. 15

Worst Case Accuracy................................................................. 15

Serial Data Interface................................................................... 15

Power-On Reset.......................................................................... 16

Microprocessor Interfacing....................................................... 16

Applications Information.............................................................. 18

Staircase Windows Comparator............................................... 18

Programmable DAC Reference Voltage .................................. 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 21

REVISION HISTORY

1/11—Rev. B to Rev. C

Added Automotive Model and Information.............. Throughout

12/09—Rev. A to Rev. B

Changes to Ordering Guide .......................................................... 21

6/06—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Ordering Guide .......................................................... 21

11/00—Revision 0: Initial Version

Rev. C | Page 2 of 24

AD7398/AD7399

SPECIFICATIONS

AD7398 12-BIT VOLTAGE OUTPUT DAC

V_DD= 5 V, V _SS= 0 V; or V_DD= + 5 V, V _SS= −5 V, V _REF= +2.5 V, −40°C < T_A< +125°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Condition

3 V to 5 V 10%

5 V 10%

Unit

STATIC PERFORMANCE

Resolution¹

Relative Accuracy²

Differential Nonlinearity²

Zero-Scale Error

Full-Scale Voltage Error

Full-Scale Tempco³

REFERENCE INPUT

V_REFIN Range⁴

N

12

1.5

1

7

2.5

1.5

12

1.5

1

2.5

1.5

Bits

INL

DNL

V_ZSE

V_FSE

TCV_FS

LSB max

mV max

ppm/°C typ

Monotonic

Data = 000_H

Data = FFF_H

V_REF

R_REF

C_REF

0/V_DD

35

5

V_SS/V_DD

35

5

V min/max

kΩ typ⁶

pF typ

Input Resistance⁵

Input Capacitance³

ANALOG OUTPUT

Output Voltage Range

Output Current

Data = 555_H, worst case

V_OUT

I_OUT

C_L

0 to V_REF

5

200

0 to V_REF

5

400

V

Data = 800_H, ΔV_OUT= 4 LSBs

No oscillation

mA typ

pF max

Capacitive Load³

LOGIC INPUTS

Logic Input Low Voltage

V_IL

V_DD= 3 V

V_DD= 5 V

CLK only

0.5

0.8

80% V_DD

2.1 to 2.4

1

10

V max

V min

μA max

pF max

0.8

4.0

2.4

1

Logic Input High Voltage

V_IH

Input Leakage Current

Input Capacitance³

INTERFACE TIMING^{3, 7}

Clock Frequency

Clock Width High

Clock Width Low

CS to Clock Setup

Clock to CS Hold

Load DAC Pulse Width

Data Setup

I_IL

C_IL

10

f_CLK

t_CH

t_CL

t_CSS

t_CSH

t_LDAC

t_DS

t_DH

t_LDS

t_LDH

11

45

10

20

45

15

10

0

16.6

30

5

MHz max

ns min

15

30

10

5

Data Hold

Load Setup to CS

Load Hold to CS

0

20

15

AC CHARACTERISTICS

Output Slew Rate

Settling Time⁸

SR

t_S

Data = 000_Hto FFF_Hto 000_H

To 0.1% of full scale

2

6

2

6

V/μs typ

μs typ

Shutdown Recovery

DAC Glitch

Digital Feedthrough

Feedthrough

t_SDR

Q

Q_DF

V_OUT/V_REF

6

μs typ

Code 7FF_Hto 800_Hto 7FF_H

150

15

−63

150

15

−63

nVs typ

dB typ

V_REF= 1.5 V_DC1 V p-p, data = 000_H,

f = 100 kHz

Rev. C | Page 3 of 24

AD7398/AD7399

Parameter

Symbol

Condition

3 V to 5 V 10%

5 V 10%

Unit

SUPPLY CHARACTERISTICS

Shutdown Supply Current

Positive Supply Current

I_{DD_SD}

I_DD

I_SS

P_DISS

PSS

No load

30/60

1.5/2.8

1.5/2.6

1.5/2.5

5

30/60

1.6/3

1.6/2.8

1.6/2.7

16

μA typ/max

mA typ/max

mW typ

V_IL= 0 V, no load, −40°C < T < +125°C

V_IL= 0 V, no load, −40°C < T_A< +85°C

V_IL= 0 V, no load

ΔV_DD= 5%

A

Negative Supply Current

Power Dissipation

Power Supply Sensitivity

0.006

%/% max

¹One LSB = V_REF/4096 V for the 12-bit AD7398.

²The first eight codes (000_Hto 007_H) are excluded from the linearity error measurement in single-supply operation.

³These parameters are guaranteed by design and not subject to production testing.

⁴When V_REFis connected to either the V_DDor the V_SSpower supply, the corresponding V_OUTvoltage programs between ground and the supply voltage minus the offset

voltage of the output buffer, which is the same as the V_ZSEerror specification. See additional information in the Theory of Operation section.

⁵Input resistance is code dependent.

⁶Typicals represent average readings measured at 25°C.

⁷All input control signals are specified with t_R= t_F= 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

⁸The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.

AD7399 10-BIT VOLTAGE OUTPUT DAC

V_DD= 5 V, V _SS= 0 V; or V_DD= + 5 V, V _SS= –5 V; V_REF= +2.5 V, −40°C < T_A< +125°C, unless otherwise noted.

Table 2.

Parameter

Symbol

Condition

3 V to 5 V 10%

5 V 10%

10

1

4

15

1.5

Unit

STATIC PERFORMANCE

Resolution¹

Relative Accuracy²

Differential Nonlinearity²

Zero-Scale Error

Full-Scale Voltage Error

Full-Scale Tempco³

REFERENCE INPUT

V_REFIN Range⁴

N

10

1

7

15

1.5

Bits

INL

DNL

V_ZSE

V_FSE

TCV_FS

LSB max

mV max

ppm/°C typ

Monotonic

Data = 000_H

Data = 3FF_H

V_REF

R_REF

C_REF

0/V_DD

40

5

V_SS/V_DD

40

5

V min/max

kΩ typ⁶

pF typ

Input Resistance⁵

Input Capacitance³

ANALOG OUTPUT

Output Voltage Range

Output Current

Data = 155_H, worst case

V_OUT

I_OUT

C_L

0 to V_REF

5

200

0 to V_REF

5

400

V

Data = 200_H, ΔV_OUT= 1 LSB

No oscillation

mA typ

pF max

Capacitive Load³

LOGIC INPUTS

Logic Input Low Voltage

V_IL

V_DD= 3 V

V_DD= 5 V

CLK only

0.5

0.8

80% V_DD

2.1 to 2.4

1

10

V max

V min

μA max

pF max

0.8

4.0

2.4

1

Logic Input High Voltage

V_IH

Input Leakage Current

Input Capacitance³

INTERFACE TIMING^{3, 7}

Clock Frequency

Clock Width High

Clock Width Low

CS to Clock Setup

Clock to CS Hold

Load DAC Pulse Width

Data Setup

I_IL

C_IL

10

f_CLK

t_CH

t_CL

t_CSS

t_CSH

t_LDAC

t_DS

t_DH

t_LDS

t_LDH

11

45

10

20

45

15

10

0

16.6

30

5

MHz max

ns min

15

30

10

5

Data Hold

Load Setup to CS

Load Hold to CS

0

20

15

Rev. C | Page 4 of 24

AD7398/AD7399

Parameter

Symbol

Condition

3 V to 5 V 10%

5 V 10%

Unit

AC CHARACTERISTICS

Output Slew Rate

Settling Time⁸

SR

t_S

Data = 000_Hto 3FF_Hto 000_H

To 0.1% of full scale

2

6

2

6

V/μs typ

μs typ

Shutdown Recovery

DAC Glitch

Digital Feedthrough

Feedthrough

t_SDR

Q

Q_DF

V_OUT/V_REF

6

μs typ

Code 1FF_Hto 200_Hto 1FF_H

150

15

−63

150

15

−63

nVs typ

dB typ

V_REF= 1.5 V_DC+ 1 V p-p,

data = 000_H, f = 100 kHz

SUPPLY CHARACTERISTICS

Shutdown Supply Current

Positive Supply Current

I_{DD_SD}

I_DD

No load

30/60

1.5/2.8

30/60

1.6/3

μA typ/max

mA typ/max

V_IL= 0 V, no load,

−40°C < T_A< +125°C

V_IL= 0 V, no load,

−40°C < T_A< +85°C

V_IL= 0 V, no load

ΔV_DD= 5%

I_DD

1.5/2.6

1.6/2.8

mA typ/max

Negative Supply Current

Power Dissipation

Power Supply Sensitivity

I_SS

P_DISS

PSS

1.5/2.5

5

0.006

1.6/2.7

16

0.006

mA typ/max

mW typ

%/% max

¹One LSB = V_REF/1024 V for the 10-bit AD7399.

²The first two codes (000_Hand 001_H) are excluded from the linearity error measurement in single-supply operation.

³These parameters are guaranteed by design and not subject to production testing.

⁴When V_REFis connected to either the V_DDor the V_SSpower supply, the corresponding V_OUTvoltage programs between ground and the supply voltage minus the offset

voltage of the output buffer, which is the same as the V_ZSEerror specification. See additional discussion in the Theory of Operation section.

⁵Input resistance is code dependent.

⁶Typicals represent average readings measured at 25°C.

⁷All input control signals are specified with t_R= t_F= 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

⁸The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.

TIMING DIAGRAMS

SDI

SA

SD

A1

A0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

IN

REG

LD

CLK

t_DS

t_DH

t_CH

t_CL

t_CSH

CS

t_CSS

t_LDH

LDAC

t_LDS

t_LDAC

Figure 3. AD7398 Timing Diagram (AD7399 with SDI = 14 Bits Only)

CLK

t_CH

t_CL

1/f_CLK

t_LDH

t_LDS

LDAC

CS

t_LDAC

t_CSS

t_CSH

t_CSS

Figure 4. Continuous Clock Timing Diagram

Rev. C | Page 5 of 24

AD7398/AD7399

ABSOLUTE MAXIMUM RATINGS

Table 3.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

V_DDto GND

V_SSto GND

V_REFto GND

−0.3 V, +7 V

+0.3 V, −7 V

V_SS, V_DD

Logic Inputs to GND

V_OUTto GND

I_OUTShort Circuit to GND

Thermal Resistance (θ_JA)

−0.3 V, +8 V

V_SS− 0.3 V, V_DD+ 0.3 V

50 mA

ESD CAUTION

16-Lead SOIC_W Package

(RW-16)

16-Lead TSSOP Package

(RU-16)

158°C/W

180°C/W

150°C

Maximum Junction

Temperature (T_JMax)

Package Power Dissipation

Operating Temperature Range

Storage Temperature Range

(T_JMax – T_A)/θ_JA

−40°C to +125°C

−65°C to +150°C

Reflow Soldering Peak

Temperature

SnPb

Pb-Free

240°C

260°C

Rev. C | Page 6 of 24

AD7398/AD7399

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

B

A

V

C

D

OUT

DD

OUT

AD7398/

AD7399

TOP VIEW

(Not to Scale)

V

SS

V

A

B

C

D

REF

GND

SDI

CLK

CS

LDAC

RS

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

2

3

4

5

6

7

V_OUT

V_SS

B

DAC B Voltage Output.

DAC A Voltage Output.

A

Negative Power Supply Input. Specified range of operation 0 V to −5.5 V.

V_REF

A

DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to V_DDpin or V_SSpin.

DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to V_DDpin or V_SSpin.

Ground Pin.

B

GND

LDAC

Load DAC Register Strobe. Level sensitive active low. Transfers all input register data to DAC registers.

Asynchronous active low input. See Table 5 for operation.

8

9

RS

CS

Resets Input and DAC Registers to All Zero Codes. Shift register contents unchanged.

Chip Select. Active low input. Disables shift register loading when high. Transfers serial register data to the input

register when CS returns high. Does not effect LDAC operation.

10

11

12

13

14

15

16

CLK

SDI

Schmitt Triggered Clock Input. Positive edge clocks data into shift register.

Serial Data Input. Input data loads directly into the shift register.

DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to V_DDpin or V_SSpin.

DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to V_DDpin or V_SSpin.

Positive Power Supply Input. Specified range of operation 3 V to 5 V 10%.

DAC D Voltage Output.

V_REF

V_DD

D

C

V_OUT

D

C

DAC C Voltage Output.

Table 5. Control Logic Truth Table

CS

CLK

LDAC

Serial Shift Register Function

Input Register Function

DAC Register

H

L

X

L

H

L

No effect

Shift register data advanced one bit

No effect

Latched

No effect

Transparent

Latched

↑+

H

L/H

L

Updated with shift register contents

↑+

H

X

Latched

↑+

NOTES

1. ↑+ = Positive logic transition; ↓– = Negative logic transition; X = Don’t Care.

2. At power-on, both the input register and the DAC register are loaded with all zeros.

3. During power shutdown, reprogramming of any internal registers can take place, but the output amplifiers do not produce the new values until the part is taken out

of shutdown mode.

LDAC

4. The

input is a level-sensitive input that controls the four DAC registers.

Rev. C | Page 7 of 24

AD7398/AD7399

INPUT REGISTERS

AD7398 SERIAL INPUT REGISTER DATA FORMAT

Data is loaded in the MSB first format.

MSB

LSB

B0

B15

SA

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

SD

A1

A0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NOTE

Bit Position B14 and Bit Position B15 are the SD and SA power shutdown control bits. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set

to Logic 1, the address decoded by Bit B12 and Bit B13 (A0 and A1) determine the DAC channel that is placed in the power shutdown state.

AD7399 SERIAL INPUT REGISTER DATA FORMAT

Data is loaded in the MSB first format.

MSB

B13

SA

LSB

B0

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

SD

A1

A0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NOTE

Bit Position B12 and Bit Position B13 are the SD and SA power shutdown control bits. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set

to Logic 1, the address decoded by Bit B10 and Bit B11 (A0 and A1) determine the DAC channel that is placed in the power shutdown state.

Table 6. AD7398/AD7399 Address Decode Control

SA

SD

X

1

A1

X

0

A0

X

0

DAC Channel Affected

All DACs shutdown

DAC A shutdown

1

0

1

0

1

DAC B shutdown

0

1

0

DAC C shutdown

0

1

DAC D shutdown

0

1

0

1

0

1

DAC A input register decoded

DAC B input register decoded

DAC C input register decoded

DAC D input register decoded

Rev. C | Page 8 of 24

AD7398/AD7399

TERMINOLOGY

Relative Accuracy (INL)

DAC Glitch Impulse (Q)

For the DAC, relative accuracy or integral nonlinearity (INL) is

a measure of the maximum deviation, in LSBs, from a straight

line passing through the endpoints of the DAC transfer function.

Figure 6 illustrates a typical INL vs. code plot.

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV −s and

is measured when the digital input code is changed by 1 LSB at the

major carry transition (midscale transition). A plot of the glitch

impulse is shown in Figure 15.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of 1 LSB maximum

ensures monotonicity. Figure 8 illustrates a typical DNL vs.

code plot.

Digital Feedthrough (Q_DF)

Digital feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital inputs of the

CS

DAC, but is measured when the DAC output is not updated.

is held high while the CLK and SDI signals are toggled. It is

Zero-Scale Error (V_ZSE

)

specified in nV − s, and is measured with a full-scale code change

on the data bus, such as from all 0s to all 1s and vice versa. A

typical plot of digital feedthrough is shown in Figure 16.

Zero-scale error is a measure of the output voltage error from

zero voltage when zero code is loaded to the DAC register.

Full-Scale Error (V_FSE

)

Power Supply Sensitivity (PSS)

Full-scale error is a measure of the output voltage error from

full-scale voltage when full-scale code is loaded to the DAC

register.

This specification indicates how the output of the DAC is

affected by changes in the power supply voltage. Power supply

sensitivity is quoted in terms of % change in output per % change

in V_DDfor full-scale output of the DAC. V_DDis varied by 10%.

Full-Scale Temperature Coefficient (TC_VFS

)

This is a measure of the change in full-scale error with a change

in temperature. It is expressed in ppm/°C or mV/°C.

Reference Feedthrough (V_OUT/V_REF

)

This is a measure of the feedthrough from the V_REFinput to the

DAC output when the DAC is loaded with all 0s. A 100 kHz,

1 V p-p is applied to V_REF. Reference feedthrough is expressed in

dB or mV p-p.

Rev. C | Page 9 of 24

AD7398/AD7399

TYPICAL PERFORMANCE CHARACTERISTICS

1.50

0.5

0.4

AD7398

V

= +5V

= –5V

V

= +5V

= –5V

DD

1.25

1.00

0.75

0.50

0.25

0

SS

= +2.5V

REF

0.3

T

= 25°C

T = 25°C

A

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.25

–0.50

–0.75

–1.00

0

512

1024

1536

2048

2560

3072

3584

4096

0

512

1024

1536

2048

2560

3072

3584

4096

CODE (Decimal)

Figure 6. AD7398 INL vs. Code (T_A= 25°C)

Figure 8. AD7398 DNL vs. Code (T_A= 25 °C)

0.50

0.25

0

0.50

0.25

0

T

V

= 25°C, V = +5V,

DD

DAC D

A

= –5V, V = +2.5V

SS

REF

–0.25

–0.50

–0.25

–0.50

T

V

= 25°C, V = +5V,

DD

A

= –5V, V

= +2.5V

SS

REF

0

128

256

384

512

640

768

896

1024

0

128

256

384

512

640

768

896

1024

CODE (Decimal)

0.50

0.25

0

0.50

0.25

0

DAC C

–0.25

–0.50

–0.25

–0.50

T

= 25°C, V = +5V,

DD

T

V

= 25°C, V = +5V,

A

A DD

V

= –5V, V

= +2.5V

= –5V, V

128

= +2.5V

SS

REF

SS

REF

0

128

256

384

512

640

896

1024

0

256

384

512

640

896

1024

CODE (Decimal)

0.50

0.25

0

0.50

0.25

0

DAC B

–0.25

–0.50

–0.25

–0.50

T

= 25°C, V = +5V,

DD

T

V

= 25°C, V = +5V,

A

A DD

V

= –5V, V

= +2.5V

= –5V, V

128

= +2.5V

SS

REF

SS

REF

128

256

384

512

640

896

1024

256

384

512

640

896

1024

CODE (Decimal)

0.50

0.25

0

0.50

0.25

0

DAC A

–0.25

–0.50

–0.25

–0.50

T

= 25°C, V = +5V,

DD

T

V

= 25°C, V = +5V,

A

A DD

V

= –5V, V

= +2.5V

= –5V, V

128

= +2.5V

SS

REF

SS

REF

128

256

384

512

640

896

1024

256

384

512

640

896

1024

CODE (Decimal)

Figure 7. AD7399 INL vs. Code (T_A= 25°C)

Figure 9. AD7399 DNL vs. Code (T_A= 25 °C)

Rev. C | Page 10 of 24

AD7398/AD7399

1.00

0.75

0.50

0.25

0

10

8

AD7398/AD7399

AD7398

= 25°C

T

= 25°C

T

A

SINKING CURRENT INTO V

OUT

V

= +5V

= –5V

DD

SS

V

= +3V, V = 0V

SS

DD

6

DNL

V

= +5V, V = –5V

SS

DD

4

2

INL

0

V

= +5V, V = 0V

SS

DD

FSE

–2

–4

–6

–8

–10

–0.25

–0.50

–0.75

–1.00

SOURCING CURRENT FROM V

OUT

V

= +5V, V = –5V

DD

SS

= +5V, V = 0V

SS

= +3V, V

=

0V

SS

–5

–4

–3

–2

–1

0

1

2

3

4

5

–20

–15

–5

0

5

10

15

(mA)

20

REFERENCE VOLTAGE (V)

SOURCE OR SINK CURRENT FROM V

OUT

Figure 10. AD7398 INL, DNL, FSE vs. Reference Voltage

Figure 13. ΔV_OUTvs. Load Current

100

90

80

70

60

50

40

30

20

10

0

25

20

15

10

5

AD7398

SAMPLE SIZE = 125

–40°C TO +125°C

V

= +5V

= –5V

DD

SS

= +2.5V

REF

T

= 25°C

A

0

512

1024

1536

2048

2560

3072

3584

4096

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6

CODE (Decimal)

FULL-SCALE ERROR TEMPCO (ppm/°C)

Figure 11. AD7398 Reference Input Current vs. Code

Figure 14. AD7398 Full-Scale Error Tempco

1000

100

10

AD7398

V

= +5V

= –5V

DD

SS

T

= 25°C

A

100

90

CS (5V/DIV)

V

(0.2V/DIV)

10

OUT

0%

0

512

1024

1536

2048

2560

3072

3584

4096

CODE (Decimal)

TIME (2µs/DIV)

Figure 12. AD7398 Reference Input Resistance vs. Code

Figure 15. AD7398 Midscale Glitch

Rev. C | Page 11 of 24

AD7398/AD7399

0

0xFFF

0x800

0x400

–12

–24

–36

–48

–60

–72

–84

–96

–108

0x200

0x100

0x080

0x040

0x020

0x010

0x008

0x004

0x002

0x001

100

90

V

(50mV/DIV)

OUT

CLOCK (5V/DIV)

10

0x000

V

= +5V

= –5V

DD

0%

SS

= +100mV rms

REF

T

= 25°C

A

100

1k

10k

FREQUENCY (Hz)

100k 1M

TIME (100ns/DIV)

Figure 19. AD7398 Multiplying Gain vs. Frequency

Figure 16. AD7398 Digital Feedthrough

5

V

= +5V, V = –5V, V = +5V

SS REF

DD

T

= 25°C

A

1. V = +5V, V = –5V, CODE = 0x000, 0xFFF

3. V = +5V, V = –5V, CODE = 0x555

DD SS

2

4

DLY 54µs

3. V = +5V, V = 0V, CODE = 0x000, 0xFFF

4

3

2

1

0

DD SS

4. V = +5V, V = 0V, CODE = 0x555

DD SS

100

90

V

(2V/DIV)

5. V = +3V, V = 0V, CODE = 0x000, 0xFFF

6. V = +3V, V = 0V, CODE = 0x555

DD SS

OUT

DD SS

1

3

6

5

10

0%

CS (5V/DIV)

5V

2v

5µs

1k

10k

100k

1M

10M

100M

CLOCK FREQUENCY (Hz)

TIME (5µs/DIV)

Figure 17. AD7398 Large Signal Settling Time

Figure 20. AD7398 Supply Current vs. Clock Frequency

V

= +5V, V = –5V, V

SS REF

= +5V

2.00

DD

AD7398

±5V

T

= 25°C

A

A2 0.8V

DLY 67µs

V

= +2.5V

REF

DUAL SUPPLY

1.75

1.50

1.25

1.00

100

90

V

(2V/DIV)

OUT

±3V

SINGLE SUPPLY

10

0%

5V

2V

2µs

2

3

4

5

6

POWER SUPPLY VOLTAGE (V)

TIME (2µs/DIV)

Figure 18. AD7398 Shutdown Recovery

Figure 21. AD7398 Supply Current vs. Supply Voltage

Rev. C | Page 12 of 24

AD7398/AD7399

3.0

2.5

2.0

1.5

1.0

0.5

0

1.00

0.75

0.50

0.25

0

AD7398/AD7399

AD7398

SAMPLE SIZE = 135

V

= +5V

= –5V

DD

SS

V

= 2.5V

REF

CODE = 0xFFF

CODE = 0x000

–50

0

50

100

150

0

100

200

300

400

500

600

TEMPERATURE (°C)

HOURS OF OPERATION AT 150°C

Figure 22. Supply Current vs. Temperature

Figure 24. AD7398 Long-Term Drift

36

35

34

33

32

31

AD7398/AD7399

V

= +5V

= –5V

DD

SS

–60 –40 –20

0

20

40

60

80

100 120 140

TEMPERATURE (°C)

Figure 23. Shutdown Current vs. Temperature

Rev. C | Page 13 of 24

AD7398/AD7399

THEORY OF OPERATION

V

A

V

B

V

C

V

D

REF

DD

REF

AD7398/AD7399

INPUT

REGISTER

DAC

REGISTER

DAC A

V

A

CS

OUT

CLK

ADDRESS

DECODE

4

SDI

INPUT

DAC

DAC B

DAC C

DAC D

V

B

C

D

OUT

REGISTER

SERIAL

REGISTER

INPUT

REGISTER

DAC

REGISTER

12/10

INPUT

REGISTER

DAC

REGISTER

POWER

ON RESET

RS

GND

LDAC

V

SS

Figure 25. Simplified Block Diagram

The AD7398/AD7399 contain four 12-bit and 10-bit,

The nominal DAC output voltage is determined by the

externally applied V_REFand the digital data (D) as

respectively, voltage output, digital-to-analog converters. Each

DAC has its own independent multiplying reference input. Both

the AD7398 and AD7399 use a 3-wire, SPI-compatible serial

V_OUT= V_REF× D/4096 (For AD7398)

V_OUT= V_REF× D/1024 (For AD7399)

where:

(1)

(2)

RS

data interface, with an asynchronous

pin for zero-scale reset.

strobe enables four-channel simultaneous

updates for hardware-synchronized output voltage changes.

LDAC

In addition, an

V

DD

D is the 12-bit or 10-bit decimal equivalent of the data word.

V

_REFis the externally applied reference voltage.

AD7398/AD7399

In order to maintain good analog performance, the user should

bypass power supplies with 0.01 μF ceramic capacitors (mount

them close to the supply pins) and 1 μF to 10 μF tantalum

capacitors in parallel. In addition, clean power supplies with low

ripple voltage capability should be used. Switching power supplies

can be used for this application, but beware of its higher ripple

voltage and PSS frequency-dependent characteristics. It is also

best to supply power to the AD7398/AD7399 from the system’s

analog supply voltages. Do not use the digital 5 V supply.

V

REF

V

A

OUT

R

GND

V

SS

Figure 26. Simplified DAC Channel

The reference input resistance is code dependent, exhibiting

worst case 35 kΩ for AD7398 when the DAC is loaded with

alternating codes 010101010101. Similarly, the reference input

resistance is 40 kΩ for AD7399 when the DAC is loaded with

0101010101.

DAC OPERATION

The internal R-2R ladder of the AD7398/AD7399 operates in

the voltage switching mode, maintaining an output voltage that

is the same polarity as the input reference voltage. A proprietary

scaling technique is used to attenuate the input reference voltage in

the DAC. The output buffer amplifies the internal DAC output to

achieve a V_REFto V_OUTgain of unity.

Rev. C | Page 14 of 24

AD7398/AD7399

SERIAL DATA INTERFACE

OPERATION WITH V_REFEQUAL TO THE SUPPLY

CS

The AD7398/AD7399 uses a 3-wire ( , SDI, CLK) SPI-

The AD7398/AD7399 are designed to approach the full output

voltage swing from ground to V_DDor V_SS. The maximum output

swing is achieved when the corresponding V_REFinput pin is tied

to the same power supply. This power supply should be low noise

and low ripple, preferably operated by a suitable reference voltage

source such as ADR292 or REF02. The output swing is limited

by the internal buffer offset voltage and the output drive current

capability of the output stage. Users should at least budget the V_ZSE

offset voltage as the closest the output voltage can get to either

supply voltage under a no load condition. Under a loaded output,

degrade the headroom by a factor of 2 mV per 1 mA of load

current. Also note that the internal op amp has an offset voltage

so that the first eight codes of AD7398 may not respond at the

supply voltage or at ground until the internal DAC voltage

exceeds the offset voltage of the output buffers. Similarly, the first

two codes of AD7399 should not be used.

compatible serial data interface. Serial data of the AD7398 and

AD7399 is clocked into the serial input register in a 16-bit and 14-

bit data-word format, respectively. MSBs are loaded first. The Input

Registers section defines the 16 data-word bits for AD7398 and the

14 data-word bits for the AD7399. Data is placed on the SDI pin,

and clocked into the register on the positive clock edge of CLK,

subject to the data setup and data hold time requirements specified

in the Specifications section. Data can only be clocked in while the

chip select pin is active low. For the AD7398, only the last 16

bits clocked into the serial register are interrogated when the

returns to the logic high state, and extra data bits are ignored. For

the AD7399, only the last 14 bits clocked into the serial register are

interrogated when the pin returns to the logic high state.

CS

Because most microcontrollers output serial data is in eight-bit

bytes, two right-justified data bytes can be written to the AD7398

CS

and AD7399. Keeping the line low between the first and second

POWER SUPPLY SEQUENCING

byte transfers results in a successful serial register update.

V_DD/V_SSof AD7398/AD7399 should be powered from the system

analog supplies. The external reference input can be supplied from

the same supply to avoid a possible latch-up when the reference is

powered on prior to V_DD/V_SS, or powered off subsequent to

V_DD/V_SS. If V_DD/V_SSand V_REFhave separate power sources, ensure

the power-up sequence is GND, V_DD, V_SS, V_REF/digital input/digital

output. The reverse sequence applies to the power-down sequence.

The order of V_REFand digital input/digital output is not important.

In addition, V_REFpins of the unused DACs should be connected to

GND or some other power sources to ensure a similar power-

up/power-down sequence.

Once the data is properly aligned in the shift register, the positive

CS

edge of the initiates the transfer of new data to the target DAC

register, determined by the decoding of Address Bit A1 and

Address Bit A0. For the AD7398, Table 5, Table 6, the Input

Registers section, Figure 3, and Figure 4 define the characteristics

of the serial interface. For the AD7399, Table 5, Table 6, the Input

Registers section, and Figure 4 (with a 14-bit exception) define the

characteristics of the serial interface. Figure 27 and Figure 28 show

the equivalent logic interface for the key digital control pins for

AD7398 and AD7399.

RS

provides hardware control reset to zero-

PROGRAMMABLE POWER SHUTDOWN

An asynchronous

code state over the preset function and DAC register loading. If

The two MSBs of the serial input register, SA and SD, are used

to program various shutdown modes. If SA is set to Logic 1, all

DACs are placed in shutdown mode. If SA = 0 and SD = 1, a

corresponding DAC is shutdown addressed by Bit A0 and

Bit A1 (see the Input Registers section).

RS

this function is not needed, the

pin can be tied to logic high.

TO INPUT REGISTER

A

B

C

D

CS

ADDRESS

DECODER

WORST CASE ACCURACY

EN

SHIFT

Assuming a perfect reference, the worst-case output voltage can

be calculated from the following equation:

REGISTER

CLK

SDI

D

V







V

 V



 V

ZSE

 INL

(3)

OUT

REF FSE

Figure 27. Equivalent Logic Interface

N

2

where:

D = decimal code loaded to DAC ranges 0 ≤ D ≤ 2^N–1.

N = number of bits.

V

_REF= applied reference voltage.

_FSE= full-scale error in volts.

_ZSE= zero-scale error in volts.

INL = integral nonlinearity in volts. INL is 0 at full scale or zero

scale.

Rev. C | Page 15 of 24

AD7398/AD7399

68HC11/68L11 to AD7398/AD7399 Interface

POWER-ON RESET

Figure 30 shows a serial interface between the AD7398/AD7399

and the 68HC11/68L11 microcontroller. SCK of the 68HC11/

68L11 drives the CLK of the DAC, and the MOSI output drives the

When the V_DDpower supply is turned on, an internal reset

strobe forces all the input and DAC registers to the zero-code

state. The V_DDpower supply should have a smooth positive

ramp without drooping in order to have consistent results,

especially in the region of V_DD= 1.5 V to 2.2 V. The V_SSsupply

has no effect on the power-on reset performance. The DAC

register data stays at zero until a valid serial register data load

takes place.

CS

serial data lines SDI. signal is driven from one of the port lines.

The 68HC11/68L11 are configured for master mode; MSTR = 1,

CPOL = 0, and CPHA = 0. Data appearing on the MOSI output is

valid on the rising edge of SCK.

68HC11/

68L11¹

AD7398/

AD7399

ESD Protection Circuits

PC6

LDAC

CS

All logic input pins contain back-biased ESD protection Zeners

connected to ground (GND) and V_DDas shown in Figure 28.

PC7

MOS1

SDI

SCK

CLK

V

DD

1

DIGITAL INPUTS

ADDITIONAL PINS OMITTED FOR CLARITY.

5kΩ

Figure 30. 68HC11/68L11 to AD7398/AD7399 Interface

MICROWIRE™ to AD7398/AD7399 Interface

GND

Figure 31 shows an interface between the AD7398/AD7399 and

any MICROWIRE-compatible device. Serial data is shifted out

on the falling edge of the serial clock and into the AD7398/

AD7399 on the rising edge of the serial clock. No glue logic is

required as the DAC clocks data into the input shift register on

the rising edge.

Figure 28. Equivalent ESD Protection Circuits

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD7398/AD7399 is via a

serial bus that uses standard protocol compatible with DSP

processors and microcontrollers. The communications channel

requires a 3-wire interface consisting of a clock signal, a data

signal, and a synchronization signal. The AD7398/AD7399

require a 16-bit/14-bit data word with data valid on the rising edge

of CLK. The DAC update can be done automatically when all the

MICROWIRE¹

AD7398/

AD7399

CS

SO

CS

SDI

LDAC

data is clocked in, or it can be done under control of

.

SCK

CLK

ADSP-2101 to AD7398/AD7399 Interface

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 29 shows a serial interface between the AD7398/AD7399

and the ADSP-2101. The ADSP-2101 is set to operate in the serial

port (SPORT) transmit alternate framing mode. The ADSP-2101 is

programmed through the SPORT control register and should be

configured as follows: Internal clock operation, active low framing,

16-bit-word length. For the AD7398, transmission is initiated by

writing a word to the Tx register after the SPORT has been

enabled. For the AD7399, the first two bits are don’t care as the

AD7399 keeps the last 14 bits. Similarly, transmission is initiated

by writing a word to the Tx register after the SPORT has been

enabled. Because of the edge-triggered difference, an inverter is

required at the SCLKs between the DSP and the DAC.

Figure 31. MICROWIRE to AD7398/AD7399 Interface

80C51/80L51 to AD7398/AD7399 Interface

A serial interface between the AD7398/AD7399 and the 80C51/

80L51 microcontroller is shown in Figure 32. TxD of the micro-

controller drives the CLK of the AD7398/AD7399, and RxD drives

the serial data line of the DAC. P3.3 is a bit-programmable pin on

CS

the serial port that is used to drive

.

80C51/

80L51¹

AD7398/

AD7399

P3.4

P3.3

RxD

LDAC

CS

SDI

ADSP-2101¹

AD7398/

AD7399

TxD

CLK

FO

TFS

DT

LDAC

CS

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 32. 80C51/80L51 to AD7398/AD7399 Interface

SDI

SCLK

CLK

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 29. ADSP-2101 to AD7398/AD7399 Interface

Rev. C | Page 16 of 24

AD7398/AD7399

Note that the 80C51/80L51 provide the LSB first, although the

AD7398/AD7399 expect the MSB of the 16-bit/14-bit word

first. Care should be taken to ensure the transmit routine takes

this into account. This can usually be done with software by

shifting out and accumulating the bits in the correct order

before inputting to the DAC. In addition, 80C51 outputs two

byte words/16 bits of data. Thus for AD7399, the first two bits,

after rearrangement, should be don’t care as they are dropped

from the 14-bit word of the AD7399.

When data is to be transmitted to the DAC, P3.3 is taken low.

Data on RxD is valid on the falling edge of TxD, so the clock

must be inverted as the DAC clocks data into the input shift

register on the rising edge of the serial clock. The 80C51/80L51

transmit their data in 8-bit bytes with only eight falling clock

edges occurring in the transmit cycle. As the AD7399 requires a

14-bit word, P3.3 (or any one of the other programmable bits) is the

CS

input signal to the DAC; therefore P3.3 should be brought low

at the beginning of the 16-bit write cycle 2 × 8 bit-words, and held

low until the 16-bit 2 × 8 cycle is completed. After that, P3.3 is

brought high again and the new data loads to the DAC. Again, the

LDAC

first two bits, after rearranging, should be don’t care.

on the

AD7398/AD7399 can also be controlled by the 80C51/80L51 serial

port output by using another bit-programmable pin, P3.4.

Rev. C | Page 17 of 24

AD7398/AD7399

APPLICATIONS INFORMATION

STAIRCASE WINDOWS COMPARATOR

V

TEST

V+

AD8564

V

REF

Many applications need to determine whether voltage levels are

within predetermined limits. Some requirements are for

nonoverlapping windows and others for overlapping windows.

Both circuit configurations are shown in Figure 33 and

Figure 34, respectively.

10kΩ

+

–

WINDOW 1

WINDOW 2

V

DD

+

–

V

A

B

V

A

B

REF

OUT

V+

10kΩ

+

–

REF

OUT

AD7398/

AD7399

V

TEST

+

–

V+

AD8564

V

C

V

C

REF

OUT

10kΩ

+

–

WINDOW 1

WINDOW 2

1/2

AD8564

V+

V

DD

+

–

10kΩ

D

V

D

+

–

REF

OUT

V+

WINDOW 3

GND

10kΩ

V

A

V

A

+

–

REF

OUT

+

–

+

–

AD7398/

AD7399

Figure 35. Overlapping Windows Comparator

V+

AD8564

V

REF

10kΩ

V

B

V

B

C

+

–

REF

OUT

WINDOW 3

WINDOW 4

WINDOW 1

V

B

A

OUT

+

–

WINDOW 2

V+

V

D

C

OUT

10kΩ

C

V

+

–

WINDOW 3

REF

OUT

GND

+

–

Figure 36. Overlapping Windows Range

The nonoverlapping circuit employs one AD7398/AD7399 and

ten comparators to achieve five voltage windows. These windows

range between V_REFand analog ground as shown in Figure 34.

Similarly, the overlapping circuit employs six comparators to

achieve three overlapping windows (see Figure 36).

1/2

V+

AD8564

10kΩ

V

D

V

D

+

–

REF

OUT

WINDOW 5

GND

+

–

Figure 33. Nonoverlapping Windows Comparator

V

REF

WINDOW 1

WINDOW 2

WINDOW 3

V

A

B

OUT

V

C

OUT

WINDOW 4

WINDOW 5

V

D

OUT

GND

Figure 34. Nonoverlapping Windows Range

Rev. C | Page 18 of 24

AD7398/AD7399

Table 7. V_REFXvs. R1 and R2

PROGRAMMABLE DAC REFERENCE VOLTAGE

R1, R2

Digital Code

V_REFX

2 V_REF

1.3 V_REF

V_REF

4 V_REF

1.6 V_REF

V_REF

With the flexibility of the AD7398/AD7399, one of the internal

DACs can be used to control a common programmable V_REFX

for the remainder of the DACs.

R1 = R2

R1 = 3R2

0000 0000 0000

1000 0000 0000

1111 1111 1111

0000 0000 0000

1000 0000 0000

1111 1111 1111

The circuit configuration is shown in Figure 37. The relationship of

V_REFXto V_REFis dependent upon the digital code and the ratio of

R1 and R2, and is given by

R2

R1

D

R2

The accuracy of V_REFXis affected by the quality of R1 and R2.

Therefore, tight tolerance, low tempco, thin film resistors

should be used.











V_REFX=V_REF× 1 +

−V

×

(4)



REFX

2^NR1

R2

R1

R2

R1





V_REF× 1 +









V_REFX

=

(5)





D





1 +

×

N

2





where:

D = decimal equivalent of input code.

N = number of bits.

V

_REF= applied external reference.

_REFX= reference voltage for DAC A to DAC D.

AD7398/AD7399

R2 ±0.1%

R1 ±0.1%

V

A

V

A

B

C

D

REF

OUT

V

REF

DAC A

VIN

ADR293

V

B

REF

DAC B

V

C

REF

TO OTHER

COMPONENTS

DAC C

V

D

REF

DAC D

Figure 37. Programmable DAC Reference

Rev. C | Page 19 of 24

AD7398/AD7399

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

16

1

9

8

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

0.75 (0.0295)

0.25 (0.0098)

1.27 (0.0500)

BSC

45°

2.65 (0.1043)

2.35 (0.0925)

0.30 (0.0118)

0.10 (0.0039)

8°

0°

COPLANARITY

0.10

SEATING

PLANE

0.51 (0.0201)

0.31 (0.0122)

1.27 (0.0500)

0.40 (0.0157)

0.33 (0.0130)

0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 38. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 39. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

Rev. C | Page 20 of 24

AD7398/AD7399

ORDERING GUIDE

Model^{1, 2}

AD7398BR

AD7398BR-REEL

AD7398BRZ

AD7398BRZ-REEL

AD7398BRU

AD7398BRU-REEL7

AD7398BRUZ

AD7398BRUZ-REEL7

AD7398WBRUZ-RL7

AD7399BR

AD7399BR-REEL

AD7399BRZ

AD7399BRZ-REEL

AD7399BRU

Resolution (Bits)

Temperature Range

−40°C to +125°C

Package Description

16-Lead SOIC_W

16-Lead TSSOP

16-Lead SOIC_W

16-Lead TSSOP

Package Option

Ordering Quantity

12

10

RW-16

RU-16

RW-16

RU-16

47

1,000

47

1,000

96

1,000

96

1,000

47

1,000

47

1,000

96

1,000

96

AD7399BRU-REEL7

AD7399BRUZ

AD7399BRUZ-REEL7

1,000

¹Z = RoHS Compliant Part.

²W = Qualified for Automotive Applications.

The AD7398 contains 3254 transistors. The die size measures 108 mils × 144 mils.

AUTOMOTIVE PRODUCTS

The AD7398WBRUZ-RL7 model is available with controlled manufacturing to support the quality and reliability requirements of

automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore,

designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for

use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and

to obtain the specific Automotive Reliability reports for this model.

Rev. C | Page 21 of 24

AD7398/AD7399

NOTES

Rev. C | Page 22 of 24

AD7398/AD7399

NOTES

Rev. C | Page 23 of 24

AD7398/AD7399

NOTES

registered trademarks are the property of their respective owners.

D02179-0-1/11(C)

Rev. C | Page 24 of 24


型号：	AD7398BRUZ-REEL7
厂家：	ADI
描述：	Quad, Serial-Input 12-Bit/10-Bit DACs 四，串行输入，12位/ 10位DAC 转换器光电二极管
文件：	总24页 (文件大小：416K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7398BRUZ-REEL7 [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E