AD7397ARUZ_技术文档

3 V, Parallel Input

Dual 12-Bit/10-Bit DACs

a

AD7396/AD7397

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Micropower: 100 ␮A/DAC

0.1 ␮A Typical Power Shutdown

Single Supply +2.7 V to +5.5 V Operation

Compact 1.1 mm Height TSSOP 24-Lead Package

AD7396: 12-Bit Resolution

AD7397: 10-Bit Resolution

0.9 LSB Differential Nonlinearity Error

V

DD

AD7396

12

DACA

REGISTER

12-BIT

DACA

LDA

OUTA

CS

INPUTA

REGISTER

A/B

12

1

V

DATA

REF

APPLICATIONS

INPUTB

REGISTER

Automotive Output Span Voltage

Portable Communications

Digitally Controlled Calibration

PC Peripherals

12

DACB

REGISTER

12-BIT

DACB

LDB

V

OUTB

AGND

DGND

RS

SHDN

GENERAL DESCRIPTION

Both parts are offered in the same pinout, allowing users to

The AD7396/AD7397 series of dual, 12-bit and 10-bit voltage-

output digital-to-analog converters are designed to operate from

a single +3 V supply. Built using a CBCMOS process, these

monolithic DACs offer the user low cost and ease of use in

single supply +3 V systems. Operation is guaranteed over the

supply voltage range of +2.7 V to +5.5 V, making this device

ideal for battery operated applications.

select the amount of resolution appropriate for their applications

without circuit card changes.

The AD7396/AD7397 are specified for operation over the ex-

tended industrial (–40°C to +85°C) temperature range. The

AD7397AR is specified for the –40°C to +125°C automotive

temperature range. AD7396/AD7397s are available in plastic

DIP, and 24-lead SOIC packages. The AD7397ARU is avail-

able for ultracompact applications in a thin 1.1 mm height

TSSOP 24-lead package.

A 12-bit wide data latch loads with a 45 ns write time allowing

interface to fast processors without wait states. The double

buffered input structure allows the user to load the input

registers one at a time, then a single load strobe tied to both

LDA+LDB inputs will simultaneously update both DAC out-

puts. LDA and LDB can also be independently activated to

immediately update their respective DAC registers. An address

input (A/B) decodes DACA or DACB when the chip select CS

input is strobed. Additionally, an asynchronous RS input sets

the output to zero-scale at power on or upon user demand.

Power shutdown to submicroamp levels is directly controlled by

the active low SHDN pin. While in the power shutdown state

register data can still be changed even though the output buffer

is in an open circuit state. Upon return to the normal operating

state the latest data loaded in the DAC register will establish the

output voltage.

1.0

V

= +3V

DD

0.8

0.6

0.4

= +2.5V

REF

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

T

= +25؇C, +85؇C, –55؇C

SUPERIMPOSED

A

0

512

1024 1536

2048

2560 3072

3584 4096

CODE – Decimal

Figure 1. DNL vs. Digital Code at Temperature

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

AD7396/AD7397–SPECIFICATIONS

AD7396 12-BIT

(@ V_{REF IN}= +2.5 V, –40؇C < T_A< +85؇C, unless otherwise noted)

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Conditions

+3 V ؎ 10% +5 V ؎ 10% Units

STATIC PERFORMANCE

Resolution¹

N

12

Bits

Relative Accuracy²

INL

DNL

V_ZSE

V_FSE

TCV_FS

T_A= +25°C

±1.75

±2.0

±0.9

±1

4.0

8.0

±1.75

±2.0

±0.9

±1

4.0

8.0

±8

±20

–45

LSB max

mV max

ppm/°C typ

Relative Accuracy²

T_A= –40°C, +85°C

T_A= +25°C, Monotonic

Monotonic

Data = 000_H, T_A= +25°C, +85°C

Data = 000_H, T_A= –40°C

Differential Nonlinearity²

Zero-Scale Error

Full-Scale Voltage Error

Full-Scale Tempco³

T_A= +25°C, +85°C, Data = FFF_H±8

T_A= –40°C, Data = FFF_H

±20

–45

REFERENCE INPUT

V

_REFRange

V_REF

R_REF

C_REF

0/V_DD

2.5

5

0/V_DD

2.5

5

V min/max

MΩ typ⁴

pF typ

Input Resistance

Input Capacitance³

ANALOG OUTPUT

Output Current (Source)

Output Current (Sink)

Capacitive Load³

I_OUT

C_L

Data = 800_H, ∆V_OUT= 5 LSB

No Oscillation

1

3

100

1

3

100

mA typ

pF typ

LOGIC INPUTS

Logic Input Low Voltage

Logic Input High Voltage

Input Leakage Current

Input Capacitance³

V_IL

V_IH

I_IL

0.5

V_DD– 0.6

10

0.8

4.0

10

V max

V min

µA max

C_IL

10

pF max

INTERFACE TIMING^{3, 5}

Chip Select Write Width

DAC Select Setup

DAC Select Hold

Data Setup

Data Hold

Load Setup

Load Hold

Load Pulsewidth

t_CS

t_AS

t_AH

t_DS

t_DH

45

30

0

30

20

10

30

40

35

15

0

15

10

20

10

30

ns min

t_LS

t_LH

t_LDW

t_RSW

Reset Pulsewidth

AC CHARACTERISTICS

Output Slew Rate

Settling Time⁶

SR

t_S

Data = 000_Hto FFF_Hto 000_H

To ±0.1% of Full Scale

0.05

70

0.05

60

V/µs typ

µs typ

Shutdown Recovery Time

DAC Glitch

Digital Feedthrough

Feedthrough

t_SDR

Q

90

65

15

80

65

15

µs typ

nV/s typ

Code 7FF_Hto 800_Hto 7FF_H

V_OUT/V_REF

V_REF= 1.5 V_DC+1 V p-p_,

Data = 000_H, f = 100 kHz

–63

dB typ

SUPPLY CHARACTERISTICS

Power Supply Range

Positive Supply Current

Shutdown Supply Current

Power Dissipation

V_{DD RANGE}

I_DD

I_{DD_SD}

P_DISS

DNL < ±1 LSB

2.7/5.5

125/200

0.1/1.5

600

2.7/5.5

125/200

0.1/1.5

1000

V min/max

µA typ/max

µW max

V_IL= 0 V, No Load

SHDN = 0, V_IL= 0 V, No Load

V_IL= 0 V, No Load

∆V_DD= ±5%

Power Supply Sensitivity

PSS

0.006

%/% max

NOTES

¹One LSB = V_REF/4096 V for the 12-bit AD7396.

²The first two codes (000_H, 001_H) are excluded from the linearity error measurement.

³These parameters are guaranteed by design and not subject to production testing.

⁴Typicals represent average readings measured at +25°C.

⁵All input control signals are specified with t_R= t_F= 2 ns (10% to 90% of +3 V) and timed from a voltage level of +1.6 V.

⁶The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.

Specifications subject to change without notice.

–2–

REV. 0

AD7396/AD7397

AD7397 10-BIT

(@ V_{REF IN}= +2.5 V, –40؇C < T_A< +85؇C, unless otherwise noted)

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Conditions

+3 V ؎ 10% +5 V ؎ 10% Units

STATIC PERFORMANCE

Resolution¹

N

10

Bits

Relative Accuracy²

INL

DNL

V_ZSE

V_FSE

TCV_FS

T_A= +25°C

T_A= –40°C, +85°C, +125°C

Monotonic

Data = 000_H

±1.75

±2.0

±1

±1.75

±2.0

±1

LSB max

mV max

ppm/°C typ

Relative Accuracy²

Differential Nonlinearity²

Zero-Scale Error

9.0

Full-Scale Voltage Error

Full-Scale Tempco³

T_A= +25°C, +85°C, +125°C, Data = 3FF_H±42

±42

±48

–45

T_A= –40°C, Data = 3FF_H

±48

–45

REFERENCE INPUT

V

_REFRange

V_REF

R_REF

C_REF

0/V_DD

2.5

5

0/V_DD

2.5

5

V min/max

MΩ typ⁴

pF typ

Input Resistance

Input Capacitance³

ANALOG OUTPUT

Output Current (Source)

Output Current (Sink)

Capacitive Load³

I_OUT

C_L

Data = 200_H, ∆V_OUT= 5 LSB

No Oscillation

1

3

100

1

3

100

mA typ

pF typ

LOGIC INPUTS

Logic Input Low Voltage

Logic Input High Voltage

Input Leakage Current

Input Capacitance³

V_IL

V_IH

I_IL

0.5

V_DD– 0.6

10

0.8

4.0

10

V max

V min

µA max

C_IL

10

pF max

INTERFACE TIMING^{3, 5}

Chip Select Write Width

DAC Select Setup

DAC Select Hold

Data Setup

Data Hold

Load Setup

Load Hold

Load Pulsewidth

t_CS

t_AS

t_AH

t_DS

t_DH

45

30

0

30

20

10

30

40

35

15

0

15

10

20

10

30

ns min

t_LS

t_LH

t_LDW

t_RSW

Reset Pulsewidth

AC CHARACTERISTICS

Output Slew Rate

Settling Time⁶

SR

t_S

Data = 000_Hto 3FF_Hto 000_H

To ±0.1% of Full Scale

0.05

70

0.05

60

V/µs typ

µs typ

Shutdown Recovery Time

DAC Glitch

Digital Feedthrough

Feedthrough

t_SDR

Q

90

65

15

80

65

15

µs typ

nV/s typ

Code 7FF_Hto 800_Hto 7FF_H

V_OUT/V_REFV_REF= 1.5 V_DC+1 V p-p_,

Data = 000_H, f = 100 kHz

–63

dB typ

SUPPLY CHARACTERISTICS

Power Supply Range

Positive Supply Current

Shutdown Supply Current

Power Dissipation

V_{DD RANGE}DNL < ±1 LSB

2.7/5.5

125/200

0.1/1.5

600

2.7/5.5

125/200

0.1/1.5

1000

V min/max

µA typ/max

µW max

I_DD

V_IL= 0 V, No Load

SHDN = 0, V_IL= 0 V, No Load

V_IL= 0 V, No Load

∆V_DD= ±5%

I_{DD_SD}

P_DISS

PSS

Power Supply Sensitivity

0.006

%/% max

NOTES

¹One LSB = V_REF/4096 V for the 10-bit AD7397.

²The first two codes (000_H, 001_H) are excluded from the linearity error measurement.

³These parameters are guaranteed by design and not subject to production testing.

⁴Typicals represent average readings measured at +25°C.

⁵All input control signals are specified with t_R= t_F= 2 ns (10% to 90% of +3 V) and timed from a voltage level of +1.6 V.

⁶The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.

Specifications subject to change without notice.

REV. 0

–3–

AD7396/AD7397

t_CSW

CS

t_AS

t_AH

1 OF 12

LATCHES

B REGISTER

A/B

OF THE 2 INPUT

REGISTERS

t_DS

t_DH

D0–D11

DBx

CS

TO DAC

REGISTERS

t_LS

t_LDW

t_LH

LDA, LDB

t_RSW

A/B

RS

t_S

1 LSB

ERROR BAND

V

OUT

Figure 2. Timing Diagram

Figure 3. Digital Control Logic

Table I. Control Logic Truth

CS

A/B

LDA

LDB

RS

SHDN

Input Register

DAC Register

L

H

X

H

L

H

L

H

X

H

L

^

H

L

H

L

^

H

L

X

Write to B

Write to A

Write to B

Write to A

Latched

Reset to Zero Scale

Latched to Zero

Latched with Previous Data

B Transparent

A Transparent

A and B Transparent

Latched with New Data from Input REG

Reset to Zero Scale

Latched to Zero

X

^

^Denotes positive edge. The SHDN pin has no effect on the digital interface data loading; however, while in the SHDN state (SHDN = 0) the output amplifiers V_OUTA

and V_OUTBexhibit an open circuit condition. Note, the LDx inputs are level-sensitive, the respective DAC registers are in a transparent state when LDx = “0.”

–4–

REV. 0

AD7396/AD7397

ABSOLUTE MAXIMUM RATINGS*

Maximum Junction Temperature (T_Jmax) . . . . . . . . .+150°C

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

AD7397AN, AD7397AR Only . . . . . . . . –40°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V

V_REFto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V_DD

Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V

V

_OUTto GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, V_DD+ 0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +2 V

I_OUTShort Circuit to GND . . . . . . . . . . . . . . . . . . . . +50 mA

Package Power Dissipation . . . . . . . . . . . . . (T_Jmax – T_A)/θ_JA

Thermal Resistance θ_JA

24-Lead Plastic DIP Package (N-24) . . . . . . . . . . +63°C/W

24-Lead SOIC Package (R-24) . . . . . . . . . . . . . . . +70°C/W

24-Lead Thin Shrink Surface Mount (RU-24) . . +143°C/W

N-24 (Soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . . .+300°C

R-24 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . . . . . . .+215°C

RU-24 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . . . . . .+224°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

ORDERING GUIDE

Res

(LSB)

Temperature

Ranges

Package

Descriptions

Package

Options

Model

AD7396AN

AD7396AR

12

–40°C to +85°C

24-Lead P-DIP

24-Lead SOIC

N-24

R-24

AD7397AN

AD7397AR

AD7397ARU

10

–40°C to +125°C

–40°C to +85°C

24-Lead P-DIP

24-Lead SOIC

24-Lead Thin Shrink Small Outline Package (TSSOP)

N-24

R-24

RU-24

The AD7396/AD7397 contains 1365 transistors. The die size measures 89 mil × 106 mil = 9434 sq mil.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7396/AD7397 features proprietary ESD protection circuitry, permanent dam-

age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–5–

AD7396/AD7397

PIN FUNCTION DESCRIPTIONS

Pin No.

Name

1

2

3

4

V_OUTA

AGND

DGND

LDA

DAC A Voltage Output.

Analog Ground.

Digital Ground.

Load DAC A Register Strobe. Transfers input register data to the DAC A register. Active

low inputs, Level sensitive latch. May be connected together with LDB to double-buffer load

both DAC registers simultaneously.

5

SHDN

Power Shutdown Active Low Input. DAC register contents are saved as long as power stays

on the V_DDpin.

6

RS

Resets Input and DAC Register to Zero Condition. Asynchronous active low input.

Twelve Parallel Input Data Bits. D11 = MSB Pin 18, D0 = LSB Pin 7, AD7396.

No Connect Pins 7 and 8 On the AD7397 Only.

Ten Parallel Input Data Bits. D9 = MSB Pin 18, D0 = LSB Pin 9, AD7397 Only.

Chip Select Latch Enable, Active Low.

7–18

7, 8

9–18

19

D0–D11

NC

D0–D9

CS

20

A/B

DAC Input Register Address Select DACA = 1 or DACB = 0.

21

LDB

Load DAC B Register Strobe. Transfers input register data to the DAC B register. Active low

inputs, Level sensitive latch. May be connected together with LDA to double-buffer load

both DAC registers simultaneously.

22

23

24

V_DD

V_REF

V_OUTB

Positive Power Supply Input. Specified range of operation +2.7 V to +5.5 V.

DAC Reference Input Pin. Establishes DAC full-scale voltage.

DAC B Voltage Output.

PIN CONFIGURATIONS

V

1

2

24

23

22

21

20

19

18

17

V

1

2

24

23

22

21

20

19

18

17

16

15

14

13

V

OUTA

OUTB

REF

DD

OUTA

OUTB

REF

DD

AGND

DGND

AGND

DGND

3

4

LDA

SHDN

RS

LDB

A/B

CS

LDA

SHDN

RS

LDB

A/B

CS

5

AD7397

TOP VIEW

(Not to Scale)

AD7396

TOP VIEW

(Not to Scale)

6

7

NC

D9

D0

D11

D10

D9

8

NC

D8

D1

D0

9

16 D7

9

D2

10

11

15

14

10

11

12

D1

D6

D5

D3

D8

D2

D4

D7

D3 12

13 D4

D5

D6

NC = NO CONNECT

–6–

REV. 0

Typical Performance Characteristics–AD7396/AD7397

30

1.0

1.5

1.0

V

= +3V

SS = 200 UNITS

DD

AD7396

V

= +2.7V

AD7397

DD

AD7397

0.8

T

= +25؇C

= +2.5V

A

REF

= +2.5V

REF

T

= –55؇C

V

= +2.7V

A

DD

0.6

0.4

0.2

= +2.5V

REF

20

0.5

0.0

T

= –55؇C

A

0.0

–0.2

–0.4

–0.6

–0.5

–1.0

10

0

T

= +25؇C, +85؇C

A

T

A

= +25؇C, +85؇C

–0.8

–1.0

–1.5

0

–5

5

10

128 256 384 512 640 768 896 1024

CODE – Decimal

0

512 1024 1536 2048 2560 3072 3584 4096

CODE – Decimal

TOTAL UNADJUSTED ERROR

HISTOGRAM – LSB

Figure 4. AD7396 INL vs. Code and

Temperature

Figure 5. AD7397 INL vs. Code and

Temperature

Figure 6. AD7397 TUE Histogram

100

1.0

60

SS = 200 UNITS

AD7396

AD7397

SS = 200 UNITS

V

= +2.7V

DD

AD7397

V

= +2.7V

0.8

DD

V

T

= +2.7V

DD

= +2.5V

REF

= +2.5V

REF

= +2.5V

REF

80

60

40

20

0

0.6

0.4

T

= –40؇C TO +85؇C

A

= –40؇C TO +85؇C

A

40

20

0

0.2

0.0

–0.2

–0.4

–0.6

–0.8

T

= +25؇C, +85؇C, –55؇C

SUPERIMPOSED

A

–1.0

0

–70

–60

–50

–40

–30

128 256 384 512 640 768 896 1024

CODE – Decimal

–55

–50

–45

–40

–35

–30

FULL-SCALE TEMPCO – ppm/؇C

FULL-SCALE OUTPUT TEMPCO

HISTOGRAM – ppm/؇C

Figure 7. AD7397 DNL vs. Code and

Temperature

Figure 8. AD7396 Full-Scale Tempco

Histogram

Figure 9. AD7397 Full-Scale Tempco

Histogram

1.5

1.0

0.5

0

40

20

40

20

0

10

V

= +5V

DD

AD7396

= +2.5V

REF

T

= +25؇C

A

8

6

4

2

0

V

= +5V

DD

= +25؇C

T

A

–0.5

–1.0

–1.5

CODE = HALF SCALE

–20

–40

–20

–40

V

= +5V

= +25؇C

DD

T

A

FSE (LSB) = FSE (V)

؋

4096/V

(V)

REF

0

1

2

3

4

5

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

1

10

100

1k

10k

100k

V – V

REF

V

– Volts

FREQUENCY – Hz

REF

Figure 10. INL Error vs. Reference

Voltage

Figure 11. Full-Scale Error vs. Refer-

ence Voltage

Figure 12. Output Noise Voltage

Density vs. Frequency

REV. 0

–7–

AD7396/AD7397

0

1.262

1.257

145

140

V

T

= +5V

V

T

= +3V

= +25؇C

DD

–5

= +2.5V

REF

A

= +25 C

V

= 0V TO +3V

–10

A

IN

135

130

CODE = 800 TO 7FF

H

5mV/DIV

V

= +3V

H

DD

CODE = FULL SCALE

–15

–20

–25

–30

–35

–40

–45

–50

V

= +3V TO 0V

IN

1.252

1.247

1.242

1.237

125

120

115

110

105

100

1k

10k

100k

1M

0

0.5

1

1.5

2

2.5

3

TIME – 2␮s/DIV

LOGIC INPUT – V (Volts)

FREQUENCY – Hz

IN

Figure 13. Reference Multiplying

Gain vs. Frequency

Figure 14. Midscale Transition

Performance

Figure 15. I_DDvs. Logic Input Voltage

35

45

5.0

4.5

T

= +25؇C

V

= +2.5V

REF

= +25؇C

V

T

= +2.5V

= +25؇C

A

REF

40

35

30

25

20

T

A

30

25

20

15

10

V

= +5V

DD

4.0

3.5

V

= +5V

DD

V

= +3V

DD

V

FROM

LOGIC

LOW TO HIGH

3.0

2.5

V

= +3V

DD

15

10

5

2.0

1.5

1.0

V

FROM

LOGIC

5

0

HIGH TO LOW

0

2

3

4

5

6

7

–120 –100 –80

–60

–40

–20

0

2

4

6

8

10

12

V

– V

⌬V

– mV

⌬V

– mV

DD

OUT

Figure 16. Logic Threshold Voltage

vs. V_DD

Figure 17. I_OUTSource Current vs.

∆ V_OUT

Figure 18. I_OUTSink Current vs.

∆ V_OUT

1000

170

200

V

= +2.5V

= +5V

V

= +2.5V

T

= +25؇C

REF

A

180

160

140

120

100

80

160

150

140

130

120

DD

V

= +3.6V, V

= +2.4V

SHDN = 0V

DD

LOGIC

V

= +5V

100

10

1

DD

V

= +5V, V

= +5V

DD

LOGIC

V

= +3V

DD

110

100

90

60

V

= +3V, V

= +3V

DD

LOGIC

40

20

80

0

–40 –20

20 40 60 80 100 120 140

–40 –20

0

20 40 60 80 100 120 140

0

1

2

3

4

5

TEMPERATURE – ؇C

V

– Volts

REF

Figure 21. Shutdown Current vs.

Temperature

Figure 19. I_DDvs. Temperature

Figure 20. I_DDvs. Reference Voltage

–8–

REV. 0

AD7396/AD7397

1400

1200

1000

800

600

400

200

0

80

70

60

50

1.0

0.9

AD7396

V

= +5V, ؎5%

DD

SAMPLE SIZE = 77

= +2.5V

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

A: V = +2.7V, CODE = 555

DD

V

H

REF

B: V = +2.7V, CODE = 3FF

DD

H

C: V = +5.5V, CODE = 155

DD

D: V = +5.5V, CODE = 3FF

DD

H

40

30

20

10

0

V

= +3V, ؎5%

CODE = FFF

DD

H

D

C

CODE = 000

H

A

B

0

100

200

300

400

500

600

1k

10k

100k

1M

10M

1

10

100

1k

10k

HOURS OF OPERATION AT +150؇C

DIGITAL INPUT FREQUENCY – Hz

FREQUENCY – Hz

Figure 22. I_DDvs. Digital Input

Frequency

Figure 23. PSRR vs. Frequency

Figure 24. Long-Term Drift Acceler-

ated by Burn-In

V

_OUT= V_REF× D/2^N

(1)

OPERATION

The AD7396 and AD7397 are a set of pin compatible, 12-bit

and 10-bit digital-to-analog converters. These single-supply

operation devices consume less than 200 µA of current while

operating from power supplies in the +2.7 V to +5.5 V range,

making them ideal for battery operated applications. They

contain a voltage-switched, 12-bit/10-bit, digital-to-analog

converter, rail-to-rail output op amps, and a parallel-input

DAC register. The external reference input has constant

2.5 MΩ input resistance independent of the digital code

setting of the DAC. In addition, the reference input can be tied

to the same supply voltage as V_DDresulting in a maximum

output voltage span of 0 to V_DD. The parallel data interface

consists of 12 data bits, DB0–DB11, for the AD7396, 10 data

bits, DB0–DB9, for the AD7397, and a CS write strobe. An RS

pin is available to reset the DAC register to zero scale. This

function is useful for power-on reset or system failure recovery

to a known state. Additional power savings are accomplished by

activating the SHDN pin resulting in a 1.5 µA maximum con-

sumption sleep mode. As long as the supply voltage, remains

data will be retained in the DAC and input register to supply

the DAC output when the part is taken out of shutdown.

where D is the decimal data word loaded into the DAC register,

and N is the number of bits of DAC resolution. In the case of

the 10-bit AD7397 using a 2.5 V reference, Equation 1 simpli-

fies to:

V

_OUT= 2.5 × D/1024

(2)

Using Equation 2, the nominal midscale voltage at V_OUTis

1.25 V for D = 512; full-scale voltage is 2.497 V. The LSB step

size is = 2.5 × 1/1024 = 0.0024 V.

For the 12-bit AD7396 operating from a 5.0 V reference equa-

tion [1] becomes:

V

_OUT= 5.0 × D/4096

(3)

Using Equation 3, the AD7396 provides a nominal midscale

voltage of 2.50 V for D = 2048, and a full-scale output of

4.998 V. The LSB step size is = 5.0 × 1/4096 = 0.0012 V.

AMPLIFIER SECTION

The internal DAC’s output is buffered by a low power con-

sumption precision amplifier. The op amp has a 60 µs typical

settling time to 0.1% of full scale. There are slight differences in

settling time for negative slewing signals versus positive. Also,

negative transition settling time to within the last 6 LSBs of zero

volts has an extended settling time. The rail-to-rail output stage

of this amplifier has been designed to provide precision perfor-

mance while operating near either power supply. Figure 26

shows an equivalent output schematic of the rail-to-rail-ampli-

fier with its N-channel pull-down FETs that will pull an output

load directly to GND. The output sourcing current is provided

by a P-channel pull-up device that can source current to GND

terminated loads.

V

DD

AD7396

12

DACA

REGISTER

12-BIT

DACA

LDA

OUTA

CS

INPUTA

REGISTER

A/B

12

1

V

DATA

REF

INPUTB

REGISTER

V

12

DD

DACB

REGISTER

12-BIT

DACB

LDB

V

OUTB

AGND

P-ch

DGND

RS

SHDN

V

OUT

Figure 25. Functional Block Diagram

N-ch

D/A CONVERTER SECTION

The voltage switched R-2R DAC generates an output voltage

dependent on the external reference voltage connected to the

REF pin according to the following equation:

AGND

Figure 26. Equivalent Analog Output Circuit

REV. 0

–9–

AD7396/AD7397

+2.7V TO +5.5V

The rail-to-rail output stage provides ±1 mA of output current.

The N-channel output pull-down MOSFET shown in Figure 26

has a 35 Ω ON resistance, which sets the sink current capability

near ground. In addition to resistive load driving capability, the

amplifier has also been carefully designed and characterized for

up to 100 pF capacitive load driving capability.

+

C

*

0.1␮F

10␮F

REF

V

DD

CS

AD7396

OR

AD7397

A/B

V

OUTA

LDA

LDB

OUTB

DATA

REFERENCE INPUT

DGND AGND

The reference input terminal has a constant input resistance

independent of digital code, which results in reduced glitches on

the external reference voltage source. The high 2.5 MΩ input

resistance minimizes power dissipation within the AD7396/

AD7397 D/A converters. The V_REFinput accepts input voltages

ranging from ground to the positive-supply voltage V_DD. One of

the simplest applications, which saves an external reference voltage

source, is connection of the V_REFterminal to the positive V_DD

supply. This connection results in a rail-to-rail voltage output

span maximizing the programmed range. The reference input

will accept AC signals as long as they are kept within the supply

voltage range, 0 < V_{REF IN}< V_DD. The reference bandwidth

and integral nonlinearity error performance are plotted in the

Typical Performance Characteristics section, see Figures 10 and

13. The ratiometric reference feature makes the AD7396/AD7397

an ideal companion to ratiometric analog-to-digital converters

such as the AD7896.

*

OPTIONAL EXTERNAL

REFERENCE BYPASS

Figure 27. Recommended Supply Bypassing

INPUT LOGIC LEVELS

All digital inputs are protected with a Zener-type ESD protec-

tion structure (Figure 28) that allows logic input voltages to

exceed the V_DDsupply voltage. This feature can be useful if the

user is driving one or more of the digital inputs with a 5 V CMOS

logic input-voltage level while operating the AD7396/AD7397

on a +3 V power supply. If this mode of interface is used, make

sure that the V_OLof the 5 V CMOS meets the V_ILinput require-

ment of the AD7396/AD7397 operating at 3 V. See Figure 16

for a graph for digital logic input threshold versus operating V_DD

supply voltage.

V

DD

LOGIC

IN

POWER SUPPLY

The very low power consumption of the AD7396/AD7397 is a

direct result of a circuit design optimizing the use of a CBCMOS

process. By using the low power characteristics of CMOS for

the logic, and the low noise, tight matching of the complemen-

tary bipolar transistors, excellent analog accuracy is achieved.

One advantage of the rail-to-rail output amplifiers used in the

AD7396/AD7397 is the wide range of usable supply voltage.

The part is fully specified and tested for operation from +2.7 V

to +5.5 V.

GND

Figure 28. Equivalent Digital Input ESD Protection

In order to minimize power dissipation from input-logic levels

that are near the V_IHand V_ILlogic input voltage specifications, a

Schmitt trigger design was used that minimizes the input-buffer

current consumption compared to traditional CMOS input

stages. Figure 15 shows a plot of incremental input voltage

versus supply current showing that negligible current consump-

tion takes place when logic levels are in their quiescent state.

The normal crossover current still occurs during logic transi-

tions. A secondary advantage of this Schmitt trigger is the pre-

vention of false triggers that would occur with slow moving logic

transitions when a standard CMOS logic interface or opto-

isolators are used. The logic inputs DB11–DB0, A/B CS, RS,

SHDN all contain Schmitt trigger circuits.

POWER SUPPLY BYPASSING AND GROUNDING

Precision analog products such as the AD7396/AD7397 require

a well filtered power source. Since the AD7396/AD7397 oper-

ates from a single +3 V to +5 V supply, it seems convenient to

simply tap into the digital logic power supply. Unfortunately,

the logic supply is often a switch-mode design, which generates

noise in the 20 kHz to 1 MHz range. In addition, fast logic gates

can generate glitches, hundred of millivolts in amplitude, due to

wiring resistance and inductance. The power supply noise gen-

erated thereby means that special care must be taken to assure

that the inherent precision of the DAC is maintained. Good

engineering judgment should be exercised when addressing the

power supply grounding and bypassing of the 12-bit AD7396.

DIGITAL INTERFACE

The AD7396/AD7397 has a double-buffered, parallel-data

input. A functional block diagram of the digital section is shown

in Figure 25, while Table I contains the truth table for the logic

control inputs. The chip select (CS) and A/B pins control load-

ing of data from the data inputs on pins DB11–DB0 into the

internal Input Register. The CS active low input places data

into the decoded A/B input register. When CS returns to logic

high within the data setup-and-hold time specifications the new

value of data in the input register will be latched. See Truth

Table for complete set of conditions. New data can only be

transferred to the corresponding DAC register when its LDx pin

is strobed active low. The LDx inputs are level-sensitive (DAC

Registers are transparent latches) and can be tied active low

The AD7396 should be powered directly from the system power

supply. Whether or not a separate power supply trace is avail-

able generous supply bypassing will reduce supply line-induced

errors. Local supply bypassing consisting of a 10 µF tantalum

electrolytic in parallel with a 0.1 µF ceramic capacitor is recom-

mended in all applications (Figure 27).

–10–

REV. 0

AD7396/AD7397

allowing any new Input Register data updates to directly control

the DAC output voltages for single-buffered applications. For

doubled-buffered applications where both DAC outputs, V_OUTA

and V_OUTB, need to be changed simultaneously to a new value,

the two inputs, LDA and LDB, can be tied together and pulsed

active low in a synchronous manner.

Table II. Unipolar Code Table

Hexadecimal

Number

Decimal

Output

Voltage (V)

(V_REF= 2.5 V)

Number

In DAC Register

FFF

801

800

7FF

000

4095

2049

2048

2047

0

2.4994

1.2506

1.2500

1.2494

0

RESET (RS) PIN

Forcing the asynchronous RS pin low will set the Input and

DAC registers to all zeros and the DAC output voltage will be

zero volts. The reset function is useful for setting the DAC

outputs to zero at power-up or after a power supply interrup-

tion. Test systems and motor controllers are two of many appli-

cations that benefit from powering up to a known state. The

external reset pulse can be generated by the microprocessor’s

power-on RESET signal, from the microprocessor, or by an

external resistor and capacitor. RESET has a Schmitt trigger

input which results in a clean reset function when using external

resistor/capacitor generated pulses. See Table I, Control-Logic

Truth.

The circuit can be configured with an external reference plus

power supply, or powered from a single dedicated regulator or

reference, depending on the application performance requirements.

BIPOLAR OUTPUT OPERATION

Although the AD7397 has been designed for single supply op-

eration, the output can easily be configured for bipolar opera-

tion. A typical circuit is shown in Figure 30. This circuit uses a

clean regulated +5 V supply for power, which also provides

the circuit’s reference voltage. Since the AD7397 output span

swings from ground to very near +5 V, it is necessary to choose

an external amplifier with a common-mode input voltage range

that extends to its positive supply rail. The micropower con-

sumption OP196 has been designed just for this purpose and

results in only 50 µA of maximum current consumption. Con-

nection of the equal-value 470 kΩ resistors results in a differen-

tial amplifier mode of operation with a voltage gain of two,

which produces a circuit output span of ten volts, that is,

–5 V to +5 V. As the AD7397 DAC is programmed from zero-

code 000_Hto midscale 200_Hto full-scale 3FF_H, the circuit out-

put voltage V_Ois set at –5 V, 0 V and +5 V (–1 LSB). The

output voltage V_Ois coded in offset binary according to

Equation 3.

POWER SHUTDOWN (SHDN)

Maximum power savings can be achieved by using the power

shutdown control function. This hardware-activated feature is

controlled by the active low input SHDN pin. This pin has a

Schmitt trigger input which helps to desensitize it to slowly

changing inputs. By placing a logic low on this pin the internal

consumption of the AD7397 or AD7397 is reduced to nanoamp

levels, guaranteed to 1.5 µA maximum over the operating tem-

perature range. If power is present at all times on the V_DDpin

while in the shutdown mode, the internal DAC register will

retain the last programmed data value. This data will be used

when the part is returned to the normal active state by placing

the DAC back to its programmed voltage setting. Shutdown

recovery time measures 80 µs. In the shutdown state the DAC

output amplifier exhibits an open-circuit high-resistance state.

Any load connected will stabilize at its termination voltage. If

the power shutdown feature is not needed then the user should

tie the SHDN pin to the V_DDvoltage thereby disabling this

function.

V

_OUT= [(D/512)–1] × 5

(4)

where D is the decimal code loaded in the AD7397 DAC regis-

ter. Note that the LSB step size is 10/1024 = 10 mV. This

circuit has been optimized for micropower consumption includ-

ing the 470 kΩ gain setting resistors, which should have low

temperature coefficients to maintain accuracy and matching

(preferably the same resistor material, such as metal film). If

better stability is required, the power supply could be substi-

tuted with a precision reference voltage such as the low dropout

REF195, which can easily supply the circuit’s 262 µA of current

and still provide additional power for the load connected to V_O.

The micropower REF195 is guaranteed to source 10 mA output

drive current, but consumes only 50 µA internally. If higher

resolution is required, the AD7396 can be used with the addi-

tion of two more bits of data inserted into the software coding,

which would result in a 2.5 mV LSB step size. Table III shows

examples of nominal output voltages, V_O, provided by the bipo-

lar operation circuit application.

UNIPOLAR OUTPUT OPERATION

This is the basic mode of operation for the AD7396. As shown

in Figure 29, the AD7396 has been designed to drive loads as

low as 5 kΩ in parallel with 100 pF. The code table for this

operation is shown in Table II.

+2.7V TO +5.5V

R

0.01␮F

0.1␮F

10␮F

V

DD

AD7396

V

REF

V

DAC A

OUTA

EXT

REF

75k⍀

100pF

V

DAC B

AGND

OUTB

16/14

DIGITAL

DGND

␮C

DIGITAL INTERFACE

CIRCUITRY OMITTED

FOR CLARITY.

Figure 29. Unipolar Output Operation

REV. 0

–11–

AD7396/AD7397

I

< 262␮A

SY

Table III. Bipolar Code Table

+5V

470k⍀

200␮A

470k⍀

Hexadecimal Number Decimal Number Analog Output

In DAC Register

Voltage (V)

< 50␮A

+5V

V

REF

V

DD

BIPOLAR

OUTPUT

SWING

3FF

201

200

1FF

000

1023

513

512

511

0

4.9902

0.0097

0.0000

–0.0097

–5.0000

O

OP196

V

OUTA

AD7397

C

–5V

GND

–5V

ONLY ONE CHANNEL SHOWN.

DIGITAL INTERFACE CIRCUITRY

OMITTED FOR CLARITY.

Figure 30. Bipolar Output Operation

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

24-Lead SOIC Package

(R-24)

24-Lead Narrow Body Plastic DIP Package

(N-24)

1.275 (32.30)

1.125 (28.60)

0.6141 (15.60)

0.5985 (15.20)

24

1

13

12

0.280 (7.11)

0.240 (6.10)

24

1

13

12

0.325 (8.25)

0.300 (7.62)

0.195 (4.95)

0.115 (2.93)

PIN 1

0.060 (1.52)

0.015 (0.38)

0.210

(5.33)

MAX

0.150

(3.81)

MIN

0.200 (5.05)

0.125 (3.18)

PIN 1

0.1043 (2.65)

0.0926 (2.35)

0.015 (0.381)

0.008 (0.204)

0.0291 (0.74)

0.0098 (0.25)

؋

45؇

0.022 (0.558) 0.100 (2.54)

0.014 (0.356)

0.070 (1.77)

0.045 (1.15)

SEATING

PLANE

BSC

0.0500 (1.27)

0.0157 (0.40)

8؇

0؇

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.0118 (0.30)

0.0040 (0.10)

SEATING

PLANE

0.0125 (0.32)

0.0091 (0.23)

24-Lead Thin Surface Mount TSSOP Package

(RU-24)

0.311 (7.90)

0.303 (7.70)

24

13

12

1

0.006 (0.15)

PIN 1

0.002 (0.05)

0.0433

(1.10)

MAX

0.028 (0.70)

0.020 (0.50)

8؇

0؇

0.0256 (0.65) 0.0118 (0.30)

SEATING

PLANE

0.0079 (0.20)

0.0035 (0.090)

BSC

0.0075 (0.19)

–12–

REV. 0


型号：	AD7397ARUZ
厂家：	ADI
描述：	3 V, Parallel Input Dual 12-Bit /10-Bit DACs 3 V ，并行输入双通道12位/ 10位DAC 转换器数模转换器光电二极管 PC
文件：	总12页 (文件大小：216K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7397ARUZ [ADI]

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