AD7393_15_技术文档

3 V, Parallel Input

Micropower 10-/12-Bit DACs

AD7392/AD7393

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Micropower: 100 μA

AD7392

V

DD

0.1 μA typical power shutdown

Single-supply 2.7 V to 5.5 V operation

AD7392: 12-bit resolution

AD7393: 10-bit resolution

0.9 LSB differential nonlinearity error

12-BIT

DAC

V

REF

OUT

SHDN

AGND

12

DAC REGISTER

12

DGND CS

D0 TO D11

RS

APPLICATIONS

Figure 1.

Automotive 0.5 V to 4.5 V output span voltage

Portable communications

Digitally controlled calibration

PC peripherals

GENERAL DESCRIPTION

The AD7392/AD7393 comprise a set of pin-compatible

10-/12-bit voltage output, digital-to-analog converters. The

parts are designed to operate from a single 3 V supply. Built

using a CBCMOS process, these monolithic DACs offer low

cost and ease of use in single-supply 3 V systems. Operation is

guaranteed over the supply voltage range of 2.7 V to 5.5 V,

making this device ideal for battery-operated applications.

Both parts are offered with similar pinouts, which allows users

to select the amount of resolution appropriate for their applica-

tions without changing the circuit card.

The AD7392/AD7393 are specified for operation over the

extended industrial temperature range of −40°C to +85°C.

The AD7393AR is specified for the automotive temperature

range of −40°C to +125°C. The AD7392/AD7393 are available

in 20-lead PDIP and 20-lead SOIC packages.

The full-scale voltage output is determined by the external ref-

erence input voltage applied. The rail-to-rail REF_INto DAC_OUT

allows a full-scale voltage equal to the positive supply V_DDor

any value in between. The voltage outputs are capable of sourc-

ing 5 mA.

For serial data input, 8-lead packaged versions, see the AD7390

and AD7391.

A data latch load of 12 bits with a 45 ns write time eliminates

wait states when interfacing to the fastest processors. Addition-

RS

ally, an asynchronous

input sets the output to a zero scale at

power-on or upon user demand.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD7392/AD7393

TABLE OF CONTENTS

Features .............................................................................................. 1

Digital-to-Analog Converters................................................... 12

Amplifier Section ....................................................................... 12

Reference Input........................................................................... 12

Power Supply............................................................................... 13

Input Logic Levels ...................................................................... 13

Digital Interface.......................................................................... 13

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Timing Diagram ........................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 12

RS

Reset Pin ( ) ............................................................................. 14

SHDN

Power Shutdown (

)......................................................... 14

Unipolar Output Operation...................................................... 14

Bipolar Output Operation......................................................... 15

Outline Dimensions....................................................................... 16

Ordering Guide .......................................................................... 17

REVISION HISTORY

8/07—Rev. B to Rev. C

Changes to Specifications Section.................................................. 3

Changes to Table 3............................................................................ 6

Changes to Theory of Operation Section.................................... 12

Changes to Figure 29...................................................................... 13

Changes to Figure 32...................................................................... 14

Changes to Figure 33...................................................................... 15

Updated Outline Dimensions....................................................... 16

Changes to Ordering Guide .......................................................... 17

6/04—Changed from Rev. A to Rev. B

Removed TSSOP.................................................................Universal

Changes to Ordering Guide .......................................................... 17

3/99—Changed from Rev. 0 to Rev. A

11/96—Revision 0: Initial Version

Rev. C | Page 2 of 20

AD7392/AD7393

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

At V_REF= 2.5 V, −40°C < T_A< +85°C, unless otherwise noted.

Table 1. AD7392

Parameter

Symbol

Conditions

3 V ꢀ0%

5 V ꢀ0%

Unit

STATIC PERFORMANCE

Resolution¹

N

INL

12

1.8

3

0.9

1

4.0

8.0

8

20

28

12

1.8

3

0.9

1

4.0

8.0

8

20

28

Bits

Relative Accuracy²

T_A= +25°C

T_A= −40°C, +85°C

LSB max

mV max

ppm/°C typ

Differential Nonlinearity²

Zero-Scale Error

DNL

V_ZSE

T_A= +25°C, monotonic

Monotonic

Data = 0x000, T_A= +25°C, +85°C

Data = 0x000, T_A= −40°C

T_A= +25°C, +85°C, data = 0xFFF

T_A= −40°C, data = 0xFFF

Full-Scale Voltage Error

V_FSE

Full-Scale Temperature Coefficient³

REFERENCE INPUT

V_REFRange

TCV_FS

V_REF

R_REF

C_REF

0/V_DD

2.5

5

0/V_DD

2.5

5

V min/max

MΩ typ⁴

pF typ

Input Resistance

Input Capacitance³

ANALOG OUTPUT

Current (Source)

I_OUT

C_L

Data = 0x800, ∆ V_OUT= 5 LSB

No oscillation

1

3

100

1

3

100

mA typ

pF typ

Output Current (Sink)

Capacitive Load³

LOGIC INPUTS

Logic Input Low Voltage

Logic Input High Voltage

Input Leakage Current

Input Capacitance³

INTERFACE TIMING^{3, 5}

Chip Select Write Width

Data Setup

V_IL

V_IH

I_IL

0.5

V_DD− 0.6

10

0.8

V_DD− 0.6

10

V max

V min

μA max

pF max

C_IL

10

t_CS

t_DS

t_DH

t_RS

45

30

20

40

45

15

5

ns min

Data Hold

Reset Pulse Width

AC CHARACTERISTICS

Output Slew Rate

Settling Time⁶

30

SR

t_S

Data = 0x000 to 0xFFF to 0x000

To 0.1% of full scale

0.05

70

0.05

60

V/μs typ

μs typ

Shutdown Recovery Time

DAC Glitch

Digital Feedthrough

Feedthrough

t_SDR

80

65

15

−63

μs typ

Code 0x7FF to Code 0x800 to Code 0x7FF

65

15

−63

nV/s typ

dB typ

V_OUT/V_REF

V_REF= 1.5 V dc + 1 V p-p, data = 0x000,

f = 100 kHz

SUPPLY CHARACTERISTICS

Power Supply Range

Positive Supply Current

Shutdown Supply Current

Power Dissipation

V_{DD RANGE}

I_DD

I_DD-SD

P_DISS

DNL < 1 LSB

V_IL= 0 V, no load

2.7/5.5

55/100

0.1/1.5

300

2.7/5.5

55/100

0.1/1.5

500

V min/max

μA typ/max

μW max

SHDN

= 0, V_IL= 0 V, no load

V_IL= 0 V, no load

Δ V_DD5%

Power Supply Sensitivity

PSS

=

0.006

%/% max

¹One LSB = V_REF/4096 V for the 12-bit AD7392.

²The first two codes (0x000, 0x001) are excluded from the linearity error measurement.

³These parameters are guaranteed by design and not subject to production testing.

⁴Typicals represent average readings measured at +25°C.

⁵All input control signals are specified with t_R= t_F= 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.

⁶The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.

Rev. C | Page 3 of 20

AD7392/AD7393

At V_REF= 2.5 V, −40°C < T_A< +85°C, unless otherwise noted.

Table 2. AD7393

Parameter

Symbol Conditions

3 V ꢀ0% 5 V ꢀ0% Unit

STATIC PERFORMANCE

Resolution¹

Relative Accuracy²

N

INL

10

1.ꢀ5

10

1.ꢀ5

Bits

T_A= +25°C

LSB max

mV max

ppm/°C typ

T_A= −40°C, +85°C, +125°C

Monotonic

Data = 0x000

T_A= +25°C, +85°C, +125°C, data = 0x3FF

T_A= −40°C, data = 0x3FF

2.0

0.8

9.0

32

42

28

2.0

0.8

9.0

32

42

28

Differential Nonlinearity²

Zero-Scale Error

DNL

V_ZSE

V_FSE

Full-Scale Voltage Error

Full-Scale Temperature Coefficient³

REFERENCE INPUT

V_{REF IN}Range

TCV_FS

V_REF

R_REF

C_REF

0/V_DD

2.5

5

0/V_DD

2.5

5

V min/max

MΩ typ⁴

pF typ

Input Resistance

Input Capacitance³

ANALOG OUTPUT

Output Current (Source)

Output Current (Sink)

Capacitive Load³

I_OUT

C_L

Data = 0x200, Δ V_OUT= 5 LSB

No oscillation

1

3

1

3

mA typ

pF typ

100

LOGIC INPUTS

Logic Input Low Voltage

Logic Input High Voltage

Input Leakage Current

Input Capacitance³

INTERFACE TIMING^{3, 5}

Chip Select Write Width

Data Setup

V_IL

V_IH

I_IL

0.5

V_DD− 0.6

10

0.8

V_DD− 0.6

10

V max

V min

μA max

pF max

C_IL

10

t_CS

t_DS

t_DH

t_RS

45

30

20

40

45

15

5

ns

Data Hold

Reset Pulse Width

AC CHARACTERISTICS

Output Slew Rate

30

SR

t_S

Data = 0x000 to 0x3FF to 0x000

To 0.1% of full scale

0.05

ꢀ0

0.05

60

V/μs typ

μs typ

Settling Time⁶

Shutdown Recovery Time

DAC Glitch

Digital Feedthrough

Feedthrough

t_SDR

80

65

15

−63

μs typ

Code 0xꢀFF to Code 0x800 to Code 0xꢀFF

65

15

−63

nV/s typ

dB typ

V_OUT/V_REFV_REF= 1.5 V dc 11 V p-p, data = 0x000, f = 100 kHz

SUPPLY CHARACTERISTICS

Power Supply Range

Positive Supply Current

V_{DD RANGE}

I_DD

DNL < 1 LSB

V_IL= 0 V, no load, T_A= +25°C

V_IL= 0 V, no load

2.ꢀ/5.5

55

100

2.ꢀ/5.5

55

100

V min/max

μA typ

μA max

Shutdown Supply Current

Power Dissipation

Power Supply Sensitivity

I_DD-SD

P_DISS

PSS

SHDN

0.1/1.5

300

0.006

0.1/1.5

500

0.006

μA typ/max

μW max

%/% max

= 0, V_IL= 0 V, no load

V_IL= 0 V, no load

Δ V_DD5%

=

¹One LSB = V_REF/1024 V for the 10-bit ADꢀ393.

²The first two codes (0x000, 0x001) are excluded from the linearity error measurement.

³These parameters are guaranteed by design and not subject to production testing.

⁴Typicals represent average readings measured at +25°C.

⁵All input control signals are specified with t_R= t_F= 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.

⁶The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.

Rev. C | Page 4 of 20

AD7392/AD7393

TIMING DIAGRAM

1

t_CS

CS

0

1

t_DS

t_DH

D11 TO D0

DATA VALID

0

1

t_RS

RS

0

FS

±0.1%FS

ERROR BAND

V

OUT

ZS

t_S

Figure 2. Timing Diagram

Rev. C | Page 5 of 20

AD7392/AD7393

ABSOLUTE MAXIMUM RATINGS

Table 3.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

V_DDto GND

V_REFto GND

Logic Inputs to GND

V_OUTto GND

I_OUTShort Circuit to GND

DGND to AGND

−0.3 V, +8 V

−0.3 V, V_DD

−0.3 V, V_DD+ 0.3 V

50 mA

−0.3 V, +2 V

Package Power Dissipation

Thermal Resistance (θ_JA)

20-Lead PDIP (N 20)

20-Lead SOIC (R-20)

Maximum Junction Temperature (T_Jmax)

Operating Temperature Range

AD7393AR

Storage Temperature Range

Lead Temperature

Reflow Soldering Peak Temperature

SnPb

(T_Jmax − T_A)/θ_JA

ESD CAUTION

57°C/W

60°C/W

150°C

−40°C to +85°C

−40°C to +125°C

−65°C to +150°C

240°C

260°C

Pb-Free

Rev. C | Page 6 of 20

AD7392/AD7393

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

1

2

3

4

5

6

7

8

9

20

19

V

DD

REF

OUT

SHDN

CS

V

1

2

3

4

5

6

7

8

9

20

19

V

DD

REF

OUT

18 AGND

17 DGND

16 D9

SHDN

CS

RS

D0

RS

18 AGND

17 DGND

16 D11

15 D10

14 D9

AD7393

NC

D0

TOP VIEW

AD7392

15 D8

(Not to Scale)

TOP VIEW

14 D7

D1

(Not to Scale)

D1

13 D6

D2

12 D5

D3

13 D8

D3 10

11 D4

D4

12 D7

D5 10

11 D6

NC = NO CONNECT

Figure 3. AD7392 Pin Configuration

Figure 4. AD7393 Pin Configuration

Table 4. AD7392 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

V_DD

SHDN

Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.

Power Shutdown Active Low Input. DAC register contents are saved as long as power stays on the V_DDpin. When

SHDN = 0, CS strobes write new data into the DAC register.

3

CS

Chip Select Latch Enable, Active Low.

Asynchronous Active Low Input. Resets the DAC register to 0.

Parallel Input Data Bits. D11 is the MSB; D0 is the LSB.

Digital Ground.

Analog Ground.

DAC Voltage Output.

4

RS

5 to 16

17

18

D0 to D11

DGND

AGND

V_OUT

19

20

V_REF

DAC Reference Input. Establishes the DAC full-scale voltage.

Table 5. AD7393 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

V_DD

SHDN

Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.

Power Shutdown Active Low Input. DAC register contents are saved as long as power stays on the V_DDpin.

When SHDN = 0, CS strobes write new data into the DAC register.

3

CS

Chip Select Latch Enable, Active Low.

Asynchronous Active Low Input. Resets the DAC register to 0.

No Connect.

Parallel Input Data Bits. D9 is the MSB; D0 is the LSB.

Digital Ground.

4

RS

5, 6

7 to 16

17

18

19

NC

D0 to D9

DGND

AGND

V_OUT

Analog Ground.

DAC Voltage Output.

20

V_REF

DAC Reference Input. Establishes the DAC full-scale voltage.

Rev. C | Page 7 of 20

AD7392/AD7393

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

100

90

80

70

60

50

40

30

20

10

0

V

T

= 2.7V

= 2.5V

= 25°C

AD7392

AD7393

DD

REF

0.8

0.6

SS = 300 UNITS

V

= 2.7V

A

DD

= 2.5V

REF

T

= 25°C

A

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

512

1024

1536

2048

2560

3072

3584

4096

–10 –3.3 3.3

10

16

23

30

36

43

50

CODE (Decimal)

TOTAL UNADJUSTED ERROR (LSB)

Figure 5. AD7392 Integral Nonlinearity Error vs. Code

Figure 8. AD7393 Total Unadjusted Error Histogram

1.0

0.8

30

24

18

12

6

V

= 2.7V

AD7393

DD

AD7393

= 2.5V

REF

SS = 100 UNITS

T

= 25°C

A

V

= 2.7V

DD

0.6

= 2.5V

REF

T

= –40°C TO +85°C

A

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

128

256

384

512

640

768

896

1024

–66 –60 –52 –46 –40 –32 –26 –20 –12 –6

FULL-SCALE TEMPERATURE COEFFICIENT (ppm/°C)

0

CODE (Decimal)

Figure 6. AD7393 Integral Nonlinearity Error vs. Code

Figure 9. AD7393 Full-Scale Output Temperature Coefficient Histogram

25

20

15

10

5

16

AD7392

SS = 100 UNITS

V

= 5V

DD

14

12

10

8

V

= 2.7V

= 2.5V

DD

REF

= 2.5V

T = 25°C

REF

A

T

= 25°C

A

6

4

2

0

5.0

5.8

6.6

7.3

8.1

8.9

9.7 10.5 11.2 12.0

1

10

100

1k

10k

100k

TOTAL UNADJUSTED ERROR (LSB)

FREQUENCY (Hz)

Figure 7. AD7392 Total Unadjusted Error Histogram

Figure 10. Voltage Noise Density vs. Frequency

Rev. C | Page 8 of 20

AD7392/AD7393

100

95

90

85

80

75

70

65

60

55

50

1000

800

600

400

200

0

AD7392

V

T

= 0V TO V TO 0V

DD

V

T

= 3V

LOGIC

DD

= 2.5V

= 25°C

V

FROM

REF

A

LOGIC

= 25°C

0V TO 3V

A

a

a. V = 5.5V, CODE = 0x155

DD

b. V = 5.5V, CODE = 0x3FF

DD

V

FROM

b

LOGIC

c. V = 2.7V, CODE = 0x155

DD

3V TO 0V

d. V = 2.7V, CODE = 0x355

DD

c

d

0

0.5

1.0

1.5

(V)

2.0

2.5

3.0

1k

10k

100k

CLOCK FREQUENCY (Hz)

1M

10M

V

IN

Figure 14. Supply Current vs. Clock Frequency

Figure 11. Supply Current vs. Logic Input Voltage

60

50

40

30

20

10

0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

T

= 25°C

AD7392

A

V

= 5V ± 5%

DD

CODE = 0xFFF

V

= 2V

REF

RS LOGIC VOLTAGE

VARIED

V

= 3V ± 5%

DD

V

FROM

LOGIC

HIGH TO LOW

V

FROM

LOGIC

LOW TO HIGH

10

100

FREQUENCY (Hz)

1k

10k

1

2

3

4

5

6

7

SUPPLY VOLTAGE (V)

Figure 15. Power Supply Rejection Ratio vs. Frequency

Figure 12. Logic Threshold vs. Supply Voltage

40

30

20

10

0

100

90

80

70

60

50

40

30

20

AD7392

V

= 5V

DD

SAMPLE SIZE = 300 UNITS

= 3V

REF

CODE = 0x000

V

= 5V, V

= 0V

DD

LOGIC

V

= 3.6V, V

= 2.4V

DD

LOGIC

V

= 3V, V

= 0V

DD

LOGIC

0

1

2

3

4

5

–55

–35

–15

5

25

45

65

85

105

125

V

(V)

TEMPERATURE (°C)

OUT

Figure 13. Supply Current vs. Temperature

Figure 16. I_OUTat Zero Scale vs. V_OUT

Rev. C | Page 9 of 20

AD7392/AD7393

5

0

2µs

AD7392

V

OUT

–5

(5mV/DIV)

V

= 5V

DD

= 100mV + 2V

REF

DC

–10

–15

–20

–25

–30

DATA = 0xFFF

V

f

= 5V

DD

CS

= 2.5V

REF

(5V/DIV)

= 50kHz

CODE: 0x7F TO 0x80

CLK

20mV

10

100

1k

FREQUENCY (Hz)

10k

100k

TIME (2µs/DIV)

Figure 17. Midscale Transition Performance

Figure 20. Reference Multiplying Bandwidth

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

AD7392

V

= 5V

DD

V

= 5V

5µs

DD

= 2.5V

CODE = 0x768

T = 25°C

A

REF

CS = HIGH

V

OUT

(5mV/DIV)

D0 TO D11

(5V/DIV)

5mV

0

1

2

3

4

5

TIME (5µs/DIV)

REFERENCE VOLTAGE (V)

Figure 18. Digital Feedthrough

Figure 21. Integral Nonlinearity Error vs. Reference Voltage

1.2

AD7392

SAMPLE SIZE = 50

100µs

AD7392

1.0

0.8

CODE = 0xFFF

V

OUT

(1V/DIV)

0.6

V

= 5V

= 2.5V

DD

0.4

CS

(5V/DIV)

V

CODE = 0x000

REF

0.2

0

1V

0

100

200

300

400

500

600

TIME (100µs/DIV)

HOURS OF OPERATION AT 150°C

Figure 19. Large Signal Settling Time

Figure 22. Long-Term Drift Accelerated by Burn-In

Rev. C | Page 10 of 20

AD7392/AD7393

1.0

0.8

V

T

= 2.7V

= 2.5V

= 25°C

AD7392

DD

REF

5V

500mV

AD7392 100µs

A

0.6

100

90

V

= 5V

DD

0.4

50

0

I

(µA)

DD

= 2.5V

REF

CODE = 0xFFF

0.2

0

R

T

= 1MΩ TO GND

= 25°C

L

2

0

1

0

V

(V)

–0.2

–0.4

–0.6

–0.8

–1.0

A

OUT

10

SHDN

0%

2V

0

512

1024

1536

2048

2560

3072

3584

4096

TIME (100µs/DIV)

CODE (Decimal)

Figure 23. Shutdown Recovery Time

Figure 25. AD7392 Differential Nonlinearity Error vs. Code

1.0

0.8

V

= 2.7V

1000

AD7393

DD

= 2.5V

AD7392

REF

T

= 25°C

A

0.6

0.4

0.2

0

100

–0.2

–0.4

–0.6

–0.8

–1.0

V

= 5.5V

DD

= 2.5V

REF

SHDN = 0V

0

128

256

384

512

640

768

896

1024

10

–55

–35

–15

5

25

45

65

85 105

125

CODE (Decimal)

TEMPERATURE (°C)

Figure 24. Shutdown Current vs. Temperature

Figure 26. AD7393 Differential Nonlinearity Error vs. Code

Rev. C | Page 11 of 20

AD7392/AD7393

THEORY OF OPERATION

The AD7392/AD7393 comprise a set of pin-compatible, 12-/10-

bit digital-to-analog converters (DACs). These single-supply

operation devices consume less than 100 μA of current while

operating from 2.7 V to 5.5 V power supplies, making them

ideal for battery-operated applications. They contain a voltage-

switched, 12-/10-bit, laser-trimmed DAC; rail-to-rail output op

amps; and a parallel input DAC register. The external reference

input has constant input resistance independent of the digital

code setting of the DAC. In addition, the reference input can be

tied to the same supply voltage as V_DD, resulting in a maximum

output voltage span of 0 V to V_DD. The parallel data interface

AMPLIFIER SECTION

The internal DACs output is buffered by a low power consump-

tion precision amplifier. The op amp has a 60 μs typical settling

time to 0.1% of full scale. There are slight differences in settling

time for negative slew signals vs. positive. Also, negative tran-

sition settling time to within the last 6 LSBs of 0 V has an extended

settling time. The rail-to-rail output stage of this amplifier has

been designed to provide precision performance while operating

near either power supply. Figure 27 shows an equivalent output

schematic of the rail-to-rail amplifier with its N-channel pull-

down FETs that pull an output load directly to GND. The

output sourcing current is provided by a P-channel, pull-up

device that can source current-to-GND terminated loads.

CS

consists of a

utilizing the AD7392 or 10 data bits (D0 to D9) if utilizing

RS

write strobe and 12 data bits (D0 to D11) if

the AD7393. An

pin is available to reset the DAC register to

V

DD

zero scale. This function is useful for power-on reset or system

failure recovery to a known state. Additional power savings are

P-CH

SHDN

V

accomplished by activating the

pin, resulting in a 1.5 μA

OUT

N-CH

maximum consumption sleep mode. While the supply voltage is

on, data is retained in the DAC register to reset the DAC output

AGND

SHDN

when the part is taken out of shutdown (

= 1).

Figure 27. Equivalent Analog Output Circuit

DIGITAL-TO-ANALOG CONVERTERS

The rail-to-rail output stage provides 1 mA of output current.

The N-channel output pull-down MOSFET, shown in Figure 27,

has a 35 Ω on resistance that sets the sink current capability

near ground. In addition to resistive load driving capability, the

amplifier also has been carefully designed and characterized for

up to 100 pF capacitive load driving capability.

The voltage switched R-2R DAC generates an output voltage

that depends on the external reference voltage connected to

the V_REFpin according to Equation 1.

D

V_OUT=V_REF

×

(1)

(2)

(3)

2^N

where:

REFERENCE INPUT

D is the decimal data-word loaded into the DAC register.

N is the number of bits of DAC resolution.

The reference input terminal has a constant input resistance

independent of digital code, which results in reduced glitches

on the external reference voltage source. The high 2.5 MΩ input

resistance minimizes power dissipation within the AD7392/

AD7393 DACs. The V_REFinput accepts input voltages ranging

from ground to the positive supply voltage V_DD. One of the

simplest applications for saving an external reference voltage

source is connecting the REF terminal to the positive V_DD

supply. This connection results in a rail-to-rail voltage output

span maximizing the programmed range. The reference input

If the 10-bit AD7393 uses a 2.5 V reference, Equation 1

becomes

D

V_OUT= 2.5×

1024

Using Equation 2, the nominal midscale voltage at V_OUTis

1.25 V, for D = 512; full-scale voltage is 2.497 V. The LSB

step size is 2.5 × 1/1024 = 0.0024 V.

If the 12-bit AD7392 uses a 5.0 V reference, Equation 1

becomes

accepts ac signals as long as they stay within the 0 V < V_REF

<

V_DDsupply voltage range. The reference bandwidth and integral

nonlinearity error performance are plotted in Figure 20 and

Figure 21. The ratiometric reference feature makes the AD7392/

AD7393 an ideal companion to ratiometric analog-to-digital

converters (ADCs) such as the AD7896.

D

4096

V_OUT= V_REF

×

Using Equation 3, the AD7392 provides a nominal midscale volt-

age of 2.50 V (for D = 2048) and a full-scale V_OUTof 4.998 V.

The LSB step size is 5.0 × 1/4096 = 0.0012 V.

Rev. C | Page 12 of 20

AD7392/AD7393

To minimize power dissipation from input logic levels that

are near the V_IHand V_ILlogic input voltage specifications, a

Schmitt-trigger design was used that minimizes the input

buffer current consumption compared to traditional CMOS

input stages. Figure 11 is a plot of supply current vs. incremental

input voltage, showing that negligible current consumption

takes place when logic levels are in their quiescent state. The

normal crossover current still occurs during logic transitions.

A secondary advantage of this Schmitt trigger is the prevention

of false triggers that would occur with slow moving logic transi-

tions when a standard CMOS logic interface or opto-isolators

POWER SUPPLY

The very low power consumption of the AD7392/AD7393 is

a direct result of a circuit design that optimizes the CBCMOS

process. By using the low power characteristics of CMOS for the

logic and the low noise, tight-matching of the complementary

bipolar transistors, excellent analog accuracy is achieved. One

advantage of the rail-to-rail output amplifiers used in the AD7392/

AD7393 is the wide range of usable supply voltage. The part is

fully specified and tested for operation from 2.7 V to 5.5 V.

FERRITE BEAD:

2 TURNS, FAIR-RITE

#2677006301

CS RS

SHDN

are used. Logic inputs D11 to D0,

the Schmitt-trigger circuits.

,

, and

all contain

5V

TTL/CMOS

LOGIC

CIRCUITS

+

100µF

ELECT.

10µF TO 22µF 0.1µF

TANT. CER.

DIGITAL INTERFACE

5V

RETURN

The AD7392/AD7393 have a parallel data input. A functional

block diagram of the digital section is shown in Figure 31,

while Table 6 contains the truth table for the logic control

5V

POWER SUPPLY

CS

inputs. The chip select pin ( ) controls loading of data from

the data inputs on Pin D11 to Pin D0. This active low input

places the input register into a transparent state allowing the

data inputs to directly change the DAC ladder values. When

Figure 28. Use Separate Traces to Reduce Power Supply Noise

Whether or not a separate power supply trace is available, gen-

erous supply bypassing reduces supply line induced errors. Local

supply bypassing, consisting of a 10 μF tantalum electrolytic in

parallel with a 0.1 μF ceramic capacitor, is recommended for all

applications (see Figure 29).

CS

returns to logic high within the data setup-and-hold time

specifications, the new value of data in the input register are

latched. See Table 6 for a complete listing of conditions.

1 OF 12 LATCHES

OF THE

DAC REGISTER

2.7V TO 5.5V

20

1

*

C

0.1µF

V

REF

DD

TO

Dx

+

INTERNAL

AD7392

OR

10µF

DAC SWITCHES

D0 TO D11

CS

RS

AD7393

SHDN

19

V

2

OUT

3

4

CS

RS

GND

17, 18

Figure 31. Digital Control Logic

* OPTIONAL EXTERNAL

REFERENCE BYPASS

Table 6. Control Logic Truth Table

CS

RS

DAC Register Function

Figure 29. Recommended Supply Bypassing for the AD7392/AD7393

H

L

H

L

Latched

Transparent

Latched with new data

Loaded with all zeros

Latched all zeros

INPUT LOGIC LEVELS

1

↑

All digital inputs are protected with a Zener-type ESD protection

structure that allows logic input voltages to exceed the V_DDsupply

voltage (see Figure 30). This feature is useful if the user is driving

one or more of the digital inputs with a 5 V CMOS logic input

voltage level while operating the AD7392/AD7393 on a 3 V

power supply. If this interface is used, make sure that the V_OL

of the 5 V CMOS meets the V_ILinput requirement of the AD7392/

AD7393 operating at 3 V. See Figure 12 for a graph of digital

logic input threshold vs. operating V_DDsupply voltage.

X²

1

H

↑

¹↑ = Positive logic transition.

²X = Don’t care.

V

DD

1kΩ

LOGIC

IN

GND

Figure 30. Equivalent Digital Input ESD Protection

Rev. C | Page 13 of 20

AD7392/AD7393

RESET PIN (RS)

UNIPOLAR OUTPUT OPERATION

This is the basic mode of operation for the AD7392. The

AD7392 is designed to drive loads as low as 5 kΩ in parallel

with 100 pF (see Figure 32). The code table for this operation is

shown in Table 7.

RS

Forcing the asynchronous

pin low sets the DAC register to

all 0s, so the DAC output voltage is 0 V. The reset function is

useful for setting the DAC outputs to 0 at power-up or after a

power supply interruption. Test systems and motor controllers

are two of many applications that benefit from powering up to a

known state. The external reset pulse can be generated by three

methods:

The circuit can be configured with an external reference

plus power supply or powered from a single dedicated regu-

lator or reference depending on the application performance

requirements.

•

The microprocessor’s power-on RESET signal

An output from the microprocessor

An external resistor and capacitor

2.7V TO 5.5V

R

1

0.1µF

10µF

0.01µF

V

DD

RESET has a Schmitt-trigger input, which results in a clean

reset function when using external resistor-/capacitor-generated

pulses (see Table 6).

AD7392

20

19

EXT

REF

V

OUT

REF

R

≥5kΩ

C

L

≥100pF

L

GND

17, 18

POWER SHUTDOWN (SHDN)

Maximum power savings can be achieved by using the power

shutdown control function. This hardware-activated feature is

NOTES

1. DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY

Figure 32. AD7392 Unipolar Output Operation

SHDN

controlled by the active low input

pin. This pin has a

Schmitt-trigger input that helps desensitize it to slowly changing

inputs. Setting this pin to logic low reduces the internal con-

sumption of the AD7392/AD7393 to nanoamp levels, guaranteed

to 1.5 μA maximum over the operating temperature range. If

power is present at all times on the V_DDpin while in shutdown

mode, the internal DAC register retains the last programmed

data value. The digital interface is still active in shutdown so

that code changes can be made that produce new DAC settings

when the device is taken out of shutdown. This data is used

when the part is returned to the normal active state by placing

the DAC back to its programmed voltage setting. Figure 23

shows a plot of shutdown recovery time with both I_DDand V_OUT

displayed. In the shutdown state, the DAC output amplifier

exhibits an open-circuit high resistance state. Any load that is

connected stabilizes at its termination voltage. If the power

Table 7. Unipolar Code Table

DAC Register No.

Hexadecimal

0xFFF

0x801

0x800

0x7FF

Decimal

4095

2049

2048

2047

0

Output Voltage (V), V_REF= 2.5 V

2.4994

1.2506

1.2500

1.2494

0

0x000

SHDN

shutdown feature is not needed, the user should tie the

pin to the V_DDvoltage to disable this function.

Rev. C | Page 14 of 20

AD7392/AD7393

If higher resolution is required, the AD7392 can be used with

two additional bits of data inserted into the software coding,

which results in a 2.5 mV LSB step size. Table 8 shows examples

of nominal output voltages (V_O) provided by the bipolar

operation circuit application.

BIPOLAR OUTPUT OPERATION

Although the AD7393 is designed for single-supply operation,

the output can be easily configured for bipolar operation. A

typical circuit is shown in Figure 33. This circuit uses a clean,

regulated 5 V supply for power, which also provides the circuit’s

reference voltage. Since the AD7393 output span swings from

ground to very near 5 V, it is necessary to choose an external

amplifier with a common-mode input voltage range that extends

to its positive supply rail. The micropower consumption OP196

is designed just for this purpose and results in only 50 μA of

maximum current consumption. Connecting the two 470 kΩ

resistors results in a differential amplifier mode of operation

with a voltage gain of 2, which produces a circuit output span

of 10 V, that is, −5 V to +5 V. As the DAC is programmed from

zero-code 0x000 to midscale 0x200 to full scale 0x3FF, the circuit

output voltage, V_O, is set at −5 V, 0 V, and +5 V (minus 1 LSB).

The output voltage, V_O, is coded in offset binary according to

Equation 4.

I

<162µA

SY

+5V

470kΩ

<2µA

<100µA

<50µA

C

+5V

–5V

BIPOLAR

OUTPUT

SWING

V

DD

REF

V

O

OP196

V

OUT

AD7393

GND

–5V

NOTES

1. DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY

Figure 33. Bipolar Output Operation

Table 8. Bipolar Code Table

DAC Register No.

Hexadecimal

0x3FF

0x201

0x200

0x1FF

Decimal

1023

513

512

511

Analog Output Voltage (V)

D

512

⎡

⎤

V_O=

−1 ×5

(4)

⎢

⎣

⎥

⎦

+4.9902

+0.0097

0.0000

−0.0097

−5.0000

where D is the decimal code loaded in the AD7393 DAC

register.

Note that the LSB step size is 10/1024 = 10 mV. This circuit

0x000

0

is optimized for micropower consumption including the 470 kΩ

gain setting resistors, which should have low temperature

coefficients to maintain accuracy and matching (preferably the

same resistor material, such as metal film).

If better stability is required, the power supply may be substi-

tuted with a precision reference voltage such as the low dropout

REF195, which can easily supply the circuit’s 162 μA of current,

and still provide additional power for the load connected to V_O.

The micropower REF195 is guaranteed to source 10 mA output

drive current, but consumes only 50 μA internally.

Rev. C | Page 15 of 20

AD7392/AD7393

OUTLINE DIMENSIONS

1.060 (26.92)

1.030 (26.16)

0.980 (24.89)

20

1

11

10

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.100 (2.54)

BSC

0.060 (1.52)

MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.210 (5.33)

MAX

0.015

(0.38)

MIN

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.015 (0.38)

GAUGE

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

PLANE

SEATING

PLANE

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.430 (10.92)

MAX

0.005 (0.13)

MIN

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 34. 20-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body

(N-20)

Dimensions shown in inches and (millimeters)

13.00 (0.5118)

12.60 (0.4961)

20

1

11

10

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

0.75 (0.0295)

0.25 (0.00

98)

45°

2.65 (0.1043)

2.35 (0.0925)

0.30 (0.0118)

0.10 (0.0039)

8°

0°

COPLANARITY

0.10

SEATING

PLANE

0.51 (0.0201)

0.31 (0.0122)

1.27 (0.0500)

0.40 (0.0157)

1.27

(0.0500)

BSC

0.33 (0.0130)

0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 35. 20-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-20)

Dimensions shown in millimeters and (inches)

Rev. C | Page 16 of 20

AD7392/AD7393

ORDERING GUIDE

Model

Resolution (Bits)

Temperature Range

−40°C to +85°C

−40°C to +125°C

Package Description

20-Lead PDIP

20-Lead SOIC_W

20-Lead PDIP

Package Option

N-20

RW-20

N-20

AD7392AN

AD7392ANZ¹

AD7392AR

AD7392AR-REEL

AD7392ARZ¹

AD7392ARZ-REEL¹

AD7393AN

AD7393AR

AD7393ARZ¹

12

10

20-Lead SOIC_W

RW-20

¹Z = RoHS Compliant Part.

Rev. C | Page 17 of 20

AD7392/AD7393

NOTES

Rev. C | Page 18 of 20

AD7392/AD7393

NOTES

Rev. C | Page 19 of 20

AD7392/AD7393

NOTES

registered trademarks are the property of their respective owners.

C01121-0-8/07(C)

Rev. C | Page 20 of 20


型号：	AD7393_15
厂家：	ADI
描述：	3 V, Parallel Input Micropower 10-/12-Bit DACs
文件：	总20页 (文件大小：458K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7393_15 [ADI]

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