AD7392 [ADI]
3 V, Parallel Input Micropower 10- and 12-Bit DACs; 3 V ，并行输入微功耗10位和12位DAC
| 型号： | AD7392 |
| 厂家： | 
ADI |
| 描述： | 3 V, Parallel Input Micropower 10- and 12-Bit DACs |
| 文件： | 总11页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
+3 V, Parallel Input
a
Micropower 10- and 12-Bit DACs
AD7392/AD7393
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Micropower: 100 A
0.1 A Typical Power Shutdown
Single-Supply +2.7 V to +5.5 V Operation
Compact 1.1 mm Height TSSOP-20 Package
AD7392/12-Bit Resolution
AD7393/10-Bit Resolution
0.9 LSB Differential Nonlinearity Error
AD7392
V
DD
12-BIT
DAC
V
REF
V
OUT
SHDN
12
DAC REGISTER
AGND
12
APPLICATIONS
DGND
CS
DB0–DB11 RS
Automotive 0.5 V to 4.5 V Output Span Voltage
Portable Communications
Digitally Controlled Calibration
PC Peripherals
GENERAL DESCRIPTION
Additionally, an asynchronous RS input sets the output to zero
The AD7392/AD7393 family of 10- and 12-bit voltage-output
digital-to-analog converters is designed to operate from a single
+3 V supply. Built using a CBCMOS process, these monolithic
DACs offer the user low cost and ease of use in single-supply
+3 V systems. Operation is guaranteed over the supply voltage
range of +2.7 V to +5.5 V, making this device ideal for battery
operated applications.
scale at power on or upon user demand.
Both parts are offered in the same pinout to allow users to select
the amount of resolution appropriate for their applications
without circuit card changes.
The AD7392/AD7393 are specified for operation over the ex-
tended industrial (–40°C to +85°C) temperature range. The
AD7393AR is specified for the –40°C to +125°C automotive
temperature range. AD7392/AD7393s are available in plastic
DIP, and 20-lead SOIC packages. The AD7393ARU is avail-
able for ultracompact applications in a thin 1.1 mm height
TSSOP-20 package.
The full-scale voltage output is determined by the external
reference input voltage applied. The rail-to-rail REFIN to
DACOUT allows for a full-scale voltage set equal to the positive
supply VDD or any value in between. The voltage outputs are
capable of sourcing 5 mA.
For serial data input, 8-lead packaged versions, see the AD7390
and AD7391 products.
A 12-bit wide data latch loads with a 45 ns write time allowing
interface to the fastest processors without wait states.
1
1
AD7393
AD7392
V
V
T
= +2.7V
= +2.5V
V
V
T
= +2.7V
= +2.5V
0.8
0.6
DD
DD
0.8
0.6
REF
REF
= 25؇C
= 25؇C
A
A
0.4
0.4
0.2
0.2
0
0
؊0.2
؊0.4
؊0.6
؊0.8
؊1
؊0.2
؊0.4
؊0.6
؊0.8
؊1
0
128
256
384
512
640
768
896
1024
0
512
1024 1536
2048 2560
3072 3584
4096
CODE – Decimal
CODE – Decimal
Figure 1. AD7392 Differential Nonlinearity Error vs. Code
Figure 2. AD7393 Differential Nonlinearity Error vs. Code
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD7392/AD7393–SPECIFICATIONS
AD7392 ELECTRICAL CHARACTERISTICS (@ VREF IN = 2.5 V, ؊40
؇
C < TA < ؉85
؇C, unless otherwise noted)
Parameter
Symbol
Conditions
3 V ؎ 10% 5 V ؎ 10%
Units
STATIC PERFORMANCE
Resolution1
N
INL
12
Ϯ1.8
Ϯ3
Ϯ0.9
Ϯ1
12
Ϯ1.8
Ϯ3
Ϯ0.9
Ϯ1
4.0
8.0
Ϯ8
Ϯ20
28
Bits
Relative Accuracy2
TA = ϩ25°C
LSB max
LSB max
LSB max
LSB max
mV max
mV max
mV max
mV max
ppm/°C typ
TA = Ϫ40°C, ϩ85°C
TA = ϩ25°C, Monotonic
Monotonic
Differential Nonlinearity2
Zero-Scale Error
DNL
VZSE
Data = 000H, TA = ϩ25°C, ϩ85°C 4.0
Data = 000H, TA = –40°C 8.0
TA = ϩ25°C, ϩ85°C, Data = FFFH Ϯ8
Full-Scale Voltage Error
VFSE
TA = Ϫ40°C, Data = FFFH
Ϯ20
28
Full-Scale Tempco3
TCVFS
REFERENCE INPUT
V
REF IN Range
VREF
RREF
CREF
0/VDD
2.5
5
0/VDD
2.5
5
V min/max
MΩ typ4
pF typ
Input Resistance
Input Capacitance3
ANALOG OUTPUT
Current (Source)
IOUT
IOUT
CL
Data = 800H, ∆VOUT = 5 LSB
Data = 800H, ∆VOUT = 5 LSB
No Oscillation
1
3
100
1
3
100
mA typ
mA typ
pF typ
Output Current (Sink)
Capacitive Load3
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance3
VIL
VIH
IIL
0.5
0.8
V max
V min
µA max
pF max
V
DDϪ0.6
V
DDϪ0.6
10
10
10
10
CIL
INTERFACE TIMING3, 5
Chip Select Write Width
Data Setup
Data Hold
Reset Pulsewidth
tCS
tDS
tDH
tRS
45
30
20
40
45
15
5
ns min
ns min
ns min
ns min
30
AC CHARACTERISTICS
Output Slew Rate
Settling Time6
Shutdown Recovery Time
DAC Glitch
Digital Feedthrough
Feedthrough
SR
tS
tSDR
Q
Data = 000H to FFFH to 000H
To ±0.1% of Full Scale
0.05
70
0.05
60
80
65
15
V/µs typ
µs typ
µs typ
nV/s typ
nV/s typ
Code 7FFH to 800H to 7FFH
65
15
Q
VOUT/VREF VREF = 1.5 V dc +1 V p-p,
Data = 000H, f = 100 kHz
–63
–63
dB typ
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Shutdown Supply Current
Power Dissipation
VDD RANGE DNL < Ϯ1 LSB
2.7/5.5
55/100
0.1/1.5
300
2.7/5.5
55/100
0.1/1.5
500
V min/max
µA typ/max
µA typ/max
µW max
IDD
VIL = 0 V, No Load
SHDN = 0, VIL = 0 V, No Load
VIL = 0 V, No Load
∆VDD = Ϯ5%
IDD SD
–
PDISS
PSS
Power Supply Sensitivity
0.006
0.006
%/% max
NOTES
1One LSB = VREF/4096 V for the 12-bit AD7392.
2The first two codes (000H, 001H) are excluded from the linearity error measurement.
3These parameters are guaranteed by design and not subject to production testing.
4Typicals represent average readings measured at +25°C.
5All input control signals are specified with tR = tF = 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.
6The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
REV. A
–2–
AD7392/AD7393
(@ VREF IN = 2.5 V, ؊40
؇
C < T < ؉85
؇
C, unless otherwise noted)
AD7393 ELECTRICAL CHARACTERISTICS
A
Parameter
Symbol
Conditions
3 V ؎ 10% 5 V ؎ 10%
Units
STATIC PERFORMANCE
Resolution1
N
INL
10
10
Bits
Relative Accuracy2
TA = ϩ25°C
TA = Ϫ40°C, ϩ85°C, ϩ125°C
Monotonic
Data = 000H
TA = ϩ25°C, ϩ85°C, ϩ125°C,
Data = 3FFH
Ϯ1.75
Ϯ2.0
Ϯ0.8
9.0
Ϯ1.75
Ϯ2.0
Ϯ0.8
9.0
LSB max
LSB max
LSB max
mV max
mV max
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage Error
DNL
VZSE
VFSE
Ϯ32
Ϯ32
TA = Ϫ40°C, Data = 3FFH
Ϯ42
28
Ϯ42
28
mV max
ppm/°C typ
Full-Scale Tempco3
TCVFS
REFERENCE INPUT
V
REF IN Range
VREF
RREF
CREF
0/VDD
2.5
5
0/VDD
2.5
5
V min/max
MΩ typ4
pF typ
Input Resistance
Input Capacitance3
ANALOG OUTPUT
Output Current (Source)
Output Current (Sink)
Capacitive Load3
IOUT
IOUT
CL
Data = 200H, ∆VOUT = 5 LSB
Data = 200H, ∆VOUT = 5 LSB
No Oscillation
1
3
100
1
3
100
mA typ
mA typ
pF typ
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance3
VIL
VIH
IIL
0.5
0.8
V max
V min
µA max
pF max
V
DDϪ0.6
V
DDϪ0.6
10
10
10
10
CIL
INTERFACE TIMING3, 5
Chip Select Write Width
Data Setup
Data Hold
Reset Pulsewidth
tCS
tDS
tDH
tRS
45
30
20
40
45
15
5
ns
ns
ns
ns
30
AC CHARACTERISTICS
Output Slew Rate
Settling Time6
Shutdown Recovery Time
DAC Glitch
Digital Feedthrough
Feedthrough
SR
tS
tSDR
Q
Data = 000H to 3FFH to 000H
To Ϯ0.1% of Full Scale
0.05
70
0.05
60
80
65
15
V/µs typ
µs typ
µs typ
nV/s typ
nV/s typ
Code 7FFH to 800H to 7FFH
65
15
Q
VOUT/VREF VREF = 1.5 V dc ϩ1 V p-p,
Data = 000H, f = 100 kHz
–63
–63
dB typ
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
VDD RANGE DNL < Ϯ1 LSB
2.7/5.5
55
100
2.7/5.5
55
100
V min/max
µA typ
µA max
IDD
VIL = 0 V, No Load, TA = ϩ25°C
VIL = 0 V, No Load
Shutdown Supply Current
Power Dissipation
Power Supply Sensitivity
IDD SD
PDISS
PSS
SHDN = 0, VIL = 0 V, No Load
VIL = 0 V, No Load
∆VDD = Ϯ5%
0.1/1.5
300
0.006
0.1/1.5
500
0.006
µA typ/max
µW max
%/% max
–
NOTES
1One LSB = VREF/1024 V for the 10-bit AD7393.
2The first two codes (000H, 001H) are excluded from the linearity error measurement.
3These parameters are guaranteed by design and not subject to production testing.
4Typicals represent average readings measured at +25°C.
5All input control signals are specified with tR = tF = 2 ns (10% to 90% of ϩ3 V) and timed from a voltage level of 1.6 V.
6The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
REV. A
–3–
AD7392/AD7393
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATIONS
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VOUT to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +2 V
Package Power Dissipation . . . . . . . . . . . . . (TJ max – TA)/θJA
Thermal Resistance θJA
20-Lead Plastic DIP Package (N-20) . . . . . . . . . . . 57°C/W
20-Lead SOIC Package (R-20) . . . . . . . . . . . . . . . . 60°C/W
20-Lead Thin-Shrink Surface Mount (RU-20) . . . 155°C/W
Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
AD7393AR . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature
1
2
20
19
1
2
20
19
V
V
V
V
V
V
DD
REF
DD
REF
SHDN
CS
SHDN
CS
OUT
OUT
3
4
3
4
18
17
18
17
AGND
DGND
D11
AGND
DGND
D9
RS
RS
5
6
5
6
D0
D1
D2
D3
16
NC
NC
D0
D1
16
AD7392
TOP VIEW
(Not to Scale)
AD7393
TOP VIEW
(Not to Scale)
15 D10
15 D8
7
8
14
7
8
14
D7
D9
13 D8
13 D6
9
9
D4
D5
12 D7
11 D6
D2
D3
12 D5
11 D4
10
10
NC = NO CONNECT
PIN DESCRIPTION
Function
#
Name
N-20 (Soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . .+300°C
R-20 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . . . . . .+215°C
RU-20 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . . . . .+220°C
1
VDD
Positive Power Supply Input. Specified range
of operation +2.7 V to +5.5 V.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
SHDN
Power Shutdown active low input. DAC regis-
ter contents are saved as long as power stays on
the VDD pin. When SHDN = 0, CS strobes will
write new data into the DAC register.
3
4
CS
RS
Chip Select latch enable, active low.
Resets DAC register to zero condition. Asyn-
chronous active low input.
1
tCS
CS
0
tDS
tDH
5, 6 NC
No connect Pins 5 and 6 on the AD7393.
1
17 DGND Digital Ground.
18 AGND Analog Ground.
DB11–DB0
DATA VALID
0
1
19 VOUT
DAC Voltage Output.
tRS
20 VREFIN
DAC Reference Input Pin. Establishes DAC
full-scale voltage.
RS
0
D0–D11 12 parallel input data bits. D11 = MSB Pin 16,
D0 = LSB Pin 5, AD7392.
D0–D9 10 parallel input data bits. D9 = MSB. Pin 16,
D0 = LSB Pin 7, AD7393.
FS
ZS
؎0.1% FS
ERROR BAND
V
OUT
tS
tS
Figure 3. Timing Diagram
ORDERING GUIDE
1 OF 12 LATCHES
Res
(LSB) Temp
Package
Description
Package
Option
OF THE
DAC REGISTER
Model
AD7392AN 12
AD7392AR 12
AD7393AN 10
AD7393AR 10
XIND
XIND
XIND
20-Lead P-DIP N-20
20-Lead SOIC R-20
20-Lead P-DIP N-20
TO
DB
X
INTERNAL
DAC
SWITCHES
CS
AUTO 20-Lead SOIC R-20
XIND TSSOP-20 RU-20
AD7393ARU 10
RS
NOTES
XIND = –40°C to +85°C; AUTO = –40°C to +125°C.
The AD7392 contains 709 transistors. The die size measures 78 mil × 85 mil =
Figure 4. Digital Control Logic
6630 sq. mil.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7392/AD7393 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–4–
Typical Performance Characteristics–AD7392/AD7393
1
0.8
1
25
20
15
10
AD7392
AD7393
AD7392
SS = 100 UNITS
V
V
T
= 2.7V
DD
0.8
= 2.5V
REF
T
= 25؇C
A
0.6
= 25؇C
0.6
A
V
V
= 2.7V
DD
0.4
0.4
= 2.5V
REF
0.2
0
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
–0.2
–0.4
–0.6
–0.8
–1
V
V
T
= 2.7V
DD
= 2.5V
REF
= 25؇C
5
0
A
0
512 1024 1536 2048 2560 3072 3584 4096
CODE – Decimal
0
128 256 384 512 640 768 896 1024
CODE – Decimal
5.0 5.8 6.6 7.3 8.1 8.9 9.7 10.5 11.2 12.0
TOTAL UNADJUSTED ERROR – LSB
Figure 5. AD7392 Integral Nonlinear-
ity Error vs. Code
Figure 6. AD7393 Integral Nonlinear-
ity Error vs. Code
Figure 7. AD7392 Total Unadjusted
Error Histogram
16
100
30
AD7392
AD7393
AD7393
SS = 100 UNITS
V
V
T
= 5V
90
DD
SS = 300 UNITS
14
12
10
8
= 2.5V
T
= 25؇C
REF
T
= ؊40؇ to 85؇C
A
A
80
70
60
50
40
30
20
10
0
24
18
12
6
= 25؇C
V
V
= 2.7V
A
DD
V
V
= 2.7V
DD
= 2.5V
REF
= 2.5V
REF
6
4
2
0
0
1
10
100
1k
10k
100k
–10 –3.3 3.3 10 16 23 30 36 43 50
TOTAL UNADJUSTED ERROR – LSB
–66 –60 –52 –46 –40 –32 –26 –20 –12 –6
0
FREQUENCY – Hz
FULL SCALE TEMPCO – ppm/؇C
Figure 10. Voltage Noise Density vs.
Frequency
Figure 8. AD7393 Total Unadjusted
Error Histogram
Figure 9. AD7393 Full-Scale Output
Tempco Histogram
100
100
5.0
AD7392
AD7392
A
AD7392
CODE = FFF
95
90
85
80
75
70
65
60
55
50
T
= 25؇C
SAMPLE SIZE = 300 UNITS
4.5
90
H
V
FROM
V
= 3.0V
LOGIC
DD
V
= 2V
REF
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
= 5.0V, V
= 0V
0V TO 3.0V
DD
LOGIC
RS LOGIC VOLTAGE
VARIED
80
70
60
50
40
30
20
V
= 3.6V, V
= 2.4V
DD
LOGIC
V
FROM
LOGIC
V
FROM
HIGH TO LOW
LOGIC
3.0V TO 0V
V
FROM
LOGIC
V
= 3.0V, V
= 0V
DD
LOGIC
LOW TO HIGH
؊55 ؊35 ؊15
5
25 45 65 85 105 125
0.0
0.5
1.0
1.5
2.0
2.5
3.0
1
2
3
4
5
6
7
TEMPERATURE – ؇C
V
– Volts
SUPPLY VOLTAGE – V
IN
Figure 12. Logic Threshold vs.
Supply Voltage
Figure 13. Supply Current vs.
Temperature
Figure 11. Supply Current vs. Logic
Input Voltage
REV. A
–5–
AD7392/AD7393
1000
40
30
20
10
0
60
50
40
30
20
10
0
AD7393
LOGIC
V
V
= 5V ؎ 5%
T = 25؇C
A
DD
V
V
= 0V TO V TO 0V
DD
= 2.5V
REF
800
600
400
200
0
T
= 25؇C
A
V
V
= +5V
DD
= +3V
REF
a
b
CODE = ØØØ
= 3V ؎ 5%
H
a. V = 5.5V, CODE = 155
DD
DD
H
b. V = 5.5V, CODE = 3FF
DD
H
c. V = 2.7V, CODE = 155
DD
H
c
d. V
DD
= 2.7V, CODE = 355
H
d
1k
10k
100k
1M
10M
0
1
2
3
4
5
10
100
1k
10k
CLOCK FREQUENCY – Hz
V
– V
OUT
FREQUENCY – Hz
Figure 16. IOUT at Zero Scale vs. VOUT
Figure 14. Supply Current vs. Clock
Frequency
Figure 15. Power Supply Rejection
vs. Frequency
TIME – 100s/DIV
TIME – 2s/DIV
TIME – 5s/DIV
Figure 19. Large Signal Settling Time
Figure 17. Midscale Transition
Performance
Figure 18. Digital Feedthrough
1.2
5
0
2.0
AD7392
AD7392
1.8
SAMPLE SIZE = 50
1.0
V
= +5V
DD
CODE = 768
H
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
T
= 25؇C
A
؊5
0.8
V
V
= +5V
DD
CODE = FFF
H
؊10
؊15
= +100mV + 2V
REF
DC
DATA = FFF
0.6
0.4
0.2
0.0
H
؊20
؊25
؊30
CODE = 000
H
10
100
1k
FREQUENCY – Hz
10k
100k
0
100
200
300
400
500
600
0
1
2
3
4
5
HOURS OF OPERATION AT 150؇C
REFERENCE VOLTAGE – V
Figure 22. Long-Term Drift
Accelerated by Burn-in
Figure 20. Reference Multiplying
Bandwidth
Figure 21. INL Error vs. Reference
Voltage
REV. A
–6–
AD7392/AD7393
1000
100
10
AD7392
100
50
0
100
90
IDD (A)
2
V
(V)
OUT
0
1
0
V
V
= 5.5V
= 2.5V
DD
10
REF
0%
SHDN = 0V
SHDN
–55 –35 –15
65 85 105 125
5
25 45
TIME – 100s/DIV
TEMPERATURE – ؇C
Figure 23. Shutdown Recovery Time
Figure 24. Shutdown Current vs. Temperature
Table I. Control Logic Truth Table
CS
RS
DAC Register Function
H
L
↑
X
H
H
H
H
L
Latched
Transparent
Latched with New Data
Loaded with All Zeros
Latched all Zeros
↑
NOTE
↑ Positive logic transition; X Don’t Care.
OPERATION
D/A CONVERTER SECTION
The AD7392 and AD7393 comprise a set of pin compatible,
12-bit/10-bit digital-to-analog converters. These single-supply
operation devices consume less than 100 microamps of current
while operating from power supplies in the +2.7 V to +5.5 V
range making them ideal for battery operated applications. They
contain a voltage-switched, 12-bit/10-bit, laser-trimmed digital-
to-analog converter, rail-to-rail output op amps, and a parallel-
input DAC register. The external reference input has constant
input resistance independent of the digital code setting of the
DAC. In addition, the reference input can be tied to the same
supply voltage as VDD, resulting in a maximum output voltage
span of 0 to VDD. The parallel data interface consists of 12 data
bits, DB0–DB11, for the AD7392; 10 data bits, DB0–DB9, for
the AD7393; and a CS write strobe. A RS pin is available to
reset the DAC register to zero scale. This function is useful for
power-on reset or system failure recovery to a known state.
Additional power savings are accomplished by activating the
SHDN pin, resulting in a 1.5 µA maximum consumption sleep
mode. As long as the supply voltage remains, data will be re-
tained in the DAC register to reset the DAC output when the
part is taken out of shutdown (SHDN = 1).
The voltage switched R-2R DAC generates an output voltage
dependent on the external reference voltage connected to the
REF pin according to the following equation:
D
2N
VOUT =VREF
×
Equation 1
where D is the decimal data word loaded into the DAC register,
and N is the number of bits of DAC resolution. In the case of
the 10-bit AD7393 using a 2.5 V reference, Equation 1 simpli-
fies to:
D
1024
VOUT = 2.5 ×
Equation 2
Using Equation 2, the nominal midscale voltage at VOUT is 1.25 V
for D = 512; full-scale voltage is 2.497 volts. The LSB step size is
= 2.5 × 1/1024 = 0.0024 volts.
For the 12-bit AD7392 operating from a 5.0 V reference Equa-
tion 1 becomes:
D
2N
VOUT =VREF
×
Equation 3
Using Equation 3, the AD7392 provides a nominal midscale
voltage of 2.50 V for D = 2048, and a full-scale output of 4.998
volts. The LSB step size is = 5.0 × 1/4096 = 0.0012 volts.
REV. A
–7–
AD7392/AD7393
AMPLIFIER SECTION
POWER SUPPLY BYPASSING AND GROUNDING
The internal DAC’s output is buffered by a low power con-
sumption precision amplifier. The op amp has a 60 µs typical
settling time to 0.1% of full scale. There are slight differences in
settling time for negative slewing signals versus positive. Also,
negative transition settling-time to within the last 6 LSBs of
zero volts has an extended settling time. The rail-to-rail output
stage of this amplifier has been designed to provide precision
performance while operating near either power supply. Figure
25 shows an equivalent output schematic of the rail-to-rail-
amplifier with its N-channel pull-down FETs that will pull an
output load directly to GND. The output sourcing current is
provided by a P-channel pull-up device that can source current
to GND terminated loads.
Precision analog products, such as the AD7392/AD7393, require a
well filtered power source. Since the AD7392/AD7393 oper-
ate from a single +3 V to +5 V supply, it seems convenient to
simply tap into the digital logic power supply. Unfortunately,
the logic supply is often a switch-mode design, which generates
noise in the 20 kHz to 1 MHz range. In addition, fast logic gates
can generate glitches of hundreds of millivolts in amplitude due
to wiring resistance and inductance. The power supply noise
generated as a result means that special care must be taken to
assure that the inherent precision of the DAC is maintained.
Good engineering judgment should be exercised when address-
ing the power supply grounding and bypassing of the AD7392.
The AD7392 should be powered directly from the system power
supply. This arrangement, shown in Figure 26, employs an LC
filter and separate power and ground connections to isolate the
analog section from the logic switching transients.
V
DD
P-CH
N-CH
V
OUT
FERRITE BEAD:
2 TURNS, FAIR-RITE
#2677006301
+5V
TTL/CMOS
LOGIC
CIRCUITS
AGND
100F
ELECT.
10-22F
TANT.
0.1F
CER.
Figure 25. Equivalent Analog Output Circuit
+5V
RETURN
The rail-to-rail output stage provides ±1 mA of output current.
The N-channel output pull-down MOSFET, shown in Figure
25, has a 35 Ω ON resistance that sets the sink current capability
near ground. In addition to resistive load driving capability, the
amplifier also has been carefully designed and characterized for
up to 100 pF capacitive load driving capability.
+5V
POWER SUPPLY
Figure 26. Use Separate Traces to Reduce Power Supply
Noise
REFERENCE INPUT
Whether or not a separate power supply trace is available, gener-
ous supply bypassing will reduce supply line induced errors.
Local supply bypassing, consisting of a 10 µF tantalum electro-
lytic in parallel with a 0.1 µF ceramic capacitor, is recom-
mended in all applications (Figure 27).
The reference input terminal has a constant input resistance
independent of digital code, which results in reduced glitches
on the external reference voltage source. The high 2.5 MΩ
input-resistance minimizes power dissipation within the
AD7392/AD7393 D/A converters. The VREF input accepts
input voltages ranging from ground to the positive-supply volt-
age VDD. One of the simplest applications that saves an external
reference voltage source is connection of the REF terminal to
the positive VDD supply. This connection results in a rail-to-rail
voltage output span maximizing the programmed range. The
reference input will accept ac signals as long as they are kept
within the supply voltage range, 0 < VREF IN < VDD. The refer-
ence bandwidth and integral nonlinearity error performance are
plotted in the typical performance section (see Figures 20 and
21). The ratiometric reference feature makes the AD7392/
AD7393 an ideal companion to ratiometric analog-to-digital
converters such as the AD7896.
+2.7V TO +5.5V
20
REF
1
C
*
V
0.1F
DD
10F
DB0–DB11
AD7392
OR
19
V
2
3
4
OUT
AD7393
SHDN
CS
RS
GND
17, 18
* OPTIONAL EXTERNAL
REFERENCE BYPASS
POWER SUPPLY
Figure 27. Recommended Supply Bypassing for the
AD7392/AD7393
The very low power consumption of the AD7392/AD7393 is a
direct result of a circuit design optimizing the use of a CBCMOS
process. By using the low power characteristics of CMOS for
the logic and the low noise, tight-matching of the complemen-
tary bipolar transistors, excellent analog accuracy is achieved.
One advantage of the rail-to-rail output amplifiers used in the
AD7392/AD7393 is the wide range of usable supply voltage.
The part is fully specified and tested for operation from +2.7 V
to +5.5 V.
REV. A
–8–
AD7392/AD7393
INPUT LOGIC LEVELS
RESET (RS) PIN
All digital inputs are protected with a Zener-type ESD protec-
tion structure (Figure 28) that allows logic input voltages to
exceed the VDD supply voltage. This feature can be useful if the
user is driving one or more of the digital inputs with a 5 V
CMOS logic input-voltage level while operating the AD7392/
AD7393 on a +3 V power supply. If this mode of interface is
used, make sure that the VOL of the 5 V CMOS meets the VIL
input requirement of the AD7392/AD7393 operating at 3 V.
See Figure 12 for a graph for digital logic input threshold versus
operating VDD supply voltage.
Forcing the asynchronous RS pin low will set the DAC register
to all zeros and the DAC output voltage will be zero volts. The
reset function is useful for setting the DAC outputs to zero at
power-up or after a power supply interruption. Test systems and
motor controllers are two of many applications that benefit from
powering up to a known state. The external reset pulse can be
generated by the microprocessor’s power-on RESET signal, by
an output from the microprocessor or by an external resistor
and capacitor. RESET has a Schmitt trigger input which results
in a clean reset function when using external resistor/capacitor
generated pulses. See the Control-Logic Truth Table I.
V
DD
1k⍀
LOGIC
IN
POWER SHUTDOWN (SHDN)
Maximum power savings can be achieved by using the power
shutdown control function. This hardware activated feature is
controlled by the active low input SHDN pin. This pin has a
Schmitt trigger input that helps desensitize it to slowly changing
inputs. By placing a logic low on this pin, the internal consump-
tion of the AD7392 or AD7393 is reduced to nanoamp levels,
guaranteed to 1.5 µA maximum over the operating temperature
range. If power is present at all times on the VDD pin while in
the shutdown mode, the internal DAC register will retain the
last programmed data value. The digital interface is still active
in shutdown, so that code changes can be made that will pro-
duce new DAC settings when the device is taken out of shut-
down. This data will be used when the part is returned to the
normal active state by placing the DAC back to its programmed
voltage setting. Figure 23 shows a plot of shutdown recovery
time with both IDD and VOUT displayed. In the shutdown state
the DAC output amplifier exhibits an open-circuit high resis-
tance state. Any load connected will stabilize at its termination
voltage. If the power shutdown feature is not needed, the user
should tie the SHDN pin to the VDD voltage thereby disabling
this function.
GND
Figure 28. Equivalent Digital Input ESD Protection
In order to minimize power dissipation from input-logic levels
that are near the VIH and VIL logic input voltage specifications, a
Schmitt trigger design was used that minimizes the input-buffer
current consumption compared to traditional CMOS input
stages. Figure 11 shows a plot of incremental input voltage
versus supply current, showing that negligible current consump-
tion takes place when logic levels are in their quiescent state.
The normal cross over current still occurs during logic transi-
tions. A secondary advantage of this Schmitt trigger is the pre-
vention of false triggers that would occur with slow moving logic
transitions when a standard CMOS logic interface or opto-
isolators are used. The logic inputs DB11–DB0, CS, RS, SHDN
all contain the Schmitt trigger circuits.
DIGITAL INTERFACE
The AD7392/AD7393 have a parallel data input. A functional
block diagram of the digital section is shown in Figure 4, while
Table I contains the truth table for the logic control inputs.
The chip select (CS) pin controls loading of data from the data
inputs on pins DB11–DB0. This active low input places the
input register into a transparent state allowing the data inputs to
directly change the DAC ladder values. When CS returns to
logic high within the data setup and hold time specifications, the
new value of data in the input-register will be latched. See Truth
Table for complete set of conditions.
REV. A
–9–
AD7392/AD7393
midscale 200H to full scale 3FFH, the circuit output voltage VO
is set at –5 V, 0 V and +5 V (minus 1 LSB). The output voltage
VO is coded in offset binary according to Equation 4.
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD7392. As shown
in Figure 29, the AD7392 has been designed to drive loads as
low as 5 kΩ in parallel with 100 pF. The code table for this
operation is shown in Table II.
D
VO
=
–1 ×5
Equation 4
512
+2.7V TO +5.5V
R
where D is the decimal code loaded in the AD7393 DAC regis-
ter. Note that the LSB step size is 10/1024 = 10 mV. This cir-
cuit has been optimized for micropower consumption including
the 470 kΩ gain setting resistors, which should have low tem-
perature coefficients to maintain accuracy and matching (prefer-
ably the same resistor material, such as metal film). If better
stability is required, the power supply could be substituted with
a precision reference voltage such as the low drop out REF195,
which can easily supply the circuit’s 162 µA of current, and still
provide additional power for the load connected to VO. The
micropower REF195 is guaranteed to source 10 mA output
drive current, but only consumes 50 µA internally. If higher
resolution is required, the AD7392 can be used with the addi-
tion of two more bits of data inserted into the software coding,
which would result in a 2.5 mV LSB step size. Table III shows
examples of nominal output voltages VO provided by the Bipolar
Operation circuit application.
1
0.01F
0.1F
10F
V
DD
AD7392
20
19
EXT
REF
REF
V
OUT
C
R
L
L
AGND/DGND
17, 18
Ն100pF
Ն5k⍀
DIGITAL INTERFACE
CIRCUITRY OMITTED
FOR CLARITY
Figure 29. AD7392 Unipolar Output Operation
Table II. Unipolar Code Table
Hexadecimal
Number
in DAC Register
Decimal
Number
in DAC Register
Output
Voltage (V)
VREF = 2.5 V
FFF
801
800
7FF
000
4095
2049
2048
2047
0
2.4994
1.2506
1.2500
1.2494
0
I
< 162A
SY
+5V
470k⍀
470k⍀
<2A
<100A
<50A
C
+5V
–5V
The circuit can be configured with an external reference plus
power supply or powered from a single dedicated regulator
or reference depending on the application performance re-
quirements.
BIPOLAR
OUTPUT
SWING
V
REF
DD
OP196
V
O
V
OUT
AD7393
GND
–5V
BIPOLAR OUTPUT OPERATION
DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY
Although the AD7393 has been designed for single-supply op-
eration, the output can be easily configured for bipolar opera-
tion. A typical circuit is shown in Figure 30. This circuit uses a
clean regulated +5 V supply for power, which also provides the
circuit’s reference voltage. Since the AD7393 output span swings
from ground to very near +5 V, it is necessary to choose an exter-
nal amplifier with a common-mode input voltage range that
extends to its positive supply rail. The micropower consump-
tion OP196 has been designed just for this purpose and results
in only 50 microamps of maximum current consumption. Con-
nection of the equal valued 470 kΩ resistors results in a differen-
tial amplifier mode of operation with a voltage gain of two,
which produces a circuit output span of ten volts (that is, –5 V
to +5 V). As the DAC is programmed from zero-code 000H to
Figure 30. Bipolar Output Operation
Table III. Bipolar Code Table
Hexadecimal
Number
In DAC Register
Decimal
Number
in DAC Register
Analog
Output
Voltage (V)
3FF
201
200
1FF
000
1023
513
512
511
0
4.9902
0.0097
0.0000
–0.0097
–5.0000
REV. A
–10–
AD7392/AD7393
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Plastic DIP Package
(N-20)
1.060 (26.90)
0.925 (23.50)
20
1
11
0.280 (7.11)
0.240 (6.10)
10
0.325 (8.25)
0.195 (4.95)
0.115 (2.93)
0.300 (7.62)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
20-Lead SOIC Package
(R-20)
0.5118 (13.00)
0.4961 (12.60)
20
11
1
10
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0138 (0.35)
20-Lead Thin Surface Mount TSSOP Package
(RU-20)
0.260 (6.60)
0.252 (6.40)
20
11
10
1
0.006 (0.15)
0.002 (0.05)
PIN 1
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
REV. A
–11–
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