AD7388 [ADI]
Differential Input, Quad, Internal Reference Simultaneous Sampling, 16-Bit SAR ADC;型号: | AD7388 |
厂家: | ADI |
描述: | Differential Input, Quad, Internal Reference Simultaneous Sampling, 16-Bit SAR ADC |
文件: | 总31页 (文件大小:611K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Differential Input, Quad, Internal Reference
Simultaneous Sampling, 16-Bit SAR ADC
AD7389-4
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
REFOUT
REFCAP REFGND
V
LOGIC
CC
16-bit ADC family
Quad simultaneous sampling
Fully differential analog inputs
Wide common-mode range
High throughput rate: 2 MSPS
Buffered 2.5 V internal voltage reference (10 ppm/°C)
On-chip oversampling function
INL (maximum): 2 LSBs
SNR (typical)
90.5 dB at VREF = 2.5 V
97.9 dB at RES = 1, OSR = 8× rolling average oversampling
2-bit resolution boost
REGCAP
LDO
REF
A
A+
IN
OSC
ADC A
OVERSAMPLING
A
A–
IN
SDOA
SDOB
SDOC
A
B+
IN
OVERSAMPLING
OVERSAMPLING
OVERSAMPLING
ADC B
ADC C
A
B–
IN
INTERFACE
AND
CONTROL
LOGIC
SDOD/
ALERT
A
C+
IN
A
C–
SCLK
SDI
IN
CS
A
D+
IN
ADC D
GND
ALERT
Out of range indicator (
)
AD7389-4
A
D–
IN
High-speed serial interface
−40°C to +125°C operation
4 mm × 4 mm, 24-lead LFCSP
GND
Figure 1.
APPLICATIONS
Motor control position feedback
Motor control current sense
Data acquisition systems
Erbium doped fiber amplifier (EDFA) applications
In phase and quadrature demodulation
GENERAL DESCRIPTION
The AD7389-4 a 16-bit, quad, simultaneous sampling, high
speed, successive approximation register (SAR), analog-to-digital
converter (ADC) that operates from a 3.0 V to 3.6 V power
supply and features throughput rates up to 2 MSPS. The analog
input type is differential, accepts a wide common-mode input
voltage, and the analog inputs are sampled and converted on
Table 1. Related Devices
No. of
Channels Input Type
16 Bits
14 Bits
12 Bits
4
2
Differential
AD7380-4 AD7381-4
AD7389-4
Differential
AD7380
AD4680
AD4681
AD7381
CS
the falling edge of
.
The AD7389-4 has on-chip oversampling blocks to improve
dynamic range and reduce noise at lower bandwidths. The
oversampling can boost up to two bits of added resolution. A
buffered internal 2.5 V reference (10 ppm/°C) is included.
Single-ended AD7386
AD7387
AD7388
PRODUCT HIGHLIGHTS
1. Quad simultaneous sampling and conversion.
2. Pin-compatible product family.
3. High throughput rate, 2 MSPS at 16-bit.
4. Space-saving, 4 mm × 4 mm LFCSP.
5. Integrated oversampling block to increase dynamic range,
reduce noise and reduce SCLK speed requirements.
6. Differential analog inputs with wide common-mode range.
7. Small sampling capacitor reduces amplifier drive burden.
The conversion process and data acquisition use standard
control inputs allowing for easy interfacing to microprocessors
or digital signal processors (DSPs). The conversion result can
clock out simultaneously via 4-wire mode for faster throughput or
via 1-wire serial mode when slower throughput is allowed. The
device is compatible with 1.8 V, 2.5 V, and 3.3 V interfaces,
using the separate logic supply.
The AD7389-4 is available in a 24-lead lead frame chip scale
package (LFCSP) with operation specified from −40°C to +125°C.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registeredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2022 Analog Devices, Inc. All rights reserved.
www.analog.com
AD7389-4
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Oversampling ............................................................................. 17
Resolution Boost ........................................................................ 19
Alert.............................................................................................. 19
Power Modes .............................................................................. 19
Internal Reference...................................................................... 20
Software Reset............................................................................. 20
Diagnostic Self Test.................................................................... 20
Interface........................................................................................... 21
Reading Conversion Results..................................................... 21
Low Latency Readback.............................................................. 22
Reading from Device Registers ................................................ 23
Writing to Device Registers...................................................... 23
CRC.............................................................................................. 23
Registers........................................................................................... 26
Addressing Registers.................................................................. 26
Configuration 1 Register........................................................... 27
Configuration 2 Register........................................................... 28
Alert Indication Register........................................................... 28
Alert Low Threshold Register .................................................. 29
Alert High Threshold Register ................................................. 30
Outline Dimensions....................................................................... 31
Ordering Guide .......................................................................... 31
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights........................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ........................................................... 8
Thermal Resistance...................................................................... 8
Electrostatic Discharge (ESD) Ratings...................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions ............................ 9
Typical Performance Characteristics........................................... 10
Terminology.................................................................................... 13
Theory of Operation ...................................................................... 14
Circuit Information ................................................................... 14
Converter Operation.................................................................. 14
Analog Input Structure.............................................................. 14
ADC Transfer Function ............................................................ 15
Applications Information.............................................................. 16
Power Supply .............................................................................. 16
Modes of Operation ....................................................................... 17
REVISION HISTORY
1/2022—Revision 0: Initial Version
Rev. 0 | Page 2 of 31
Data Sheet
AD7389-4
SPECIFICATIONS
VCC = 3.0 V to3.6 V, VLOGIC = 1.65 V to 3.6 V, internal reference voltage (VREF) = 2.5 V, fSAMPLE = 2 MSPS, TA = −40°C to +125°C, no
oversampling enabled, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION
16
Bits
THROUGHPUT
Conversion Rate (fSAMPLE
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Common-Mode Input Range
)
2
MSPS
AINx+ − AINx−
AINx+, AINx−
AINx+, AINx−
−VREF
−0.1
0.2
+VREF
VREF + 0.1
VREF × 0.5 VREF − 0.2
−76
V
V
V
dB
Analog Input Common-Mode Rejection Ratio fIN = 500 kHz
(CMRR)
µA
pF
pF
DC Leakage Current
Input Capacitance
0.1
18
5
1
Track mode
Hold mode
DC ACCURACY
No Missing Codes
16
Bits
Differential Nonlinearity (DNL) Error
Integral Nonlinearity (INL) Error
Gain Error
Gain Error Temperature Drift
Gain Error Match
Zero Error
Zero Error Temperature Drift
Zero Error Match
−1.0
−2.5
−0.02
−1
−0.0125
−0.25
−1
0.7
0.1
0.006
0.1
0.004
0.1
+1.0
+2.5
LSB
LSB
+0.02
+1
+0.0125
+0.25
+1
% FS
ppm/°C
% FS
mV
µV/°C
mV
0.2
0.1
−0.125
+0.125
AC ACCURACY
fIN = 1 kHz
Dynamic Range
Oversampled Dynamic Range
Signal-to-Noise Ratio (SNR)
91.3
dB
dB
dB
dB
OSR = 4×, RES = 1 (decimal)
97.4
90.5
97.9
89
Rolling average OSR = 8×, RES = 1
(decimal)
fIN = 100 kHz
88.6
−105
−106
−105
90
dB
dB
dB
dB
dB
dB
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
fIN = 100 kHz
Signal-to-Noise-and-Distortion (SINAD) Ratio
Channel to Channel Isolation
88.5
−126
Rev. 0 | Page 3 of 31
AD7389-4
Data Sheet
VCC = 3.0 V to3.6 V, VLOGIC = 1.65 V to 3.6 V, internal VREF = 2.5 V, TA = −40°C to +125°C, no oversampling enabled, unless otherwise
noted.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SAMPLING DYNAMICS
Input Bandwidth
At −0.1 dB
At −3 dB
6.6
MHz
MHz
ns
ps
ps
26.8
26.2
46.8
20
Aperture Delay
Aperture Delay Match
Aperture Jitter
145
REFERENCE OUTPUT
VREF Output Voltage
VREF Temperature Coefficient
VREF Noise
−40°C to +125°C
2.495
2.5
2
7
2.505
10
V
ppm/°C
µV rms
DIGITAL INPUTS (SCLK, SDI, CS)
Logic Levels
Input Low Voltage (VIL)
0.2 ×
VLOGIC
V
Input High Voltage (VIH)
Input Low Current (IIL)
Input High Current (IIH)
DIGITAL OUTPUTS (SDOA, SDOB, SDOC, SDOD/ALERT)
Output Coding
Output Low Voltage (VOL)
Output High Voltage (VOH)
Floating State Leakage Current
Floating State Output Capacitance
POWER SUPPLIES
0.8 × VLOGIC
−1
−1
V
µA
µA
+1
+1
Twos complement
0.4
VLOGIC − 0.3
Bits
V
V
µA
pF
Current sink (ISINK) = 300 µA
Current source (ISOURCE)= −300 µA
1
10
VCC
VLOGIC
3.0
1.65
3.3
3.6
3.6
V
V
VCC Supply Current (IVCC
)
Normal Mode (Operational)
Normal Mode (Static)
Shutdown Mode
21
1.7
101
23
2
200
mA
mA
µA
VLOGIC Current (IVLOGIC
)
Analog inputs at positive full scale
Normal Mode (Static)
Normal Mode (Operational)
Shutdown Mode
10
3.7
10
200
4.1
200
nA
mA
nA
Power Dissipation
Total (PTOTAL
)
89
98
mW
VCC Power (PVCC
)
Normal Mode (Operational)
Normal Mode (Static)
Shutdown Mode
75.6
6.1
363.6 720
83
7.2
mW
mW
µW
VLOGIC Power (PVLOGIC
)
Analog inputs at positive full scale
Normal Mode (Static)
Normal Mode (Operational)
Shutdown Mode
36
13.3
36
720
15
720
nW
mW
µW
Rev. 0 | Page 4 of 31
Data Sheet
AD7389-4
TIMING SPECIFICATIONS
VCC = 3.0 V to3.6 V, VLOGIC = 1.65 V to 3.6 V, VREF = 2.5 V, TA = −40°C to +125°C, unless otherwise noted. When referencing a single function of
ALERT
a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed, such as
names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.
. For full pin
Table 4.
Parameter
Min
500
5
Typ
Max
Unit
ns
ns
Description
tCYC
Time between conversions
CS falling edge to first SCLK falling edge
SCLK period
SCLK high time
SCLK low time
tSCLKED
tSCLK
tSCLKH
tSCLKL
12.5
5.5
5.5
20
ns
ns
ns
ns
tCSH
CS pulse width
tQUIET
tSDOEN
20
ns
Interface quiet time prior to conversion
CS Low to SDOA and SDOB enabled
VLOGIC ≥ 2.25 V
5.5
8
ns
ns
ns
1.65 V ≤ VLOGIC < 2.25 V
tSDOH
tSDOS
3
SCLK rising edge to SDOA and SDOB hold time
SCLK rising edge to SDOA and SDOB setup time
VLOGIC ≥ 2.25 V
5.5
8
8
ns
ns
ns
ns
ns
ns
ns
ns
1.65 V ≤ VLOGIC < 2.25 V
tSDOT
CS rising edge to SDOA and SDOB high impedance
SDI setup time prior to SCLK falling edge
SDI hold time after SCLK falling edge
SCLK rising edge to CS rising edge
Conversion time
tSDIS
tSDIH
tSCLKCS
tCONVERT
tACQUIRE
tRESET
4
4
0
190
310
Acquire time
Valid time to start conversion after software reset (see Figure 33)
Valid time to start conversion after soft reset
Valid time to start conversion after hard reset
Supply active to conversion
250
800
ns
ns
tPOWERUP
5
11
5
ms
ms
ms
First conversion allowed
Settled to within 1% with internal reference
Supply active to register read write access allowed
Exiting shutdown mode to conversion
Settled to within 1% with internal reference
Conversion time for first sample in oversampling (OS) normal mode
Conversion time for xth sample in OS normal mode
Time from CS to ALERT indication
tREGWRITE
tSTARTUP
11
10
ms
ns
ns
ns
ns
ns
tCONVERT0
tCONVERTx
tALERTS
6
8
tCONVERT0 + (320 × (x – 1))
220
10
tALERTC
Time from CS to ALERT clear
tALERTS_NOS
20
Time from internal conversion with exceeded threshold to ALERT indication
Rev. 0 | Page 5 of 31
AD7389-4
Data Sheet
Timing Diagrams
tCYC
tSCLK
tCSH
tSCLKED
tSCLKH
tSCLKL
tQUIET
tSCLKCS
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TRISTATE
SDOA
TRISTATE
DB15
DB14
DB13
DB12
DB12
DB11
DB11
DB10
DB10
DB9
DB9
DB8
DB8
DB7
DB7
DB6
DB5
DB5
DB4
DB3
DB2
DB0
DB0
1
1
TRISTATE
SDOB
TRISTATE
tSDOT
DB15
DB14
DB13
DB6
DB4
DB3
DB2
tSDOEN
tSDOH
tSDOS
SDI
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB0
1
tSDIS
tSDIH
Figure 2. Serial Interface Timing Diagram
tCONVERT
CS
CONVERSION
ACQUIRE
CONVERSION
ACQUIRE
tACQUIRE
Figure 3. Internal Conversion Acquire Timing
tPOWERUP
V
CC
CS
TIME TO ACCURATE CONVERSION
Figure 4. Power-Up Time to Conversion
tREGWRITE
VCC
CS
REG
WRITE
SDI
Figure 5. Power-Up Time to Register Read Write Access
tSTARTUP
CS
SDI
SHUTDOWN
SHUTDOWN MODE
NORMAL
NORMAL MODE
ACCURATE CONVERSION
Figure 6. Shutdown Mode to Normal Mode Timing
tCONVERT0
CS
INTERNAL
CONVERSION
ACQUIRE
CONVERSION
ACQUIRE
CONVERSION
ACQUIRE
CONVERSION
ACQUIRE
tCONVERT1
tCONVERT2
tCONVERT3
tCONVERTx
Figure 7. Conversion Timing During OS Normal Mode
Rev. 0 | Page 6 of 31
Data Sheet
AD7389-4
tALERTS
tALERTC
CS
SDOA
NO OVERSAMPLING OR
ROLLING AVERAGE OS
INTERNAL
ALERT
CONV
ACQ
CONV
ACQ
CONV
ACQ
CONV
ACQ
EXCEEDS THRESHOLD
CS
SDOA
NORMAL
OVERSAMPLING
INTERNAL
ALERT
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
EXCEEDS THRESHOLD
tALERTS_NOS
tALERTC
ALERT
Figure 8.
Timing
Rev. 0 | Page 7 of 31
AD7389-4
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
VCC to GND
VLOGIC to GND
−0.3 V to +4 V
−0.3 V to +4 V
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Analog Input Voltage to GND
−0.3 V to VREF +0.3 V, or
VCC + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−0.3 V to VCC +0.3 V
10 mA
Digital Input Voltage to GND
Digital Output Voltage to GND
REFOUT Input to GND
Input Current to Any Pin Except
Supplies
Table 6. Thermal Resistance
Package Type
CP-24-251
θJA
θJC
0.432
Unit
48.4
°C/W
Temperature Range
Operating
Storage
1 Test Condition 1: thermal impedance simulated values are based on
JEDEC 2S2P thermal test board with four thermal vias. See JEDEC JESDS1.
2 Test Condition 2: a cold plate attached to the package surface and measured
at the exposed pad.
−40°C to +125°C
−65°C to +150°C
150°C
Maximum Junction Temperature
ELECTROSTATIC DISCHARGE (ESD) RATINGS
Pb-Free Soldering Reflow
Temperature
260°C
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Field induced charge device model (FICDM) per
ANSI/ESDA/JEDEC JS-002.
ESD Ratings for AD7389-4
Table 7. AD7389-4, 24-Lead LFCSP
ESD Model
Withstand Threshold (V)
Class
3A
C3
HBM
FICDM
4000
1250
ESD CAUTION
Rev. 0 | Page 8 of 31
Data Sheet
AD7389-4
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
18
17
GND
CS
V
REFOUT
LOGIC
AD7389-4
16 GND
REGCAP
15 REFCAP
14 GND
V
4
5
CC
TOP VIEW
(Not to Scale)
GND
A
D– 6
IN
A
A+
IN
13
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND.
Figure 9. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 5, 14, 16
2
3
GND
VLOGIC
REGCAP
Ground Reference Point. These pins are the ground reference points for all circuitry on the device.
Logic Interface Supply Voltage, 1.65 V to 3.6 V. Decouple this pin to GND with a 1 µF capacitor.
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this pin to GND with a
1 µF capacitor. The voltage at this pin is 1.9 V typical.
4
VCC
Power Supply Input Voltage. 3.0 V to 3.6 V. Decouple this pin to GND using a 1 µF capacitor.
Analog Inputs of ADC D. These analog inputs form a fully differential pair.
Analog Inputs of ADC C. These analog inputs form a fully differential pair.
Analog Inputs of ADC B. These analog inputs form a fully differential pair.
Analog Inputs of ADC A. These analog inputs form a fully differential pair.
6, 7
8, 9
10, 11
12, 13
15
AIND−, AIND+
AINC−, AINC+
AINB−, AINB+
AINA−, AINA+
REFCAP
Decoupling Capacitor Pin for Bandgap Reference. Decouple this pin to GND with a 0.1 μF capacitor. The
voltage at this pin is 2.5 V typical.
17
18
REFOUT
CS
Reference Output. Decoupling is required on this pin. Apply a 1 µF capacitor from this pin to GND.
Chip Select Input. Active low, logic input. This input provides the dual function of initiating conversions
on the AD7389-4 and framing the serial data transfer.
19
SDOA
Serial Data Output A. This pin functions as a serial data output pin to access the conversion results and
register contents.
20
21
22
23
SDOB
SDI
SCLK
SDOC
Serial Data Output B. This pin functions as a serial data output pin to access the conversion results.
Serial Data Input. This input provides the data written to the on-chip control registers.
Serial Clock Input. This serial clock input is for data transfers to and from the ADC.
Serial Data Output C. This pin functions as a serial data output pin to access the conversion results and
register contents.
24
SDOD/ALERT Serial Data Output D (SDOD). This pin functions as a serial data output to access the conversion results.
Alert Indication Output (ALERT).This pin operates as an alert going low to indicate that a conversion
result has exceeded a configured threshold.
This pin can operate as a serial data output pin or alert indication output.
Not applicable EPAD
Exposed Pad. The exposed pad must be connected to ground.
Rev. 0 | Page 9 of 31
AD7389-4
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0
94
92
90
88
86
84
82
80
78
76
74
fIN = 1kHz
INTERNAL REFERENCE VOLTAGE = 2.5V
SNR = 90.38dB
THD = –111.29dB
–20
SINAD = 90.35dB
= 2.5V (INTERNAL)
–40
V
REF
–60
–80
–100
–120
–140
–160
–180
1
10
100
FREQUENCY (kHz)
1000
0
200
400
600
800
1000
FREQUENCY (kHz)
Figure 10. Fast Fourier Transform (FFT), 1 kHz Input Tone, −0.5 dBFS, Internal
Reference = 2.5 V
Figure 13. SINAD vs. Frequency
94
96
94
92
90
88
86
84
82
80
INTERNAL REFERENCE VOLTAGE = 2.5V
92
90
88
86
84
82
80
78
76
74
1
10
100
1000
–40 –25 –10
5
20
35
50
65
80
95 110 125
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 11. SNR vs. Frequency
Figure 14. SNR vs. Temperature
–70
–75
–80
INTERNAL REFERENCE VOLTAGE = 2.5V
–85
–90
–80
–85
–95
–90
–100
–105
–110
–115
–120
–125
–130
–95
–100
–105
–110
–115
–120
1
10
100
1000
–40 –25 –10
5
20
35
50
65
80
95 110 125
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 12. THD vs. Frequency
Figure 15. THD vs. Temperature
Rev. 0 | Page 10 of 31
Data Sheet
AD7389-4
96
94
92
90
88
86
84
82
–40
–50
–60
–70
–80
–90
–100
–110
80
0.1
1
10
100
1000
–40 –25 –10
5
20
35
50
65
80
95 110 125
RIPPLE FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 19. CMRR vs. Ripple Frequency
Figure 16. SINAD vs. Temperature
104
102
100
98
30
NORMAL AVERAGING OVERSAMPLING
RES = 1
RES = 0
V
= 2.5V (INTERNAL)
REF
I
I
VCC
LOGIC
25
20
15
10
5
96
94
92
90
88
86
84
0
1
2
4
8
16
32
0
0.5
1.0
1.5
2.0
OVERSAMPLING RATIO
THROUGHPUT RATE (MSPS)
Figure 20. SNR vs. Oversampling Ratio, Normal Averaging
Figure 17. Dynamic Current vs. Throughput Rate
100
98
96
94
92
90
88
86
84
40
35
30
25
20
15
10
5
ROLLING AVERAGING OVERSAMPLING
THROUGHPUT RATE = 2MSPS
REF
RES = 1
RES = 0
V
= 2.5V (INTERNAL)
I
I
VCC
VLOGIC
0
1
2
4
8
–40 –25 –10
5
20
35
50
65
80
95 110 125
OVERSAMPLING RATIO
TEMPERATURE (°C)
Figure 21. SNR vs. Oversampling Ratio, Rolling Average
Figure 18. Dynamic Current vs. Temperature
Rev. 0 | Page 11 of 31
AD7389-4
Data Sheet
200000
180000
160000
140000
120000
100000
80000
60000
40000
20000
0
1.0
182548
0.8
A
V
+ = A
= V
÷ 2
INX
INX
REF
= 2.5V
0.6
REF
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
41718
–1
37983
0
243
2
0
–4
–3
–2
0
1
3
4
–32000 –24000 –16000 –8000
0
8000 16000 24000 32000
CODE
CODE
Figure 22. INL vs. Code
Figure 24. DC Histogram Codes at Code Center
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–32000 –24000 –16000 –8000
0
8000 16000 24000 32000
CODE
Figure 23. DNL vs. Code
Rev. 0 | Page 12 of 31
Data Sheet
AD7389-4
TERMINOLOGY
Signal-to-Noise Ratio (SNR)
Differential Nonlinearity (DNL)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the
Nyquist frequency, excluding harmonics and dc. The value for
SNR is expressed in decibels.
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. DNL is often
specified in terms of resolution for which no missing codes are
guaranteed.
Spurious-Free Dynamic Range (SFDR)
Integral Nonlinearity (INL)
INL is the deviation of each individual code from a line drawn
from negative full scale through positive full scale. The point
used as negative full scale occurs ½ LSB before the first code
transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line.
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and
is expressed in decibels.
Gain Error
Signal-to-Noise-and-Distortion (SINAD) Ratio
The first transition (from 100 … 000 to 100 …001) occurs at a
level ½ LSB above nominal negative full scale. The last
transition (from 011 … 110 to 011 … 111) occurs for an analog
voltage 1½ LSB below the nominal full scale. The gain error is
the deviation of the difference between the actual level of the
last transition and the actual level of the first transition from
the difference between the ideal levels.
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value for SINAD is expressed in decibels.
Common-Mode Rejection Ratio (CMRR)
CMRR is the ratio of the power in the ADC output at the
frequency, f, to the power of a 200 mV p-p sine wave applied to
the common-mode voltage of AINx+ and AINx− of frequency, f.
CMRR is expressed in decibels.
Gain Error Drift
The gain error change due to a temperature change of 1°C.
Gain Error Matching
CMRR = 10log(PADC_IN/PADC_OUT
where:
ADC_IN is the common-mode power at the frequency, f, applied
to the AINx+ and AINx inputs.
ADC_OUT is the power at the frequency, f, in the ADC output.
)
Gain error matching is the difference in negative full-scale error
between the input channels and the difference in positive full-
scale error between the input channels.
P
Zero Error
P
Zero error is the difference between the ideal midscale voltage,
0 V, and the actual voltage producing the midscale output code,
0 LSB.
Aperture Delay
Aperture delay is the measure of the acquisition performance
CS
and is the time between the falling edge of the
when the input signal is held for a conversion.
input and
Zero Error Temperature Drift
Zero error temperature drift is the zero error change due to a
temperature change of 1°C.
Aperture Delay Match
Aperture delay match is the difference of the aperture delay
between each ADC channel.
Zero Error Match
Zero error match is the difference in zero error between the
input channels.
Aperture Jitter
Aperture jitter is the variation in aperture delay.
Rev. 0 | Page 13 of 31
AD7389-4
Data Sheet
THEORY OF OPERATION
When the ADC starts a conversion (see Figure 26), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected when the
conversion begins. The control logic and charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator back
into a balanced condition. When the comparator is rebalanced,
the conversion is complete. The control logic generates the
ADC output code. The output impedances of the sources
driving the AINx+ and AINx− pins must be matched. Otherwise,
the two inputs have different settling times, resulting in errors.
CIRCUIT INFORMATION
The AD7389-4 is a high speed, quad, fully differential, 16-bit, SAR
ADC. The device operates from a 3.0 V to 3.6 V power supply
and features throughput rates up to 2 MSPS.
The AD7389-4 contains four successive approximation ADCs,
and a serial interface with four separate data output pins. The
device is housed in a 24-lead LFCSP, offering the user
considerable space-saving advantages over alternative
solutions.
Data is accessed from the device via the serial interface. The
interface can be operated with two, four, or one serial output.
The AD7389-4 has an on-chip 2.5 V internal reference
(10 ppm/°C). If the internal reference is used elsewhere in the
system, the reference output must be buffered. The differential
analog input range for the AD7389-4 is VCM VREF/2.
CAPACITIVE
DAC
COMPARATOR
B
A
C
C
S
A
x+
x–
IN
SW1
SW2
CONTROL
LOGIC
SW3
S
A
B
A
The AD7389-4 features on-chip oversampling blocks to
improve performance. Normal averaging and rolling average
oversampling modes are available. Power-down options to
allow power saving between conversions are available.
Configuration of the device is implemented via the standard
serial interface, as described in the Interface section.
IN
V
REF
Figure 26. ADC Conversion Phase
ANALOG INPUT STRUCTURE
CONVERTER OPERATION
Figure 27 shows the equivalent circuit of the analog input struc-
ture of the AD7389-4. The four diodes provide ESD protection
for the analog inputs. Ensure that the analog input signals never
exceed the supply rails by more than 300 mV. Exceeding the limit
causes these diodes to become forward-biased and start
The AD7389-4 has four successive approximation ADCs, each
based around two capacitive DACs. Figure 25 and Figure 26
show simplified schematics of one of these ADCs in acquisition
and conversion phases, respectively. The ADC comprises
control logic, a SAR, and two capacitive DACs. In Figure 25
(the acquisition phase), SW3 is closed, SW1 and SW2 are in
Position A, the comparator is held in a balanced condition,
and the sampling capacitor (CS) arrays can acquire the
differential signal on the input.
conducting into the substrate. These diodes can conduct up to
10 mA without causing irreversible damage to the device.
The C1 capacitors in Figure 27 are typically 3 pF and can
primarily be attributed to pin capacitance. The R1 resistors
are lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 200 Ω.
The C2 capacitors are the ADC sampling capacitors with a
typical capacitance of 15 pF.
CAPACITIVE
DAC
COMPARATOR
C
C
B
A
S
A
x+
IN
V
CC
SW1
SW2
CONTROL
LOGIC
SW3
S
C2
D
D
A
B
R1
A
x–
IN
A
x+
IN
C1
V
REF
CAPACITIVE
DAC
V
CC
Figure 25. ADC Acquisition Phase
C2
D
D
R1
A
x–
IN
C1
Figure 27. Equivalent Analog Input Circuit,
Conversion Phase—Switches Open, Track Phase—Switches Closed
Rev. 0 | Page 14 of 31
Data Sheet
AD7389-4
ADC TRANSFER FUNCTION
The AD7389-4 uses a 2.5 V reference. The AD7389-4 converts
the differential voltage of the analog inputs (AINx+ and AINx−)
into a digital output.
011...111
011...110
011...101
The conversion result is MSB first, twos complement. The LSB
size is (2 × VREF)/2N, where N is the ADC resolution. The ADC
resolution is determined by the resolution of the device chosen
and if resolution boost mode is enabled. Table 9 outlines the
LSB size expressed in microvolts for different resolutions with a
2.5 V reference voltage.
100...010
100...001
100...000
The ideal transfer characteristic of the AD7389-4 is shown in
Figure 28.
–FSR
–FSR + 1LSB
+FSR – 1LSB
–FSR + 0.5LSB
+FSR – 1.5LSB
ANALOG INPUT
Figure 28. ADC Ideal Transfer Function (FSR = Full-Scale Range)
Table 9. LSB Size
Resolution (Bits)
2.5 V Reference (μV)
16
18
76.3
19.1
V+ = 5V
LDO
V–
LDO
LDO
1.65V
TO
3.5V
3.0V
TO
V+
3.6V
V
= V
÷ 2
CM
REF
10kΩ
10kΩ
V
= 2.5V
1µF
REF
1µF
V+
A
x+
IN
V
V
REF
REFOUT
V
CC
R
R
V
CM
0V
A
A
A+
A–
IN
V
LOGIC
C1
1µF
V–
V+
C2
AD7389-4
A
x–
IN
SDI
REF
IN
100Ω
V
SDOA
CM
0V
100Ω
DIGITAL HOST
(MICROPROCESSOR/FPGA)
SDOB
SCLK
CS
C1
EXPOSED
PAD
V–
A
A
A
A
C+
C–
D+
D–
IN
IN
IN
IN
100Ω
100Ω
SDOC
SDOD/ALERT
REGCAP
1µF
GND
REFCAP
0.1µF
NOTES
1. V– IS THE EXTERNAL SUPPLY VOLTAGE (–2.5 V) FOR THE DRIVER AMPLIFIER.
2. PLACE DECOUPLING CAPACITORS CLOSE TO (IDEALLY, RIGHT UP AGAINST)
THE DEVICE SUPPLY PINS AND REFERENCE PIN.
Figure 29. Typical Application Circuit
Rev. 0 | Page 15 of 31
AD7389-4
Data Sheet
APPLICATIONS INFORMATION
Figure 29 shows an example of a typical application circuit for
the AD7389-4. Decouple the VCC, VLOGIC, REGCAP, and
REFOUT pins with suitable decoupling capacitors as shown.
The exposed pad is a ground reference point for circuitry on
the device and must be connected to the board ground.
ADC driver can be supplied by a 5 V (V+) and a −2.5 V (V−)
derived from the inverting charge pump, the ADP5600, that
converts 5 V to −5 V, then to the ADP7182 for the low noise
voltage regulator to output −2.5 V. Two independent power
supply sources are derived from a low dropout (LDO) regulator
to power the VCC supply for the analog circuitry and the VLOGIC
supply for the digital interface of the AD7389-4. A very low
quiescent current LDO regulator like the ADP166 is a suitable
supply with a fixed output voltage range from 1.2 V to 3.3 V for
typical VCC and VLOGIC levels. The VCC supply and the VLOGIC
supply must be decoupled separately with a 1 µF capacitor.
Additionally, an internal LDO regulator supplies the AD7389-4.
The on-chip regulator provides a 1.9 V supply only for internal
use on the device. Decouple the REGCAP pin with a 1 µF
capacitor to GND.
A differential RC filter must be placed on the analog inputs to
ensure optimal performance is achieved. In a typical
application, R = 33 Ω, C1 = 68 pF, and C2 = 68 pF are
recommended. These RC combinations must be the same for
all channels of the AD7389-4.
The four differential channels of the AD7389-4 can accept an
input voltage range from 0 V to VREF and have a wide common-
mode range to convert a variety of signals. These analog input
pins (AINx ) can easily be driven with an amplifier. Table 10
lists the recommended driver amplifiers that can best fit and
add value to the application.
Power-Up
The AD7389-4 is not easily damaged by power supply
sequencing. VCC and VLOGIC can be applied in any sequence. The
external reference must be applied after VCC and VLOGIC are
applied. Analog and digital signals must be applied after the
external reference is applied.
The performance of the AD7389-4 device can be impacted by
noise on the digital interface. This impact is dependent on-board
layout and design. Keep a minimal distance of the digital line to
the digital interface or place a 100 Ω resistor in series and close
ALERT
to the SDOA, SDOB, SDOC, and SDOD/
pins to reduce
The AD7389-4 requires tPOWERUP from applying VCC and VLOGIC
until the ADC conversion results are stable. Interfacing with
the AD7389-4 prior to the setup time elapsing does not have a
negative impact on ADC operation. See Figure 4 for the
recommended signal condition during power-up. It is highly
recommended to issue a software reset after power-up (see the
Software Reset section for details).Conversion results are not
guaranteed to meet data sheet specifications during this time,
however.
noise from the digital interface coupling of the AD7389-4.
The AD7389-4 uses an internal 2.5 V reference voltage. When
this reference voltage is used for other circuits externally, for
example as a common-mode voltage for the driver amplifier, it
is recommended to use an external buffer amplifier like the
ADA4807-2.
POWER SUPPLY
For a typical application, the AD7389-4 circuitry shown in
Figure 29 can be driven from a 5 V (V+) supply to power the
system. The 5 V (V+) can be supplied from the ADP7104. The
Table 10. Signal Chain Components
Companion Devices
Part Name
Description
Typical Application
ADC Driver
ADA4896-2 1 nV/√Hz, rail-to-rail output amplifier
Precision, low noise, high frequency
ADA4940-2 Ultra low power, full differential, low distortion amplifier
ADA4807-2 1 mA, rail-to-rail output amplifier
Precision, low density, low power
Precision, low power, high frequency
3.0 V to 3.6 V supply for VCC and VLOGIC
5 V supply
−2.5 V supply for ADC driver amplifier
Voltage inverter for negative supply
Precision, low power, high frequency
LDO Regulator
ADP166
Very low quiescent, 150 mA, LDO regulator
500mA Low Noise, CMOS LDO regulator
Low noise line regulator
ADP7104
ADP7182
ADP5600
Interleaved inverting charge pump with negative LDO
Reference Buffer
ADA4807-2 1 mA, rail-to-rail output amplifier
Rev. 0 | Page 16 of 31
Data Sheet
AD7389-4
MODES OF OPERATION
The AD7389-4 has several on-chip configuration registers for
controlling the operational mode of the device.
before the register updates. That is, after writing to the OSR
bits, two conversion cycles take place before the conversion
results clock out with the updated OSR bits. The oversampling
ratio of the digital filter is controlled using the oversampling
bits, OSR (see Table 11).
OVERSAMPLING
Oversampling is a common method used in analog electronics
to improve the accuracy of the ADC result. Multiple samples of
the analog input are captured and averaged to reduce the noise
component from quantization noise and thermal noise (kTC
noise) of the ADC. The AD7389-4 offers an oversampling
function on-chip. The AD7389-4 has two user configurable
oversampling modes: normal averaging and rolling average.
Table 11 provides the oversampling bit decoding to select the
different oversample rates. The output result is decimated to
16-bit resolution. If required, additional resolution can be
achieved by configuring the resolution boost bit (RES) in the
Configuration 1 register. See the Resolution Boost section for
further details.
The oversampling functionality is configured by programming
the OS_MODE bit and OSR bits in the Configuration 1
register.
The number of samples (n), defined by the OSR bits, are taken
and added together, and the result is divided by n. The initial
CS
ADC conversion is initiated by the falling edge of
and the
Normal Averaging Oversampling
AD7389-4 controls all subsequent samples in the oversampling
sequence internally. The sampling rate of the additional n
samples at the device maximum sampling rate is 2 MSPS. The
data is ready for readback on the next serial interface access.
After the averaging technique is applied, the sample data used
in the calculation is discarded. This process is repeated every
time the application needs a new conversion result and is
Normal averaging oversampling mode can be used in
applications where slower output data rates are allowed and
where higher SNR or dynamic range is desirable. Normal
averaging involves taking a number of samples, adding them
together and dividing the result by the number of samples
taken. This result is then output from the device. The sample
data is cleared when the process completes.
CS
initiated by the next falling edge of
.
Normal averaging oversampling mode is configured by setting
the OS_MODE bit to Logic 0 and having a valid nonzero value
in the OSR bits. Writing to the OSR bits has a two-cycle latency
As the output data rate is reduced by the oversampling ratio,
the serial peripheral interface (SPI) SCLK frequency required to
transmit the data is reduced accordingly.
Table 11. Normal Averaging Oversampling Overview
SNR with 2.5 V Internal Reference (dB Typical)
OSR, Bits[2:0]
OS Ratio
RES = 0
90
RES = 1
90
93.4
96.5
99.2
Data Output Rate (kSPS Maximum)
000
001
010
011
100
101
No OS
2
4
8
16
32
2000
1500
750
375
187.5
93.75
92.3
94.1
95.6
96.4
96.7
100.5
101.7
CS
S
S
S
S
S
S
INTERNAL
ACQ
ACQ
ACQ
ACQ
1
2
n
1
2
n
SDOA
SDOB
DON'T CARE
t0 RESULT
DON'T CARE
t0 RESULT
CONVERT START AT t0
CONVERT START AT t1
Figure 30. Normal Averaging Oversampling Operation
Rev. 0 | Page 17 of 31
AD7389-4
Data Sheet
bit in the Configuration 1 register. See the Resolution Boost
section for further details.
Rolling Average Oversampling
Rolling average oversampling mode can be used in applications
where higher output data rates are required and where a higher
SNR or dynamic range is desirable. Rolling averaging involves
taking a number of samples, adding them together, and
dividing the result by the number of samples taken. This result
is then output from the device. The sample data is not cleared
when the process completes. The rolling oversampling mode
uses a first in, first out (FIFO) buffer of the most recent samples
in the averaging calculation, allowing the ADC throughput rate
and output data rate to stay the same.
In rolling average oversampling mode, all ADC conversions are
CS
controlled and initiated by the falling edge of . When a
conversion is complete, the result is loaded into the FIFO. The
FIFO length is 8, regardless of the oversampling ratio set. The
FIFO is filled on the first conversion after a power-on reset
(POR), on the first conversion after a software controlled hard
or soft reset. A new conversion result is shifted into the FIFO
on completion of every ADC conversion regardless of the status
of the OSR bits and the OS_MODE bit. This conversion allows
a seamless transition from no oversampling to rolling average
oversampling, or different rolling average oversampling ratios
without waiting for the FIFO to fill.
Rolling average oversampling mode is configured by setting the
OS_MODE bit to Logic 1 and having a valid nonzero value in
the OSR bits. The oversampling ratio of the digital filter is
controlled using the oversampling bits, OSR (see Table 12).
The number of samples, n, defined by the OSR bits are taken
from the FIFO, added together and the result is divided by n.
Table 12 provides the oversampling bit decoding to select the
different oversample rates. The output result is decimated to
16-bit resolution for the AD7389-4. If required, additional
resolution can be achieved by configuring the resolution boost
Table 12. Rolling Average Oversampling Overview
SNR with 2.5 V Internal Reference (dB Typical)
OSR, Bits[2:0]
OS Ratio
RES = 0
90.2
91.5
93.2
94.7
RES = 1
90.2
92.4
95
97.3
Data Output Rate (kSPS Ma2ximum)
000
001
010
011
110
111
No OS
2
4
8
Invalid
Invalid
2000
2000
2000
2000
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
V
CC
CS
INTERNAL
S1
ACQ
S2
ACQ
S3
ACQ
S4
ACQ
S5
ACQ
S6
ACQ
S7
ACQ
ENABLE OS = 2
S1
ENABLE OS = 4
SDI
SDOA
SDOB
(F + F + F + F )/4
DON’T CARE
S2
(F + F )/2
(F + F )/2
(F + F )/2
1
2
3
4
1
2
1
2
1
2
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
1
2
3
4
5
6
7
8
S
1
2
3
4
5
6
7
8
S
S
S
S
S
S
S
S
1
S
S
S
S
S
S
S
S
1
2
3
4
5
6
7
8
S
S
S
S
S
S
S
S
1
2
3
4
5
6
7
8
S
S
S
S
S
S
S
S
1
2
3
4
5
6
7
8
S
S
S
S
S
S
S
S
1
2
3
4
5
6
7
8
S
S
S
S
S
S
S
S
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
3
2
1
1
1
1
1
1
4
3
2
1
1
1
1
1
5
4
3
2
1
1
1
1
6
5
4
3
2
1
1
1
7
6
5
4
3
2
1
1
S
S
S
S
S
S
S
2
3
4
5
6
7
8
Figure 31. Rolling Average Oversampling Mode Configuration
Rev. 0 | Page 18 of 31
Data Sheet
AD7389-4
ALERT
CS
pin is cleared with a falling edge of . Issuing a
SDOD/
RESOLUTION BOOST
software reset also clears the alert status in the alert indication
register.
The default resolution and output data size for the AD7389-4 is
16 bits. When the on-chip oversampling function is enabled the
performance of the ADC can exceed the default resolution. To
accommodate the performance boost achievable, it is possible
to enable an additional two bits of resolution. If the RES bit in
the Configuration 1 register is set to Logic 1 and the AD7389-4
is in a valid oversampling mode, the conversion result size for
the AD7389-4 is 18 bits. In this mode, 18 SCLK cycles are
required to propagate the data for the AD7389-4.
ALERT
See Figure 8 for the
timing diagram.
POWER MODES
The AD7389-4 has two power modes that can be set in the
Configuration 1 register: normal mode and shutdown mode.
These modes of operation provide flexible power management
options, allowing optimization of the power dissipation and
throughput rate ratio for different application requirements.
ALERT
Program the PMODE bit in the Configuration 1 register to
configure the power modes in the AD7389-4. Set PMODE to
Logic 0 for normal mode and Logic 1 for shutdown mode.
The alert functionality is an out of range indicator and can be
used as an early indicator of an out of bounds conversion
result. An alert event triggers when the value in the conversion
result register exceeds the alert high limit value in the alert high
threshold register or falls below the alert low limit value in the
alert low threshold register. The alert high threshold register
and the alert low threshold register are common to all ADCs.
When setting the threshold limits, the alert high threshold must
always be greater than the alert low threshold. Detailed alert
information is accessible in the alert indication register.
Normal Mode
Keep the AD7389-4 in normal mode to achieve the fastest
throughput rate. All blocks within the AD7389-4 always remain
fully powered and an ADC conversion can be initiated by a
CS
falling edge of
when required. When the AD7389-4 is not
converting, it is in static mode and power consumption is
automatically reduced. Additional current is required to
perform a conversion. Therefore, power consumption of the
AD7389-4 scales with throughput.
The register contains two status bits per ADC, one corresponding
to the high limit, and the other to the low limit. A logical OR of
alert signals for all ADCs creates a common alert value. This
Shutdown Mode
ALERT
value can be configured to drive out on the
function of
pin is configured as
by configuring the following bits in the Configuration 1
register and the Configuration 2 register:
When slower throughput rates and lower power consumption
are required, use shutdown mode by either powering down the
ADC between each conversion or by performing a series of
conversions at a high throughput rate and then powering down
the ADC for a relatively long duration between these burst
conversions. When the AD7389-4 is in shutdown mode, all
analog circuitry powers down. The serial interface remains
active during shutdown mode to allow the AD7389-4 to exit
shutdown mode.
ALERT ALERT
the SDOD/
ALERT
pin. The SDOD/
Set the SDO bits to any value other than 0b10.
Set the ALERT_EN bit to 1.
Set a valid value in the alert high threshold register and the
alert low threshold register.
The alert indication function is available in oversampling
(rolling average, normal averaging, and in nonoversampling
modes).
To enter shutdown mode, write to the power mode
configuration bit, PMODE, in the Configuration 1 register.
The AD7389-4 shuts down, and current consumption reduces.
To exit shutdown mode and return to normal mode, set the
PMODE bit in the Configuration 1 register to Logic 0. All
register configuration settings remain unchanged entering or
leaving shutdown mode. After exiting shutdown mode, allow
sufficient time for the circuitry to turn on before starting a
conversion.
ALERT
The alert function of the SDOD/
pin updates at the end
ALERT
of conversion. The alert indication status bits in the
register are updated as well and must be read before the end of
the next conversion.
Bits[7:0] in the alert indication register are cleared by reading
the alert indication register contents. The alert function of the
CS
SCLK
1
2
3
14
15
16
17
18
SDOA
SDOB
DB
DB
DB
DB
DB
DB
DB
DB
0
17
16
15
4
3
2
1
SDI
DB
DB
DB
DB
DB
DB
0
15
14
13
2
1
Figure 32. Resolution Boost
Rev. 0 | Page 19 of 31
AD7389-4
Data Sheet
and FIFO are flushed. The alert indication register is cleared.
The reference and LDO regulator remain powered.
INTERNAL REFERENCE
The AD7389-uses a low noise, low drift (10 ppm/°C) 2.5 V
buffered internal reference during conversion. The internal
2.5 V reference of the AD7389-4 allows excellent performance
with typically 90.5 dB of SNR. When using the internal 2.5 V
reference for an external circuit, the internal 2.5 V reference can
be accessed via the REFOUT pin. It is recommended to add a
buffer, such as the ADA4807-2, when using the 2.5 V internal
reference as a source for a common-mode voltage (VCM).
Connecting a 1 µF capacitor to the REFOUT pin is
recommended.
tRESET
CS
SDI
SOFTWARE RESET
Figure 33. Software Reset Operation
A hard reset, in addition to the blocks reset by a soft reset,
resets all user registers to the default status, resets the reference
buffer, and resets the internal oscillator block.
DIAGNOSTIC SELF TEST
SOFTWARE RESET
The AD7389-4 runs a diagnostic self test after a POR or after a
software hard reset to ensure the correct configuration is
loaded into the device.
The AD7389-4 has two reset modes: a soft reset and a hard
reset. A reset is initiated by writing to the reset bits in the
Configuration 2 register.
The result of the self test is displayed in the SETUP_F bit in the
alert indication register. If the SETUP_F bit is set to Logic 1, the
diagnostic self test has failed. If the test fails, perform a software
hard reset to reset the AD7389-4 registers to the default status.
A soft reset maintains the contents of the configurable registers
but refreshes the interface and the ADC blocks. Any internal
state machines are reinitialized, and the oversampling block
tSTARTUP
CS
SDI
SHUTDOWN
SHUTDOWN MODE
NORMAL
NORMAL MODE
ACCURATE CONVERSION
Figure 34. Shutdown Mode Operation
Rev. 0 | Page 20 of 31
Data Sheet
AD7389-4
INTERFACE
The interface to the AD7389-4 is via a serial interface. The
The conversion result is shifted out of the device as a 16-bit
result for the AD7389-4. The MSB of the conversion result is
CS
out of the device under the control of the serial clock (SCLK)
input. The data is shifted out on the rising edge of SCLK, and
the data bits are valid on both the falling edge and the rising
CS
interface consists of , SCLK, SDOA, SDOB, SDOC, and
shifted out on the
falling edge. The remaining data is shifted
SDOD, and SDI. When referencing a single function of a
multifunction pin, only the portion of the pin name that is relevant
to the specification is listed, such as SDOD. For full pin names of
multifunction pins, refer to the Pin Configuration and Function
Descriptions section.
CS
edge. After the final SCLK falling edge, take
high again to
return the serial data output pins to a high impedance state.
CS
The
signal frames a serial data transfer and initiates an ADC
CS
The number of SCLK cycles to propagate the conversion results
on the serial data output pins is dependent on the serial mode
of operation configured and if resolution boost mode is enabled
(see Figure 35 and Table 13 for details). If CRC reading is
enabled, additional SCLK pulses are required to propagate the
CRC information. See the CRC section for more details.
conversion process. The falling edge of
puts the track-and-
hold into hold mode, at which point the analog input is
sampled and the bus is taken out of three-state. The ADC
conversion operation is driven internally by an on-board
oscillator and is independent of the SCLK signal.
The SCLK signal synchronizes data in and out of the device via
the SDOA, SDOB, SDOC, SDOD, and SDI signals. A minimum
of 16 SCLK cycles are required for a write to or read from a
register. The minimum numbers of SCLK cycles for a
conversion read is dependent on the resolution of the device
and the configuration settings (see Table 13).
CS
Because the
signal initiates a conversion as well as framing
the data, any data access must be completed within a single frame.
Table 13. Number of SCLK Cycles (n) Required for Reading
Conversion Results
Interface
Configuration
Resolution
Boost Mode
CRC
Read
No. of SCLK
Cycles
The ADC conversion operation is driven internally by an
on-board oscillator and is independent of the SCLK signal.
4-Wire
2-Wire
1-Wire
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled 16
Enabled 24
Disabled 18
Enabled 26
Disabled 32
Enabled 40
Disabled 36
Enabled 44
Disabled 64
Enabled 72
Disabled 72
Enabled 80
The AD7389-4 has four serial output signals: SDOA, SDOB,
SDOC, and SDOD. Programming the SDO bits in the
Configuration 2 register configures 2-wire, 1-wire, or 4-wire
mode. To achieve the highest throughput of the device, it is
required to use either the 2-wire or 4-wire mode to read the
conversion results. If a reduced throughput is required or
oversampling is used, it is possible to use 1-wire mode, SDOA
signal only, for reading conversion results.
Configuring cyclic redundancy check (CRC) operation for SPI
reads, SPI writes, and oversampling mode with resolution boost
mode enabled can alter the operation of the interface. Refer to
the CRC section to ensure correct operation.
Serial 4-Wire Mode
READING CONVERSION RESULTS
Configure 4-wire mode by setting the SDO bits to 0b10 in the
Configuration 2 register. In 4-wire mode, the conversion results
for ADC A is output on SDOA, ADC B on SDOB, ADC C on
SDOC, and ADC D on SDOD.
CS
The
signal initiates the conversion process. A high to low
CS
transition on the
signal initiates a simultaneous conversion
of the four ADCs, ADC A, ADC B, ADC C, and ADC D. The
AD7389-4 has a one-cycle readback latency. Therefore, the
conversion results are available on the next SPI access. Then,
Serial 2-Wire Mode
Configure 2-wire mode by setting the SDO bits to 0b00 in the
Configuration 2 register. In 2-wire mode, the conversion results
for ADC A and ADC C are output on SDOA. The conversion
result for ADC B and ADC D are output on SDOB.
CS
take the
signal low, and the conversion result clocks out on
the serial data output pins. The next conversion is also initiated
at this point.
CS
1
n – 2
n – 1
n
1
2
3
SCLK
SDOx
1
CONVERSION RESULTS
CONSULT TABLE 12 FOR VALUES FOR n, THE NUMBER OF SCLK PULSES REQUIRED.
Figure 35. Reading Conversion Results
Rev. 0 | Page 21 of 31
AD7389-4
Data Sheet
Serial 1-Wire Mode
LOW LATENCY READBACK
In applications where slower throughput rates are allowed or
normal averaging oversampling is used, the serial interface can
be configured to operate in 1-wire mode. In 1-wire mode, the
conversion results from ADC A, ADC B, ADC C, and ADC D
are output on SDOA. Additional SCLK cycles are required to
propagate all data. ADC A data is output first followed by the
ADC B, ADC C, and ADC D conversion results.
The interface on the AD7389-4 has a one-cycle latency as
shown in Figure 36. For applications that operate at lower
throughput rates the latency of reading the conversion result
can be reduced. After the conversion time (tCONVERT) elapses, a
CS
CS
second
pulse after the initial
pulse that initiated the
conversion can be used to read back the conversion result. This
operation is shown in Figure 39.
S
S
S
S
0
1
2
3
CS
SDOA
SDOB
SDOC
SDOD
SDI
S
S
S
S
S
S
S
S
INVALID
INVALID
INVALID
INVALID
NOP
1A
1B
1C
1D
0A
0B
0C
0D
NOP
NOP
Figure 36. Read Conversion Results, 4-Wire Mode
S
S
S
3
0
1
2
CS
SDOA
SDOB
SDI
INVALID
S
S
S
S
S
S
S
S
0A
0C
1A
1C
INVALID
NOP
0B
0D
1B
1D
NOP
NOP
Figure 37. Reading Conversion Results, 2-Wire Mode
S
S
S
3
0
1
2
CS
SDOA
SDI
S
S
S
S
0D
S
S
S
S
1D
INVALID
NOP
0A
0B
0C
1A
1B
1C
NOP
NOP
Figure 38. Read Conversion Results, 1-Wire Mode
CS
CNV
DON'T CARE
ACQ
CNV
DON'T CARE
RESULT
ACQ
INTERNAL
n
n + 1
SDOA
SDOB
RESULT
n
n + 1
SCLK
TARGET SAMPLE PERIOD
Figure 39. Low Throughput Low Latency
Rev. 0 | Page 22 of 31
Data Sheet
AD7389-4
function for SPI writes to prevent unexpected changes to the
device configuration but do not enable it on SPI reads to
maintain a higher throughput rate. The CRC feature is controlled
by programming of the CRC_W bit and CRC_R bit in the
Configuration 1 register.
READING FROM DEVICE REGISTERS
All registers in the device can be read over the serial interface. A
register read is performed by issuing a register read command
followed by an additional SPI command that can be either a
valid command or no operation command (NOP). The format
for a read command is shown in Table 16. Bit D15 must be set
to 0 to select a read command. Bits[D14:D12] contain the
register address. The subsequent 12 bits, Bits[D11:D0], are
ignored.
CRC Read
If enabled, a CRC consisting of an 8-bit word is appended to the
conversion result or register reads. The CRC is calculated on the
conversion result for ADC A, ADC B, ADC C, and ADC D, and
is output on SDOA. A CRC is also calculated and appended to
register read outputs.
WRITING TO DEVICE REGISTERS
All the read/write registers in the AD7389-4 can be written to
over the serial interface. The length of an SPI write access is
determined by the CRC write function. An SPI access is 16-bit
if CRC write is disabled and 24-bit when CRC write is enabled.
The format for a write command is shown in Table 16. Bit D15
must be set to 1 to select a write command. Bits[D14:D12] contain
the register address. The subsequent 12 bits, Bits[D11:D0],
contain the data to be written to the selected register.
The CRC read function can be used in 2-wire SPI mode, 1-wire
SPI mode, 4-wire SPI mode, and resolution boost mode.
CRC Write
To enable the CRC write function, the CRC_W bit in the
Configuration 1 register must be set to 1. To set the CRC_W bit
to 1 to enable the CRC feature, a valid CRC must be appended
to the request frame.
CRC
After the CRC feature is enabled, all register write requests are
ignored unless they are accompanied by a valid CRC command.
A valid CRC is required to both enable and disable the CRC
write feature.
The AD7389-4 has CRC checksum modes that can be used to
improve interface robustness by detecting errors in data
transmissions. The CRC feature is independently selectable for
SPI interface reads and writes. For example, enable the CRC
S
S
S
S
S
4
0
1
2
3
CS
SDI
NOP
READ REG 1
READ REG 2
REG 1 DATA
NOP
NOP
SDOA
INVALID
INVALID
RESULT S
REG 2 DATA
RESULT S
3
0
SDOB
SDOC
SDOD
RESULT S
RESULT S
3
0
Figure 40. Register Read
S
S
S
2
S
3
0
1
CS
SDI
NOP
WRITE REG 1
WRITE REG 2
NOP
SDOx
INVALID
RESULT S
RESULT S
RESULT S
2
0
1
Figure 41. Register Write
Rev. 0 | Page 23 of 31
AD7389-4
Data Sheet
adjacent to the leftmost Logic 1 of the new result, and the
CRC Polynomial
procedure is repeated. This process repeats until the original
data is reduced to a value less than the polynomial, which is the
8-bit checksum.
For CRC checksum calculations, the following polynomial is
always used: x8 + x2 + x + 1.
To generate the checksum, the 16-bit data conversion result of
the four channels are combined to produce a 64-bit data
stream. The 8 MSBs of the 64-bit data are inverted and then the
data is appended by eight bits to create a number ending in
eight Logic 0s. The polynomial is aligned such that its MSB is
adjacent to the leftmost Logic 1 of the data. An exclusive OR
(XOR) function is applied to the data to produce a new, shorter
number. The polynomial is again aligned such that its MSB is
For example, the AD7389-4 polynomial is 100000111. Let the
original data of four channels be 0xAAAA, 0x5555, 0xAAAA,
and 0x5555. The eight MSBs of the data are inverted. The data
is then appended to include eight 0s on right. In the final XOR
operation, the reduced data is less than the polynomial.
Therefore, the remainder is the CRC for the assumed data.
Table 14. Example CRC Calculation for 4-Channel, 16-Bit Data
Data
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X1 X1 X1 X1 X1 X1 X1 X1
Process Data 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
1
1
1
1
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
CRC
0
0
1 X means don’t care.
Rev. 0 | Page 24 of 31
Data Sheet
AD7389-4
16 + 16 + 8 = 40 BITS
RESULT C
CRC
SDOA
SDOB
RESULT A
A,B,C,D
2-WIRE 16-BIT
RESULT B
RESULT D
16 + 16 + 16 + 16 + 8 = 72 BITS
CRC
A,B,C,D
RESULT A
RESULT B
RESULT C
RESULT D
1-WIRE 16-BIT
2-WIRE 18-BIT
SDOA
18 + 18 + 8 = 44 BITS
RESULT C
CRC
SDOA
SDOB
RESULT A
RESULT B
A,B,C,D
RESULT D
18 + 18 + 18 + 18 + 8 = 80 BITS
RESULT B RESULT C
CRC
SDOA
RESULT A
RESULT D
A,B,C,D
1-WIRE 18-BIT
4-WIRE 16-BIT
16 + 8 = 24 BITS
RESULT A
CRC
SDOA
SDOx
A,B,C,D
RESULT x
18 + 8 = 26 BITS
RESULT A
CRC
SDOA
SDOx
A,B,C,D
4-WIRE 18-BIT
RESULT x
16 + 8 = 24 BITS
REGISTER
CRC
REGISTER x
SDOA
SDI
REG x
READ RESULT
16 + 8 = 24 BITS
REGISTER
READ REQUEST
CRC
REGISTER x
REG x
16 + 8 = 24 BITS
REGISTER
WRITE
CRC
SDI
WRITE REGISTER x
REG x
Figure 42. CRC Operation
Rev. 0 | Page 25 of 31
AD7389-4
Data Sheet
REGISTERS
The AD7389-4 has user-programmable, on-chip registers for configuring the device. Table 15 shows a complete overview of the registers
available on the AD7389-4.
The registers are either read/write (R/W) or read only (R). Any read request to a write only register is ignored. Any write to a read only
register is ignored. Writes to the NOP registers and the reserved register are ignored. Any read request to the NOP registers or reserved
registers are considered a no operation and the data transmitted in the next SPI frame are the conversion results.
Table 15. Register Description
Bit 15
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Reg Name
Bits
Bit 7
Reset
RW
0x1 Configuration 1 [15:8]
ADDRESSING
CRC_W
RESERVED
OS_MODE OSR, Bit 2
0x0000 R/W
[7:0]
0x2 Configuration 2 [15:8]
[7:0]
OSR, Bits[1:0]
CRC_R
ALERT_EN RES
RESERVED
RESERVED
PMODE
SDO
ADDRESSING
0x0000 R/W
RESET
0x3 Alert indication [15:8]
[7:0]
ADDRESSING
RESERVED
CRCW_F
SETUP_F
0x0000
R
AL_D_HIGH AL_D_LOW AL_C_HIGH AL_C_LOW AL_B_HIGH AL_B_LOW AL_A_HIGH AL_A_LOW
0x4 Alert low
threshold
[15:8]
[7:0]
ADDRESSING
ALERT_LOW, Bits[11:8]
0x0800 R/W
0x07FF R/W
ALERT_LOW, Bits[7:0]
ALERT_HIGH, Bits[7:0]
0x5 Alert high
threshold
[15:8]
[7:0]
ADDRESSING
ALERT_HIGH, Bits[11:8]
ADDRESSING REGISTERS
A serial register transfer on the AD7389-4 consists of 16 SCLK cycles. The four MSBs written to the device are decoded to determine
which register is addressed. The four MSBs consist of the register address (REGADDR), Bits[2:0], and the read/write bit (WR). The
register address bits determine which on-chip register is selected. If the addressed register is a valid write register, the read/write bit
determines whether the remaining 12 bits of data on the SDI input are loaded into the addressed register. If the WR bit is 1, the bits load
into the register addressed by the register select bits. If the WR bit is 0, the command is seen as a read request. The addressed register
data is available to be read during the next read operation.
Table 16. Addressing Register Format
MSB
D15
WR
LSB
D0
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
REGADDR, Bits[2:0]
Data, Bits[11:0]
Table 17. Bit Descriptions for Addressing Registers
Bit
Mnemonic
Description
D15
WR
When a 1 is written to this bit, Bits[11:0] of this register are written to the register specified by REGADDR if it
is a valid address.
Alternatively, when a 0 is written, the next data sent out on the SDOA pin is a read from the designated
register if it is a valid address.
D14 to D12 REGADDR
When WR = 1, the contents of REGADDR determine the register for selection as outlined in Table 15.
When WR = 0 and the REGADDR bits contain a valid register address, the contents on the requested register
are output on the SDOA pin during the next interface access.
When WR = 0 and the REGADDR bits contain 0x0, 0x6, or 0x7, the contents on the SDI line are ignored. The
next interface access results in the conversion results being read back.
D11 to D0
Data
These bits are written into the corresponding register specified by the REGADDR bits when the WR bit = 1
and the REGADDR bits contain a valid address.
Rev. 0 | Page 26 of 31
Data Sheet
AD7389-4
CONFIGURATION 1 REGISTER
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[15:12] ADDRESSING (R/W)
[0] PMODE (R/W)
Addressing.
Power-Down Mode.
[11:10] RESERVED
[1] RESERVED
[9] OS_MODE (R/W)
[2] RES (R/W)
Oversampling Mode.
Resolution.
[8:6] OSR (R/W)
[3] ALERT_EN (R/W)
Oversampling Ratio.
Enable Alert Indicator Function.
[5] CRC_W (R/W)
[4] CRC_R (R/W)
CRC Write.
CRC Read.
Table 18. Bit Descriptions for Configuration 1 Register
Bits Bit Name Description
Reset Access
[15:12] ADDRESSING Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers 0x0
section for further details.
R/W
[11:10] RESERVED
Reserved.
0x0
0x0
R
9
OS_MODE
Oversampling Mode. Sets the oversampling mode of the ADC.
0: normal averaging.
R/W
1: rolling average.
[8:6]
OSR
Oversampling Ratio. Sets the oversampling ratio for all the ADCs in the relevant mode. Normal
averaging mode supports oversampling ratios of 2×, 4×, 8×, 16×, and 32×. Rolling average
mode supports oversampling ratios of 2×, 4×, and 8×.
0x0
R/W
000: disabled.
001: 2×.
010: 4×.
011: 8×.
100: 16×.
101: 32×.
110: disabled.
111: disabled.
5
CRC_W
CRC Write. Controls the CRC functionality for the SDI interface When setting this bit from a 0 to
a 1, the command must be followed by a valid CRC to set this configuration bit. If a valid CRC is
not received, the entire frame is ignored. If the bit is set to 1, it requires a CRC to clear it to 0.
0x0
R/W
0: no CRC function.
1: CRC function.
4
3
CRC_R
CRC Read. Controls the CRC functionality for the SDOx interface
0: no CRC function.
1: CRC function.
0x0
0x0
R/W
R/W
ALERT_EN
Enable Alert Indicator Function. This bit functions when the SDO bits = 01. Otherwise, the
ALERT_EN bit is ignored.
0: SDOB.
1: ALERT.
2
RES
Resolution. Sets the size of the conversion result data. If OSR = 0, these bits are ignored and the 0x0
resolution is set to default resolution.
R/W
0: normal resolution.
1: 2-bit higher resolution.
1
0
RESERVED
PMODE
Reserved.
0x0
0x0
R/W
R/W
Power-Down Mode. Sets the power modes.
0: normal mode.
1: shutdown mode.
Rev. 0 | Page 27 of 31
AD7389-4
Data Sheet
CONFIGURATION 2 REGISTER
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[15:12] ADDRESSING(R/W)
[7:0] RESET (R/W)
Addressing
Reset
[11:10] RESERVED
[9:8] SDO (R/W)
SDO
Table 19. Bit Descriptions for Configuration 2 Register
Bits Bit Name Description
Reset Access
[15:12] ADDRESSING Addressing. Bits[15:12] define the address of the relevant register. See the Addressing
Registers section for further details.
0x0
R/W
[11:10] RESERVED
Reserved.
0x0
0x0
R
R/W
[9:8]
SDO
SDO. Conversion Results Serial Data Output
00: 2-wire. Conversion data are output on both SDOA and SDOB.
01: 1-wire. Conversion data are output on SDOA only.
10: 4-wire. Conversion data are output on SDOA, SDOB, SDOC, and SDOD/ALERT.
11: 1-wire. Conversion data are output on SDOA only.
Reset.
[7:0]
RESET
0x0
R/W
0x3C: performs a soft reset. Refreshes some blocks. Register contents remain unchanged.
Clears alert indication register and flushes any oversampling stored variables or active state
machine.
0xFF: performs a hard reset. Resets all possible blocks in the device. Registers contents are
set to defaults. All other values are ignored.
ALERT INDICATION REGISTER
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[15:12] ADDRESSING (R)
[0] AL_A_LOW (R)
Addressing.
Alert A Low.
[11:10] RESERVED
[1] AL_A_HIGH (R)
Alert A High.
[9] CRCW_F (R)
CRC Error.
[2] AL_B_LOW (R)
Alert B Low.
[8] SETUP_F (R)
Load Error.
[3] AL_B_HIGH (R)
Alert B High.
[7] AL_D_HIGH (R)
Alert D High.
[4] AL_C_LOW (R)
Alert C Low.
[6] AL_D_LOW (R)
Alert D Low.
[5] AL_C_HIGH (R)
Alert C High.
Table 20. Bit Descriptions for Alert Indication Register
Bits Bit Name Description
Reset Access
[15:12] ADDRESSING Addressing. Bits[15:12] define the address of the relevant register. See the Addressing
Registers section for further details.
0x0
R
[11:10] RESERVED
Reserved.
0x0
0x0
R
R
9
CRCW_F
CRC Error. Indicates that a register write command failed due to a CRC error. This fault bit is
sticky and remains set until the register is read
0: no CRC error.
1: CRC error.
8
SETUP_F
Load Error. The SETUP_F indicates that the device configuration data did not load correctly
on startup. This bit does not clear on an alert indication register read. A hard reset via the
Configuration 2 register is required to clear this bit and restart the device setup again.
0: no setup error.
1: setup error.
Alert D High. The alert indication high bit indicates if a conversion result for the respective
input channel exceeds the value set in the alert high threshold register. This fault bit is sticky
and remains set until the register is read.
0x0
0x0
R
R
7
AL_D_HIGH
1: alert indication.
0: no alert indication.
Rev. 0 | Page 28 of 31
Data Sheet
AD7389-4
Bits
Bit Name
Description
Reset Access
6
AL_D_LOW
AL_C_HIGH
AL_C_LOW
AL_B_HIGH
AL_B_LOW
AL_A_HIGH
AL_A_LOW
Alert D Low. The alert indication low bit indicates if a conversion result for the respective
input channel exceeds the value set in the alert low threshold register. This fault bit is sticky
and remains set until the register is read.
0: no alert indication.
1: alert indication.
Alert C High. The alert indication high bit indicates if a conversion result for the respective
input channel exceeds the value set in the alert high threshold register. This fault bit is sticky
and remains set until the register is read.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R
R
R
R
R
R
R
5
4
3
2
1
0
1: alert indication.
0: no alert indication.
Alert C Low. The alert indication low bit indicates if a conversion result for the respective
input channel exceeds the value set in the alert low threshold register. This fault bit is sticky
and remains set until the register is read.
1: alert indication.
0: no alert indication.
Alert B High. The alert indication high bit indicates if a conversion result for the respective
input channel exceeds the value set in the alert high threshold register. This fault bit is sticky
and remains set until the register is read.
1: alert indication.
0: no alert indication.
Alert B Low. The alert indication low bit indicates if a conversion result for the respective
input channel exceeds the value set in the alert low threshold register. This fault bit is sticky
and remains set until the register is read.
1: alert indication.
0: no alert indication.
Alert A High. The alert indication high bit indicates if a conversion result for the respective
input channel exceeds the value set in the alert high threshold register. This fault bit is sticky
and remains set until the register is read.
0: no alert indication.
1: alert indication.
Alert A Low. The alert indication low bit indicates if a conversion result for the respective
input channel exceeds the value set in the alert low threshold register. This fault bit is sticky
and remains set until the register is read.
1: alert indication.
0: no alert indication.
ALERT LOW THRESHOLD REGISTER
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
[15:12] ADDRESSING (R/W)
[11:0] ALERT_LOW (R/W)
Addressing
Alert Low
Table 21. Bit Descriptions for Alert Low Threshold Register
Bits Bit Name Description
[15:12] ADDRESSING Addressing. Bits[15:12] define the address of the relevant register. See the Addressing
Registers section for further details.
Reset Access
0x0 R/W
[11:0]
ALERT_LOW
Alert Low. Bits[11:0] from ALERT_LOW move to the MSBs of the internal alert low register,
D[15:4]. The remaining bits, D[3:0] of the internal register are fixed at 0x0. Sets an alert when
the converter result is below the value in the alert low threshold register, and the alert is
disabled when it is above the value in the alert low threshold register.
0x800 R/W
Rev. 0 | Page 29 of 31
AD7389-4
Data Sheet
ALERT HIGH THRESHOLD REGISTER
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
[15:12] ADDRESSING (R/W)
[11:0] ALERT_HIGH (R/W)
Addressing
Alert High
Table 22. Bit Descriptions for Alert High Threshold Register
Bits Bit Name Description
Reset Access
[15:12] ADDRESSING Addressing. Bits[15:12] define the address of the relevant register. See the Addressing
Registers section for further details.
0x0
R/W
[11:0]
ALERT_HIGH Alert High. Bits D[11:0] from ALERT_HIGH move to the MSBs of the internal alert high
register, D[15:4]. The remaining bits, D[3:0] of the internal are fixed at 0xF. Sets an alert when
the converter result is above the value in the alert high threshold register, and the alert is
disabled when it is below the value in the alert high threshold register.
0x7FF R/W
Rev. 0 | Page 30 of 31
Data Sheet
AD7389-4
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.20
PIN 1
CORNER
1
PIN
INDICATOR
19
24
18
1
0.50
BSC
0.60
0.50 SQ
0.40
0.45
0.40
0.30
13
12
6
7
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.60
0.55
0.50
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.050 MAX
0.035 NOM
COPLANARITY
SEATING
PLANE
0.08
SECTION OF THIS DATA SHEET.
0.152 REF
COMPLIANT TO JEDEC STANDARDS MO-248-UGGD
Figure 43. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.55 mm Package Height
(CP-24-25)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3
AD7389-4BCPZ
AD7389-4BCPZ-RL
AD7389-4BCPZ-RL7
EVAL-AD7380-4FMCZ
EVAL-SDP-CH1Z
Resolution
16-Bit
16-Bit
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
CP-24-25
CP-24-25
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
AD7380-4 Evaluation Board
16-Bit
CP-24-25
Evaluation Board Controller
1 Z = RoHS Compliant Part.
2 The EVAL-AD7380-4FMCZ is configurable to use with the AD7389-4.
3 The EVAL-AD7380-4FMCZ is compatible with the EVAL-SDP-CH1Z high speed controller board.
©2022 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D22956-1/22(0)
Rev. 0 | Page 31 of 31
相关型号:
AD7389-4BCPZ-RL
Differential Input, Quad, Internal Reference Simultaneous Sampling, 16-Bit SAR ADC
ADI
AD7389-4BCPZ-RL7
Differential Input, Quad, Internal Reference Simultaneous Sampling, 16-Bit SAR ADC
ADI
AD7390AR-REEL
IC SERIAL INPUT LOADING, 70 us SETTLING TIME, 12-BIT DAC, PDSO8, 1.75 MM HEIGHT, SOIC-8, Digital to Analog Converter
ADI
©2020 ICPDF网 联系我们和版权申明