AD7305YR [ADI]
+3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC; 3 V / + 5 V ，轨到轨四路， 8位DAC
| 型号： | AD7305YR |
| 厂家： | 
ADI |
| 描述： | +3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC |
| 文件： | 总14页 (文件大小：931K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
+3 V/+5 V, Rail-to-Rail
Quad, 8-Bit DAC
a
AD7304/AD7305*
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Four 8-Bit DACs in One Package
+3 V, +5 V and ꢀ5 V Operation
Rail-to-Rail REF-Input to Voltage Output Swing
2.6 MHz Reference Multiplying Bandwidth
Compact 1.1 mm Height TSSOP 16-/20-Lead Package
Internal Power ON Reset
SPI Serial Interface Compatible—AD7304
Fast Parallel Interface—AD7305
40 ꢁA Power Shutdown
V
B V A
V
REF REF
DD
8
8
8
8
8
8
8
8
PWR ON
RESET
INPUT
REG A
DAC A
REG
DAC A
DAC B
DAC C
DAC D
V
V
A
B
OUT
OUT
8
INPUT
REG B
DAC B
REG
CS
SDI/SHDN
CLK
INPUT
REG C
DAC C
REG
V
V
C
D
OUT
OUT
SERIAL
REG
INPUT
REG D
DAC D
REG
APPLICATIONS
Automotive Output Span Voltage
Instrumentation, Digitally Controlled Calibration
Pin-Compatible AD7226 Replacement when VDD < 5.5 V
AD7304
V
C V D
REF
V
GND
CLR LDAC
SS
REF
V
V
REF
DD
8
8
8
8
8
GENERAL DESCRIPTION
PWR ON
RESET
INPUT
REG A
DAC A
DAC A
DAC B
DAC C
DAC D
V
V
A
B
REG
OUT
OUT
The AD7304/AD7305 are quad, 8-bit DACs that operate from a
single +3 V to +5 V supply or 5 V supplies. The AD7304 has a
serial interface, while the AD7305 has a parallel interface. Inter-
nal precision buffers swing rail-to-rail. The reference input range
includes both supply rails allowing for positive or negative full-
scale output voltages. Operation is guaranteed over the supply
voltage range of +2.7 V to +5.5 V, consuming less than 9 mW
from a +3 V supply.
DB0
DB1
DB2
DB3
DB4
DB5
DB6
8
INPUT
REG B
DAC B
REG
8
8
DAC C
REG
INPUT
REG C
V
C
D
OUT
8
INPUT
REG D
DAC D
REG
V
OUT
WR
A0/SHDN
A1
DECODE
AD7305
The full-scale voltage output is determined by the external refer-
ence input voltage applied. The rail-to-rail VREF input to DAC
V
LDAC
GND
SS
V
V
OUT allows for a full-scale voltage set equal the positive supply
DD, the negative supply VSS or any value in between.
An internal power ON reset places both parts in the zero-scale
state at turn ON. A 40 µA power shutdown (SHDN) feature is
activated on both parts by tristating the SDI/SHDN pin on the
AD7304, and tristating the A0/SHDN address pin on the
AD7305.
The AD7304’s doubled-buffered serial-data interface offers high
speed, three-wire, SPI and microcontroller compatible inputs
using data in (SDI), clock (CLK) and chip select (CS) pins.
Additionally, an internal power-on reset sets the output to zero
scale.
The AD7304/AD7305 are specified over the extended industrial
(–40°C to +85°C), and the automotive (–40°C to +125°C)
temperature ranges. AD7304s are available in 16-lead plastic
DIP (N-16), and wide-body SOL-16 (R-16) packages. The
parallel input AD7305 is available in the 20-lead plastic DIP
(N-20), and the SOL-20 (R-20) surface mount package. For
ultracompact applications the thin 1.1 mm TSSOP-16 (RU-16)
package will be available for the AD7304, while the TSSOP-20
(RU-20) will house the AD7305.
The parallel input AD7305 uses a standard address decode
along with the WR control line to load data into the input regis-
ters. The double buffered architecture allows all four input
registers to be preloaded with new values, followed by a LDAC
control strobe which copies all the new data into the DAC regis-
ters thereby updating the analog output values. When operating
from less than +5.5 V, the AD7305 is pin-compatible with the
popular industry standard AD7226.
*Protected under Patent Number 5684481.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
(@ VDD = +3 V or +5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, VSS
≤ V ≤ VDD, –40ꢂC < TA < +85ꢂC/+125ꢂC, unless otherwise noted.)
AD7304/AD7305–SPECIFICATIONS
REF
Parameter
Symbol
Condition
3 V ꢀ 10% 5 V ꢀ 10% ꢀ5 V ꢀ 10%
Units
STATIC PERFORMANCE
Resolution1
N
8
8
8
5
Bits
Integral Nonlinearity2
Differential Nonlinearity
Zero-Scale Error
INL
DNL
VZSE
VFSE
TCVFS
1
1
1
1
1
1
15
4
LSB max
LSB max
mV max
LSB max
ppm/°C typ4
Monotonic, All Codes 0 to FFH
Data = 00H
Data = FFH
15
4
5
15
4
5
Full-Scale Voltage Error
Full-Scale Tempco3
REFERENCE INPUT
V
REFIN Range
VREFIN
RREFIN
RREFIN
CREFIN
VSS/VDD
VSS/VDD
VSS/VDD
V min/max
kΩ typ
kΩ typ
pF typ
Input Resistance (AD7304)
Input Resistance (AD7305)
Input Capacitance3
Code = 55H
All DACs at Code = 55H
28
7.5
5
28
7.5
5
28
7.5
5
ANALOG OUTPUTS
Output Voltage Range
Output Current Drive
Shutdown Resistance
Capacitive Load3
VOUT
IOUT
ROUT
CL
VSS/VDD
3
VSS/VDD
3
120
VSS/VDD
3
120
V min/max
mA typ
kΩ typ
Code = 80H, ∆VOUT < 1 LSB
DAC Outputs Placed in Shutdown State 120
No Oscillation
200
200
200
pF typ
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current5
Input Capacitance3
VIL
VIH
IIL
0.6
2.1
10
8
0.8
2.4
10
8
0.8
2.4
10
8
V min
V max
µA max
pF max
CIL
AC CHARACTERISTICS3
Output Slew Rate
Reference Multiplying
Total Harmonic Distortion
Settling Time6
Shutdown Recovery Time
Time to Shutdown
DAC Glitch
Digital Feedthrough
Feedthrough
SR
BW
THD
tS
tSDR
tSDN
Q
Code = 00H to FFH to 00H
Small Signal, VSS = –5 V
VREF = 4 V p-p, VSS = –5 V, f = 1 kHz
To 0.1% of Full Scale
1/2.7
1/3.6
1/3.6
2.6
0.025
1.0/2
2
15
15
2
–65
V/µs min/typ
MHz typ
%
µs typ/max
µs max
µs typ
nVs typ
nVs typ
dB
1.1/2
2
15
15
2
1.0/2
2
15
15
2
To 0.1% of Full Scale
Q
VOUT/VREF Code = 00H, VREF =1 V p-p, f = 100 kHz
SUPPLY CHARACTERISTICS
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Down
Power Supply Sensitivity
IDD
ISS
PDISS
IDD_SD
PSS
VLOGIC = 0 V or VDD, No Load
VSS = –5 V
VLOGIC = 0 V or VDD, No Load
SDI/SHDN = Floating
6
6
6
6
mA max
mA max
mW max
µA typ
15
40
0.004
30
40
0.004
60
40
0.004
∆VDD
=
10%
%/%
NOTES
1One LSB = VREF/256.
2The first three codes (00H, 01H, 10H) are excluded from the integral nonlinearity error measurement in single supply operation +3 V or +5 V.
3These parameters are guaranteed by design and not subject to production testing.
4Typicals represent average readings measured at +25°C.
5SDI/SHDN and A0/SHDN pins have 30 µA maximum IIL input leakage current.
6The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground in single supply operation.
Specifications subject to change without notice.
5V
V
= 10V p-p
REF
f = 20kHz
5V
0V
0V
–5V
V
= 10V p-p
OUT
–5V
(OUT)
(IN)
Figure 1. AD7304/AD7305 Rail-to-Rail Reference Input to Output at 20 kHz
–2–
REV. A
AD7304/AD7305
(@ VDD = +3 V or +5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, VSS ≤ VREF ≤ VDD, –40ꢂC < TA <
+85ꢂC/125ꢂC, unless otherwise noted.)
TIMING SPECIFICATIONS
Parameter
Symbol
3 V ꢀ 10%
5 V ꢀ 10%
ꢀ5 V ꢀ 10%
Units
INTERFACE TIMING SPECIFICATIONS1, 2
AD7304 Only
Clock Width High
Clock Width Low
Data Setup
Data Hold
Load Pulsewidth
Load Setup
Load Hold
Clear Pulsewidth
Select
tCH
tCL
tDS
tDH
tLDW
tLD1
tLD2
tCLWR
tCSS
tCSH
70
70
50
30
70
40
40
60
30
60
55
55
40
20
60
30
30
60
20
40
55
55
40
20
60
30
30
60
20
40
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Deselect
AD7305 Only
Data Setup
Data Hold
Address Setup
Address Hold
Write Width
Load Pulsewidth
Load Setup
tDS
tDH
tAS
tAH
tWR
tLDW
tLS
60
30
60
30
60
60
60
30
40
20
40
20
50
50
40
20
40
20
40
20
50
50
40
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Load Hold
tLH
NOTES
1These parameters are guaranteed by design and not subject to production testing.
2All input control signals are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
Temperature
Range
Package
Description
Package
Options
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –8 V
Model
VREFX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
Logic Inputs to GND . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
AD7304BN
AD7304BR
AD7304YR
AD7304BRU
–40°C/+85°C
–40°C/+85°C
–40°C/+125°C
–40°C/+85°C
16-Lead P-DIP N-16
16-Lead SOIC R-16
16-Lead SOIC R-16
VOUTX to GND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . . (TJ MAX–TA)/θJA
Thermal Resistance θJA
TSSOP-16
RU-16
AD7305BN
AD7305BR
AD7305YR
AD7305BRU
–40°C/+85°C
–40°C/+85°C
–40°C/+125°C
–40°C/+85°C
20-Lead P-DIP N-20
20-Lead SOIC R-20
20-Lead SOIC R-20
16-Lead Plastic DIP Package (N-16) . . . . . . . . . . 103°C/W
16-Lead SOIC Package (R-16) . . . . . . . . . . . . . . . 73°C/W
TSSOP-16 Package (RU-16) . . . . . . . . . . . . . . . . 180°C/W
20-Lead Plastic DIP Package (N-20) . . . . . . . . . . 120°C/W
20-Lead SOIC Package (R-20) . . . . . . . . . . . . . . . 74°C/W
TSSOP-20 Package (RU-20) . . . . . . . . . . . . . . . . 155°C/W
TSSOP-20
RU-20
The AD7304/AD7305 contains 2759 transistors. Die size: 103 mil × 102 mil,
10,506 sq mil.
Maximum Junction Temperature (TJ MAX) . . . . . . . . .+150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature
N-16 and N-20 (Soldering, 10 secs) . . . . . . . . . . . .+300°C
R-16, R-20, RU-16, RU-20 (Vapor Phase, 60 secs) . .+215°C
R-16, R-20, RU-16, RU-20 (Infrared, 15 secs) . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7304/AD7305 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–3–
REV. A
AD7304/AD7305
SDI
CLK
CS
SA
SI
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
tCSS
tCSH
tLD2
LDAC
tLD1
SDI
tDS
tDH
tCH
tCL
CLK
tLDW
LDAC
tCLRW
CLR
tS
FS
ꢀ1 LSB
ERROR BAND
V
OUT
ZS
tS
Figure 2. AD7304 Timing Diagram
tSDN
SDI/SHDN
tSDR
I
DD
Figure 3. AD7304 Timing Diagram
Table I. AD7304 Control Logic Truth Table
Serial Shift Register Function Input REG Function
CS
CLK LDAC CLR
DAC Register Function
H
L
↑+
H
H
H
X
↑+
L
X
X
X
H
H
H
L
H
H
H
H
H
H
↓–
↑+
No Effect
Data Advanced 1 Bit
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
Updated with SR Contents2
Latched with SR Contents2
Loaded with 00H
Latched with 00H
All Input Register Contents Transferred3
Loaded with 00H
Latched with 00H
No Effect
NOTES
1↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.
2One Input Register receives the data bits D7–D0 decoded from the SR address bits (A1, A0); where REG A = (0, 0); B = (0, 1); C = (1, 0); D = (1, 1).
3LDAC is a level-sensitive input.
Table II. AD7304 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
B11
LSB
B0
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
AD7304 SAC
SDC
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
If B11 (SAC), Shutdown All Channels, is set to logic LOW, all DACs are placed in a power shutdown mode, all output voltages become high resistance. If B10 (SDC),
Shutdown Decoded Channel, is set to logic LOW, only the DAC decoded by address bits A1 and A0 is placed in the shutdown mode.
–4–
REV. A
AD7304/AD7305
Table III. AD7305 Control Logic Truth Table
LDAC Input Register Function DAC Register Function
WR A1
A0
L
↑+
L
↑+
L
↑+
L
↑+
H
L
H
H
L
L
L
L
H
H
H
H
X
X
X
X
L
L
H
H
L
H
H
H
H
H
H
H
H
L
REG A Loaded with DB0–DB7
REG A Latched with DB0–DB7
REG B Loaded with DB0–DB7
REG B Latched with DB0–DB7
REG C Loaded with DB0–DB7
REG C Latched with DB0–DB7
REG D Loaded with DB0–DB7
REG D Latched with DB0–DB7
No Effect
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
All Input Register Contents Loaded, Register Transparent
Register Transparent
L
H
H
X
X
X
X
L
↑+
H
Input REG x Transparent to DB0–DB7
No Effect
No Effect, Device Not Selected
All Input Register Contents Latched
No Effect, Device Not Selected
NOTES
1↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.
2LDAC is a level sensitive input.
PIN CONFIGURATIONS
1
2
20
19
18
17
16
15
14
13
12
11
V
C
D
V
V
B
A
OUT
tWR
OUT
V
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
V
V
V
C
D
V
V
B
A
OUT
DD
OUT
V
OUT
OUT
DD
OUT
WR
3
SS
OUT
V
tAS
tAH
4
A0/SHDN
A1
V
REF
SS
A
A0, A1
5
AD7304
TOP VIEW
(Not to Scale)
GND
V
V
C
D
AD7305
TOP VIEW
(Not to Scale)
REF
REF
6
B
WR
LDAC
DB7
DB6
DB5
DB4
tDS
REF
tDH
REF
7
DB0
DB1
DB2
SDI/SHDN
CLK
GND
D0–D7
8
LDAC
CLR
tLS
tLDW
9
tLH
CS
10
DB3
LDAC
tS
ꢀ1 LSB
ERROR BAND
V
OUT
Figure 4. AD7305 Timing Diagram
tSDN
A0/SHDN
tSDR
I
DD
Figure 5. AD7305 Timing Diagram
–5–
REV. A
AD7304/AD7305
AD7304 PIN FUNCTION DESCRIPTIONS
Pin # Name
Function
1
VOUT
VOUT
VSS
B
Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to VREFB pin. Output
is open circuit when SHDN is enabled.
2
A
Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to VREFA pin. Output
is open circuit when SHDN is enabled.
3
4
5
6
7
Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.
VREFA
Channel A Reference Input. Establishes VOUTA full-scale voltage. Specified range of operation VSS < VREFA < VDD
.
VREFB
Channel B Reference Input. Establishes VOUTB full-scale voltage. Specified range of operation VSS < VREFB < VDD
.
GND
Common Analog and Digital Ground.
LDAC
Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous
active low input. DAC Register is transparent when LDAC = 0. See Control Logic Truth Table for operation.
8
9
CLR
CS
Clears all Input and DAC registers to the zero condition. Asynchronous active low input. The serial register is not effected.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers Serial Input Register Data to the
decoded Input Register when CS returns HIGH. Does not effect LDAC operation.
10
11
CLK
Clock input, positive edge clocks data into shift register. Disabled by chip select CS.
SDI/SHDN Serial Data-Input loads directly into the shift register, MSB first. Hardware shutdown (SHDN) control input, active
when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as power is
present on VDD
Channel D Reference Input. Establishes VOUTD full-scale voltage. Specified range of operation VSS < VREFD < VDD
Channel C Reference Input. Establishes VOUTC full-scale voltage. Specified range of operation VSS < VREFC < VDD
.
12
13
14
15
VREF
VREF
VDD
D
.
C
.
Positive power supply input. Specified range of operation +2.7 V to +5.5 V.
VOUT
D
Channel D rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to VREFD pin. Output
is open circuit when SHDN is enabled.
16
V
OUTC
Channel C rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to VREFC pin. Output
is open circuit when SHDN is enabled.
AD7305 PIN FUNCTION DESCRIPTIONS
Function
Pin # Name
1
V
OUTB
Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to VREFB pin. Output
is open circuit when SHDN is enabled.
2
V
OUTA
Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to VREFA pin. Output
is open circuit when SHDN is enabled.
3
4
5
6
VSS
Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.
VREF
GND
LDAC
Channel B Reference Input. Establishes VOUT full-scale voltage. Specified range of operation VSS < VREF < VDD
.
Common Analog and Digital Ground.
Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous
active low input. DAC Register is transparent when LDAC = 0. See Control Logic Truth Table for operation.
7
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
WR
MSB Digital Input Data Bit.
8
Data Bit 6.
9
Data Bit 5.
10
11
12
13
14
15
16
17
Data Bit 4.
Data Bit 3.
Data Bit 2.
Data Bit 1.
LSB Digital Input Data Bit.
Write data into Input Register control line, active low. See Control Logic Truth Table for operation.
Address Bit 1.
A1
A0/SHDN
Address Bit 0/Hardware shutdown (SHDN) control input, active when pin is left floating by a three-state logic driver.
Does not effect DAC register contents as long as power is present on VDD
.
18
19
VDD
Positive Power Supply Input. Specified range of operation +2.7 V to +5.5 V.
VOUT
D
C
Channel D rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to VREFD pin. Output
is open circuit when SHDN is enabled.
20
VOUT
Channel C rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to VREFC pin. Output
is open circuit when SHDN is enabled.
–6–
REV. A
Typical Performance Characteristics–AD7304/AD7305
144
120
96
72
48
24
0
1.0
V
V
V
= +5V
= –5V
DD
SS
= V
REF
DD
0.6
DATA = 00
H
DAC D
0.2
–0.2
DAC C
DAC B
V
V
= +5V
= –5V
DD
SS
DAC A
–0.6
–1.0
DATA = 80
H
T
= +25ꢂC
A
0
3
6
9
12
15
–5.0
–3.0
–1.0
1.0
3.0
5.0
V
– mV
REFERENCE INPUT VOLTAGE – Volts
OUT
Figure 6. IOUTSINK vs. VOUT Rail-to-Rail Performance
Figure 9. INL vs. Reference Input Voltage
0.500
0.375
–35
V
V
V
= +5V
= –5V
DD
V
V
V
= +5V
= –5V
DD
SS
SS
= 2.5V
REF
–28
–21
–14
–7
= V
REF
DD
0.250
DATA = FF
H
0.125
0.000
–0.125
–0.250
–0.375
–0.500
0
0
32
64
96
128
160
192
224
256
4.0
4.2
4.4
4.6
4.8
5.0
CODE – Decimal
V
OUTPUT VOLTAGE – Volts
OUT
Figure 10. DNL vs. Code
Figure 7. IOUTSOURCE vs. VOUT Rail-to-Rail Performance
4.0
3.6
3.2
2.8
2.4
2.0
1
V
V
V
= +5.5V
DD
SS
0
DAC A
= 0V
= +5.45V
–1
REF
1
0
DAC B
–1
1
0
V
V
V
= +5V
= –5V
DD
DAC C
SS
–1
1
= +2.5V
REF
T
= +25ꢂC
A
0
DAC D
64
–1
0
32
96
128
160
192
224
256
–55
–35
–15
5
25
45
65
85
105
125
CODE – Decimal
TEMPERATURE – ꢂC
Figure 8. INL vs. Code, All DAC Channels
Figure 11. Zero Scale Voltage vs. Temperature
–7–
REV. A
AD7304/AD7305
CS
V
V
= +5V
DD
NO LOAD
= 70kꢃ
V
C
= +5V
= 150pF
DD
= +4V
REF
V
OUT
L
R
L
DATA = 00
FF
H
H
R
= 10kꢃ
L
0V
5V
0V
V
OUT
CS
5ꢁs/DIV
2ꢁs/DIV
Figure 15. Time to Shutdown
Figure 12. Large-Signal Settling Time
CS
5V
DATA = FF
V
H
REFIN
I
DD
(ꢀ5V @
50kHz)
0V
–5V
5V
1mA/V
V
= +5V
DD
0V
V
OUT
V
OUTA
–5V
2ꢁs/DIV
Figure 13. Multiplying Mode Step Response and Output
Slew Rate
Figure 16. Shutdown Recovery Time (Wakeup)
6
10
V
V
= +5V
= –5V
DD
A
SS
V
V
= +5V
= –5V
DD
SS
DATA = FF
H
4
0
V
= 100mV rms
REF
1
0.1
f–3dB = 2.6MHz
–4
0.010
0.001
–6
–8
10k
100k
FREQUENCY – Hz
1M
10M
10m
1
2
3
V
4
5
6
7
8
9
10
AMPLITUDE – V p-p
REF
Figure 14. Multiplying Mode Gain vs. Frequency
Figure 17. THD vs. Reference Input Amplitude
–8–
REV. A
AD7304/AD7305
1
A
V
V
= +5V
= –5V
DD
SS
V
V
V
= +5V
= –5V
DD
SS
= 2.5V
REF
0.1
V
OUT
F = 1MHz
DATA = 80
7F
H
H
0.010
0.001
CS
20
100
1k
10k
100k
FREQUENCY – Hz
Figure 18. THD vs. Frequency
Figure 21. Midscale Transition Glitch
3.0
2.4
1.8
40
20
0
V
V
V
= +5V
= –5V
V
V
V
= +5V
= –5V
DD
SS
DD
SS
= 4V
= 50mV rms
REF
REF
DATA = FF
DAC A DATA = FF
DAC B, C, D DATA = 00
H
H
–20
–40
H
–60
–80
1.2
0.6
0
–100
–120
–140
–160
V
OUTB
CT = 20 LOG
V
REF
1
10
100
1k
10k
100k
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 22. Crosstalk vs. Frequency
Figure 19. Output Noise Voltage Density vs. Frequency
60
50
40
–PSRR, V = –5V ꢀ ꢄ10%
SS
+PSRR, V = +5V ꢀ ꢄ10%
DD
V
–PSRR, V = –3V ꢀ ꢄ10%
SS
OUTB
30
20
10
0
+PSRR, V = +3V ꢀ ꢄ10%
DD
V
V
V
= +5V
= –5V
DD
SS
= 2.5V
REF
DAC A = FF
DAC B = OO
F = 2MHz
H
H
CLK
DATA = 80
H
T
= +25ꢂC
A
10
100
1k
10k
100k
50ns/DIV
FREQUENCY – Hz
Figure 23. Power Supply Rejection vs. Frequency
Figure 20. Digital Feedthrough
–9–
REV. A
AD7304/AD7305
80
70
60
50
40
12
V
V
V
= +5V
= –5V
= 2.5V
V
V
V
= +5.5V
= –5.5V
= 2.5V
DD
SS
DD
SS
10
8
REF
REF
A0 = 5V
ALL OTHER DIGITAL
PINS VARYING
PIN A0 FLOATING
6
I
DD
4
I
SS
2
30
20
0
0
1
2
3
4
5
–55
–35
–15
5
25
45
65
85
105
125
DIGITAL INPUT VOLTAGE – Volts
TEMPERATURE – ꢂC
Figure 24. Supply Current vs. Digital Input Voltage
Figure 27. Shutdown Supply Current vs. Temperature
10.0000
1.0000
0.08
READING MADE AT T = +25ꢂC
SAMPLE SIZE = 924 UNITS
A
0.04
0
V
V
V
= +5V
= –5V
DD
0.1000
0.0100
SS
V
= 2.7V
DD
= 2.5V
REF
ALL DIGITAL PINS VARY,
EXCEPT A0 = 5V
I
DD
V
= 5.5V
DD
–0.04
–0.08
I
0.0010
0.0001
SS
0
1
2
3
4
5
0
84
168
252
336
420
504
DIGITAL INPUT VOLTAGE – Volts
DEGREES CELCIUS
Figure 25. Shutdown Supply Current vs. Digital Input
Voltage (A0 Only)
Figure 28. Normalized TUE Drift Accelerated by Burn-In
Hours of Operation @ 150°C
5.0
V
V
V
= +5V
= –5V
DD
SS
= 2.5V
4.4
3.8
3.2
2.6
2.0
REF
I
AND I
SS
DD
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE – ꢂC
Figure 26. Supply Current vs. Temperature
–10–
REV. A
AD7304/AD7305
directly to the same supply as the VDD or VSS pin (Figure 30).
Under these conditions clean power supply voltages (low ripple,
avoid switching supplies) appropriate for the application should
be used.
CIRCUIT OPERATION
The AD7304/AD7305 are a set of four-channel, 8-bit, voltage-
output, digital-to-analog converters differing primarily in digital
logic interface and number of reference inputs. Both parts share
the same internal DAC design and true rail-to-rail output buff-
ers. The AD7304 contains four independent multiplying refer-
ence inputs, while the AD7305 has one common reference input.
The AD7304 uses a 3-wire SPI compatible serial data interface,
while the AD7305 offers a 8-bit parallel data interface.
V
DD
Q1
V
X
OUT
120kꢃ
Q2
D/A Converter Section
Each part contains four voltage-switched R-2R ladder DACs.
Figure A shows a typical equivalent DAC. These DACs are
designed to operate both single-supply or dual supply, depend-
ing on whether the user supplies a negative voltage on the VSS
pin. In a single-supply application the VSS is tied to ground. In
either mode the DAC output voltage is determined by the VREF
input voltage and the digital data (D) loaded into the corre-
sponding DAC register according to Equation 1.
V
SS
Figure 30. Equivalent DAC Amplifier Output Circuit
AD7304 SERIAL DATA INTERFACE
The AD7304 uses a 3-wire (CS, SDI, CLK) SPI compatible
serial data interface. New serial data is clocked into the serial
input register in a 12-bit data-word format. MSB bits are loaded
first. Table II defines the 12 data-word bits. Data is placed on
the SDI/SHDN pin and clocked into the register on the positive
clock edge of CLK subject to the data setup and data hold time
requirements specified in the TIMING SPECIFICATIONS.
Data can only be clocked in while the CS chip select pin is
active low. Only the last 12-bits clocked into the serial register
will be interrogated when the CS pin returns to the logic high
state, extra data bits are ignored. Since most microcontrollers
output serial data in 8-bit bytes, two right justified data bytes
can be written to the AD7304. Keeping the CS line low between
the first and second byte transfer will result in a successful serial
register update.
V
OUT = VREF × D/256
(1)
Note that the output full-scale polarity is the same as the VREF
polarity for dc reference voltages.
V
DD
V
REF
DB7
DB6
V
OUT
2R
2R
R
V
SS
DB0
2R
Once the data is properly aligned in the shift register the positive
edge of the CS initiates either the transfer of new data to the
target DAC register, determined by the decoding of address bits
A1 and A0, or the shutdown features will be activated based on
the SAC or SDC bits. When either SAC or SDC pins are set
(Logic = 0) the loading of new data determined by Bits B9 to
B0 are still loaded, but the results do not appear on the buffer
outputs until the device is brought out of the shutdown state.
The selected DAC output voltages become high impedance with
a nominal resistance of 120 kΩ to ground, Figure 30. If both
SAC and SDC pins are set, all channels are still placed in the
shutdown mode. When the AD7304 has been programmed into
the power shutdown state, the present DAC register data is
maintained as long as VDD remains greater than 2.7 volts. The
remaining characteristics of the software serial interface are
defined by Tables I, II and Figure 3 timing diagram.
2R
Figure 29. Typical Equivalent DAC Channel
These DACs are also designed to accommodate ac reference
input signals. As long as the ac signals are maintained between
VSS < VREF <VDD, the user can expect 50 kHz of full-power
multiplying bandwidth performance. In order to use negative
input reference voltages, the VSS pin must be biased with a nega-
tive voltage of equal or greater magnitude than the reference
voltage.
The reference inputs are code-dependent, exhibiting worst case
minimum resistance values specified in the parametric specifica-
tion table. The DAC outputs VOUTA, B, C, D are each capable
of driving 2 kΩ loads in parallel with up to 500 pF loads. Output
source and sink current is shown in Figures 6 and 7. The output
slew rate is nominally 3.6 V/µs while operating from 5 V sup-
plies. The low output impedance of the buffers minimizes
crosstalk between analog input channels. At 100 kHz, 65 dB of
channel-to-channel isolation exists (Figure 22). Output voltage
noise is plotted in Figure 19. In order to maintain good analog
performance, power supply bypassing of 0.01 µF in parallel with
1 µF is recommended. The true rail-to-rail capability of the
AD7304/AD7305 allows the user to connect the reference inputs
Two additional pins CLR and LDAC on the AD7304 provide
hardware control over the clear function and the DAC Register
loading. If these functions are not needed the CLR pin can be
tied to logic high, and the LDAC pin can be tied to logic low.
The asynchronous input CLR pin forces all input and DAC
registers to the zero-code state. The asynchronous LDAC pin
can be strobed to active low when all DAC Registers need to be
updated simultaneously from their respective Input Registers.
The LDAC pin places the DAC Register in a transparent mode
while in the logic low state.
–11–
REV. A
AD7304/AD7305
VREF
A
VREF
B
VREF
C
VREF
D
VDD
VREF
VDD
EN
CS
CLK
AD7304
8
AD7305
DATA
DB0–DB7
D0
D1
D2
D3
D4
D5
D6
D7
INPUT
REGISTER
DAC A
INPUT
DAC A
DAC A
DAC A
OE
WR
VOUT
A
B
V
OUTA
REGISTER
OE
REGISTER
REGISTER
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
SDI
g
8
D
Q
DACA
DAC A
INPUT
REGISTER
DAC B
REGISTER
INPUT
REGISTER
DAC B
REGISTER
DAC B
OE
A1
DAC B
OE
VOUT
VOUT
B
B
C
B
C
2:4
DECODE
2:4
DECODE
A0
A1
g
A0/SHDN
D
D
D
Q
SDC
SAC
INPUT
REGISTER
DAC C
REGISTER
DAC C
OE
INPUT
REGISTER
DAC C
REGISTER
DAC C
OE
VOUT
C
D
VDD
VOUT
C
D
g
V
DD
640kꢃ 680kꢃ
D
Q
640kꢃ
680kꢃ
DAC D
REGISTER
INPUT
REGISTER
DAC D
OE
DAC D
REGISTER
INPUT
REGISTER
DAC D
OE
VOUT
VOUT
80kꢃ
g
D
80kꢃ
Q
POWER-
ON
RESET
POWER-
ON
RESET
280kꢃ 320kꢃ
280kꢃ
320kꢃ
VSS
GND
LDAC
CLR
VSS
GND
LDAC
Figure 31. AD7304 Equivalent Logic Interface
AD7304 Hardware Shutdown SHDN
Figure 32. AD7305 Equivalent Logic Interface
the same time. This will result in the analog outputs all chang-
ing to their new values at the same time. The LDAC pin is a
level-sensitive input. If the simultaneous update feature is not
required the LDAC pin can be tied to logic low. When the
LDAC is tied to logic low, the DAC Registers become transpar-
ent and the Input Register data determines the DAC output
voltage. See Figure 32 for an equivalent interface logic diagram.
If a three-state driver is used on the SDI/SHDN pin, the AD7304
can be placed into a power shutdown mode when the SDI/
SHDN pin is placed in a high impedance state. For proper
operation no other termination voltages should be present on
this pin. An internal window comparator will detect when the
logic voltage on the SHDN pin is between 28% and 36% of
VDD. A high impedance internal bias generator provides this
voltage on the SHDN pin. The four DAC output voltages be-
come high impedance with a nominal resistance of 120 kΩ to
ground. See Figure 30 for an equivalent circuit.
AD7226 Pin Compatibility
By tying the LDAC pin to ground, the AD7305 has the same
pin out and functionality as the AD7226, with the exception of
a lower power supply operating voltage.
AD7305 Hardware Shutdown SHDN
AD7304/AD7305 POWER ON RESET
If a three state driver is used on the A0/SHDN pin, the AD7305
can be placed into a power shutdown mode when the A0/SHDN
pin is placed in a high impedance state. For proper operation no
other termination voltages should be present on this pin. An
internal window comparator will detect when the logic voltage
on the SHDN pin is between 28% and 36% of VDD. A high
impedance internal bias generator provides this voltage on the
SHDN pin. The four DAC output voltages become high imped-
ance with a nominal resistance of 120 kΩ to ground.
When the VDD power supply is turned on, an internal reset
strobe forces all the Input and DAC registers to the zero-code
state. The VDD power supply should have a monotonically in-
creasing ramp in order to have consistent results, especially in
the region of VDD = 1.5 V to 2.3 V. The VSS supply has no effect
on the power ON reset performance. The DAC register data
will stay at zero until a valid serial register software load takes
place. In the case of the double buffered AD7305 the output
DAC register can only be changed once the LDAC strobe is
initiated.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND). The VREF pins also contain a
back-biased ESD protection Zener connected to VDD (see
Figure 33).
AD7305 PARALLEL DATA INTERFACE
The AD7305 has an 8-bit parallel interface DB7 = MSB,
DB0 = LSB. Two address Bits A1 and A0 are decoded when an
active low write strobe is placed on the WR pin, see Table III.
The WR is a level-sensitive input pin, therefore the data setup
and data hold times defined in the TIMING SPECIFICATIONS
need to be adhered to.
DIGITAL
INPUTS
V
DD
V
X
REF
The LDAC pin provides the capability of simultaneously updat-
ing all DAC registers with new data from the Input Registers at
GND
Figure 33. Equivalent ESD Protection Circuits
–12–
REV. A
AD7304/AD7305
APPLICATIONS
+5V
10kꢃ
10kꢃ
The AD7304/AD7305 is inherently a 2-quadrant multiplying
D/A converter. That is, it can easily be set up for unipolar out-
put operation. The full-scale output polarity is the same as the
reference input voltage polarity.
–5V < V
< +5V
OUT
AD7304
REF
In some applications it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing.
This is easily accomplished using an external true rail-to-rail op
amp, such as the OP295. Connecting the external amplifier with
two equal value resistors as shown in Figure 34 results in a full
4-quadrant multiplying circuit. In this circuit the amplifier pro-
vides a gain of two, which increases the output span magnitude
to 10 volts. The transfer equation of this circuit shows that both
negative and positive output voltages are created as the input
data (D) is incremented from code zero (VOUT = –5 V) to mid-
scale (VOUT = 0 V) to full scale (VOUT = +5 V).
Figure 34. Four-Quadrant Multiplying Application Circuit
V
OUT = (D/128 –1) × VREF
(2)
–13–
REV. A
AD7304/AD7305
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead SOIC
(R-20)
16-Lead Wide SOIC
(R-16)
0.5118 (13.00)
0.4961 (12.60)
0.4133 (10.50)
0.3977 (10.00)
20
11
16
9
1
10
1
8
0.1043 (2.65)
0.0926 (2.35)
PIN 1
0.1043 (2.65)
0.0926 (2.35)
PIN 1
0.0291 (0.74)
0.0098 (0.25)
0.0291 (0.74)
0.0098 (0.25)
x 45ꢂ
x 45ꢂ
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
0.0157 (0.40)
0.0500 (1.27)
0.0157 (0.40)
8ꢂ
0ꢂ
8ꢂ
0ꢂ
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
16-Lead Plastic DIP
(N-16)
20-Lead Plastic DIP
(N-20)
1.060 (26.90)
0.925 (23.50)
0.840 (21.33)
0.745 (18.93)
20
1
11
10
16
1
9
8
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.325 (8.25)
0.300 (7.62)
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.195 (4.95)
0.115 (2.93)
PIN 1
PIN 1
0.060 (1.52)
0.015 (0.38)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
16-Lead TSSOP
(RU-16)
20-Lead Thin Surface Mount (TSSOP)
(RU-20)
0.201 (5.10)
0.193 (4.90)
0.260 (6.60)
0.252 (6.40)
16
20
11
10
9
8
1
1
0.006 (0.15)
0.002 (0.05)
PIN 1
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8ꢂ
0ꢂ
0.028 (0.70)
0.020 (0.50)
8ꢂ
0ꢂ
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
–14–
REV. A
相关型号：
AD7305YRZ
PARALLEL, 8 BITS INPUT LOADING, 1 us SETTLING TIME, 8-BIT DAC, PDSO20, MS-013AC, SOIC-20
ROCHESTER
AD7305YRZ-REEL
PARALLEL, 8 BITS INPUT LOADING, 1 us SETTLING TIME, 8-BIT DAC, PDSO20, MS-013AC, SOIC-20
ROCHESTER
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