AD7305BRUZ_技术文档

3 V/5 V, Rail-to-Rail

Quad, 8-Bit DAC

AD7304/AD7305

FUNCTIONAL BLOCK DIAGRAMS

FEATURES

Four 8-bit DACs in one package

V

B

V

A

V

REF

DD

+3 V, +5 V, and 5 V operation

8

PWR-ON

RESET

INPUT

REG A

DAC A

REG

V

A

B

C

D

DAC A

DAC B

DAC C

DAC D

Rail-to-rail REF input to voltage output swing

2.6 MHz reference multiplying bandwidth

Internal power-on reset

SPI serial interface-compatible—AD7304

Fast parallel interface—AD7305

40 µA power shutdown

OUT

8

INPUT

REG B

DAC B

REG

OUT

CS

INPUT

REG C

DAC C

REG

OUT

SERIAL

REG

SDI/SHDN

CLK

INPUT

REG D

DAC D

REG

APPLICATIONS

Automotive output span voltage

Instrumentation, digitally controlled calibration

Pin-compatible AD7226 replacement when V_DD< 5.5 V

AD7304

V

GND

V

C V

D

REF

SS

REF

CLR LDAC

Figure 1.

V

8

V

REF

DD

GENERAL DESCRIPTION

8

PWR-ON

RESET

INPUT

REG A

DAC A

The AD7304/AD7305¹are quad, 8-bit DACs that operate from

a single +3 V to +5 V supply, or 5 V supplies. The AD7304 has

a serial interface, while the AD7305 has a parallel interface.

Internal precision buffers swing rail-to-rail. The reference input

range includes both supply rails, allowing for positive or negative

full-scale output voltages. Operation is guaranteed over the

supply voltage range of 2.7 V to 5.5 V, consuming less than

9 mW from a 3 V supply.

V

A

DAC A

DAC B

DAC C

DAC D

OUT

REG

DB0

DB1

DB2

DB3

DB4

DB5

DB6

8

INPUT

REG B

DAC B

B

OUT

REG

8

INPUT

REG C

DAC C

V

C

D

OUT

REG

8

INPUT

REG D

DAC D

REG

WR

A0/SHDN

A1

DECODE

AD7305

V

SS

GND

LDAC

The full-scale voltage output is determined by the external

reference input voltage applied. The rail-to-rail V_REFinput to

DAC V_OUTallows for a full-scale voltage set equal to the positive

supply, V_DD, the negative supply, V_SS, or any value in between.

Figure 2.

When operating from less than 5.5 V, the AD7305 is

pin-compatible with the popular industry-standard AD7226.

The AD7304’s doubled-buffered serial data interface offers high

speed, 3-wire, SPI®-, and microcontroller-compatible inputs

An internal power-on reset places both parts in the zero-scale

state at turn-on. A 40 µA power shutdown (SHDN) feature is

activated on both parts by three-stating the SDI/SHDN pin on

the AD7304 and three-stating the A0/SHDN address pin on the

AD7305.

CS

using data in (SDI), clock (CLK), and chip select ( ) pins.

Additionally, an internal power-on reset sets the output to zero

scale.

The parallel input AD7305 uses a standard address decode

The AD7304/AD7305 are specified over the extended industrial

−40°C to +85°C and the automotive −40°C to +125°C

temperature ranges. AD7304s are available in a wide-body

16-lead SOIC (R-16) package. The parallel input AD7305 is

available in the wide-body 20-lead SOIC (R-20) surface-mount

package. For ultracompact applications, the thin 1.1 mm,

16-lead TSSOP (RU-16) package is available for the AD7304,

while the 20-lead TSSOP (RU-20) houses the AD7305.

WR

along with the

registers.

control line to load data into the input

The double-buffered architecture allows all four input registers

LDAC

to be preloaded with new values, followed by an

control

strobe that copies all the new data into the DAC registers,

thereby updating the analog output values.

_____________________________________________________

¹Protected under Patent No. 5684481.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

AD7304/AD7305

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ........................................... 10

Circuit Operation ........................................................................... 14

DAC Section................................................................................ 14

AD7304 Serial Data Interface ....................................................... 15

AD7304 Hardware Shutdown SHDN...................................... 15

AD7304/AD7305 Power-On Reset.......................................... 15

Power up sequence..................................................................... 15

AD7305 Parallel Data Interface.................................................... 16

AD7226 Pin Compatibility ....................................................... 16

AD7305 Hardware Shutdown SHDN...................................... 16

ESD Protection Circuits ............................................................ 16

Applications..................................................................................... 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 19

Revision History

11/04—Data Sheet Changed from Rev. B to Rev. C

Update Format ....................................................................Universal

Update Features ................................................................................ 1

Changes to Figure 35...................................................................... 15

Add Power-Up Sequence............................................................... 15

Changes to Figure 36...................................................................... 16

Change to Figure 37 ....................................................................... 16

Updated Outline Dimensions....................................................... 18

2/04—Data Sheet Changed from Rev. A to Rev. B

Renumber TPCs and Figures............................................Universal

Deleted N-16 and N-20 packages.....................................Universal

Changes to Absolute Maximum Ratings....................................... 3

Changes to Ordering Guide ............................................................ 4

Updated Outline Dimensions....................................................... 14

3/98—Changed from Rev. 0 to Rev. A

2/98—Revision 0: Initial Version

Rev. C | Page 2 of 20

AD7304/AD7305

SPECIFICATIONS

@ V_DD= 3 V or 5 V, V_SS= 0 V; or V_DD= +5 V and V_SS= –5 V, V_SS≤ V_REF≤ V_DD, −40°C < T_A< +85°C/+125°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Condition

3 V 10%

5 V 10%

5 V 10% Unit

STATIC PERFORMANCE

Resolution¹

Integral Nonlinearity²

Differential Nonlinearity

Zero-Scale Error

Full-Scale Voltage Error

Full-Scale Temperature

Coefficient³

N

8

5

Bits

LSB max

INL

DNL

V_ZSE

V_FSE

TCV_FS

1

Monotonic, all codes 0 to 0xFF

Data = 0x00

Data = 0xFF

1

15

4

LSB max

mV max

LSB max

ppm/°C typ⁴

15

4

5

15

4

5

REFERENCE INPUT

V_REFINRange

Input Resistance (AD7304) R_REFIN

Input Resistance (AD7305) R_REFIN

Input Capacitance³

V_REFIN

V_SS/V_DD

28

7.5

V_SS/V_DD

28

7.5

V_SS/V_DD

28

7.5

V min/max

kΩ typ

Code = 0x55

All DACs at code = 0x55

C_REFIN

5

pF typ

ANALOG OUTPUTS

Output Voltage Range

Output Current Drive

Shutdown Resistance

V_OUT

I_OUT

R_OUT

V_SS/V_DD

3

120

V_SS/V_DD

3

120

V_SS/V_DD

3

120

V min/max

mA typ

kΩ typ

Code = 0x80, ∆V_OUT< 1 LSB

DAC outputs placed in shutdown

state

Capacitive Load³

LOGIC INPUTS

C_L

No oscillation

200

pF typ

Logic Input Low Voltage

Logic Input High Voltage

Input Leakage Current⁵

Input Capacitance³

AC CHARACTERISTICS³

Output Slew Rate

Reference Multiplying

Total Harmonic Distortion

Settling Time⁶

Shutdown Recovery Time

Time to Shutdown

DAC Glitch

Digital Feedthrough

Feedthrough

V_IL

V_IH

I_IL

0.6

2.1

10

8

0.8

2.4

10

8

0.8

2.4

10

8

V min

V max

µA max

pF max

C_IL

SR

Code = 0x00 to 0xFFto 0x00

Small signal, V_SS= –5 V

1/2.7

1/3.6

1.0/3.6

2.6

V/µs min/typ

MHz typ

%

µs typ/max

µs max

µs typ

nVs typ

dB

BW

THD

t_S

t_SDR

t_SDN

Q

V_REF= 4 V p-p, V_SS= –5 V, f = 1 kHz

To 0.1% of full scale

0.025

1.0/2

2

15

1.1/2

2

15

2

1.0/2

2

15

2

Q

2

V_OUT/V_REF

Code = 0x00, V_REF= 1 V p-p, f = 100 kHz

−65

SUPPLY CHARACTERISTICS

Positive Supply Current

Negative Supply Current

Power Dissipation

Power Down

Power Supply Sensitivity

I_DD

I_SS

P_DISS

I_{DD_SD}

PSS

V_LOGIC= 0 V or V_DD, no load

V_SS= –5 V

V_LOGIC= 0 V or V_DD, no load

SDI/SHDN = floating

6

mA max

mW max

µA typ

15

40

0.004

30

40

0.004

60

40

0.004

∆V_DD

=

10%

%/%

¹One LSB = V_REF/256.

²The first three codes (0x00, 0x01, 0x10) are excluded from the integral nonlinearity error measurement in single-supply operation 3 V or 5 V.

³These parameters are guaranteed by design and not subject to production testing.

⁴Typical specifications represent average readings measured at 25°C.

⁵The SDI/SHDN and A0/SHDN pins have a 30 µA maximum I_ILinput leakage current.

⁶The settling time specification does not apply for negative going transitions within the last three LSBs of ground in single-supply operation.

Rev. C | Page 3 of 20

AD7304/AD7305

+5V

V

= 10V p-p

REF

f = 20kHz

+5V

0V

–5V

V

= 10V p-p

OUT

–5V

(OUT)

(IN)

Figure 3. Rail-to-Rail Reference Input to Output at 20 kHz

TIMING SPECIFICATIONS

@ V_DD= 3 V or 5 V, V_SS= 0 V; or V_DD= +5 V and V_SS= –5 V, V_SS≤ V_REF≤ V_DD, –40°C < T_A< +85°C/+125°C, unless otherwise noted.

Table 2.

Parameter

Symbol

3 V 10%

5 V 10%

Unit

INTERFACE TIMING SPECIFICATIONS^{1, 2}

AD7304 Only

Clock Width High

Clock Width Low

Data Setup

t_CH

t_CL

t_DS

t_DH

t_LDW

t_LD1

t_LD2

t_CLWR

t_CSS

t_CSH

70

50

30

70

40

60

30

60

55

40

20

60

30

60

20

40

55

ns min

55

40

20

60

30

60

20

40

Data Hold

Load Pulse Width

Load Setup

Load Hold

Clear Pulse Width

Select

Deselect

AD7305 Only

Data Setup

t_DS

t_DH

t_AS

t_AH

t_WR

t_LDW

t_LS

60

30

60

30

60

30

40

20

40

20

50

40

20

40

20

40

20

50

40

20

ns min

Data Hold

Address Setup

Address Hold

Write Width

Load Pulse Width

Load Setup

Load Hold

t_LH

¹These parameters are guaranteed by design and not subject to production testing.

²All input control signals are specified with t_R= t_F= 2 ns (10% to 90% of V_DD) and timed from a voltage level of 1.6 V.

Rev. C | Page 4 of 20

AD7304/AD7305

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may

affect device reliability.

Rating

V_DDto GND

−0.3 V, +8 V

+0.3 V, −8 V

V_SS, V_DD

V_SSto GND

V_REFXto GND

Logic Inputs to GND

V_OUTXto GND

−0.3 V, V_DD+ 0.3 V

50 mA

I_OUTShort-Circuit to GND

Package Power Dissipation

(T_{J MAX}– T_A)/θ_JA

Thermal Resistance θ_JA

16-Lead SOIC Package (R-16)

16-Lead TSSOP Package (RU-16)

20-Lead SOIC Package (R-20)

20-Lead TSSOP Package (RU-20)

73°C/W

180°C/W

74°C/W

155°C/W

Maximum Junction Temperature (T_{J MAX}

Operating Temperature Range

Storage Temperature Range

Lead Temperature

)

150°C

−40°C to +85°C

−65°C to +150°C

R-16, R-20, RU-16, RU-20 (Vapor Phase, 60 sec) 235°C

R-16, R-20, RU-16, RU-20 (Infrared, 15 sec)

220°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. C | Page 5 of 20

AD7304/AD7305

SA

SI

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SDI

CLK

t_CSS

t_CSH

CS

t_LD2

LDAC

t_LD1

SDI

t_DS

t_DH

t_CH

t_CL

CLK

t_LDW

LDAC

t_CLRW

CLR

FS

t_S

±1 LSB

ERROR BAND

V

OUT

ZS

t_S

Figure 4. AD7304 General Timing Diagram

t_SDN

t_SDR

SDI/SHDN

I

DD

Figure 5. AD7304 Timing Diagram Zoom In

Table 4. AD7304 Control Logic Truth Table

CLK¹LDAC CLR¹Serial Shift Register Function Input REG Function

1

CS

DAC Register Function

H

L

X

H

L

H

No effect

Data advanced 1 bit

No effect

↑+

L

H

Updated with SR contents²No effect

Latched with SR contents²

↑+

H

X

H

No effect

All input register contents transferred³

X

H

No effect

Loaded with 0x00

Latched with 0x00

↓–

↑+

X

No effect

Latched with 0x00

¹↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.

²One input register receives the data bits D7–D0 decoded from the SR address bits (A1, A0), where REG A = (0, 0), B = (0, 1), C = (1, 0), and D = (1, 1).

³LDAC

is a level-sensitive input.

Table 5. AD7304 Serial Input Register Data Format, Data is Loaded in MSB-First Format

MSB

B11

LSB

B0

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

AD7304 SAC

SDC

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

If B11 (SAC), Shutdown All Channels, is set to logic low, all DACs are placed in a power shutdown mode, and all output voltages become

high resistance. If B10 (SDC), Shutdown Decoded Channel, is set to logic low, only the DAC decoded by Address Bits A1 and A0 is placed

in shutdown mode.

Rev. C | Page 6 of 20

AD7304/AD7305

Table 6. AD7305 Control Logic Truth Table

WR ¹

A1

A0

LDAC²Input Register Function

DAC Register Function

L

H

L

Register A loaded with DB0 to DB7

Latched with previous contents, no change

All input register contents loaded, register transparent

Register transparent

Register A latched with DB0 to DB7

Register B loaded with DB0 to DB7

Register B latched with DB0 to DB7

Register C loaded with DB0 to DB7

Register C latched with DB0 to DB7

Register D loaded with DB0 to DB7

Register D latched with DB0 to DB7

No effect

↑+

L

H

L

↑+

L

H

X

L

↑+

L

H

X

↑+

H

L

Input register x transparent to DB0 to DB7

No effect

H

All input register contents latched

↑+

H

No effect, device not selected

¹↑+ positive logic transition; ↓– negative logic transition; X don’t care.

²LDAC

is a level-sensitive input.

t_WR

WR

t_AS

t_AH

A0, A1

t_DS

t_DH

D0–D7

LDAC

t_LS

t_LDW

t_LH

t_S

±1 LSB

ERROR BAND

V

OUT

Figure 6. AD7305 General Timing Diagram

t_SDN

t_SDR

A0/SHDN

I

DD

Figure 7. AD7305 Timing Diagram Zoom In

Rev. C | Page 7 of 20

AD7304/AD7305

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

B

A

1

2

3

4

5

6

7

8

16

15

14

13

12

V

C

D

OUT

DD

OUT

V

SS

AD7304

V

A

B

C

REF

TOP VIEW

(Not to Scale)

D

GND

11 SDI/SHDN

10 CLK

LDAC

CLR

9

CS

Figure 8. AD7304 Pin Configuration

Table 7. AD7304 Pin Function Descriptions

Pin No. Mnemonic Description

1

2

3

V_OUT

V_SS

B

Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V_REFB pin.

Output is open circuit when SHDN is enabled.

Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V_REFA pin.

Output is open circuit when SHDN is enabled.

A

Negative Power Supply Input. Specified range of operation is 0 V to −5.5 V.

4

5

6

7

V_REF

GND

A

B

Channel A Reference Input. Establishes V_OUTA full-scale voltage. Specified range of operation is V_SS< V_REFA < V_DD.

Channel B Reference Input. Establishes V_OUTB full-scale voltage. Specified range of operation is V_SS< V_REFB < V_DD.

Common Analog and Digital Ground.

Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the

corresponding DAC registers. Asynchronous active low input. DAC register is transparent when LDAC = 0. See

Table 4 for operation.

LDAC

8

9

CLR

CS

Clears All Input and DAC Registers to the Zero Condition. Asynchronous active low input. The serial register is

not effected.

Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial input register data to

the decoded input register when CS returns high. Does not effect LDAC operation.

10

11

CLK

Clock Input, Positive Edge Clocks Data into Shift Register. Disabled by chip select CS.

SDI/SHDN

Serial Data Input Loads Directly into the Shift Register, MSB First. Hardware shutdown (SHDN) control input,

active when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as

power is present on V_DD.

12

13

14

15

V_REF

V_DD

D

C

Channel D Reference Input. Establishes V_OUTD full-scale voltage. Specified range of operation is V_SS< V_REFD < V_DD.

Channel C Reference Input. Establishes V_OUTC full-scale voltage. Specified range of operation is V_SSV_REFC < V_DD.

Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V.

Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V_REFD pin.

Output is open circuit when SHDN is enabled.

V_OUT

D

C

16

V_OUT

Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V_REFC pin.

Output is open circuit when SHDN is enabled.

Rev. C | Page 8 of 20

AD7304/AD7305

1

2

20

19

18

17

16

15

14

13

12

11

V

B

A

V

C

OUT

V

D

OUT

DD

3

V

SS

AD7305

TOP VIEW

(Not to Scale)

4

V

A0/SHDN

A1

REF

5

GND

6

LDAC

DB7

DB6

DB5

DB4

WR

7

DB0

DB1

DB2

DB3

8

9

10

Figure 9. AD7305 Pin Configuration

Table 8. AD7305 Pin Function Description

Pin No. Mnemonic Description

1

V_OUTB

Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V_REFB pin. Output is

open circuit when SHDN is enabled.

2

V_OUTA

Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V_REFA pin. Output is

open circuit when SHDN is enabled.

3

4

5

6

V_SS

V_REF

GND

Negative Power Supply Input. Specified range of operation is 0 V to –5.5 V.

Channel B Reference Input. Establishes V_OUTfull-scale voltage. Specified range of operation is V_SS< V_REF< V_DD.

Common Analog and Digital Ground.

Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the

corresponding DAC registers. Asynchronous active low input. DAC register is transparent when LDAC = 0. See Table 6

for operation.

LDAC

7

8

9

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

WR

MSB Digital Input Data Bit.

Data Bit 6.

Data Bit 5.

Data Bit 4.

Data Bit 3.

Data Bit 2.

Data Bit 1.

LSB Digital Input Data Bit.

10

11

12

13

14

15

16

17

Write Data into Input Register Control Line, Active Low. See Table 6 for operation.

Address Bit 1.

Address Bit 0/Hardware Shutdown (SHDN) Control Input, Active When Pin Is Left Floating by a Three-State Logic

Driver. Does not effect DAC register contents as long as power is present on V_DD.

A1

A0/SHDN

18

19

V_DD

V_OUT

Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V.

Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V_REFD pin. Output is

open circuit when SHDN is enabled.

Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V_REFC pin. Output is

open circuit when SHDN is enabled.

D

C

20

V_OUT

Rev. C | Page 9 of 20

AD7304/AD7305

TYPICAL PERFORMANCE CHARACTERISTICS

144

1.0

0.6

V

= +5V

= –5V

DD

SS

120

96

72

48

24

0

= V

REF

DD

DATA = 0x00

DAC D

0.2

–0.2

DAC C

DAC B

V

= +5V

= –5V

DD

DAC A

SS

DATA = 0x80

–0.6

–1.0

T

= +25°C

A

0

3

6

9

12

15

–5.0

–3.0

–1.0

1.0

3.0

5.0

V

(mV)

OUT

REFERENCE INPUT VOLTAGE (V)

Figure 10. I_OUTSink vs. V_OUTRail-to-Rail Performance

Figure 13. INL vs. Reference Input Voltage

–35

–28

–21

–14

–7

0.500

0.375

0.250

0.125

0

V

= +5V

= –5V

DD

V

= +5V

= –5V

DD

SS

= +2.5V

REF

= V

REF

DD

DATA = 0xFF

–0.125

–0.250

–0.375

–0.500

0

4.0

4.2

4.4

4.6

4.8

5.0

0

32

64

96

128

160

192

224

256

V

OUTPUT VOLTAGE (V)

OUT

CODE (Decimal)

Figure 11. I_OUTSOURCE vs. V_OUTRail-to-Rail Performance

Figure 14. DNL vs. Code

+1

0

4.0

3.6

3.2

2.8

2.4

2.0

V

= 5.5V

= 0V

DD

DAC A

DAC B

SS

= 5.45V

–1

+1

0

REF

–1

+1

0

–1

+1

0

V

= +5V

= –5V

DD

DAC C

SS

= +2.5V

REF

T

= +25°C

A

DAC D

64

–1

0

32

96

128

160

192

224

256

–55

–35

–15

5

25

45

65

85

105

125

CODE (Decimal)

TEMPERATURE (°C)

Figure 12. INL vs. Code, All DAC Channels

Figure 15. Zero-Scale Voltage vs. Temperature

Rev. C | Page 10 of 20

AD7304/AD7305

CS

V

= 5V

= 4V

DD

NO LOAD

= 70kΩ

V

C

= 5V

= 150pF

REF

DD

V

OUT

DATA = 0x00

0xFF

L

R

L

R

= 10kΩ

L

0V

5V

0V

V

OUT

CS

2µs/DIV

5µs/DIV

Figure 19. Time to Shutdown

Figure 16. Large-Signal Settling Time

CS

+5V

0V

DATA = 0xFF

V

REFIN

I

DD

1mA/V

(±5V @

50kHz)

–5V

+5V

0V

V

= 5V

DD

V

OUT

V

A

OUT

–5V

2µs/DIV

Figure 20. Shutdown Recovery Time (Wakeup)

Figure 17. Multiplying Mode Step Response and Output Slew Rate

6

10

1

V

= +5V

= –5V

DD

SS

V

= +5V

= –5V

DD

SS

DATA = 0xFF

= 100mV rms

V

4

0

REF

0.1

f

= 2.6MHz

–3dB

–4

0.01

–6

–8

0.001

10k

100k

1M

10M

10m

1

2

3

4

5

6

7

8

9

10

V

AMPLITUDE (V p-p)

FREQUENCY (Hz)

REF

Figure 21. THD vs. Reference Input Amplitude

Figure 18. Multiplying Mode Gain vs. Frequency

Rev. C | Page 11 of 20

AD7304/AD7305

1

V

= +5V

= –5V

DD

SS

V

= +5V

= –5V

DD

SS

= +2.5V

REF

0.1

F = 1MHz

V

OUT

DATA = 0x80 0x7F

0.01

CS

0.001

20

100

1k

10k

100k

FREQUENCY (Hz)

Figure 25. Midscale Transition Glitch

Figure 22. THD vs. Frequency

3.0

2.4

1.8

1.2

0.6

0

40

20

V

= +5V

= –5V

V

= +5V

= –5V

= +4V

DD

SS

DD

SS

= 50mV rms

REF

0

–20

–40

DAC A DATA = 0xFF

DAC B, DAC C, DAC D DATA = 0x00

DATA = 0xFF

–60

–80

–100

–120

–140

–160

V

B

OUT

CT = 20 LOG

V

REF

1

10

100

1k

10k

100k

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 26. Crosstalk vs. Frequency

Figure 23. Output Noise Voltage Density vs. Frequency

60

50

40

–PSRR, V = –5V ± ∆10%

SS

+PSRR, V = +5V ± ∆10%

DD

V

B

OUT

–PSRR, V = –3V ± ∆10%

SS

V

= +5V

= –5V

DD

30

20

10

0

+PSRR, V = +3V ± ∆10%

DD

SS

= +2.5V

REF

DAC A = 0xFF

DAC B = 0x00

F = 2MHz

CLK

DATA = 0x80

= +25°C

T

A

10

100

1k

FREQUENCY (Hz)

10k

100k

50ns/DIV

Figure 27. Power-Supply Rejection vs. Frequency

Figure 24. Digital Feedthrough

Rev. C | Page 12 of 20

AD7304/AD7305

80

70

60

50

40

12

10

8

V

= +5V

= –5V

V

= +5.5V

= –5.5V

= +2.5V

DD

SS

DD

SS

= +2.5V

REF

A0 = +5V

ALL OTHER DIGITAL

PINS VARYING

PIN A0 FLOATING

6

I

DD

4

I

SS

2

30

20

0

1

2

3

4

5

–55

–35

–15

5

25

45

65

C)

85

105

125

TEMPERATURE (

°

DIGITAL INPUT VOLTAGE (V)

Figure 28. Supply Current vs. Digital Input Voltage

Figure 31. Shutdown Supply Current vs. Temperature

0.08

0.04

0

10

1

READING MADE AT T = +25°C

A

SAMPLE SIZE = 924 UNITS

V

= +5V

= –5V

DD

0.1

0.01

SS

V

= +2.7V

DD

= +2.5V

REF

ALL DIGITAL PINS VARY,

EXCEPT A0 = +5V

I

DD

I

V

= +5.5V

DD

–0.04

–0.08

0.001

SS

0.0001

0

84

168

252

336

C)

420

504

0

1

2

3

4

5

TEMPERATURE (

°

DIGITAL INPUT VOLTAGE (V)

Figure 32. Normalized TUE Drift Accelerated by Burn-In Hours

of Operation @ 150°C

Figure 29. Shutdown Supply Current vs. Digital Input Voltage (A0 Only)

5.0

V

= +5V

= –5V

DD

SS

= +2.5V

REF

4.4

3.8

3.2

2.6

2.0

I

AND I

SS

DD

–55 –35

–15

5

25

45

65

C)

85

105

125

TEMPERATURE (

°

Figure 30. Supply Current vs. Temperature

Rev. C | Page 13 of 20

AD7304/AD7305

CIRCUIT OPERATION

The AD7304/AD7305 are 4-channel, 8-bit, voltage output

DACs, differing primarily in digital logic interface and number

of reference inputs. Both parts share the same internal DAC

design and true rail-to-rail output buffers. The AD7304 contains

four independent multiplying reference inputs, while the

AD7305 has one common reference input. The AD7304 uses a

3-wire SPI-compatible serial data interface, while the AD7305

offers an 8-bit parallel data interface.

These DACs are also designed to accommodate ac reference

input signals. As long as the ac signals are maintained between

V_SS< V_REF< V_DD, the user can expect 50 kHz of full power,

multiplying bandwidth performance. In order to use negative

input reference voltages, the V_SSpin must be biased with a

negative voltage of equal or greater magnitude than the

reference voltage.

The reference inputs are code dependent, exhibiting worst-case

minimum resistance values specified in the parametric specifi-

DAC SECTION

cation table. The DAC outputs V_OUTA, V_OUTB, V_OUTC, and V_OUT

D

Each part contains four voltage-switched R-2R ladder DACs.

Figure 33 shows a typical equivalent DAC. These DACs are

designed to operate both single-supply or dual-supply,

depending on whether the user supplies a negative voltage on

the V_SSpin. In a single-supply application, the V_SSis tied to

ground. In either mode, the DAC output voltage is determined

by the V_REFinput voltage and the digital data (D) loaded into

the corresponding DAC register according to Equation 1.

are each capable of driving 2 kΩ loads in parallel with up to 500 pF

loads. Output sink current and source current are shown in

Figure 10 and Figure 11, respectively. The output slew rate is

nominally 3.6 V/µs while operating from 5 V supplies. The

low output impedance of the buffers minimizes crosstalk

between analog input channels. At 100 kHz, 65 dB of channel-

to-channel isolation exists (Figure 26). Output voltage noise is

plotted in Figure 23. In order to maintain good analog perform-

ance, power supply bypassing of 0.01 µF in parallel with 1 µF is

recommended. The true rail-to-rail capability of the AD7304/AD7305

allows the user to connect the reference inputs directly to the

same supply as the V_DDor V_SSpin (Figure 34). Under these

conditions, clean power supply voltages (low ripple, avoid

switching supplies) appropriate for the application should be

used.

V

_OUT= V_REFD/256

(1)

Note that the output full-scale polarity is the same as the V_REF

polarity for dc reference voltages.

V

DD

V

REF

DB7

DB6

V

2R

OUT

V

R

DD

V

SS

Q1

V

X

OUT

DB0

2R

120kΩ

Q2

2R

V

SS

Figure 33. Typical Equivalent DAC Channel

Figure 34. Equivalent DAC Amplifier Output Circuit

Rev. C | Page 14 of 20

AD7304/AD7305

AD7304 SERIAL DATA INTERFACE

V

A

V

B

V

D

V

DD

V

C

REF

CS

The AD7304 uses a 3-wire ( , SDI, CLK) SPI-compatible

serial data interface. New serial data is clocked into the serial

input register in a 12-bit data-word format. MSB bits are loaded

first.

CS

CLK

AD7304

EN

D0

D1

D2

D3

D4

D5

D6

D7

INPUT

REGISTER

DAC A

OE

DAC A

V

A

B

C

D

REGISTER

OUT

R

SDI

8

Table 5 defines the 12 data-word bits. Data is placed on the

SDI/SHDN pin and clocked into the register on the positive

clock edge of CLK subject to the data setup and data hold time

requirements specified in the Timing Specifications section.

D

Q

DAC A

INPUT

REGISTER

DAC B

OE

DAC B

REGISTER

B

C

OUT

2:4

DECODE

A0

A1

SDC

SAC

D

Q

CS

Data can only be clocked in while the

active low. Only the last 12-bits clocked into the serial register

CS

chip select pin is

INPUT

REGISTER

DAC C

OE

DAC C

REGISTER

V

OUT

DD

R

are interrogated when the

pin returns to the logic high state,

640kΩ 680kΩ

D

Q

extra data bits are ignored. Since most microcontrollers output

serial data in 8-bit bytes, two right-justified data bytes can be

DAC D

OE

INPUT

REGISTER

DAC D

REGISTER

OUT

80kΩ

CS

written to the AD7304. Keeping the

line low between the

D

Q

first and second byte transfer results in a successful serial

register update.

POWER-

ON

RESET

280kΩ 320kΩ

Once the data is properly aligned in the shift register, the

GND

V

SS

LDAC

CLR

CS

positive edge of the

initiates either the transfer of new data

Figure 35. AD7304 Equivalent Logic Interface

to the target DAC register, determined by the decoding of

Address Bits A1 and A0, or the shutdown features is activated

based on the SAC or SDC bits. When either SAC or SDC pins

are set (Logic 0), the loading of new data determined by Bits B9

to B0 are still loaded, but the results do not appear on the buffer

outputs until the device is brought out of the shutdown state.

The selected DAC output voltages become high impedance with

a nominal resistance of 120 kΩ to ground, see Figure 34. If

both the SAC and SDC pins are set, all channels are still placed

in shutdown mode. When the AD7304 has been programmed

into the power shutdown state, the present DAC register data is

maintained as long as V_DDremains greater than 2.7 V. The

remaining characteristics of the software serial interface are

defined by Table 4, Table 5, and Figure 5.

AD7304 HARDWARE SHUTDOWN SHDN

If a three-state driver is used on the SDI/SHDN pin, the

AD7304 can be placed into a power shutdown mode when the

SDI/ SHDN pin is placed in a high impedance state. For proper

operation, no other termination voltages should be present on

this pin. An internal window comparator detects when the logic

voltage on the SHDN pin is between 28% and 36% of V_DD. A

high impedance internal bias generator provides this voltage on

the SHDN pin. The four DAC output voltages become high

impedance with a nominal resistance of 120 kΩ to ground (see

Figure 34 for an equivalent circuit).

AD7304/AD7305 POWER-ON RESET

When the V_DDpower supply is turned on, an internal reset

strobe forces all the input and DAC registers to the zero-code

state. The V_DDpower supply should have a monotonically

increasing ramp in order to have consistent results, especially in

the region of V_DD= 1.5 V to 2.3 V. The V_SSsupply has no effect

on the power-on reset performance. The DAC register data

stays at zero until a valid serial register software load takes

place. In the case of the double-buffered AD7305, the output

CLR

LDAC

, on the AD7304 provide

Two additional pins,

hardware control over the clear function and the DAC register

CLR

and

loading. If these functions are not needed, the

tied to logic high, and the

pin can be

pin can be tied to logic low.

pin forces all input and DAC

LDAC

CLR

The asynchronous input

LDAC

registers to the zero-code state. The asynchronous

can be strobed to active low when all DAC registers need to be

updated simultaneously from their respective input registers.

LDAC

DAC register can only be changed once the

initiated.

strobe is

LDAC

The

pin places the DAC register in a transparent mode

POWER-UP SEQUENCE

while in the logic low state.

It is recommended to power V_DD/V_SSfirst before applying any

voltage to the reference terminals to avoid potential latch up.

The ideal power-up sequence is in the following order: GND,

V_DD, V_SS, Digital Inputs, and V_REFx. The order of powering

digital inputs and reference inputs is not important as long as

they are powered after V_DD/V_SS.

Rev. C | Page 15 of 20

AD7304/AD7305

AD7305 PARALLEL DATA INTERFACE

LDAC

is tied to Logic Low, the DAC registers become

The AD7305 has an 8-bit parallel interface DB7 = MSB, DB0 =

LSB. Two address bits, A1 and A0, are decoded when an active

transparent and the input register data determines the DAC

output voltage (see Figure 36 for an equivalent interface logic

diagram).

WR

low write strobe is placed on the

pin, see Table 6. The

is a level-sensitive input pin, therefore, the data setup and data

hold times defined in the Timing Specifications section need to

be adhered to.

AD7226 PIN COMPATIBILITY

LDAC

By tying the

pin to ground, the AD7305 has the same pin

V

DD

REF

configuration and functionality as the AD7226, with the

exception of a lower power supply operating voltage.

8

AD7305

DATA

DB0–DB7

AD7305 HARDWARE SHUTDOWN SHDN

INPUT

DAC A

WR

V

A

B

C

D

REGISTER

OUT

If a three-state driver is used on the A0/SHDN pin, the AD7305

can be placed into a power shutdown mode when the A0/SHDN

pin is placed in a high impedance state. For proper operation,

no other termination voltages should be present on this pin. An

internal window comparator detects when the logic voltage on

the SHDN pin is between 28% and 36% of V_DD. A high imped-

ance, internal-bias generator provides this voltage on the SHDN

pin. The four DAC output voltages become high impedance

with a nominal resistance of 120 kΩ to ground.

REGISTER

OE

R

DAC A

INPUT

REGISTER

DAC B

REGISTER

DAC B

OE

A1

B

C

R

2:4

A0/SHDN

DECODE

D

INPUT

REGISTER

DAC C

REGISTER

DAC C

OE

V

DD

680k

Ω

640k

Ω

INPUT

REGISTER

DAC D

REGISTER

DAC D

OE

ESD PROTECTION CIRCUITS

80kΩ

All logic input pins contain back-biased ESD protection Zeners

connected to ground (GND). The V_REFpins also contain a back-

biased ESD protection Zener connected to V_DD(see Figure 37).

POWER-

ON

RESET

280k

Ω

320kΩ

V

GND

LDAC

SS

DIGITAL

INPUTS

V

DD

Figure 36. AD7305 Equivalent Logic Interface

LDAC

V

X

The

updating all DAC registers with new data from the input

registers at the same time. This results in the analog outputs all

LDAC

pin provides the capability of simultaneously

REF

GND

Figure 37. Equivalent ESD Protection Circuits

changing to their new values at the same time. The

a level-sensitive input. If the simultaneous update feature is not

LDAC

pin is

required, the

pin can be tied to logic low. When the

Rev. C | Page 16 of 20

AD7304/AD7305

APPLICATIONS

The AD7304/AD7305 are inherently 2-quadrant multiplying

DACs. That is, they can easily be set up for unipolar output

operation. The full-scale output polarity is the same as the

reference input voltage polarity.

the input data (D) is incremented from code zero (V_OUT= –5 V)

to midscale (V_OUT= 0 V) to full scale (V_OUT= +5 V).

D

(2)

V_OUT

=

×V_REF

128 −1

In some applications, it may be necessary to generate the full

4-quadrant multiplying capability or a bipolar output swing.

This is easily accomplished using an external true rail-to-rail op

amp, such as the OP295. Connecting the external amplifier with

two equal value resistors, as shown in Figure 38, results in a full

4-quadrant multiplying circuit. In this circuit, the amplifier

provides a gain of two, which increases the output span

+5V

10kΩ

2.2pF

–5V < V

< +5V

OUT

AD7304

REF

magnitude to 10 V. The transfer equation of this circuit shows

Figure 38. 4-Quadrant Multiplying Application Circuit

that both negative and positive output voltages are created as

Rev. C | Page 17 of 20

AD7304/AD7305

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

5.10

5.00

4.90

16

1

9

7.60 (0.2992)

7.40 (0.2913)

16

9

8

4.50

4.40

4.30

10.65 (0.4193)

10.00 (0.3937)

6.40

BSC

8

1

1.27 (0.0500)

0.75 (0.0295)

0.25 (0.0098)

2.65 (0.1043)

2.35 (0.0925)

PIN 1

BSC

× 45°

1.20

MAX

0.30 (0.0118)

0.10 (0.0039)

0.15

0.05

0.20

0.09

8°

0°

0.75

0.60

0.45

0.51 (0.0201)

0.31 (0.0122)

SEATING

PLANE

8°

0°

COPLANARITY

0.10

1.27 (0.0500)

0.40 (0.0157)

0.30

0.19

0.33 (0.0130)

0.20 (0.0079)

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MS-013AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MO-153AB

Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Figure 39. 16-Lead Standard Small Outline Package [SOIC]

Wide Body (R-16)

Dimensions shown in millimeters

Dimensions shown in millimeters and (inches)

6.60

6.50

6.40

13.00 (0.5118)

12.60 (0.4961)

20

1

11

10

7.60 (0.2992)

7.40 (0.2913)

20

11

10

4.50

4.40

4.30

10.65 (0.4193)

10.00 (0.3937)

6.40 BSC

1

2.65 (0.1043)

2.35 (0.0925)

0.75 (0.0295)

0.25 (0.0098)

× 45°

PIN 1

0.30 (0.0118)

0.10 (0.0039)

0.65

BSC

1.20 MAX

0.15

0.05

8°

0°

0.20

0.09

1.27

(0.0500)

BSC

SEATING

PLANE

0.51 (0.0201)

0.31 (0.0122)

1.27 (0.0500)

0.40 (0.0157)

0.75

0.60

0.45

COPLANARITY

0.10

0.33 (0.0130)

0.20 (0.0079)

8°

0°

0.30

0.19

COPLANARITY

0.10

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-013AC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MO-153AC

Figure 42. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Figure 40. 20-Lead Standard Small Outline Package [SOIC]

Wide Body (R-20)

Dimensions shown in millimeters

Dimensions shown in millimeters and (inches)

Rev. C | Page 18 of 20

AD7304/AD7305

ORDERING GUIDE

Model

AD7304BR

AD7304BR-REEL

AD7304BRZ¹

AD7304BRZ-REEL¹

Temperature Range

–40°C to +85°C

–40°C to +125°C

–40°C to +85°C

–40°C to +125°C

–40°C to +85°C

Package Description

16-Lead SOIC

16-Lead TSSOP

20-Lead SOIC

20-Lead TSSOP

Package Options

R-16

AD7304YR

AD7304YRZ¹

R-16

AD7304BRU

AD7304BRU-REEL7

AD7305BR

AD7305BR-REEL

AD7305YR

AD7305YR-REEL

AD7305BRU

AD7305BRU-REEL7

AD7305BRUZ¹

AD7305BRUZ-REEL7¹

RU-16

R-20

RU-20

¹Z = Pb-free part.

Rev. C | Page 19 of 20

AD7304/AD7305

NOTES

©

registered trademarks are the property of their respective companies.

Printed in the U.S.A. C01114-0-11/04(C)

Rev. C | Page 20 of 20


型号：	AD7305BRUZ
厂家：	ADI
描述：	3 V/5 V, Rail-to-Rail Quad, 8-Bit DAC 3 V / 5 V ，轨到轨四路， 8位DAC 转换器数模转换器光电二极管 PC
文件：	总20页 (文件大小：902K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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