AD664KPZ_技术文档

Monolithic

12-Bit Quad DAC

a

AD664

PIN CONFIGURATIONS

FEATURES

Four Complete Voltage Output DACs

Data Register Readback Feature

“Reset to Zero” Override

44-Pin Package

Multiplying Operation

Double-Buffered Latches

Surface Mount and DIP Packages

MIL-STD-883 Compliant Versions Available

APPLICATIONS

Automatic Test Equipment

Robotics

Process Control

Disk Drives

Instrumentation

Avionics

PRODUCT DESCRIPTION

The AD664 is four complete 12-bit, voltage-output DACs on

one monolithic IC chip. Each DAC has a double-buffered input

latch structure and a data readback function. All DAC read and

write operations occur through a single microprocessor-compatible

I/O port.

28-Pin DIP Package

The I/O port accommodates 4-, 8- or 12-bit parallel words al-

lowing simple interfacing with a wide variety of microprocessors.

A reset to zero control pin is provided to allow a user to simulta-

neously reset all DAC outputs to zero, regardless of the contents

of the input latch. Any one or all of the DACs may be placed in

a transparent mode allowing immediate response by the outputs

to the input data.

The analog portion of the AD664 consists of four DAC cells,

four output amplifiers, a control amplifier and switches. Each

DAC cell is an inverting R-2R type. The output current from

each DAC is switched to the on-board application resistors and

output amplifier. The output range of each DAC cell is pro-

grammed through the digital I/O port and may be set to unipo-

lar or bipolar range, with a gain of one or two times the reference

voltage. All DACs are operated from a single external reference.

4. The asynchronous RESET control returns all D/A outputs

to zero volts.

5. DAC-to-DAC matching performance is specified and tested.

The functional completeness of the AD664 results from the

combination of Analog Devices’ BiMOS II process, laser-trimmed

thin-film resistors and double-level metal interconnects.

6. Linearity error is specified to be 1/2 LSB at room tempera-

ture and 3/4 LSB maximum for the K, B and T grades.

7. DAC performance is guaranteed to be monotonic over the

full operating temperature range.

PRODUCT HIGHLIGHTS

1. The AD664 provides four voltage-output DACs on one chip

offering the highest density 12-bit D/A function available.

8. Readback buffers have tristate outputs.

9. Multiplying-mode operation allows use with fixed or vari-

able, positive or negative external references.

2. The output range of each DAC is fully and independently

programmable.

10. The AD664 is available in versions compliant with MIL-

STD-883. Refer to the Analog Devices Military Products

Databook or current AD664/883B data sheet for detailed

specifications.

3. Readback capability allows verification of contents of the in-

ternal data registers.

D

REV.

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

781/329-4700

781/461-3113

Fax:

Tel:

(V_LL= +5 V, V_CC= +15 V, V_EE= –15 V, V_REF= +10 V, T_A= +25؇C

unless otherwise noted)

AD664–SPECIFICATIONS

Model

JN/JP/AD/AJ/SD

KN/KP/BD/BJ/BE/TD/TE

Min

Typ

Max

Min

Typ

Max

Units

RESOLUTION

12

*

Bits

ANALOG OUTPUT

Voltage Range¹

UNI Versions

BIP Versions

Output Current

Load Resistance

Load Capacitance

Short-Circuit Current

0

V_CC– 2.0²

*

Volts

mA

kΩ

pF

mA

V_EE+ 2.0²

5

2

*

500

40

*

25

ACCURACY

Gain Error

–7

–2

–3

–3/4

–1

±3

7

2

3

3/4

1

–5

–1

–2

–1/2

–3/4

–1/2

±2

5

1

2

1/2

3/4

1/2

LSB

Unipolar Offset

±1/2

±3/4

±1/2

±3/4

±1/4

±1/2

±1/4

±1/2

Bipolar Zero³

Linearity Error⁴

Linearity T_MINto T_MAX

Differential Linearity

Differential Linearity T_MINto T_MAX

Gain Error Drift

–3/4

3/4

Monotonic @ All Temperatures

Unipolar 0 V to +10 V Mode

Bipolar –5 V to +5 V Mode

Bipolar –10 V to +10 V Mode

Unipolar Offset Drift

Unipolar 0 V to +10 V Mode

Bipolar Zero Drift

–12

±7

12

–10

±5

10

ppm of FSR⁵/°C

ppm of FSR/°C

–3

±l.5

3

–2

±l

2

ppm of FSR/°C

Bipolar –5 V to +5 V Mode

Bipolar –10 V to +10 V Mode

–12

±7

12

–10

±5

10

ppm of FSR/°C

REFERENCE INPUT

Input Resistance

1.3

2. 6

*

kΩ

Volts

Voltage Range⁶

V_EE+ 2.0²

V_CC– 2.0²

POWER REOUIREMENTS

V_LL

I_LL

4.5

5.0

5.5

*

Volts

@ V_IH, V_IL= 5 V, 0 V

@ V_IH, V_IL= 2.4 V, 0.4 V

V_CC/V_EE

I_CC

I_EE

0.1

3

1

6

*

mA

Volts

mA

؎11.4

؎16.5

15

19

12

15

400

*

Total Power

525

mW

ANALOG GROUND CURRENT⁷

–600

±400

+600

*

µA

MATCHING PERFORMANCE

Gain⁸

–6

–2

–3

–1.5

±3

±1/2

±1

6

2

3

1.5

–4

–1

–2

–1

±2

±1/4

±1

4

1

2

1

LSB

Offset⁹

Bipolar Zero¹⁰

Linearity¹¹

±1/2

CROSSTALK

Analog

Digital

–90

–60

*

dB

DYNAMIC PERFORMANCE (R_L= 2 kΩ, C_L= 500 pF)

Settling Time to ±1/2 LSB

Off←Bits→On, GAIN = 1, V_REF= 10

Settling Time to ±1/2 LSB

–10←V_REF→10 V, GAIN = 1, Bits On

Glitch Impulse

8

10

*

µs

10

µs

nV-sec

500

MULTIPLYING MODE PERFORMANCE

Reference Feedthrough @ 1 kHz

Reference –3 dB Bandwidth

–75

70

*

dB

kHz

POWER SUPPLY GAIN SENSITIVITY

11.4 V←V_CC→16.5 V

–16.5 V←V_EE→–11.4 V

±2

؎5

*

ppm/%

4.5 V←V_LL→5.5 V

D

–2–

REV.

AD664

Model

JN/JP/AD/AJ/SD

KN/KP/BD/BJ/BE/TD/TE

Min

Typ

Max

Min

Typ

Max

Units

DIGITAL INPUTS

V_IH

V_IL

2.0

0

*

Volts

0.8

*

Data Inputs

I_IH@ V_IN= V_LL

I_IL@ V_IN= DGND

CS/DS0/DS1/RST/RD/LS

I_IH@ V_IN= V_LL

I_IL@ V_IN= V_LL

MS/TR¹²

–10

±1

10

*

µA

–10

±1

10

*

µA

I_IH@ V_IN= V_LL

I_IL@ V_IN= DGND

QS0/QSl/QS2 ^l2

I_IH@ V_IN= V_LL

I_IL@ V_IN= DGND

–10

5

–5

10

0

*

µA

–10

5

±1

10

*

µA

DIGITAL OUTPUTS

V_OL@ 1.6 mA Sink

V_OH@ 0.5 mA Source

0.4

*

Volts

2.4

*

TEMPERATURE RANGE

JN/JP/KN/KP

AD/AJ/BD/BJ/BE

SD/TD/TE

0

–40

–55

+70

+85

+125

*

°C

NOTES

¹A minimum power supply of ±12.0 V is required for 0 V to +10 V and ±10 V operation. A minimum power supply of ±11.4 V is required for –5 V to +5 V operation.

²For V_CC< +12 V and V_EE> –12 V. Voltage not to exeeed 10 V maximum.

³Bipolar zero error is the difference from the ideal output (0 volts) and the actual output voltage with code 100 000 000 000 applied to the inputs.

⁴Linearity error is defined as the maximum deviation of the actual DAC output from the ideal output (a straight line drawn from 0 to F.S. – 1 LSB).

⁵FSR means Full-Scale Range and is 20 V for ±10 V range and 10 V for ±5 V range.

⁶A minimum power supply of ±12.0 V is required for a 10 V reference voltage.

⁷Analog Ground Current is input code dependent.

⁸Gain error matching is the largest difference in gain error between any two DACs in one package.

⁹Offset error matching is the largest difference in offset error between any two DACs in one package.

¹⁰Bipolar zero error matching is the largest difference in bipolar zero error between any two DACs in one package.

¹¹Linearity error matching is the difference in the worst ease linearity error between any two DACs in one package.

¹²44-pin versions only.

*Specifications same as JN/JP/AD/AJ/SD.

Specifications subject to change without notice.

Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min

and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

ABSOLUTE MAXIMUM RATINGS*

V_LLto DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +7 V

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Outputs . . . . . . . . . . . . . . . . . . . . . Indefinite Shorts to

V

_CCto DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V

_EEto DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V to 0 V

V_CC,V_LL, V_EEand GND

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –1 V to +1 V

Reference Input . . . . . . . . . . . . . . . . . . V_REF≤ ±10 V and V_REF

≤ (V_CC– 2 V, V_EE+ 2 V)

V

_CCto V_EE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +36 V

CAUTION

ESD (electrostatic discharge) sensitive device. Unused devices must be stored in conductive foam

or shunts. The protective foam should be discharged to the destination socket before devices are

removed.

WARNING!

ESD SENSITIVE DEVICE

D

REV.

–3–

AD664

Figure 1a. 44-Pin Block Diagram

FUNCTIONAL DESCRIPTION

tions. This register may also be read back to check its contents.

A RESET-TO-ZERO feature allows all DACs to be reset to 0

volts out by strobing a single pin.

The AD664 combines four complete 12-bit voltage output D/A

converters with a fast, flexible digital input/output port on one

monolithic chip. It is available in two forms, a 44-pin version

shown in Figure 1a and a 28-pin version shown in Figure 1b.

44-Pin Versions

Each DAC offers flexibility, accuracy and good dynamic perfor-

mance. The R-2R structure is fabricated from thin-film resistors

which are laser-trimmed to achieve 1/2 LSB linearity and guar-

anteed monotonicity. The output amplifier combines the best

features of the bipolar and MOS devices to achieve good dy-

namic performance and low offset. Settling time is under 10 µs

and each output can drive a 5 mA, 500 pF load. Short-circuit

protection allows indefinite shorts to V_LL, V_CC, V_EEand GND.

The output and span resistor pins are available separately. This

feature allows a user to insert current-boosting elements to in-

crease the drive capability of the system, as well as to overcome

parasitics.

Digital circuitry is implemented in CMOS logic. The fast, low

power, digital interface allows the AD664 to be interfaced with

most microprocessors. Through this interface, the wide variety

of features on each chip may be accessed. For example, the in-

put data for each DAC is programmed by way of 4-, 8-, 12- or

16-bit words. The double-buffered input structure of this latch

allows all four DACs to be updated simultaneously. A readback

feature allows the internal registers to be read back through the

same digital port, as either 4-, 8- or 12-bit words. When dis-

abled, the readback drivers are placed in a high impedance

(tristate) mode. A TRANSPARENT mode allows the input data

to pass straight through both ranks of input registers and appear

at the DAC with a minimum of delay. One D/A may be placed

in the transparent mode at a time, or all four may be made

transparent at once. The MODE SELECT feature allows the

output range and mode of the DACs to be selected via the data

bus inputs. An internal mode select register stores the selec-

Figure 1b. 28-Pin Block Diagram

28-Pin Versions

The 28-pin versions are dedicated versions of the 44-pin

AD664. Each offers a reduced set of features from those offered

in the 44-pin version. This accommodates the reduced number

of package pins available. Data is written and read with 12-bit

words only. Output range and mode select functions are also

not available in 28-pin versions. As an alternative, users specify

either the UNI (unipolar, 0 to V_REF) models or the BIP (bipolar,

–V_REFto V_REF) models depending on the application require-

ments. Finally, the transparent mode is not available on the

28-pin versions.

D

REV.

–4–

AD664

Table I. Transfer Functions

Mode = UNI

Mode = BIP

000000000000 = 0 V

Gain = 1 100000000000 = V_REF/2

111111111111 = V_REF– 1 LSB

000000000000 = – V_REF/2

100000000000 = 0 V

111111111111 = V_REF/2 –1 LSB

000000000000 = 0 V

Gain = 2 100000000000 = V_REF

111111111111 = 2 × V_REF– 1 LSB

000000000000 = V_REF

100000000000 = 0 V

111111111111 = +V_REF– 1 LSB

DEFINITIONS OF SPECIFICATIONS

UNIPOLAR OFFSET ERROR: Unipolar offset error is the dif-

ference between the ideal output (0 V) and the actual output of

a DAC when the input is loaded with all “0s” and the MODE is

unipolar.

LINEARITY ERROR: Analog Devices defines linearity error as

the maximum deviation of the actual, adjusted DAC output

from the ideal analog output (a straight line drawn from 0 to FS

– 1 LSB) for any bit combination. This is also referred to as

relative accuracy. The AD664 is laser-trimmed to typically

maintain linearity errors at less than ±1/4 LSB.

BIPOLAR ZERO ERROR: Bipolar zero error is the difference

between the ideal output (0 V) and the actual output of a DAC

when the input code is loaded with the MSB = “1” and the rest

of the bits = “0” and the MODE is bipolar.

MONOTONICITY: A DAC is said to be monotonic if the out-

put either increases or remains constant for increasing digital

inputs such that the output will always be a nondecreasing func-

tion of input. All versions of the AD664 are monotonic over

their full operating temperature range.

SETTLING TIME: Settling time is the time required for the

output to reach and remain within a specified error band about

its final value, measured from the digital input transition.

CROSSTALK: Crosstalk is the change in an output caused by

a change in one or more of the other outputs. It is due to

capacitive and thermal coupling between outputs.

DIFFERENTIAL LINEARITY: Monotonic behavior requires

that the differential linearity error be less than 1 LSB both at

25°C as well as over the temperature range of interest. Differen-

tial nonlinearity is the measure of the variation in analog value,

normalized to full scale, associated with a 1 LSB change in digi-

tal input code. For example, for a 10 V full-scale output, a

change of 1 LSB in digital input code should result in a

2.44 mV change in the analog output (V_REF= 10 V, Gain = 1,

1 LSB = 10 V × 1/4096 = 2.44 mV). If in actual use, however, a

1 LSB change in the input code results in a change of only

0.61 mV (1/4 LSB) in analog output, the differential non-

linearity error would be –1.83 mV, or –3/4 LSB.

REFERENCE FEEDTHROUGH: The portion of an ac refer-

ence signal that appears at an output when all input bits are low.

Feedthrough is due to capacitive coupling between the reference

input and the output. It is specified in decibels at a particular

frequency.

REFERENCE 3 dB BANDWIDTH: The frequency of the ac

reference input signal at which the amplitude of the full-scale

output response falls 3 dB from the ideal response.

GLITCH IMPULSE: Glitch impulse is an undesired output

voltage transient caused by asymmetrical switching times in the

switches of a DAC. These transients are specified by their net

area (in nV-sec) of the voltage vs. time characteristic.

GAIN ERROR: DAC gain error is a measure of the difference

between the output span of an ideal DAC and an actual device.

PIN CONFIGURATIONS

28-Pin DIP Package

44-Pin Package

D

REV.

–5–

AD664

ANALOG CIRCUIT CONSIDERATIONS

Grounding Recommendations

greater than both the external reference and the inverted exter-

nal reference.

The AD664 has two pins, designated ANALOG and DIGITAL

ground. The analog ground pin is the “high quality” ground ref-

erence point for the device. A unique internal design has

resulted in low analog ground current. This greatly simplifies

management of ground current and the associated induced volt-

age drops. The analog ground pin should be connected to the

analog ground point in the system. The external reference and

any external loads should also be returned to analog ground.

Output Considerations

Each DAC output can source or sink 5 mA of current to an

external load. Short-circuit protection limits load current to a

maximum load current of 40 mA. Load capacitance of up to

500 pF can be accommodated with no effect on stability.

Should an application require additional output current, a cur-

rent boosting element can be inserted into the output loop with

no sacrifice in accuracy. Figure 3 details this method.

The digital ground pin should be connected to the digital

ground point in the circuit. This pin returns current from the

logic portions of the AD664 circuitry to ground.

Analog and digital grounds should be connected at one point in

the system. If there is a possibility that this connection be bro-

ken or otherwise disconnected, then two diodes should be con-

nected between the analog and digital ground pins of the

AD664 to limit the maximum ground voltage difference.

Power Supplies and Decoupling

The AD664 requires three power supplies for proper operation.

Figure 3. Current-Boosting Scheme

V

_LLpowers the logic portions of the device and requires

AD664 output voltage settling time is 10 µs maximum. Figure 4

shows the output voltage settling time with a fixed 10 V refer-

ence, gain = 1 and all bits switched from 1 to 0.

+5 volts. V_CCand V_EEpower the remaining portions of the cir-

cuitry and require +12 V to +15 V and –12 V to –15 V, respec-

tively. V_CCand V_EEmust also be a minimum of two volts greater

then the maximum reference and output voltages anticipated.

Decoupling capacitors should be used on all power supply pins.

Good engineering practice dictates that the bypass capacitors be

located as near as possible to the package pins. V_LLshould be

bypassed to digital ground. V_CCand V_EEshould be decoupled to

analog ground.

Driving the Reference Input

The reference input of the AD664 can have an impedance as

low as 1.3 kΩ. Therefore, the external reference voltage must be

able to source up to 7.7 mA of load current. Suitable choices

include the 5 V AD586, the 10 V AD587 and the 8.192 V

AD689.

The architecture of the AD664 derives an inverted version of

the reference voltage for some portions of the internal circuitry.

This means that the power supplies must be at least 2 V

Figure 4. Settling Time; All Bits Switched from On to Off

Alternately, Figure 5 shows the settling characteristics when the

reference is switched and the input bits remain fixed. In this

case, all bits are “on,” the gain is 1 and the reference is switched

from –5 V to +5 V.

Figure 5. Settling Time; Input Bits Fixed, Reference

Switched

Figure 2. Recommended Circuit Schematic

D

REV.

–6–

AD664

Multiplying Mode Performance

Figure 6 illustrates the typical open-loop gain and phase perfor-

mance of the output amplifiers of the AD664.

the DAC operating mode data. All registers are double-buffered

to allow for simultaneous updating of all outputs. Register data

may be read back to verify the respective contents. The digital

port also allows transparent operation. Data from the input pins

can be sent directly through both ranks of latches to the DAC.

+20

GAIN

+15

+90

+45

0

+10

+5

0

PHASE

10k

100k

FREQUENCY – H

1M

z

Figure 6. Gain and Phase Performance of AD664 Outputs

Figure 8. Typical Output Noise

Crosstalk

Partial address decoding is performed by the DS0, DS1, QS0,

QS1 and QS2 address bits. QS0, QS1 and QS2 allow the 44-pin

versions of the AD664 to be addressed in 4-bit nibble, 8-bit byte

or 12-bit parallel words.

Crosstalk is a spurious signal on one DAC output caused by a

change in the output of one or more of the other DACs.

Crosstalk can be induced by capacitive, thermal or load current

induced feedthrough. Figure 7 shows typical crosstalk. DAC B

is set to output 0 volts. The outputs of DAC A, C and D switch

2 kΩ loads from 10 V to 0 V. The first disturbance in the output

of DAC B is caused by digital feedthrough from the input data

lows. The second disturbance is caused by analog feedthrough

from the other DAC outputs.

The RST pin provides a simple method to reset all output

voltages to zero. Its advantages are speed and low software

overhead.

INPUT DATA

In general, two types of data will be input to the registers of the

AD664, input code data and mode select data. Input code data

sets the DAC inputs while the mode select data sets the gain

and range of each DAC.

The versatile I/O port of the AD664 allows many different types

of data input schemes. For example, the input code for just one

of the DACs may be loaded and the output may or may not be

updated. Or, the input codes for all four DACs may be written,

and the outputs may or may not be updated.

The same applies for MODE SELECTION. The mode of just

one or many of the DACs may be rewritten and the user can

choose to immediately update the outputs or wait until a later

time to transfer the mode information to the outputs.

A user may also write both input code and mode information

into their respective first ranks and then update all second ranks

at once.

Figure 7. Output Crosstalk

Finally, transparent operation allows data to be transferred from

the inputs to the outputs using a single control line. This feature

is useful, for example, in a situation where one of the DACs is

used in an A/D converter. The SAR register could be connected

directly to a DAC by using the transparent mode of operation.

Another use for this feature would be during system calibration

where the endpoints of the transfer function of each DAC would

be measured. For example, if the full-scale voltages of each

DAC were to be measured, then by making all four DACs

transparent and putting all “1s” on the input port, all four

DACs would be at full-scale. This requires far less software

overhead than loading each register individually.

Output Noise

Wideband output noise is shown in Figure 8. This measurement

was made with a 7 MHz noise bandwidth, gain = 1 and all bits

on. The total rms noise is approximately one fifth the visual

peak-to-peak noise.

DIGITAL INTERFACE

As Table II shows, the AD664 makes a wide variety of operating

modes available to the user. These modes are accessed or pro-

grammed through the high speed digital port of the quad DAC.

On-board registers program and store the DAC input codes and

D

REV.

–7–

AD664

Table II. AD664 Digital Truth Table

Function

DS1, DS0

LS

MS

TR

QS0, 1, 2¹

RD

CS

RST

Load 1st Rank (data)

DACA

DACB

DACC

DACD

00

01

10

11

0

1

Select Quad

1

1→0

1

Load 2nd Rank (data)

Readback 2nd Rank (data)

Reset

XX

1

XXX

1

1→0

X

1

0

Select D/A

XX

X

1

Select Quad

XXX

0

X

Transparent¹

All DACs

DACA

XX

00

01

10

11

1

0

1

0

000

1

1→0

1

DACB

DACC

DACD

Mode Select^{1, 2}

1st Rank

2nd Rank

XX

0

1

0

1

00X

XXX

1

1→0

1

Readback Mode¹

XX

X

0

1

00X

0

1→0

1

Update 2nd Rank

and Mode

XX

1

0

XXX

1

1→0

1

NOTES

X = Don’t Care.

¹For 44-pin versions only. Allow the AD664 to be addressed in 4-bit nibble, 8-bit byte or 12-bit parallel words.

²For MS, TR, LS = 0, a MS 1st write occurs.

The following sections detail the timing requirements for

various data loading schemes. All of the timing specifica-

tions shown assume V_IH= 2.4 V, V_IL= 0.4 V, V_CC= +15 V,

V

_EE= –15 V and V_LL= +5 V.

Load and Update One DAC Output

In this first example, the object is simply to change the output of

one of the four DACs on the AD664 chip. The procedure is to

select the address bits that indicate the DAC to be programmed,

pull LATCH SELECT (LS) low, pull CHIP SELECT (CS)

low, release LS and then release CS. When CS goes low, data

enters the first rank of the input latch. As soon as LS goes high,

the data is transferred into the second rank and produces the

new output voltage. During this transfer, MS, TR, RD and RST

should be held high.

Figure 9a. Update Output of a Single DAC

25؇C

MIN (ns)

T_MINto T_MAX

MIN (ns)

SYMBOL

t_LS

Preloading the First Rank of One DAC

*

0

In this case, the object is to load new data into the first rank of

one of the DACs but not the output. As in the previous case, the

address and data inputs are placed on the appropriate pins. LS

is then brought to “0” and then CS is asserted. Note that in this

situation, however, CS goes high before LS goes high. The in-

put data is prevented from getting to the second rank and affect-

ing the output voltage.

t_DS

t_DH

t_LW

t_CH

t_AS

t_AH

0

60

30

0

80

50

0

*FOR t_LS> 0, THE WIDTH OF LS MUST BE

INCREASED BY THE SAME AMOUNT THAT

t_LSIS GREATER THAN 0 ns.

Figure 9b. Update Output of a Single DAC Timing

D

REV.

–8–

AD664

Figure 12. Preload First Rank Registers

Load and Update Multiple DAC Outputs

The following examples demonstrate two ways to update all

DAC outputs. The first method involves doing all data transfers

during one long CS low period. Note that in this case, shown in

Figure 13, LS returns high before CS goes high. Data hold time,

relative to an address change, is 70 ns. This updates the outputs

of all DACs simultaneously.

Figure 10a. Preload First Rank of a DAC

25؇C

MIN (ns)

T_MINto T_MAX

MIN (ns)

SYMBOL

t_LS

t_LH

t_CW

t_DS

t_DH

t_AS

t_AH

0

15

80

0

15

0

15

100

0

15

0

15

Figure 10b. Preload First Rank of a DAC Timing

This allows the user to “preload” the data to a DAC and strobe

it into the output latch at some future time. The user could do

this by reproducing the sequence of signals illustrated in the

next section.

Figure 13. Update All DAC Outputs

Update Second Rank of a DAC

The second method involves doing a CS assertion (low) and an

LS toggle separately for each DAC. It is basically a series of

preload operations (Figure 10). In this case, illustrated in Figure

14, two LS signals are shown. One, labeled LS, goes high before

CS returns high. This transfers the “new” input word to the

DAC outputs sequentially. The second LS signal, labeled Alter-

nate LS, stays low until CS returns high. Using this sequence

loads the first ranks with each “new” input word but doesn’t up-

date the DAC outputs. To then update all DAC outputs simul-

taneously would require the signals illustrated in Figure 11.

Assuming that a new input code had previously been placed into

the first rank of the input latches, the user can update the out-

put of the DAC by simply pulling CS low while keeping LS,

MS, TR, RD and RST high. Address data is not needed in this

case. In reality, all second ranks are being updated by this pro-

cedure, but only those which receive data different from that

already there would manifest a change. Updating the second

rank does not change the contents of the first rank.

Figure 11. Update Second Rank of a DAC

The same options that exist for individual DAC input loading

also exist for multiple DAC input loading. That is, the user can

choose to update the first and second ranks of the registers or

preload the first ranks and then update them at a future time.

Figure 14. Load and Update Multiple DACs

Preload Multiple First Rank Registers

SELECTING GAIN RANGE AND MODES (44-PIN

VERSIONS)

The first ranks of the DAC input registers may be preloaded

with new input data without disturbing the second rank data.

This is done by transferring the data into the first rank by bring-

ing CS low while LS is low. But CS must return high before LS.

This prevents the data from the first rank from getting into the

second rank. A simple second rank update cycle as shown in

Figure 11 would move the “preloaded” information to the

DACs.

The AD664’s mode select feature allows a user to configure the

gain ranges and output modes of each of the four DACs.

On-board switches take the place of up to eight external relays

that would normally be required to accomplish this task. The

switches are programmed by the mode select word entered via

the data I/O port. The mode select word is eight-bits wide and

D

REV.

–9–

AD664

occupies the topmost eight bits of the input word. The last four

bits of the input word are “don’t cares.”

Preloading the Mode Select Register

Mode data can be written into the first rank of the mode select

latch without changing the modes currently being used. This

feature is useful when a user wants to preload new mode infor-

mation in anticipation of strobing that in at a future time. Fig-

ure 17 illustrates the correct sequence and timing of control

signals to accomplish this task.

Figure 15 shows the format of the MODE SELECT word. The

first four bits determine the gain range of the DAC. When set to

be a gain of 1, the output of the DAC spans a voltage of 1 times

the reference. When set to a gain of 2, the output of the DAC

spans a voltage of 2 times the reference.

This allows the user to “preload” the data to a DAC and strobe

it into the output latch at some future time. The user could do

this by reproducing the sequence of signals illustrated in Figures

17c and 17d.

The next four bits determine the mode of the DAC. When set to

UNIPOLAR, the output goes from 0 to REF or 0 to 2 REF.

When the BIPOLAR mode is selected, the output goes from

–REF/2 to REF/2 or –REF to REF.

Figure 15. Mode Select Word Format

Load and Update Mode of One DAC

Figure 17a. Preload Mode Select Register

In this next example, the object is to load new mode informa-

tion for one of the DACs into the first rank of latches and then

immediately update the second rank. This is done by putting the

new mode information (8-bit word length) onto the databus.

Then MS and LS are pulled low. Following that, CS is pulled

low. This loads the mode information into the first rank of

latches. LS is then brought high. This action updates the second

rank of latches (and, therefore, the DAC outputs). The load

cycle ends when CS is brought high.

Figure 17b. Preload Mode Select Register Timing

In reality, this load cycle really updates the modes of all the

DACs, but the effect is to only change the modes of those

DACs whose mode select information has actually changed.

1

DATA

INPUT/OUTPUT

BITS

0

1

ADDRESS

___ ___ ___

QS0,QS1,QS2

DS0,DS1

0

__

MS

t_MS

__

CS

t_MH

t_W

Figure 17c. Update Second Rank of Mode Select Latch

25؇C

T_MINto T_MAX

SYMBOL

t_MS

t_MH

MIN (ns)

0

MIN (ns)

0

Figure 16a. Load and Update Mode of One DAC

t_W

80

100

25؇C

MIN (ns)

T_MINto T_MAX

MIN (ns)

Figure 17d. Update Second Rank of Mode Select Latch

Timing

SYMBOL

t_MS

0

Transparent Operation (44-Pin Versions)

t_LS

*

Transparent operation allows data from the inputs of the

AD664 to be transferred into the DAC registers without the

intervening step of being latched into the first rank of latches.

Two modes of transparent operation exist, the “partially trans-

parent” mode and a “fully transparent” mode. In the “partially

transparent” mode, one of the DACs is transparent while the

remaining three continue to use the data latched into their

respective input registers. Both modes require a 12-bit wide

input word!

t_DS

t_LW

t_CH

t_DH

t_MH

0

60

70

0

70

80

0

*FOR t_LS> 0, THE WIDTH OF LS MUST BE

INCREASED BY THE SAME AMOUNT THAT

t_LSIS GREATER THAN 0 ns.

Figure 16b. Load and Update Mode of One DAC Timing

D

REV.

–10–

AD664

Fully transparent operation can be thought of as a simultaneous

load of data from Figure 9a where replacing LS with TR causes

all 4 DACs to be loaded at once.

OUTPUT DATA

Two types of outputs may be obtained from the internal data

registers of the AD664 chip, mode select and DAC input code

data. Readback data may be in the same forms in which it can

be entered; 4-, 8-, and 12-bit wide words (12 bits only for

28-pin versions).

The Fully transparent mode is achieved by asserting lows on

QS0, QS1, QS2, TR and CS while keeping LS high in addition

to MS and RB. Figure 18a illustrates the necessary timing rela-

tionships. Fully transparent operation will also work with TR

tied low (enabled).

DAC Data Readback

DAC input code readback data is obtained by setting the address

of the DAC (DS0, DS1) and Quads (QS0, QS1, QS2) on the

address pins and bringing the RD and CS pins low. The timing

diagram for a DAC code readback operation appears in Figure 20.

1

LS

DATA INPUT/

DATA VALID

OUTPUT BITS

t_DH

t_QH

t_DS

QS

TR

CS

t_QS

t_TW

t_TS

t_CH

Figure 18a. Fully Transparent Mode

25؇C

MIN (ns)

T_MINto T_MAX

MIN (ns)

SYMBOL

t_AS

t_QS

0

Figure 20a. DAC Input Code Readback

t_TS

*

t_TW

t_CH

t_DH

t_QH

80

90

0

90

110

0

25°C

MIN (ns)

T_MINto T_MAX

MIN (ns)

SYMBOL

t_AS

t_RS

t_DV

t_DF

t_AH

t_RH

0

150

60

0

180

75

0

*FOR t_TS> 0, THE WIDTH OF TR MUST BE

INCREASED BY THE SAME AMOUNT THAT

t_TSIS GREATER THAN 0 ns.

Figure 18b. Fully Transparent Mode Timing

0

Partially transparent operation can be thought of as preloading

the first rank in Figure 10a without requiring the additional CS

pulse from Figure 11.

Figure 20b. DAC Input Code Readback Timing

Mode Data Readback

Mode data is read back in a similar fashion. By settingMS, QS0,

QS1, RD and CS low while setting TR and RST high, the mode

select word is presented to the I/O port pins. Figure 21 shows the

timing diagram for a readback of the mode select data register.

The partially transparent mode is achieved by setting CS, QS0,

QS1, QS2, LS, and TR low while keeping RD and MS high.

The address of the transparent DAC is asserted on DS0 and

DS1. Figure 19a illustrates the necessary timing relationships.

Partially transparent operation will also work with TR tied low

(enabled).

DATA INPUT/

DATA VALID

OUTPUT BITS

t_DH

t_DS

ADDRESS

QS0, QS1, QS2

DS0, DS1, LS

ADDRESS VALID

t_AH

t_AS

t_TS

TR

t_TH

t_W

CS

Figure 21a. Mode Data Readback

Figure 19a. Partially Transparent

25؇C

MIN (ns)

T_MINto T_MAX

MIN (ns)

25°C

MIN (ns)

T_MINto T_MAX

MIN (ns)

SYMBOL

t_DS

t_AS

t_TS

t_W

t_DH

t_AH

t_TH

0

90

15

0

110

15

t_AS

t_MS

t_DV

t_DF

t_AH

t_MH

0

150

60

0

180

75

0

Figure 21b. DAC Mode Readback Timing

Figure 19b. Partially Transparent Mode Timing

D

REV.

–11–

AD664

Output Loads

+5V

Readback timing is tested with the output loads shown in Figure

22.

AD664

#1

AD664

#N

10kΩ

RST

100nF

Figure 24. Power-On Reset

It is obvious from inspection that the scheme shown in Figure

24 is only appropriate for systems in which the RST is otherwise

not used. Should the user wish to use the RST pin, an addi-

tional logic gate may be included to combine the power-on reset

with the reset signal.

INTERFACING THE AD664 TO MICROPROCESSORS

The AD664 is easy to interface with a wide variety of popular

microprocessors. Common architectures include processors with

dedicated 8-bit data and address buses, an 8-bit bus over which

data and address are multiplexed, an 8-bit data and 16-bit

address partially muxed, and separate 16-bit data and address

buses.

Figure 22. Output Loads

Asynchronous Reset Operation

AD664 addressing can be accomplished through either

memory-mapped or I/O techniques. In memory-mapped

schemes, the AD664 appears to the host microprocessor as

RAM memory. Standard memory addressing techniques are

used to select the AD664. In the I/O schemes, the AD664 is

treated as an external I/O device by the host. Dedicated I/O pins

are used to address the AD664.

The asynchronous reset signal shown in Figure 23 may be

asserted at any time. A minimum pulse width (t_RW) of 90 ns is

required. The reset feature is designed to return all DAC out-

puts to 0 volts regardless of the mode or range selected. In the

44-pin versions, the modes are reset to unipolar 10 V span (gain

of 1), and the input codes are rewritten to be “0s.” Previous

DAC code and mode information is erased.

MC6801 Interface

In Figures 25a–25d, we illustrate a few of the various methods

that can be used to connect an AD664 to the popular MC6801

microprocessor. In each of these cases, the MC6801 is intended

to be configured in its expanded, nonmultiplexed mode of

operation. In this mode, the MC6801 can address 256 bytes of

external memory over 8-bit data (Port 3) and 8-bit address

(Port 4) buses. Eight general-purpose I/O lines (Port 1) are also

available. On-board RAM and ROM provide program and data

storage space.

Figure 23a. Asynchronous Reset Operation

In Figure 25a, the three least significant address bits (P40, P41

and P42) are employed to select the appropriate on-chip

addresses for the various input registers of the AD664. Three

I/O lines (P17, P16 and P15) are used to select various operat-

ing features of the the AD664. IOS and E(nable) are combined

to produce an appropriate CS signal. This addressing scheme

leaves the five most significant address bits and five I/O lines

free for other tasks in the system.

Figure 23b. Asynchronous Reset Operation Timing

In the 28-pin versions of the AD664, the mode remains

unchanged, the appropriate input code is rewritten to reset the

output voltage to 0 volts. As in the 44-pin versions, the previous

input data is erased.

At power-up, an AD664 may be activated in either the read or

write modes. While at the device level this will not produce any

problems, at the system level it may. Analog Devices recom-

mends the addition of a simple power-on reset scheme to any

system where the possibility of an unknown start-up state could

be a problem. The simplest version of this scheme is illustrated

in Figure 24.

Figure 25b shows another way to interface an AD664 to the

MC6801. Here we’ve used the six least significant address lines

to select AD664 features and registers. This is a purely memory-

mapped scheme while the one illustrated in Figure 25a uses

some memory-mapping as well as some dedicated I/O pins. In

Figure 25b, two address lines and all eight I/O lines remain free

for other system tasks.

D

REV.

–12–

AD664

Expansion of the scheme employed in Figure 25a results in that

shown in Figure 25c. Here, two AD664s are connected to an

MC6801, providing a total of eight 12-bit, software program-

mable DACs. Again, the three least significant bits of address

are used to select the on-chip registers of the AD664. IOS and

E, as well as a fourth address bit, are decoded to provide the

appropriate CS signals. Four address and five I/O lines remain

uncommitted.

A slightly more sophisticated approach to system expansion is

illustrated in Figure 25d. Here, a 74LS138 (1-of-8 decoder) is

used to address one of the eight AD664s connected to the

MC6801. The three least significant address bits are used to

select on-chip register and DAC. The next three address bits are

used to select the appropriate AD664. IOS and E gate the

74LS138 output.

Figure 25a. Simple AD664 to MC6801 Interface

Figure 25b. Alternate AD664 to MC6801 Interface

Figure 25c. Interfacing Two AD664s to an MC6801

–13–

D

REV.

AD664

The schemes in Figure 25 illustrate some of the trade-offs which

a designer may make when configuring a system. For example,

the designer may use I/O lines instead of address bits or vice

versa. This decision may be influenced by other I/O tasks or sys-

tem expansion requirements. He/she can also choose to imple-

ment only a subset of the features available. Perhaps the RST

pin isn’t really needed. Tying that input pin to V_LOGICfrees up

another I/O or address bit. The same consideration applies to

Each of the schemes illustrated in Figure 25 operates with an

MC6801 at clock rates up to and including 1.5 MHz. Similar

schemes can be derived for other 8-bit microprocessors and

microcontrollers such as the 8051/8086/8088/6502, etc. One

such scheme developed for the 8051/AD664 is illustrated in

Figure 26.

8051 Interface

Figure 26 shows the AD664 combined with an 8051 µcontroller

chip. Three LSBs of address provide the quad and DAC select

signals. Control signals from Port 1 select various operating

modes such as readback, mode select and reset as well as pro-

viding the LS signal. Read and write signals from the 8051 are

decoded to provide the CS signal.

mode select. In all of these cases TR is shown tied to V_LOGIC

because the MC6801 cannot provide the 12-bit-wide input

word required for the transparent mode. In situations where

,

transparent operation isn’t required, and mode select is also not

needed, the designer may consider specifying the DIP version of

the device (either the UNI or BIP version).

Figure 25d. Interfacing Eight AD664s to an MC6801

D

REV.

–14–

AD664

IBM PC* Interface

is required to transfer the word or words previously written to

the second rank. A 12-bit-wide word again requires at least two

read cycles; one for the 8 MSBs and four for the LSBs. The

page select signal produces a CS strobe for any address from

300H to 31FH.

Figure 27 illustrates a simple interface between an IBM PC and

an AD664. The three least significant address bits are used to

select the Quad and DAC. The next two address bits are used

for LS and MS. In this scheme, a 12-bit input word requires

two load cycles, an 8-bit word and a 4-bit word. Another write

Figure 26. AD664 to 8051 Interface

Figure 27. AD664 to IBM PC Interface

*IBM PC is a trademark of International Business Machines Corp.

D

REV.

–15–

AD664

Table III details the memory locations and addresses used by this interface.

Table III. IBM PC Memory Map

HEX

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

REGISTER SELECTED

300

301

302

303

304

305

306

307

308

309

30A

30B

30C

30D

30E

30F

310

311

312

313

314

315

316

317

318

319

31A

31B

31C

31D

31E

31F

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Illegal Address

Mode Select, 1st Rank

Illegal Address

Mode Select, 1st Rank

Illegal Address

Mode Select, 1st Rank

Illegal Address

▼

Mode Select, 1st Rank

Mode Select, 2nd Rank

1

▼

1

0

DAC A, 4 LSBs, 1st Rank

DAC A, 8 MSBs, 1st Rank

DAC B, 4 LSBs, 1st Rank

DAC B, 8 MSBs, 1st Rank

DAC C, 4 LSBs, 1st Rank

DAC C, 8 MSBs, 1st Rank

DAC D, 4 LSBs, 1st Rank

DAC D, 8 MSBs, 1st Rank

2nd Rank

▼

1

▼

Note: Shaded registers are readable.

D

REV.

–16–

AD664

The following IBM PC Basic routine produces four output volt-

age ramps from one AD664. Line numbers 10 through 70 de-

fine the hardware addresses for the first and second ranks of

DAC registers as well as the first and second ranks of the mode

select register. Program variables are initialized in line numbers

110 through 130. Line number 170 writes “0s” out to the first

rank and, then, the second rank of the mode select register.

Line numbers 200 through 320 calculate output voltages. Fi-

nally line numbers 410 through 450 update the first, then the

second ranks of the DAC input registers. Hardware registers

may be read with the “INP” instruction. For example, the con-

tents of the DAC A register may be accessed with the following

com mand: Line# A = INP(DACA).

5

10

REM----AD664 LISSAJOUS PATTERNS----

REM ---ASSIGN HARDWARE ADDRESSES---

20

DACA = 785

30

DACB = 787

40

DACC = 789

50

DACD = 791

60

DAC2ND = 792

70

MODE1 = 769: MODE2 = 776

80

REM

90

REM

100

110

120

130

140

150

160

170

180

190

200

210

220

230

240

250

260

270

280

290

300

310

320

330

340

400

410

420

430

440

450

500

510

520

530

REM ---INITIALIZE VARIABLES---

X = 0: Y1 = 128: Y2 = 64: Y3 = 32

CX = 1: CY1 = 1: CY2 = -1: CY3= 1

FX = 9: FY1 = 5: FY2 = 13: FY3 = 15

REM

REM ---INITIALIZE MODES AND GAINS---

OUT MODE1,0: OUT MODE2,0

REM

REM ---CALCULATE VARIABLES---

X = X + FX*CX

Y1 = Y1 + FY1*CY1

Y2 = Y2 + FY2*CY2

Y3 = Y3 + FY3*CY3

IF X > 255 THEN X = 255: CX = -1: GOTO 270

IF X < 0 THEN X = 0: CX = 1

IF Y1 > 255 THEN Y1 = 255: CY1 = -1: GOTO 290

IF Y1 < 0 THEN Y1 = 0: CY1 = 1

IF Y2 > 255 THEN Y2 = 255: CY2 = -1 GOTO 310

IF Y2 < 0 THEN Y2 = 0: CY2 = -1

IF Y3 > 255 THEN Y3 = 255: CY3 = -1: GOTO 400

IF Y3 < 0 THEN Y3 = 0: CY3 = 1

REM

REM ---SEND DAC DATA---

OUT DACA,X

OUT DACB,Yl

OUT DACC,Y2

OUT DACD,Y3

OUT DAC2ND,0

REM

REM ---LOOP BACK---

GOTO 210

D

REV.

–17–

AD664

Simple AD664 to MC68000 Interface

This scheme can be converted to write “right-justified’’ data by

connecting the data inputs to DATA bits D0 through D11

respectively. Other options include controlling the QS0, QS1

and QS2 pins with UDS and LDS to provide a way to write

8-bit input and read 8-bit output words.

Figure 28 shows an AD664 connected to an MC68000. In this

memory-mapped I/O scheme, the “left-justified” data is written

in one 12-bit input word. Four address bits are used to perform

the on-chip D/A selection as well as the various operating fea-

tures. The R/W signal controls the RD function and system

reset controls RST.

Figure 28. AD664 to MC68000 Interface

D

REV.

–18–

AD664

Figure 29. AD664 in “Tester-per-Pin” Architecture

APPLICATIONS OF THE AD664

“Tester-Per-Pin” ATE Architecture

some software where the previous example would require only a

single reset strobe signal!

Figure 29 shows the AD664 used in a single channel of a digital

test system. In this scheme, the AD664 supplies four individual

output voltages. Two are provided to the V_HIGHand V_LOWin-

puts of the AD345 pin driver I.C. to set the digital output levels.

Two others are routed to the inputs of the AD96687 dual com-

parator to supply reference levels of the readback features. This

approach can be replicated to give as many channels of stimulus/

readback as the tester has pins. The AD664 is a particularly

appropriate choice for a large-scale system because the low

power requirements (under 500 mW) ease power supply and

cooling requirements. Analog ground currents of 600 µA or less

make the ground current management task simpler. All DACs

can be driven from the same system reference and will track

over time and temperature. Finally, the small board area

required by the AD664 (and AD345 and AD96687) allows a

high functional density.

Drawing scaling can be achieved by taking advantage of the

AD664’s software programmable gain settings. If, for example,

an “A” size drawing is created with gain settings of 1, then a

“C” size drawing can be created by simply resetting all DAC

gains to 2 and redrawing the object. Conversely, a “C” size

drawing created with gains of 2 can be reduced to “A” size sim-

ply by changing the gains to 1 and redrawing. The same princi-

pal applies for conversion from “B” size to “D” size or “D” size

to “B” size. The multiplying capability of the AD664 provides

another scaling option. Changing the reference voltage provides

a proportional change in drawing size. Inverting the reference

voltage would invert the drawing.

Swapping digital input data from the X channel to the Y chan-

nel would rotate the drawing 90 degrees.

X-Y Plotters

Figure 30 is a block diagram of the control section of a

microprocessor-controlled X-Y pen plotter. In this conceptual

exercise, two of the DACs are used for the X-channel drive and

two are used for the Y-channel drive. Each provides either the

coarse or fine movement control for its respective channel. This

approach offers increased resolution over some other approaches.

A designer can take advantage of the reset feature of the AD664

in the following manner. If the system is designed such that the

“HOME” position of the pen (or galvanometer, beam, head or

similar mechanism) results when the outputs of all of the DACs

are at zero, then no system software is required to home the

pen. A simple reset signal is sufficient.

Figure 30. X-Y Plotter Block Diagram

Similarly, the transparent feature could be used to the same

end. One code can be sent to all DACs at the same time to send

the pen to the home position. Of course, this would require

D

REV.

–19–

AD664

OUTLINE DIMENSIONS

0.100 (2.54)

MAX

0.005 (0.13)

MIN

28

15

0.610 (15.49)

0.580 (12.73)

PIN 1

1

4

0.620 (15.75)

0.590 (14.99)

1.490 (37.85) MAX

0.085 (2.16)

0.060 (1.52)

0.015 (0.38)

MAX

0.150

(3.81)

MIN

0.018 (0.46)

0.008 (0.20)

0.200 (5.08)

0.125 (3.18)

SEATING

PLANE

0.026 (0.66)

0.014 (0.36)

0.070 (1.78)

0.030 (0.76)

0.100 (2.54)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 31. 28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]

(D-28-2)

Dimensions shown in inches and (millimeters)

1.565 (39.75)

1.380 (35.05)

28

1

15

0.580 (14.73)

0.485 (12.31)

14

0.625 (15.88)

0.600 (15.24)

0.100 (2.54)

BSC

0.195 (4.95)

0.125 (3.17)

0.250 (6.35)

MAX

0.015 (0.38)

GAUGE

PLANE

0.015

(0.38)

MIN

0.200 (5.08)

0.115 (2.92)

0.015 (0.38)

0.008 (0.20)

SEATING

PLANE

0.700 (17.78)

MAX

0.022 (0.56)

0.014 (0.36)

0.005 (0.13)

MIN

0.070 (1.78)

0.050 (1.27)

COMPLIANT TO JEDEC STANDARDS MS-011

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS.

Figure 32. 28-Lead Plastic Dual In-Line Package [PDIP]

Wide Body

(N-28-2)

Dimensions shown in inches and (millimeters)

–20–

REV. D

AD664

0.100 (2.54)

0.064 (1.63)

0.055 (1.40)

0.045 (1.14)

0.075 (1.91) REF

6

40

39

0.020 (0.51)

44

7

1

REF  45°

0.662 (16.82)

0.640 (16.27)

0.028 (0.71)

0.022 (0.56)

SQ

0.050

(1.27)

BSC

BOTTOM VIEW

29

28

17

0.040 (1.02)

REF  45°

3 PLACES

18

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 33. 44-Terminal Ceramic Leadless Chip Carrier [LCC]

(E-44-1)

Dimensions shown in inches and (millimeters)

0.078 (1.98)

0.054 (1.37)

0.040 (1.02)

REF

0.020 (0.51)

REF

 45°

0.662 (16.82)

0.628 (15.95)

SQ

 45°

0.025 (0.64)

MIN

3 PLACES

39

29

40

28

0.032 (0.81)

0.020 (0.51)

PIN 1 INDEX

0.065 (1.65)

0.050

(1.27)

BSC

0.650 (16.51)

0.610 (15.49)

PIN 1

0.500 (12.70)

0.492 (12.50)

TOP VIEW

BOTTOM VIEW

0.023 (0.58)

0.013 (0.33)

6

18

7

17

0.700 (17.78)

0.680 (17.27)

SQ

0.135 (3.43)

0.100 (2.54)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 34. 44-Lead Ceramic Leaded Chip Carrier, J-Formed Leads [JLCC]

(J-44)

Dimensions shown in inches and (millimeters)

REV. D

–21–

AD664

0.180 (4.57)

0.165 (4.19)

0.048 (1.22)

0.042 (1.07)

0.056 (1.42)

0.042 (1.07)

0.020 (0.51)

MIN

6

7

40

39

0.048 (1.22)

0.042 (1.07)

0.021 (0.53)

0.013 (0.33)

PIN 1

IDENTIFIER

0.630 (16.00)

0.590 (14.99)

BOTTOM VIEW

(PINS UP)

0.050

(1.27)

BSC

TOP VIEW

(PINS DOWN)

0.032 (0.81)

0.026 (0.66)

17

18

29

28

0.045 (1.14)

0.025 (0.64)

R

0.656 (16.66)

0.650 (16.51)

0.120 (3.05)

0.090 (2.29)

SQ

0.695 (17.65)

0.685 (17.40)

SQ

COMPLIANT TO JEDEC STANDARDS MO-047-AC

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 35. 44-Lead Plastic Leaded Chip Carrier [PLCC]

(P-44)

Dimensions shown in inches and (millimeters)

ORDERING GUIDE

Model¹

Temperature Range

Package Description

28-Lead Side-Brazed SBDIP

44-Lead LCC

28-Lead Side-Brazed SBDIP

44-Lead JLCC

28-Lead Side-Brazed SBDIP

44-Lead LCC

44-Lead JLCC

28-Lead PDIP

44-Lead PLCC

Package Option

5962-8871901MXA

5962-8871902MXA

5962-8871903MYA

AD664AD-BIP

AD664AD-UNI

AD664AJ

AD664BD-BIP

AD664BD-UNI

AD664BE

−55°C to +125°C

−40°C to +85°C

0°C to +70°C

D-28-2

E-44-1

D-28-2

J-44

D-28-2

E-44-1

J-44

N-28-2

P-44

AD664BJ

AD664JN-BIP

AD664JN-UNI

AD664JNZ-BIP

AD664JNZ-UNI

AD664JP

0°C to +70°C

AD664JPZ

0°C to +70°C

44-Lead PLCC

P-44

AD664KN-BIP

AD664KNZ-BIP

AD664KNZ-UNI

AD664KP

0°C to +70°C

28-Lead PDIP

44-Lead PLCC

N-28-2

P-44

AD664KPZ

0°C to +70°C

44-Lead PLCC

P-44

AD664SD-BIP

AD664SD-BIP/883B

AD664SD-UNI

AD664SD-UNI/883B

AD664TD-BIP

AD664TD-BIP/883B

AD664TD-UNI/883B

AD664TE/883B

AD664TJ/883B

−55°C to +125°C

28-Lead Side-Brazed SBDIP

44-Lead LCC

D-28-2

E-44-1

J-44

44-Lead JLCC

¹Z = RoHS Compliant Part.

–22–

REV. D

AD664

REVISION HISTORY

2/12—Rev. C to Rev. D

Updated Outline Dimensions....................................................... 20

Changes to Ordering Guide .......................................................... 21

12/91—Rev. B to Rev. C

registered trademarks are the property of their respective owners.

D10590-0-2/12(D)

REV. D

–23–


型号：	AD664KPZ
厂家：	ADI
描述：	Monolithic 12-Bit Quad DAC 单片12位四路DAC
文件：	总23页 (文件大小：671K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD664KPZ [ADI]

相关型号：

AD664SD-BIP

AD664SD-BIP/883B

AD664SD-UNI

AD664SD-UNI/883B

AD664TD-BIP

AD664TD-BIP/883B

AD664TD-UNI

AD664TD-UNI/883B

AD664TE-BIP

AD664TE/883B

AD664TJ/883B

AD6650