AD6640AST [ADI]
12-Bit, 65 MSPS IF Sampling A/D Converter; 12位， 65 MSPS IF采样A / D转换器
| 型号： | AD6640AST |
| 厂家： | 
ADI |
| 描述： | 12-Bit, 65 MSPS IF Sampling A/D Converter |
| 文件： | 总24页 (文件大小：491K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit, 65 MSPS
IF Sampling A/D Converter
a
AD6640
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
65 MSPS Minim um Sam ple Rate
80 dB Spurious-Free Dynam ic Range
IF-Sam pling to 70 MHz
AV
DV
CC
CC
710 m W Pow er Dissipation
Single +5 V Supply
AIN
A
TH1
TH2
TH3
BUF
ADC
AIN
On-Chip T/ H and Reference
Tw os Com plem ent Output Form at
3.3 V or 5 V CMOS-Com patible Output Levels
+2.4V
REFERENCE
ADC
DAC
7
V
AD6640
REF
6
ENCODE
INTERNAL
TIMING
DIGITAL ERROR CORRECTION LOGIC
ENCODE
APPLICATIONS
MSB
LSB
Cellular/ PCS Base Stations
Multichannel, Multim ode Receivers
GPS Anti-J am m ing Receivers
Com m unications Receivers
Phased Array Receivers
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
GND
P RO D UCT D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
T he AD6640 is a high speed, high performance, low power,
monolithic 12-bit analog-to-digital converter. All necessary
functions, including track-and-hold (T /H) and reference are
included on-chip to provide a complete conversion solution.
The AD6640 runs on a single +5 V supply and provides CMOS-
compatible digital outputs at 65 MSPS.
1. Guaranteed sample rate is 65 MSPS.
2. Fully differential analog input stage specified for frequencies
up to 70 MHz; enables “IF Sampling.”
3. Low power dissipation: 710 mW off a single +5 V supply.
4. Digital outputs may be run on +3.3 V supply for easy inter-
face to digital ASICs.
Specifically designed to address the needs of multichannel,
multimode receivers, the AD6640 maintains 80 dB spurious-
free dynamic range (SFDR) over a bandwidth of 25 MH z.
Noise performance is also exceptional; typical signal-to-noise
ratio is 68 dB.
5. Complete Solution: reference and track-and-hold.
6. Packaged in small, surface mount, plastic 44-terminal TQFP.
The AD6640 is built on Analog Devices’ high speed complemen-
tary bipolar process (XFCB) and uses an innovative multipass
architecture. Units are packaged in a 44-terminal Plastic T hin
Quad Flatpack (T QFP) specified from –40°C to +85°C.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1998
AD6640–SPECIFICATIONS
(AV = +5 V, DV = +3.3 V; TMIN = –40؇C, TMAX = +85؇C)
DC SPECIFICATIONS
CC
CC
Test
AD 6640AST
Typ
P aram eter
Tem p
Level
Min
Max
Units
RESOLUT ION
12
Bits
ACCURACY
No Missing Codes
Offset Error
+25°C
Full
Full
+25°C
Full
I
GUARANT EED
VI
VI
I
–10
–10
–1.0
3.5
4.0
±0.5
±1.25
+10
+10
+1.5
mV
Gain Error
% FS
LSB
LSB
Differential Nonlinearity (DNL)1
Integral Nonlinearity (INL)1
V
T EMPERAT URE DRIFT
Offset Error
Gain Error
Full
Full
V
V
50
100
ppm/°C
ppm/°C
POWER SUPPLY REJECT ION (PSRR)
Full
Full
V
V
±0.5
mV/V
V
2
REFERENCE OUT (VREF
ANALOG INPUT S (AIN,
)
2.4
3
)
Analog Input Common-Mode Range4
Differential Input Voltage Range
Differential Input Resistance
Full
Full
Full
+25°C
V
V
IV
V
VREF ± 0.05
V
2.0
0.9
1.5
V p-p
kΩ
pF
0.7
1.1
Differential Input Capacitance
POWER SUPPLY
Supply Voltage
AVCC
Full
Full
VI
VI
4.75
3.0
5.0
3.3
5.25
5.25
V
V
DVCC
Supply Current
IAVCC (AVCC = 5.0 V)
IDVCC (DVCC = 3.3 V)
Full
Full
VI
VI
135
10
160
20
mA
mA
POWER CONSUMPT ION
Full
VI
710
865
mW
NOT ES
1 ENCODE = 20 MSPS
2 If VREF is used to provide a dc offset to other circuits, it should first be buffered.
3T he AD6640 is designed to be driven differentially. Both AIN and
should be driven at levels VREF ± 0.5 volts. T he input signals should be 180 degrees out of phase to
produce a 2 V p-p differential input signal. See Driving the Analog Inputs section for more details.
4 Analog input common-mode range specifies the offset range the analog inputs can tolerate in dc-coupled applications (see Figure 35 for more detail).
Specifications subject to change without notice
.
(AV = +5 V, DV = +3.3 V; TMIN = –40؇C, TMAX = +85؇C)
DIGITAL SPECIFICATIONS
CC
CC
Test
Level
AD 6640AST
Typ
P aram eter
Tem p
Min
Max
Units
1
LOGIC INPUT S (ENC,
)
Encode Input Common-Mode Range2
Differential Input Voltage
Single-Ended Encode
Full
Full
IV
IV
0.2
0.4
2.2
10
V
V p-p
V p-p
Logic Compatibility3
T T L/CMOS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (VINH = 5 V)
Logic “0” Current (VINL = 0 V)
Input Capacitance
Full
Full
Full
Full
VI
VI
VI
VI
V
2.0
0
500
–400
5.0
0.8
800
–200
V
V
µA
µA
pF
650
–320
2.5
+25°C
LOGIC OUT PUT S (
Logic Compatibility
–D0)4
CMOS
Logic “1” Voltage (DVCC = +3.3 V)
Logic “0” Voltage (DVCC = +3.3 V)
Logic “1” Voltage (DVCC = +5.0 V)
Logic “0” Voltage (DVCC = +5.0 V)
Output Coding
Full
Full
Full
Full
VI
VI
IV
IV
2.8
4.5
DVCC – 0.2
V
V
V
V
0.2
DVCC – 0.3
0.35
0.5
0.5
T wos Complement
NOT ES
1Best dynamic performance is obtained by driving ENC and
shown in Figure 18 under T ypical Performance Characteristics.
differentially. See Encoding the AD6640 section for more details. Performance versus ENC/
power is
2For dc-coupled applications, Encode Input Common-Mode Range specifies the common-mode range the encode inputs can tolerate when driven differentially by minimum
differential input voltage of 0.4 V p-p. For differential input voltage swings greater than 0.4 V p-p, the common-mode range will change. T he minimum value insures that the
input voltage on either encode pin does not go below 0 V. T he maximum value insures that the input voltage on either encode pin does not go below 2.0 V or above AVCC (e.g.,
for a differential input swing of 0.8 V, the min and max common-mode specs become 0.4 V and 2.4 V respectively).
3ENC or
may be driven alone if desired, but performance will likely be degraded. Logic Compatibility specifications are provided to show that T T L or CMOS clock sources
will work. When driving only one encode input, bypass the complementary input to GND with 0.01 µF.
4Digital output load is one LCX gate.
Specifications subject to change without notice.
–2–
REV. 0
AD6640
1
SWITCHING SPECIFICATIONS (AV = +5 V, DV = +3.3 V; ENCODE & ENCODE = 65 MSPS; TMIN = –40؇C, TMAX = +85؇C)
CC
CC
Test
AD 6640AST
Typ
P aram eter (Conditions)
Tem p
Level
Min
Max
Units
Maximum Conversion Rate
Minimum Conversion Rate2
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
ENCODE Pulsewidth High3
ENCODE Pulsewidth Low
Output Delay (tOD) DVCC +3.3 V/5.0 V4
Full
Full
VI
IV
V
65
MSPS
MSPS
ps
ps rms
ns
6.5
+25°C
+25°C
+25°C
+25°C
Full
400
0.3
V
IV
IV
IV
6.5
6.5
8.5
ns
ns
10.5
12.5
NOT ES
1All switching specifications tested by driving ENCODE and ENCODE differentially.
2A plot of Performance vs. Encode is shown in Figure 16 under T ypical Performance Characteristics.
3A plot of Performance vs. Duty Cycle (Encode = 65 MSPS) is shown in Figure 17 under T ypical Performance Characteristics.
4Outputs driving one LCX gate. Delay is measured from differential crossing of ENC,
Specifications subject to change without notice.
to the time when all output data bits are within valid logic levels.
1
(AV = +5 V, DV = +3.3 V; ENCODE & ENCODE = 65 MSPS; TMIN = –40؇C, TMAX = +85؇C)
AC SPECIFICATIONS
CC
CC
Test
Level
AD 6640AST
Typ
P aram eter (Conditions)
Tem p
Min
Max
Units
SNR
Analog Input 2.2 MHz
+25°C
+25°C
+25°C
+25°C
V
I
V
V
68
dB
dB
dB
dB
@ –1 dBFS
15.5 MHz
31.0 MHz
69.0 MHz
64
67.7
67.5
66
SINAD
Analog Input 2.2 MHz
+25°C
+25°C
+25°C
+25°C
V
I
V
V
68
dB
dB
dB
dB
@ –1 dBFS
15.5 MHz
31.0 MHz
69.0 MHz
63.5
74
67.2
67.0
65.5
Worst Harmonic2 (2nd or 3rd)
Analog Input 2.2 MHz
+25°C
+25°C
+25°C
+25°C
V
I
V
V
80
80
79.5
78.5
dBc
dBc
dBc
dBc
@ –1 dBFS
15.5 MHz
31.0 MHz
69.0 MHz
Worst Harmonic2 (4th or Higher)
Analog Input 2.2 MHz
+25°C
+25°C
+25°C
+25°C
V
I
V
V
85
85
85
84
dBc
dBc
dBc
dBc
@ –1 dBFS
15.5 MHz
31.0 MHz
69.0 MHz
74
Multitone SFDR (w/Dither)3
Eight T ones @ –20 dBFS
Full
V
90
dBFS
T wo-T one IMD Rejection4
F1, F2 @ –7 dBFS
Analog Input Bandwidth5
Full
V
V
80
dBc
+25°C
300
MHz
NOT ES
1All ac specifications tested by driving ENCODE and
differentially.
2For a single test tone at –1 dBFS, the worst case spectral performance is typically limited by the direct or aliased 2nd or 3rd harmonic. If a system is designed such
that the 2nd and 3rd harmonics fall out-of-band, overall performance in the band of interest is typically improved by 5 dB. Worst Harmonic (4th or Higher) includes
4th and higher order harmonics and all other spurious components. Reference Figure 12 for more detail.
3See Overcoming Static Nonlinearities with Dither section for details on improving SFDR performance. T o measure SFDR, eight tones from 14 MHz to 18 MHz
(0.5 MHz spacing) are swept from –20 dBFS to –90 dBFS. An open channel at 16 MHz is used to monitor SFDR.
4F1 = 14.9 MHz, F2 = 16 MHz.
5Specification is small signal bandwidth. Plots of Performance versus Analog Input Frequency are shown in Figures 10, 11 and 12. Sampling wide bandwidths
(5 MHz–15 MHz) should be limited to 70 MHz center frequency.
Specifications subject to change without notice.
REV. 0
–3–
AD6640
ABSO LUTE MAXIMUM RATINGS1
EXP LANATIO N O F TEST LEVELS
Test Level
P aram eter
Min
Max Units
I
II
–
–
100% production tested.
ELECT RICAL
100% production tested at +25°C, and sample tested at
specified temperatures. AC testing done on sample
basis.
Sample tested only.
Parameter is guaranteed by design and characterization
testing.
AVCC Voltage
0
0
0
7
7
V
V
V
mA
V
mA
DVCC Voltage
Analog Input Voltage
Analog Input Current
Digital Input Voltage (ENCODE)
Digital Output Current
AVCC
25
AVCC
10
III
IV
–
–
0
–10
V
VI
–
–
Parameter is a typical value only.
All devices are 100% production tested at +25°C; sample
tested at temperature extremes.
ENVIRONMENT AL2
Operating T emperature Range
(Ambient)
–40
+85
°C
Maximum Junction T emperature
Lead T emperature (Soldering, 10 sec)
Storage T emperature Range (Ambient) –65
+150 °C
+300 °C
+150 °C
NOT ES
1Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2T ypical thermal impedances (44-terminal T QFP); θJA = 55°C/W.
O RD ERING GUID E
Model
Tem perature Range
P ackage D escription
P ackage O ption
AD6640AST
AD6640ST /PCB
–40°C to +85°C (Ambient)
44-T erminal T QFP (T hin Quad Plastic Flatpack)
Evaluation Board with AD6640AST
ST -44
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6640 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–4–
AD6640
P IN FUNCTIO N D ESCRIP TIO NS
Function
P in No.
Nam e
1, 2, 36, 37, 40, 41
DVCC
+3.3 V/+5 V Power Supply (Digital). Powers output stage only.
Encode Input. Data conversion initiated on rising edge.
3
4
ENCODE
ENCODE
Complement of ENCODE. Drive differentially with ENCODE or bypass to
Ground for single-ended clock mode. See Encoding the AD6640 section.
5, 6, 13, 14, 17, 18, 21,
22, 24, 34, 35, 38, 39
GND
AIN
Ground.
7
8
9
Analog Input.
Complement of Analog Input.
VREF
Internal Voltage Reference. Nominally +2.4 V. Bypass to Ground with
0.1 µF + 0.01 µF microwave chip capacitor.
10
C1
Internal Bias Point. Bypass to ground with 0.01 µF capacitor.
+5 V Power Supply (Analog).
No Connect.
11, 12, 15, 16, 19, 20
AVCC
23
NC
25
D0 (LSB)
D1–D8
D9–D10
Digital Output Bit (Least Significant Bit).
Digital Output Bits.
26–33
42, 43
44
Digital Output Bits.
(MSB)1
Digital Output Bit (Most Significant Bit).
NOT E
1Output coded as twos complement.
P IN CO NFIGURATIO N
44 43 42 41 40 39 38 37 36 35 34
DV
DV
33
32
31
30
29
28
27
1
2
D8
D7
D6
D5
D4
D3
D2
CC
PIN 1
CC
ENCODE
3
4
ENCODE
GND
5
AD6640
TOP VIEW
(Not to Scale)
GND
6
7
AIN
AIN
26 D1
8
25 D0 (LSB)
24 GND
23 NC
V
9
REF
10
11
C1
AV
CC
13
20
21 22
12
14 15 16 17 18 19
NC = NO CONNECT
REV. 0
–5–
AD6640
D EFINITIO N O F SP ECIFICATIO NS
Analog Bandwidth (Sm all Signal)
T he analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
P ower Supply Rejection Ratio
T he ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-D istor tion (SINAD )
T he ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Aper tur e D elay
T he delay between a differential crossing of ENCODE and
and the instant at which the analog input is sampled.
Signal-to-Noise Ratio (SNR)
Aper tur e Uncer tainty (Jitter )
T he sample-to-sample variation in aperture delay.
T he ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
D iffer ential Nonlinear ity
T he deviation of any code from an ideal 1 LSB step.
Spur ious-Fr ee D ynam ic Range (SFD R)
T he ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. T he peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
Encode P ulsewidth/D uty Cycle
Pulsewidth high is the minimum amount of time that the EN-
CODE pulse should be left in logic “1” state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. At a given clock rate, these
specs define an acceptable Encode duty cycle.
Two-Tone Inter m odulation D istor tion Rejection
T he ratio of the rms value of either input tone to the rms
value of the worst third order intermodulation product; re-
ported in dBc.
Integr al Nonlinear ity
T he deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Two-Tone SFD R
T he ratio of the rms value of either input tone to the rms value
of the peak spurious component. T he peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
Minim um Conver sion Rate
T he encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maxim um Conver sion Rate
T he encode rate at which parametric testing is performed.
Wor st H ar m onic
T he ratio of the rms signal amplitude to the rms value of the
worst harmonic component, reported in dBc.
O utput P r opagation D elay
The delay between a differential crossing of ENCODE and
and the time when all output data bits are within
valid logic levels.
REV. 0
–6–
Equivalent Circuits–AD6640
tA
AIN
N
ANALOG
INPUTS
N + 1
AIN
ENCODE INPUTS
(ENCODE)
DIGITAL OUTPUTS
N – 2
N – 1
N
(D11–D0)
tOD
Figure 1. Tim ing Diagram
V
AV
CH
CC
DV
CC
CURRENT
MIRROR
AIN
T/H
BUF
450⍀
450⍀
V
V
CL
CH
V
BUF
REF
AV
CC
DV
CC
AIN
T/H
BUF
V
REF
D0–D11
V
CL
Figure 2. Analog Input Stage
AV
CC
CURRENT
MIRROR
AV
CC
AV
CC
R1
17k⍀
Figure 5. Digital Output Stage
R1
17k⍀
ENCODE
ENCODE
TIMING
CIRCUITS
R2
8k⍀
R2
8k⍀
AV
CC
AV
CC
2.4V
V
REF
Figure 3. Encode Inputs
0.5mA
AV
CC
Figure 6. 2.4 V Reference
V
REF
AV
CC
AV
CC
CURRENT
MIRROR
C1
Figure 4. Com pensation Pin, C1
REV. 0
–7–
AD6640–Typical Performance Characteristics
0
ENCODE = 65MSPS
AIN = 2.2MHz
ENCODE = 65MSPS
81
80
79
78
77
TEMP = –40 C, +25 C, & +85 C
20
40
60
T = +25 C
2
3
4
5
6
7
8
9
T = –40 C, +85 C
80
100
120
0
7
14
21
28
35
42
49
56
63
70
dc
6.5
13.0
19.5
26.0
32.5
ANALOG INPUT FREQUENCY – MHz
FREQUENCY – MHz
Figure 7. Single Tone at 2.2 MHz
Figure 10. Harm onics vs. AIN
0
ENCODE = 65MSPS
AIN = 15.5MHz
ENCODE = 65MSPS
69
68
67
66
65
TEMP = –40 C, +25 C, & +85 C
20
40
T = –40 C
T = +25 C
60
4
8
9
5
3
7
6
2
T = +85 C
80
100
120
0
7
14
21
28
35
42
49
56
63
70
dc
6.5
13.0
19.5
26.0
32.5
ANALOG INPUT FREQUENCY – MHz
FREQUENCY – MHz
Figure 11. Noise vs. AIN
Figure 8. Single Tone at 15.5 MHz
90
80
70
60
50
40
30
0
20
ENCODE = 65MSPS
WORST OTHER SPUR
HARMONICS (2nd, 3rd)
ENCODE = 65MSPS
AIN = 31.0MHz
40
SNR
60
2
4
6
8
9
7
5
3
80
100
120
1
2
4
10
20
40
100
200 300
dc
6.5
13.0
19.5
26.0
32.5
ANALOG INPUT FREQUENCY – MHz
FREQUENCY – MHz
Figure 9. Single Tone at 31.0 MHz
Figure 12. Harm onics, Noise vs. AIN
REV. 0
–8–
AD6640
85
80
75
70
65
60
0
20
AIN = 19.5MHz
ENCODE = 65MSPS
AIN = 15.0, 16.0MHz
NO DITHER
WORST SPUR
40
60
SNR
80
100
120
dc
8
16
24
32
40
48
56
64
72
80
dc
6.5
13.0
19.5
26.0
32.5
SAMPLE RATE – MSPS
FREQUENCY – MHz
Figure 16. SNR, Worst Spurious vs. Encode
Figure 13. Two Tones at 15.0 MHz & 16.0 MHz
100
90
ENCODE = 65MSPS
AIN = 2.2MHz
85
90
80
70
60
50
40
30
20
10
0
dBFS
80
WORST SPUR
75
70
ENCODE = 65MSPS
AIN = 31.0MHz
SNR
65
60
55
50
45
40
35
30
SFDR = 80dB
REFERENCE LINE
dBc
–80
–70
–60
–50
–40
–30
–20
–10
0
25
30
35
40
45
50
55
60
65
70
75
ANALOG INPUT POWER LEVEL – dBFS
ENCODE DUTY CYCLE – %
Figure 14. Single Tone SFDR
Figure 17. SNR, Worst Spurious vs. Duty Cycle
100
90
80
70
60
50
40
30
20
10
0
90
85
80
75
70
65
60
55
50
45
40
35
30
ENCODE = 65MSPS
69MHz
2.2MHz
WORST SPUR
dBFS
dBc
ENCODE = 65MSPS
F1 = 15.0MHz
F2 = 16.0MHz
2.2MHz
69MHz
SNR
SFDR = 80dB
REFERENCE LINE
–80
–70
–60
–50
–40
–30
–20
–10
0
–15 –12
–9
–6
–3
0
3
6
9
12
15
INPUT POWER LEVEL (F1 = F2) – dBFS
ENCODE POWER – dBm
Figure 15. Two Tone SFDR
Figure 18. SNR, Worst Spurious vs. Encode Power
REV. 0
–9–
AD6640
0
0
ENCODE = 65MSPS
AIN = 19.5MHz @ –36dBFS
NO DITHER
ENCODE = 65MSPS
AIN = 19.5MHz @ –36dBFS
DITHER = –32.5dBm
–20
–20
–40
–40
–60
–60
–80
–80
–100
–100
–120
–120
dc
65
13.0
19.5
26.0
32.5
dc
65
13.0
19.5
26.0
32.5
FREQUENCY – MHz
FREQUENCY – MHz
Figure 19. 16K FFT without Dither
Figure 22. 16K FFT with Dither
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
ENCODE = 65MSPS
AIN = 19.5MHz
NO DITHER
ENCODE = 65MSPS
AIN = 19.5MHz
DITHER = –32.5dBm
SFDR = 80dB
REFERENCE LINE
SFDR = 80dB
REFERENCE LINE
–80
–70
–60
–50
–40
–30
–20
–10
0
–80
–70
–60
–50
–40
–30
–20
–10
0
ANALOG INPUT POWER LEVEL – dBFS
ANALOG INPUT POWER LEVEL – dBFS
Figure 20. SFDR without Dither
Figure 23. SFDR with Dither
0
–20
0
0
–20
0
ENCODE = 50MSPS
AIN = 65.5, 68.5MHz
NO DITHER
ENCODE = 50MSPS
AIN = 65.5MHz, 68.5MHz
DITHER = –32.5dBm
–30
–30
ALIASED
SIGNALS
–40
–40
ALIASED
SIGNALS
–60
–60
ANALOG IF
FILTER MASK
–60
–60
ANALOG IF
FILTER MASK
–80
–80
–90
–90
–100
–120
–100
–120
–120
75
–120
50
55
60
65
70
50
55
60
65
70
75
FREQUENCY – MHz
FREQUENCY – MHz
Figure 21. IF-Sam pling at 70 MHz without Dither
Figure 24. IF-Sam pling at 70 MHz with Dither
REV. 0
–10–
AD6640
TH EO RY O F O P ERATIO N
+5V
R1
ENCODE
SOURCE
T he AD6640 analog-to-digital converter (ADC) employs a two-
stage subrange architecture. T his design approach ensures
12-bit accuracy, without the need for laser trim, at low power.
ENCODE
V
l
ENCODE
RX
R2
0.01F
As shown in the functional block diagram, the AD6640 has
AD6640
complementary analog input pins, AIN and
. Each analog
input is centered at 2.4 volts and should swing ±0.5 volts
Figure 26. Lower Logic Threshold for Encode
around this reference (ref. Figure 2). Since AIN and
180 degrees out of phase, the differential analog input signal is
2 volts peak-to-peak.
are
5R2
Vl =
R1RX
to raise logic threshold.
Both analog inputs are buffered prior to the first track-and-hold,
T H1. T he high state of the ENCODE pulse places T H1 in
hold mode. T he held value of T H1 is applied to the input of a
6-bit coarse ADC. T he digital output of the coarse ADC drives
a 6-bit DAC; the DAC is 12 bits accurate. T he output of the 6-
bit DAC is subtracted from the delayed analog signal at the
input of T H3 to generate a residue signal. T H2 is used as an
analog pipeline to null out the digital delay of the coarse ADC.
R2 +
R1+ RX
AV
CC
RX
+5V
R1
ENCODE
SOURCE
ENCODE
ENCODE
V
l
R2
T he 6-bit coarse ADC word and 7-bit residue word are added
together and corrected in the digital error correction logic to
generate the output word. T he result is a 12-bit parallel digital
CMOS-compatible word, coded as twos complement.
0.01F
AD6640
Figure 27. Raise Logic Threshold for Encode
While the single-ended encode will work well for many applica-
tions, driving the encode differentially will provide increased
performance. Depending on circuit layout and system noise, a
1 dB to 3 dB improvement in SNR can be realized. It is not
recommended that differential T T L logic be used however,
because most TTL families that support complementary outputs
are not delay or slew rate matched. Instead, it is recommended
that the encode signal be ac-coupled into the ENCODE and
pins.
AP P LYING TH E AD 6640
Encoding the AD 6640
Best performance is obtained by driving the encode pins dif-
ferentially. However, the AD6640 is also designed to interface
with T T L and CMOS logic families. T he source used to drive
the ENCODE pin(s) must be clean and free from jitter. Sources
with excessive jitter will limit SNR (reference Equation 1 under
“Noise Floor and SNR”).
T he simplest option is shown below. T he low jitter T T L signal
is coupled with a limiting resistor, typically 100 ohms, to the
primary side of an RF transformer (these transformers are inex-
pensive and readily available; part number in Figure 28 is from
Mini-Circuits). T he secondary side is connected to the EN-
AD6640
TTL OR CMOS
ENCODE
SOURCE
ENCODE
0.01F
CODE and
pins of the converter. Since both encode
inputs are self-biased, no additional components are required.
Figure 25. Single-Ended TTL/CMOS Encode
0.1F
T he AD6640 encode inputs are connected to a differential input
stage (see Figure 3 under EQUIVALENT CIRCUIT S). With
no input signal connected to either ENCODE pin, the voltage
dividers bias the inputs to 1.6 volts. For T T L or CMOS usage,
the encode source should be connected to ENCODE, Pin 3.
should be decoupled using a low inductance or mi-
100⍀
T1–1T
ENCODE
TTL
AD6640
ENCODE
Figure 28. TTL Source – Differential Encode
crowave chip capacitor to ground.
A clean sine wave may be substituted for a T T L clock. In this
case, the matching network is shown below. Select a transformer
ratio to match source and load impedances. T he input impedance
of the AD6640 encode is approximately 11 kΩ differentially.
T herefore “R,” shown in the Figure 29, may be any value that is
convenient for available drive power.
If a logic threshold other than the nominal 1.6 V is required, the
following equations show how to use an external resistor, Rx, to
raise or lower the trip point (see Figure 3; R1 = 17 kΩ, R2 = 8 kΩ).
5R2Rx
Vl =
to lower logic threshold.
R1R2 + R1Rx + R2Rx
REV. 0
–11–
AD6640
T o take full advantage of this high input impedance, a 20:1
transformer would be required. T his is a large ratio and could
result in unsatisfactory performance. In this case, a lower
step-up ratio could be used. For example, if RT were set to
260 ohms, along with a 4:1 transformer, the input would match
to a 50 ohm source with a full-scale drive of +4 dBm (Figure
33). Note that the external load resistor, RT , is in parallel with
the AD6640 analog input resistance of 900 ohms. T he external
resistor value can be calculated from the following equation:
T1–1T
SINE
SOURCE
ENCODE
AD6640
R
ENCODE
Figure 29. Sine Source – Differential Encode
If a low jitter ECL clock is available, another option is to ac-
couple a differential ECL signal to the encode input pins as
shown below. T he capacitors shown here should be chip ca-
pacitors but do not need to be of the low inductance variety.
1
RT =
1
1
–
Z
900
0.1F
ENCODE
where Z is the desired impedance (200 Ω for a 4:1 transformer
with 50 Ω input source).
ECL
GATE
AD6640
0.1F
ENCODE
510⍀
510⍀
1:4
AIN
ANALOG
INPUT
SIGNAL
R
T
AD6640
–V
S
AIN
Figure 30. Differential ECL for Encode
V
REF
As a final alternative, the ECL gate may be replaced by an ECL
comparator. T he input to the comparator could then be a logic
signal or a sine signal.
0.1F
0.01F
Figure 33. Transform er-Coupled Analog Input Signal
AD96687 (1/2)
0.1F
If the lower drive power is attractive, a combination transformer
match and LC match could be employed that would use a 4:1
transformer with an LC as shown in Figure 34. T his solution is
useful when good performance in the third Nyquist zone is
required. Such a requirement arises when digitizing high inter-
mediate frequencies in communications receivers.
ENCODE
AD6640
0.1F
50⍀
ENCODE
510⍀
510⍀
–V
S
ANALOG
+j100⍀
1:4
Figure 31. ECL Com parator for Encode
D r iving the Analog Input
SIGNAL
AIN
AT
–3dBm
–j125⍀
AD6640
Because the AD6640 operates from a single +5 volt supply, the
analog input voltage range is offset from ground by 2.4 volt.
Each analog input connects through a 450 ohm resistor to the
2.4 volt bias voltage and to the input of a differential buffer
(Figure 32). T his resistor network on the input properly biases
the followers for maximum linearity and range. T herefore, the
analog source driving the AD6640 should be ac-coupled to the
input pins. Since the differential input impedance of the AD6640
is 0.9 kΩ, the analog input power requirement is only –3 dBm,
simplifying the drive amplifier in many cases.
AIN
V
REF
0.1F
0.01F
Figure 34. Low Power Drive Circuit
In applications where gain is needed but dc-coupling is not
necessary, an extension of Figure 34 is recommended. A
50 ohm gain block may be placed in front of the LC matching
network. Such gain blocks are readily available for commercial
applications. These low cost modules can have excellent NF and
intermodulation performance. T his circuit is especially good for
the “IF” receiver application previously mentioned.
BUF
AIN
AD6640
450⍀
BUF
450⍀
In applications where dc-coupling is required the following
circuit can be used (Figure 35). It should be noted that the
addition of circuitry for dc-coupling may compromise performance
in terms of noise, offset and dynamic performance. T his circuit
requires an inverting and noninverting signal path. Additionally,
an offset must be generated so that the analog input to each pin
is centered near 2.4 volts. Since the input is differential, small
differences in the dc voltage at each input can translate into an
offset for the circuit. T he same holds true for gain mismatch.
T herefore, some means of adjusting the gain and offset between
BUF
AIN
V
REF
+2.4V
REFERENCE
0.1F
0.01F
Figure 32. Differential Analog Inputs
REV. 0
–12–
AD6640
the device. A full-scale transition can cause up to 120 mA
(12 bits × 10 mA/bit) of current to flow through the digital
output stages. T he series resistor will minimize the output
currents that can flow in the output stage. T hese switching
currents are confined between ground and the DVCC pin. Stan-
dard T T L gates should be avoided since they can appreciably
add to the dynamic switching currents of the AD6640.
the sides should be implemented. The addition of small value
resistors between the AD9631 and the AD6640 will prevent
oscillation due to the capacitive input of the ADC.
AD9631
62⍀
SIGNAL
15⍀
SOURCE
AIN
467⍀
78⍀
350⍀
AD6640
Layout Infor m ation
1000⍀
T he schematic of the evaluation board (Figure 36) represents a
typical implementation of the AD6640. T he pinout of the
AD6640 facilitates ease of use and the implementation of high
frequency/high resolution design practices. All of the digital
outputs are on one side while the other sides contain all of the
inputs. It is highly recommended that high quality ceramic chip
capacitors be used to decouple each supply pin to ground di-
rectly at the device. Depending on the configuration used for
the encode and analog inputs, one or more capacitors are required
on those input pins. The capacitors used on the ENCODE and
VREF pins must be a low inductance chip capacitor as referenced
previously in the data sheet.
OP279
(1/2)
OP279
(1/2)
V
750⍀
425⍀
REF
0.1F
0.01F
0.1F
350⍀
467⍀
350⍀
15⍀
AIN
127⍀
AD9631
Figure 35. DC-Coupled Analog Input Circuit
A multilayer board is recommended to achieve best results. Care
should be taken when placing the digital output runs. Because
the digital outputs have such a high slew rate, the capacitive
loading on the digital outputs should be minimized. Circuit
traces for the digital outputs should be kept short and connect
directly to the receiving gate (broken only by the insertion of the
series resistor). Digital data lines should be kept clear of analog
and encode traces.
P ower Supplies
Care should be taken when selecting a power source. Linear
supplies are strongly recommended as switching supplies tend to
have radiated components that may be “received” by the
AD6640. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 µF chip capacitors.
T he AD6640 has separate digital and analog +5 V pins. T he
analog supplies are denoted AVCC and the digital supply pins
are denoted DVCC. Although analog and digital supplies may be
tied together, best performance is achieved when the supplies
are separate. T his is because the fast digital output swings can
couple switching noise back into the analog supplies. Note that
AVCC must be held within 5% of 5 volts; however the DVCC
supply may be varied according to output digital logic family
(i.e., DVCC should be connected to the same supply as the digi-
tal circuitry). T he AD6640 is specified for DVCC = 3.3 V as this
is a common supply for digital ASICs.
Evaluation Boar ds
T he evaluation board for the AD6640 is very straightforward,
consisting of power, signal inputs and digital outputs. T he
evaluation board includes the option for an onboard clock oscil-
lator for the encode.
Power to the analog supply pins is connected via banana jacks.
T he analog supply powers the crystal oscillator and the AVCC
pins of the AD6640.
T he DVCC power is supplied via J3, the digital interface. T his
digital supply connection also powers the digital gates on the
PCB. By maintaining separate analog and digital power supplies,
degradation in SNR and SFDR is kept to a minimum. T otal
power requirement is approximately 200 mA. This configuration
allows for easy evaluation of different logic families (i.e., con-
nection to a 3.3 volt logic board).
O utput Loading
Care must be taken when designing the data receivers for the
AD6640. It is recommended that the digital outputs drive a
series resistor (e.g. 348 ohms) followed by a gate like the
74LCX574. T o minimize capacitive loading, there should only
be one gate on each output pin. An example of this is shown in
the evaluation board schematic shown in Figure 36. T he digital
outputs of the AD6640 have a constant rise time output stage.
T he output slew rate is about 1 V/ns when DVCC = +5 V. A
typical CMOS gate combined with PCB trace and through hole
will have a load of approximately 10 pF. T herefore as each bit
switches, 10 mA
T he analog input is connected via J2 and is transformer-coupled
to the AD6640 (see Driving the Analog Input). T he onboard
termination resistor is 270 Ω. T his resistor, in parallel with the
AD6640’s input resistance (900 Ω), provides a 50 Ω load to the
analog source driving the 1:4 transformer. If a different input
impedance is required, replace R16 by using the following
equation
1V
1ns
1
10 pF ×
R16 =
of dynamic current per bit will flow in or out of
1
1
−
Z
900
where Z is desired input impedance (200 Ω for a 4:1 trans-
former with 50 Ω source).
REV. 0
–13–
AD6640
T he analog input range of the PCB is ±0.5 volts (i.e., signal ac-
coupled to AD6640).
AD6640 output data is latched using 74LCX574 (U3, U4)
latches following 348 ohm series resistors. T he resistors limit
the current that would otherwise flow due to the digital output
slew rate. T he resistor value was chosen to represent a time
constant of ~25% of the data rate at 65 MHz. T his reduces slew
rate while not appreciably distorting the data waveform. Data is
latched in a pipeline configuration; a rising edge generates the
new AD6640 data sample, latches the previous data at the con-
verter output, and strobes the external data register over J3.
T he encode signal may be generated using an onboard crystal
oscillator, U1. T he oscillator is socketed and may be replaced
by an external encode source via J1. If an external source is
used, it should be a high quality T T L source. A transformer
converts the single-ended T T L signal to a differential clock (see
Encoding the AD6640). Since the encode is coupled with a
transformer, a sine wave could have been used; note, however,
that U5 requires T T L levels to function properly.
NOT E: Power and ground must be applied to J3 to power the
digital logic section of the evaluation board.
Table I. AD 6640ST/P CB Bill of Material
Item
Quantity
Reference
D escription
1
2
+5 VA, GND
Banana Jack
2
3
11
2
C7–C9, C11–C17, C19
C4, C6
Ceramic Chip Capacitor 0805, 0.1 µF
T antalum Chip Capacitor 10 µF
4
5
1
3
J3
40-Pin Double Row Male Header
BNC Coaxial PCB Connector
J1, J2, J4
6
7
8
9
10
11
12
13
14
15
16
17
1
25
1
1
2
1
1
2
1
R1
Surface Mount Resistor 1206, 348 Ω
Surface Mount Resistor 1206, 348 Ω
Surface Mount Resistor 1206, 100 Ω
Surface Mount Resistor 1206, 270 Ω
Surface Mount T ransformer Mini-Circuits T 4–1T , 1:4 Ratio
Clock Oscillator (Optional)
AD6640AST 12-Bit–65 MSPS ADC Converter
74LCX574 Octal Latch
74LVQ00 Quad T wo Input NAND Gate
Ceramic Chip Capacitor 0508, 0.01 µF Low Inductance
Ceramic Chip Capacitor 0508, 0.1 µF Low Inductance
1N2810 Schottky Diode
R2–R14, R20–R25, R30–R35
R15
R16
T 1, T 2
U1
DUT
U3, U4
U5
C1, C18
C2, C3
CR1, CR2
1
2
2
REV. 0
–14–
AD6640
348⍀
348⍀
+5VA
74LCX574
(DV
U5
)
CC
74LVQ00
348⍀
9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
(+5VA)
B06
8D
7D
6D
5D
4D
3D
2D
1D
8Q
1
2
4
348⍀
3
6
BUFLAT
B07
7Q
6Q
5Q
4Q
5
348⍀
B08
348⍀
348⍀
0.1F
B09
348⍀
348⍀
J4
B10
348⍀
348⍀
3Q
2Q
1Q
B11
348⍀
E1
DV
CC
ENCODE
INPUT
348⍀
DVCC (+3.3V OR +5.0V)
CK
OE
42
44 43
41 40 39 38 37 36 35 34
J3
1
2
3
4
5
40
39
38
37
36
35
34
33
32
E2
GND
GND
GND
GND
GND
GND
GND
GND
11
1
J1
348⍀
DV
B11
B10
B09
B08
B07
B06
CC
100⍀
T4–1T
4
1
2
33
32
31
30
29
28
27
26
25
24
23
DV
CC
D8
D7
D6
D5
D4
D3
D2
D1
DV
CC
3
6
7
8
9
DV
CC
TWO COMPLEMENT
BUFFERED OUTPUTS
2
1
3
ENCODE
6
B05
B04
4
ENCODE
GND
GND
GND
1:4
10
11
12
13
14
31
30
29
28
27
5
ANALOG
INPUT
BUFLAT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DUT
AD6640
T4–1T
4
6
GND
AIN
B03
B02
3
7
J2
270⍀
2
1
B01
B00
8
AIN
15
16
17
18
26
25
24
23
6
9
V
(LSB) D0
GND
GND
GND
GND
GND
REF
1:4
10
11
C1
GND
NC
348⍀
348⍀
AV
CC
19
20
22
21
U4
74LCX574
(DV
0.01F
0.1F
0.01F
)
CC
0.1F
348⍀
12 348⍀
9
12
14 15 16 17 18 19
21 22
20
13
B00
8D
8Q
7Q
6Q
5Q
4Q
348⍀
348⍀
8
7
6
5
4
3
2
13
B01
B02
B03
B04
B05
7D
6D
5D
4D
3D
2D
1D
+5VA
348⍀
348⍀
14
GND
COMMON
NC = NO CONNECT
15 348⍀
16 348⍀
+5V ANALOG
SUPPLY
+5VA
348⍀
17
18
19
348⍀
3Q
2Q
1Q
OE
DV
CC
+
+
C6
10F
C7
C8
C11
0.1F
C12
0.1F
C13
C15
CK
C16
0.1F
0.1F
0.1F
0.1F
11
1
+5VA
C4
C9
C17
10F
0.1F
0.1F
0.1F
Figure 36. AD6640ST/PCB Schem atic
REV. 0
–15–
AD6640
Figure 37. AD6640ST/PCB Top Side Silkscreen
Figure 39. AD6640ST/PCB Top Side Copper
Figure 38. AD6640ST/PCB Bottom Side Silkscreen
Figure 40. AD6640ST/PCB Bottom Side Copper (Positive)
NOT E: Evaluation boards are often updated, consult factory for latest version.
REV. 0
–16–
AD6640
Figure 41. AD6640ST/PCB Ground Layer (Negative)
Figure 42. AD6640ST/PCB “Split” Power Layer (Negative)
REV. 0
–17–
AD6640
is used for demodulation, different routines may be used to
demodulate different standards such as AM, FM, GMSK or any
other desired standard. In addition, as new standards arise or
new software revisions are generated, they may be field installed
with standard software update channels. A radio that performs
demodulation in software as opposed to hardware is often
referred to as a soft radio because it may be changed or modified
simply through code revision.
D IGITAL WID EBAND RECEIVERS
Intr oduction
Several key technologies are now being introduced that may
forever alter the vision of radio. Figure 43 shows the typical
dual conversion superheterodyne receiver. T he signal picked up
by the antenna is mixed down to an intermediate frequency (IF)
using a mixer with a variable local oscillator (LO); the variable
LO is used to “tune-in” the desired signal. T his first IF is
mixed down to a second IF using another mixer stage and a
fixed LO. Demodulation takes place at the second or third IF
using either analog or digital techniques.
System D escr iption
In the wideband digital radio (Figure 44), the first down conver-
sion functions in much the same way as a block converter does.
An entire band is shifted in frequency to the desired interme-
diate frequency. In the case of cellular base station receivers,
5 MHz to 30 MHz of bandwidth are down-converted simulta-
neously to an IF frequency suitable for digitizing with a wide-
band analog-to-digital converter. Once digitized the broadband
digital data stream contains all of the in-band signals. T he
remainder of the radio is constructed digitally using special
purpose and general purpose programmable DSP to perform
filtering, demodulation and signal conditioning not unlike the
analog counter parts.
ADCs
NARROWBAND
FILTER
NARROWBAND
FILTER
LNA
I
Q
IF
IF
2
1
RF
e.g.
900MHz
FIXED
ONE RECEIVER PER CHANNEL
VARIABLE
SHARED
Figure 43. Narrowband Digital Receiver Architecture
If demodulation takes place in the analog domain then tradi-
tional discriminators, envelop detectors, phase locked loops or
other synchronous detectors are generally employed to strip the
modulation from the selected carrier.
In the narrowband receiver (Figure 43), the signal to be received
must be tuned. T his is accomplished by using a variable local
oscillator at the first mix down stage. T he first IF then uses a
narrow band filter to reject out of band signals and condition
the selected carrier for signal demodulation.
However, as general purpose DSP chips such as the ADSP-2181
become more popular, they will be used in many baseband-
sampled applications like the one shown in Figure 43. As
shown in the figure, prior to ADC conversion, the signal must
be mixed down, filtered, and the I and Q components separated.
T hese functions are realizable through DSP techniques, how-
ever several key technology breakthroughs are required: high
dynamic range ADCs such as the AD6640, new DSPs (highly
programmable with onboard memory, fast), digital tuners and
filters such as the AD6620, wide band mixers and amplifiers.
In the digital wideband receiver (Figure 44), the variable local
oscillator has been replaced with a fixed oscillator, so tuning
must be accomplished in another manner. T uning is performed
digitally using a digital down conversion and filter chip fre-
quently called a channelizer. T he term channelizer is used
because the purpose of these chips is to select one channel out
of many within the broadband spectrum present in the digital
data stream of the ADC.
DECIMATION
FILTER
LOW-PASS
FILTER
I
COS
DIGITAL
DIGITAL TUNER/FILTER
WIDEBAND
DSP
ADC
WIDEBAND
FILTER
DATA
WIDEBAND
MIXER
TUNER
LNA
SIN
"n" CHANNELS
TO DSP
DECIMATION
FILTER
LOW-PASS
FILTER
Q
RF
e.g. 900MHz
12.5MHz
(416 CHANNELS)
DIGITAL TUNER/FILTER
DSP
Figure 45. AD6620 Digital Channelizer
FIXED
Figure 45 shows the block diagram of a typical channelizer, such
as the AD6620. Channelizers consist of a complex NCO (Nu-
merically Controlled Oscillator), dual multiplier (mixer), and
matched digital filters. T hese are the same functions that would
be required in an analog receiver, however implemented in
digital form. T he digital output from the channelizer is the
desired carrier, frequently in I & Q format; all other signals have
been filtered and removed based on the filtering characteristics
desired. Since the channelizer output consists of one selected
RF channel, one tuner chip is required for each frequency re-
ceived, although only one wideband RF receiver is needed for
the entire band. Data from the channelizer may then be pro-
cessed using a digital signal processor such as the ADSP-2181
or the SHARC® processor, the ADSP-21062. T his data may
then be processed through software to demodulate the informa-
tion from the carrier.
SHARED
CHANNEL SELECTION
Figure 44. Wideband Digital Receiver Architecture
Figure 44 shows such a wideband system. T his design shows
that the front end variable local oscillator has been replaced with
a fixed oscillator and the back end has been replaced with a
wide dynamic range ADC, digital tuner and DSP. T his tech-
nique offers many benefits.
First, many passive discrete components have been eliminated
that formed the tuning and filtering functions. T hese passive
components often require “tweaking” and special handling
during assembly and final system alignment. Digital compo-
nents require no such adjustments; tuner and filter characteristics
are always exactly the same. Moreover, the tuning and filtering
characteristics can be changed through software. Since software
SHARC is a registered trademark of Analog Devices, Inc.
REV. 0
–18–
AD6640
AD6620
(REF. FIG 45)
+5V (A)
+3.3V (D)
CMOS
BUFFER
ADSP-2181
PRESELECT
FILTER
5–15MHz
PASSBAND
LNA
348⍀
D11
AIN
AIN
I & Q
DATA
LO
DRIVE
NETWORK
CONTROLLER
INTERFACE
12
AD6640
1900MHz
ENCODE
M/N PLL
SYNTHESIZER
REF
IN
ENCODE
D0
CLK
65.00MHz
REFERENCE
CLOCK
Figure 46. Sim plified Wideband PCS Receiver
System Requir em ents
power dissipation is not a function of sample rate. T hus there is
no penalty paid in power by operating at faster sample rates. All
of this is good because, by carefully selecting input frequency
range and sample rate, some of the drive amplifier and ADC
harmonics can actually be placed out-of-band.
Figure 46 shows a typical wideband receiver subsystem based
around the AD6640. T his strip consists of a wideband IF filter,
amplifier, ADC, latches, channelizer and interface to a digital
signal processor. T his design shows a typical clocking scheme
used in many receiver designs. All timing within the system is
referenced back to a single clock. While this is not necessary, it
does facilitate PLL design, ease of manufacturing, system test,
and calibration. Keeping in mind that the overall performance
goal is to maintain the best possible dynamic range, many con-
siderations must be made.
For example, if the system has second and third harmonics that
are unacceptably high, by carefully selecting the encode rate and
signal bandwidth, these second and third harmonics can be
placed out-of-band. For the case of an encode rate equal to
60 MSPS and a signal bandwidth of 7.5 MHz, placing the fun-
damental at 7.5 MHz places the second and third harmonics out
of band as shown in the table below.
One of the biggest challenges is selecting the amplifier used to
drive the AD6640. Since this is a communications application,
it is common to directly sample an intermediate frequency (IF)
signal. As such, IF gain blocks can be implemented instead of
baseband op amps. For these gain block amplifiers, the critical
specifications are third order intercept point and noise figure. A
bandpass filter will remove harmonics generated within the
amplifier, but intermods should be better than the performance
of the A/D converter. In the case of the AD6640, amplifier
intermods must be better than –80 dBFS when driving full-
scale power. As mentioned earlier, there are several amplifiers
to choose from and the specifications depend on the end
application. Figure 47 shows a typical multitone test.
Table II.
Encode Rate
60 MSPS
Fundamental
7.5 MHz–15 MHz
Second Harmonic
T hird Harmonic
15 MHz–30 MHz
22.5 MHz–30 MHz, 30 MHz–15 MHz
Another option can be found through bandpass sampling. If the
analog input signal range is from dc to FS/2, then the amplifier
and filter combination must perform to the specification re-
quired. However, if the signal is placed in the third Nyquist
zone (FS to 3 FS/2), the amplifier is no longer required to meet
the harmonic performance required by the system specifications
since all harmonics would fall outside the passband filter. For
example, the passband filter would range from FS to 3 FS/2.
T he second harmonic would span from 2 FS to 3 FS, well out-
side the passband filter’s range. The burden then has been passed
off to the filter design provided that the ADC meets the basic
specifications at the frequency of interest. In many applications,
this is a worthwhile tradeoff since many complex filters can
easily be realized using SAW and LCR techniques alike at these
relatively high IF frequencies. Although harmonic performance
of the drive amplifier is relaxed by this technique, intermodula-
tion performance cannot be sacrificed since intermods must be
assumed to fall in-band for both amplifiers and converters.
0
–20
ENCODE = 65MSPS
–40
–60
–80
–100
–120
dc
6.5
13.0
19.5
26.0
32.5
Noise Floor and SNR
FREQUENCY – MHz
Oversampling is sampling at a rate that is greater than twice the
bandwidth of the signal desired. Oversampling does not have
anything to do with the actual frequency of the sampled sig-
nal, it is the bandwidth of the signal that is key. Bandpass or
“IF” sampling refers to sampling a frequency that is higher than
Nyquist and often provides additional benefits such as down
conversion using the ADC and replacing a mixer with a track-
and-hold. Oversampling leads to processing gains because the
Figure 47. Multitone Perform ance
T wo other key considerations for the digital wideband receiver
are converter sample rate and IF frequency range. Since per-
formance of the AD6640 converter is largely independent of
both sample rate and analog input frequency (Figures 10, 11
and 16), the designer has greater flexibility in the selection of
these parameters. Also, since the AD6640 is a bipolar device,
REV. 0
–19–
AD6640
faster the signal is digitized, the wider the distribution of noise.
Since the integrated noise must remain constant, the actual
noise floor is lowered by 3 dB each time the sample rate is
doubled. T he effective noise density for an ADC may be calcu-
lated by the equation:
O ver com ing Static Nonlinear ities with D ither
T ypically, high resolution data converters use multistage
techniques to achieve high bit resolution without large com-
parator arrays that would be required if traditional “flash” ADC
techniques were employed. T he multistage converter typically
provides better wafer yields meaning lower cost and much lower
power. However, since it is a multistage device, certain portions
of the circuit are used repetitively as the analog input sweeps
from one end of the converter range to the other. Although the
worst DNL error may be less than an LSB, the repetitive nature
of the transfer function can play havoc with low level dynamic
signals. Spurious signals for a full-scale input may be –80 dBc.
However at 36 dB below full scale, these repetitive DNL errors
may cause spurious-free dynamic range (SFDR) to fall below
80 dBFS as shown in Figure 20.
10−SNR /20
VNOISE rms
/ Hz =
4 FS
For a typical SNR of 68 dB and a sample rate of 65 MSPS, this
is equivalent to 25 nV/√ . T his equation shows the relation-
ship between SNR of the converter and the sample rate FS.
T his equation may be used for computational purposes to deter-
mine overall receiver noise.
T he signal-to-noise ratio (SNR) for an ADC can be predicted.
When normalized to ADC codes, the following equation accu-
rately predicts the SNR based on three terms. T hese are jitter,
average DNL error and thermal noise. Each of these terms
contributes to the noise within the converter.
A common technique for randomizing and reducing the effects
of repetitive static linearity is through the use of dither. T he
purpose of dither is to force the repetitive nature of static linear-
ity to appear as if it were random. T hen, the average linearity
over the range of dither will dominate SFDR performance. In
the AD6640, the repetitive cycle is every 15.625 mV p-p.
Equation 1:
1/2
2
2
V
2
1+ ε
212
T o ensure adequate randomization, 5.3 mV rms is required;
this equates to a total dither power of –32.5 dBm. T his will
randomize the DNL errors over the complete range of the
residue converter. Although lower levels of dither such as that
from previous analog stages will reduce some of the linearity
errors, the full effect will only be gained with this larger dither.
Increasing dither even more may be used to reduce some of the
global INL errors. However, signals much larger than the mVs
proposed here begin to reduce the usable dynamic range of the
converter.
NOISE rms
212
SNR = –20 log 2 πF
t
+
+
(
)
J rms
ANALOG
FANALOG = analog input frequency
t J
= rms jitter of the encode (rms sum of encode source
and internal encode circuitry)
rms
ε
= average DNL of the ADC (typically 0.51 LSB)
VNOISE rms = V rms thermal noise referred to the analog input of
the ADC (typically 0.707 LSB)
P r ocessing Gain
Even with the 5.3 mV rms of noise suggested, SNR would be
limited to 36 dB if injected as broadband noise. T o avoid this
problem, noise may be injected as an out-of-band signal. Typically,
this may be around dc but may just as well be at FS/2 or at
some other frequency not used by the receiver. T he bandwidth
of the noise is several hundred kilohertz. By band-limiting and
controlling its location in frequency, large levels of dither may
be introduced into the receiver without seriously disrupting
receiver performance. T he result can be a marked improvement
in the SFDR of the data converter.
Processing gain is the improvement in signal-to-noise ratio
(SNR) gained through oversampling and digital filtering. Most
of this processing gain is accomplished using the channelizer
chips. T hese special purpose DSP chips not only provide chan-
nel selection and filtering but also provide a data rate reduction.
T he required rate reduction is accomplished through a process
called decimation. T he term decimation rate is used to indicate
the ratio of input data rate to output data rate. For example, if
the input data rate is 65 MSPS and the output data rate is
1.25 MSPS, then the decimation rate is 52.
Figure 23 shows the same converter shown earlier but with this
injection of dither (reference Figure 20).
Large processing gains may be achieved in the decimation and
filtering process. T he purpose of the channelizer, beyond tun-
ing, is to provide the narrowband filtering and selectivity that
traditionally has been provided by the ceramic or crystal filters
of a narrowband receiver. T his narrowband filtering is the
source of the processing gain associated with a wideband re-
ceiver and is simply the ratio of the passband to whole band
expressed in dB. For example, if a 30 kHz AMPS signal is
being digitized with an AD6640 sampling at 65 MSPS, the ratio
would be 0.015 MHz/32.5 MHz. Expressed in log form, the
processing gain is –10 × log (0.015 MHz/32.5 MHz) or 33.4 dB.
+15V
16k⍀
LOW CONTROL
(0–1 VOLT)
1F
A
NC202
NOISE
2.2k⍀
DIODE
(NoiseCom)
+5V
REF
2k⍀
–5V
1k⍀
A
OP27
Additional filtering and noise reduction techniques can be
achieved through DSP techniques; many applications do use
additional process gains through proprietary noise reduction
algorithms.
0.1F
AD600
OPTIONAL HIGH
POWER DRIVE
CIRCUIT
39⍀
390⍀
Figure 48. Noise Source (Dither Generator)
REV. 0
–20–
AD6640
T he simplest method for generating dither is through the use of
a noise diode (Figure 48). In this circuit, the noise diode NC202
generates the reference noise that is gained up and driven by the
AD600 and OP27 amplifier chain. T he level of noise may be
controlled by either presetting the control voltage when the
system is set up, or by using a digital-to-analog converter (DAC)
to adjust the noise level based on input signal conditions. Once
generated, the signal must be introduced to the receiver strip.
T he easiest method is to inject the signal into the drive chain
after the last down conversion as shown in Figure 49.
T he first noise calculation to make is based on the signal band-
width at the antenna. In a typical broadband cellular receiver,
the IF bandwidth is 12.5 MHz. Given that the power of noise in
a given bandwidth is defined by Pn = kTB, where B is band-
width, k = 1.38 × 10–23 is Boltzman’s constant and T = 300k
is absolute temperature, this gives an input noise power of
5.18 × 10–14 watts or –102.86 dBm. If our receiver front end has
a gain of 30 dB and a noise figure of 10 dB, then the total noise
presented to the ADC input becomes –62.86 dBm (–102.86 + 30
+ 10) or 0.16 mV rms. Comparing receiver noise to dither re-
quired for good SFDR, we see that in this example, our receiver
supplies about 3% of the dither required for good SFDR.
BPF
IF AMP
FROM
RF/IF
Based on a typical ADC SNR specification of 68 dB, the
equivalent internal converter noise is 0.140 mV rms. T here-
fore total broadband noise is 0.21 mV rms. Before process-
ing gain, this is an equivalent SNR (with respect to full scale)
of 64.5 dB. Assuming a 30 kH z AMPS signal and a sample
rate of 61.44 MSPS, the SNR through processing gain is in-
creased by approximately 33 dB to 97.5 dB. However, if eight
strong and equal signals are present in the ADC bandwidth,
then each must be placed 18 dB below full scale to prevent
ADC overdrive. T herefore we give away 18 dB of range and
reduce the carrier-to-noise ratio (C/N) to 79.5 dB.
AIN
COMBINER
AIN
LPF
NOISE SOURCE
AD6640
(REF. FIGURE 48)
V
REF
0.1F
0.01F
Assuming that the C/N ratio must be 10 dB or better for
accurate demodulation, one of the eight signals may be reduced by
66.5 dB before demodulation becomes unreliable. At this point,
the input signal power would be –90.5 dBm. Referenced to the
antenna, this is –120.5 dBm.
Figure 49. Using the AD6640 with Dither
Receiver Exam ple
T o determine how the ADC performance relates to overall re-
ceiver sensitivity, the simple receiver in Figure 50 will be exam-
ined. T his example assumes that the overall down conversion
process can be grouped into one set of specifications, instead of
individually examining all components within the system and
summing them together. Although a more detailed analysis
should be employed in a real design, this model will provide a
good approximation.
T o improve sensitivity, several things can be done. First, the
noise figure of the receiver can be reduced. Since front end
noise dominates the 0.16 mV rms, each dB reduction in noise
figure translates to an additional dB of sensitivity. Second, pro-
viding broadband AGC can improve sensitivity by the range of
the AGC. However, the AGC would only provide useful im-
provements if all in-band signals are kept to an absolute minimal
power level so that AGC can be kept near the maximum gain.
In examining a wideband digital receiver, several considerations
must be applied. Although other specifications are important,
receiver sensitivity determines the absolute limits of a radio
excluding the effects of other outside influences. Assuming that
receiver sensitivity is limited by noise and not adjacent signal
strength, several sources of noise can be identified and their
overall contribution to receiver sensitivity calculated.
T his noise limited example does not adequately demonstrate the
true limitations in a wideband receiver. Other limitations such
as SFDR are more restrictive than SNR and noise. Assume that
the analog-to-digital converter has an SFDR specification of
–80 dBFS or –76 dBm (Full scale = +4 dBm). Also assume
that a tolerable carrier-to-interferer (C/I) (different from C/N)
ratio is 18 dB. T his means that the minimum signal level is
–62 dBFS (–80 plus 18) or –58 dBm. At the antenna, this is
–88 dBm. T herefore, as can be seen, SFDR (single or multi-
tone) would limit receiver performance in this example. How-
ever, as shown previously, SFDR can be greatly improved
through the use of dither (Figures 19, 22). In many cases, the
addition of the out-of-band dither can improve receiver sensitiv-
ity nearly to that limited by thermal noise.
GAIN = 30dB
NF = 10dB
BW =12.5MHz
SINGLE CHANNEL
BW = 30kHz
RF/IF
AD6640
ENC
CHANNELIZER
DSP
REF IN
61.44MHz
Figure 50. Receiver Analysis
REV. 0
–21–
AD6640
Figures 21 and 24 in T ypical Performance Characteristics illus-
trate a multicarrier, IF Sampling System. By using dither, all
spurious components are forced below 90 dBFS (Figure 24).
T he dashed line illustrates how a 5 MHz bandpass filter could
be centered at 67.5 MHz. As discussed earlier, this approach
greatly reduces the size and complexity of the receiver’s RF/IF
section.
IF Sam pling, Using the AD 6640 as a Mix-D own Stage
Since performance of the AD6640 extends beyond the baseband
region into the third Nyquist zone, the converter has many uses
as a mix-down converter in both narrowband and wideband
applications. T his application is called bandpass sampling. Do-
ing this has several positive implications in terms of the selection
of the IF drive amplifier. Not only is filtering a bit easier, the
selection of drive amplifiers is extended to classical IF gain
blocks. In the third Nyquist zone and above, the second and
third harmonics are easily filtered with a bandpass filter. Now
only in-band spurs that result from third order products are
important.
0
ALIASED
SIGNALS
20
ALIASED
3RD HARMONIC
In narrowband applications, harmonics of the ADC can be
placed out-of-band. One example is the digitization of a
201 MHz IF signal using a 17.333 MH z clock. As shown in
Figure 51, the spurious performance has diminished due to
internal slew rate limitations of the ADC. However, the SNR of
the converter is still quite good. Subsequent digital filtering with
a channelizer chip such as the AD6620 will yield even better SNR.
40
60
ANALOG IF
FILTER MASK
ALIASED
2ND HARMONIC
80
For multicarrier applications, third order intercept of the drive
amplifier is important. If the input network is matched to the
internal 900 ohm input impedance, the required full-scale drive
level is –3 dBm. If spurious products delivered to the ADC are
required to be below –90 dBFS, the typical performance of the
ADC with dither applied, then the required third order intercept
point for the drive amplifier can be calculated.
100
198
199.8
201.6
FREQUENCY – MHz
203.4
205.2
207
Figure 51. IF-Sam pling a 201 MHz Input
RECEIVE CH AIN FO R A P H ASED ARRAY CELLULAR
BASE STATIO N
T he AD6640 is an excellent digitizer for beam forming in
phased array antenna systems. T he price performance of the
AD6640 followed by AD6620 channelizers allows for a very
competitive solution. Phase array base stations allow better
coverage by focusing the receivers’ sensitivity in the direction
needed. Phased array systems allow for the electronic beam to
form on the receive antennas.
For multicarrier applications, the AD6640 is useful up to about
80 MHz analog in. For single channel applications, the AD6640
is useful to 200 MHz as shown from the bandwidth charts. In
either case, many common IF frequencies exist in this range of
frequencies. If the ADC is used to sample these signals, they will
be aliased down to baseband during the sampling process in
much the same manner that a mixer will down-convert a signal.
For signals in various Nyquist zones, the following equations
may be used to determine the final frequency after aliasing.
A typical phased array system may have eight antennas as shown
in Figure 52. Since a typical base station will handle 32 calls,
each antenna would have to be connected to 32 receivers. If
done with analog or traditional radios, the system grows quite
rapidly. With a multicarrier receiver, however, the design is
quite compact. Each antenna will have a wideband down-
converter with one AD6640 per receiver. T he output of each
AD6640 would drive 32 AD6620 channelizers, which are phase
locked in groups of eight—one per antenna. T his allows each
group of eight AD6620’s to tune and lock onto a different user.
When the incoming signal direction is determined, the relative
phase of each AD6620 in the group can be adjusted such the
output signals sum together in a constructive manner, giving
high gain and directivity in the direction of the caller. T his ap-
plication would not be possible with traditional receiver designs.
f1NYQUISTS = fSAMPLE − fSIGNAL
f2NYQUISTS = abs ( fSAMPLE − fSIGNAL
f3NYQUISTS = 2 × fSAMPLE − fSIGNAL
f4NYQUISTS = abs (2 × fSAMPLE − fSIGNAL
)
)
Using the converter to alias down these narrowband or wideband
signals has many potential benefits. First and foremost is the
elimination of a complete mixer stage along with amplifiers,
filters and other devices, reducing cost and power dissipation. In
some cases, the elimination of two IF stages is possible.
REV. 0
–22–
AD6640
SYNC 1
AD6620 (1)
AD6620 (2)
AD6620 (3)
EIGHT WIDEBAND FRONT ENDS
ANTENNA 1
AD6640
AD6620 (30)
AD6620 (31)
AD6620 (32)
COMMON LO
ANTENNA 2
AD6620s (32 CHANNELS)
AD6640
COMBINE SIGNALS
FROM EIGHT ANTENNA'S
SYNC 1
AD6620 (1)
AD6620 (2)
AD6620 (3)
ADSP-21xx
(1)
SUM
SUM
SUM
ANTENNA 3
ADSP-21xx
(2)
AD6640
AD6620 (30)
AD6620 (31)
AD6620 (32)
ANTENNA 4
ADSP-21xx
(3)
AD6640
AD6620s (32 CHANNELS)
32 CHANNELS OUT
EACH CHANNEL IS SUMMATION
FROM EIGHT ANTENNA'S
SYNC 1
ADSP-21xx
(30)
AD6620 (1)
AD6620 (2)
AD6620 (3)
SUM
SUM
SUM
ANTENNA 5
ADSP-21xx
(31)
AD6640
AD6620 (30)
AD6620 (31)
AD6620 (32)
ADSP-21xx
(32)
ANTENNA 6
AD6620s (32 CHANNELS)
AD6640
SYNC 1
AD6620 (1)
AD6620 (2)
AD6620 (3)
ANTENNA 7
AD6640
AD6620 (30)
AD6620 (31)
AD6620 (32)
ANTENNA 8
AD6640
AD6620s (32 CHANNELS)
Figure 52. Receive Chain for a Phased Array Cellular Base Station with Eight Antennas and 32 Channels
REV. 0
–23–
AD6640
AD 6640AST O UTLINE D IMENSIO NS
D imensions shown in inches and (mm)
44-Ter m inal P lastic Thin Q uad Flatpack
(ST-44)
0.063 (1.60)
MAX
0.472 (12.00) SQ
0.030 (0.75)
0.018 (0.45)
33
23
34
22
SEATING
PLANE
0.394
(10.0)
SQ
TOP VIEW
(PINS DOWN)
44
12
1
11
0.006 (0.15)
0.002 (0.05)
0.018 (0.45)
0.012 (0.30)
0.031 (0.80)
BSC
0.057 (1.45)
0.053 (1.35)
REV. 0
–24–
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