AD633TRZ-EP [ADI]
Low Cost Analog Multiplier;
| 型号： | AD633TRZ-EP |
| 厂家： | 
ADI |
| 描述： | Low Cost Analog Multiplier |
| 文件： | 总8页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost
a
Analog Multiplier
AD633
FEATURES
Four-Quadrant Multiplication
CONNECTION DIAGRAMS
8-Lead Plastic DIP (N) Package
Low Cost 8-Lead Package
Complete—No External Components Required
Laser-Trimmed Accuracy and Stability
Total Error Within 2% of FS
Differential High Impedance X and Y Inputs
High Impedance Unity-Gain Summing Input
Laser-Trimmed 10 V Scaling Reference
+V
W
8
7
X1
X2
1
2
S
1
A
1
10V
Z
Y1
Y2
3
4
6
5
APPLICATIONS
1
–V
Multiplication, Division, Squaring
Modulation/Demodulation, Phase Detection
Voltage-Controlled Amplifiers/Attenuators/Filters
S
AD633JN/AD633AN
8-Lead Plastic SOIC (SO-8) Package
PRODUCT DESCRIPTION
X2
X1
Y1
Y2
1
2
8
7
1
1
The AD633 is a functionally complete, four-quadrant, analog
multiplier. It includes high impedance, differential X and Y
inputs and a high impedance summing input (Z). The low im-
pedance output voltage is a nominal 10 V full scale provided by
a buried Zener. The AD633 is the first product to offer these
features in modestly priced 8-lead plastic DIP and SOIC packages.
1
10V
–V
+V
A
3
4
6
5
S
S
W
Z
The AD633 is laser calibrated to a guaranteed total accuracy of
2% of full scale. Nonlinearity for the Y-input is typically less
than 0.1% and noise referred to the output is typically less than
100 µV rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz band-
width, 20 V/µs slew rate, and the ability to drive capacitive loads
make the AD633 useful in a wide variety of applications where
simplicity and cost are key concerns.
AD633JR/AD633AR
(X – X ) (Y – Y )
1
2
1
2
W =
+ Z
10V
PRODUCT HIGHLIGHTS
1. The AD633 is a complete four-quadrant multiplier offered in
low cost 8-lead plastic packages. The result is a product that
is cost effective and easy to apply.
The AD633’s versatility is not compromised by its simplicity.
The Z-input provides access to the output buffer amplifier,
enabling the user to sum the outputs of two or more multipliers,
increase the multiplier gain, convert the output voltage to a
current, and configure a variety of applications.
2. No external components or expensive user calibration are
required to apply the AD633.
3. Monolithic construction and laser calibration make the de-
vice stable and reliable.
4. High (10 MΩ) input resistances make signal source loading
The AD633 is available in an 8-lead plastic DIP package (N)
and 8-lead SOIC (R). It is specified to operate over the 0°C to
+70°C commercial temperature range (J Grade) or the –40°C to
+85°C industrial temperature range (A Grade).
negligible.
5. Power supply voltages can range from ±8 V to ±18 V. The
internal scaling voltage is generated by a stable Zener diode;
multiplier accuracy is essentially supply insensitive.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(TA = +25؇C, VS = ؎15 V, RL ≥ 2 k⍀)
AD633–SPECIFICATIONS
Model
AD633J, AD633A
X1 − X2 Y1 − Y2
(
)
(
)
W =
+ Z
TRANSFER FUNCTION
10 V
Parameter
Conditions
–10 V ≤ X, Y ≤ +10 V
Min
Typ
Max
Unit
MULTIPLIER PERFORMANCE
Total Error
±1
±3
؎
2
% Full Scale
% Full Scale
% Full Scale
% Full Scale
% Full Scale
% Full Scale
% Full Scale
% Full Scale
mV
TMIN to TMAX
Scale Voltage Error
Supply Rejection
Nonlinearity, X
Nonlinearity, Y
X Feedthrough
Y Feedthrough
Output Offset Voltage
SF = 10.00 V Nominal
VS = ±14 V to ±16 V
X = ±10 V, Y = +10 V
Y = ±10 V, X = +10 V
Y Nulled, X = ±10 V
X Nulled, Y = ±10 V
±0.25%
±0.01
±0.4
±0.1
±0.3
±0.1
±5
؎
؎
؎
؎
؎
1
0.4
1
0.4
50
DYNAMICS
Small Signal BW
Slew Rate
VO = 0.1 V rms
VO = 20 V p-p
∆ VO = 20 V
1
20
2
MHz
V/µs
µs
Settling Time to 1%
OUTPUT NOISE
Spectral Density
Wideband Noise
0.8
1
90
µV/√Hz
mV rms
µV rms
f = 10 Hz to 5 MHz
f = 10 Hz to 10 kHz
OUTPUT
Output Voltage Swing
Short Circuit Current
؎
11
V
mA
RL = 0 Ω
30
40
INPUT AMPLIFIERS
Signal Voltage Range
Differential
Common Mode
؎
؎
10
10
V
V
mV
dB
µA
MΩ
Offset Voltage X, Y
CMRR X, Y
Bias Current X, Y, Z
Differential Resistance
±5
80
0.8
10
؎
30
VCM = ±10 V, f = 50 Hz
60
2.0
POWER SUPPLY
Supply Voltage
Rated Performance
Operating Range
Supply Current
±15
V
V
mA
؎
8
؎
6
18
Quiescent
4
NOTES
Specifications shown in boldface are tested on all production units at electrical test. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 500 mW
Input Voltages3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD633J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD633A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V
Temperature Package
Package
Option
Model
Range
Description
AD633AN
AD633AR
–40°C to +85°C Plastic DIP
–40°C to +85°C Plastic SOIC
AD633AR-REEL –40°C to +85°C 13" Tape and Reel SO-8
AD633AR-REEL7 –40°C to +85°C 7" Tape and Reel SO-8
N-8
SO-8
AD633JN
AD633JR
AD633JR-REEL
0°C to +70°C
0°C to +70°C
0°C to +70°C
Plastic DIP
Plastic SOIC
13" Tape and Reel SO-8
7" Tape and Reel SO-8
N-8
SO-8
NOTES
AD633JR-REEL7 0°C to +70°C
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied.
28-Lead Plastic DIP Package: θJA = 90°C/W; 8-Lead Small Outline Package: θJA
155°C/W.
=
3For supply voltages less than ± 18 V, the absolute maximum input voltage is equal
to the supply voltage.
–2–
REV. B
AD633
FUNCTIONAL DESCRIPTION
voltage controlled amplifiers, and frequency doublers. Note that
these applications show the pin connections for the AD633JN
pinout (8-lead DIP), which differs from the AD633JR pinout
(8-lead SOIC).
The AD633 is a low cost multiplier comprising a translinear
core, a buried Zener reference, and a unity gain connected
output amplifier with an accessible summing node. Figure 1
shows the functional block diagram. The differential X and Y
inputs are converted to differential currents by voltage-to-current
converters. The product of these currents is generated by the
multiplying core. A buried Zener reference provides an overall
scale factor of 10 V. The sum of (X × Y)/10 + Z is then applied
to the output amplifier. The amplifier summing node Z allows
the user to add two or more multiplier outputs, convert the
output voltage to a current, and configure various analog com-
putational functions.
Multiplier Connections
Figure 3 shows the basic connections for multiplication. The X
and Y inputs will normally have their negative nodes grounded,
but they are fully differential, and in many applications the
grounded inputs may be reversed (to facilitate interfacing with
signals of a particular polarity, while achieving some desired
output polarity) or both may be driven.
+15V
0.1F
+V
1
2
3
4
8
7
6
5
S
X1
X2
X
+V
8
7
X1
X2
1
2
(X – X ) (Y – Y )
S
INPUT
1
2
1
2
1
W
Z
W =
+ Z
10V
AD633JN
OPTIONAL SUMMING
INPUT, Z
A
Y1
Y2
W
Y
INPUT
1
–V
S
10V
0.1F
–15V
Z
Y1
Y2
3
4
6
5
1
AD633
–V
S
Figure 3. Basic Multiplier Connections
Squaring and Frequency Doubling
Figure 1. Functional Block Diagram (AD633JN
Pinout Shown)
As Figure 4 shows, squaring of an input signal, E, is achieved
simply by connecting the X and Y inputs in parallel to produce
an output of E2/10 V. The input may have either polarity, but
the output will be positive. However, the output polarity may be
reversed by interchanging the X or Y inputs. The Z input may
be used to add a further signal to the output.
Inspection of the block diagram shows the overall transfer func-
tion to be:
X1 − X2 Y1 − Y2
(
)
(
)
+ Z
W =
(Equation 1)
10 V
+15V
0.1F
ERROR SOURCES
+V
1
2
3
4
8
7
6
5
E
S
X1
X2
2
Multiplier errors consist primarily of input and output offsets,
scale factor error, and nonlinearity in the multiplying core. The
input and output offsets can be eliminated by using the optional
trim of Figure 2. This scheme reduces the net error to scale
factor errors (gain error) and an irreducible nonlinearity compo-
nent in the multiplying core. The X and Y nonlinearities are
typically 0.4% and 0.1% of full scale, respectively. Scale factor
error is typically 0.25% of full scale. The high impedance Z
input should always be referenced to the ground point of the
driven system, particularly if this is remote. Likewise, the differ-
ential X and Y inputs should be referenced to their respective
grounds to realize the full accuracy of the AD633.
E
W
W =
10V
AD633JN
Y1
Z
–V
Y2
S
0.1F
–15V
Figure 4. Connections for Squaring
When the input is a sine wave E sin ωt, this squarer behaves as a
frequency doubler, since
2
)
E2
20V
+V
S
E sin ωt
(
(Equation 2)
=
1 − cos 2 ωt
(
)
10 V
؎50mV
300k⍀
TO APPROPRIATE
INPUT TERMINAL
(E.G. X , X , Z)
50k⍀
Equation 2 shows a dc term at the output which will vary
strongly with the amplitude of the input, E. This can be avoided
using the connections shown in Figure 5, where an RC network
is used to generate two signals whose product has no dc term. It
uses the identity:
1k⍀
2
2
–V
S
Figure 2. Optional Offset Trim Configuration
APPLICATIONS
The AD633 is well suited for such applications as modulation
and demodulation, automatic gain control, power measurement,
1
cos θ sin θ = sin 2 θ
(Equation 3)
(
)
2
–3–
REV. B
AD633
R
10k⍀
+15V
0.1F
+15V
0.1F
+V
1
2
3
4
8
7
6
5
E
S
X1
X2
+15
2
R
E
+V
0.1F
E
1
8
7
6
5
W
Z
S
W =
X1
X2
X
10V
R1
1k⍀
R
10k⍀
AD633JN
W
Z
2
3
4
Y1
Y2
E
R2
3k⍀
C
1N4148
AD633JN
AD711
Y1
Y2
–V
S
0.1F
–V
S
0.1F
0.1F
–15V
–15V
W = –10V
–15
Figure 5. ”Bounceless” Frequency Doubler
E
E
X
At ωo = 1/CR, the X input leads the input signal by 45° (and is
attenuated by √2), and the Y input lags the X input by 45° (and
is also attenuated by √2). Since the X and Y inputs are 90° out of
phase, the response of the circuit will be (satisfying Equation 3):
Figure 7. Connections for Division
Likewise, Figure 7 shows how to implement a divider using a
multiplier in a feedback loop. The transfer function for the
divider is
1
E
E
W =
sin ωot + 45°
sin ωot − 45°
(
) (
)
E
10V
2
2
(
)
W = − 10V
(
)
(Equation 6)
EX
E2
(Equation 4)
=
sin 2 ωot
(
)
+15V
0.1F
40V
(
)
which has no dc component. Resistors R1 and R2 are included to
restore the output amplitude to 10 V for an input amplitude of 10 V.
+V
S
1
2
3
4
8
7
6
5
X1
X2
X
INPUT
(X – X ) (Y – Y ) (R1 + R2)
1
2
1
2
W
W =
+ S
R1
10V
R1
AD633JN
The amplitude of the output is only a weak function of fre-
quency: the output amplitude will be 0.5% too low at ω =
0.9 ωo, and ωo = 1.1 ωo.
1k⍀ R1, R2 100k⍀
Y1
Z
Y
R2
INPUT
–V
Y2
S
S
0.1F
–15V
Generating Inverse Functions
Inverse functions of multiplication, such as division and square
rooting, can be implemented by placing a multiplier in the feed-
back loop of an op amp. Figure 6 shows how to implement a
square rooter with the transfer function
Figure 8. Connections for Variable Scale Factor
Variable Scale Factor
In some instances, it may be desirable to use a scaling voltage
other than 10 V. The connections shown in Figure 8 increase
the gain of the system by the ratio (R1 + R2)/R1. This ratio is
limited to 100 in practical applications. The summing input, S,
may be used to add an additional signal to the output or it may
be grounded.
W = − 10V E
(Equation 5)
(
)
for the condition E<0.
R
10k⍀
Current Output
+15V
0.1F
The AD633’s voltage output can be converted to a current
output by the addition of a resistor R between the AD633’s W
and Z pins as shown in Figure 9 below. This arrangement forms
+15
+V
0.1F
1
8
7
6
5
X1
X2
S
R
10k⍀
E
W
Z
2
3
4
1N4148
AD633JN
Y1
AD711
+15V
0.1F
–V
Y2
0.1F
S
0.1F
+V
1
2
3
4
8
7
6
5
S
X1
X2
X
–15V
W =
R
(X – X ) (Y – Y )
INPUT
1
R
1
2
1
2
–15
W
Z
I
=
O
10V
–(10V)E
AD633JN
Y1
Y2
1k⍀
R
100k⍀
Y
INPUT
Figure 6. Connections for Square Rooting
–V
S
0.1F
–15V
Figure 9. Current Output Connections
–4–
REV. B
AD633
dB
the basis of voltage controlled integrators and oscillators as will
be shown later in this Applications section. The transfer func-
tion of this circuit has the form
f2 f1
f
0
+15V
0.1F
–6dB/OCTAVE
OUTPUTA
OUTPUTB
+V
1
2
3
4
8
7
6
5
X1
X2
S
CONTROL
X1 − X2 Y1 − Y2
(
)
(
)
1
1 + T P
1
1 + T P
INPUT E
IO
=
C
W
Z
(Equation 7)
OUTPUT B =
OUTPUT A =
2
R
10V
AD633JN
R
1
SIGNAL
Y1
INPUT E
1 + T P
2
S
C
Linear Amplitude Modulator
–V
Y2
1
W
S
T
T
=
=
= RC
1
The AD633 can be used as a linear amplitude modulator with
no external components. Figure 10 shows the circuit. The car-
rier and modulation inputs to the AD633 are multiplied to
produce a double-sideband signal. The carrier signal is fed
forward to the AD633’s Z input where it is summed with the
double-sideband signal to produce a double-sideband with carrier
output.
0.1F
1
1
W
10
R
=
2
E
–15V
C
C
2
Figure 11. Voltage Controlled Low-Pass Filter
dB
f1 f2
f
0
+15V
0.1F
Voltage Controlled Low-Pass and High-Pass Filters
Figure 11 shows a single multiplier used to build a voltage con-
trolled low-pass filter. The voltage at output A is a result of
filtering, ES. The break frequency is modulated by EC, the con-
trol input. The break frequency, f2, equals
OUTPUTB
+6dB/OCTAVE
OUTPUTA
+V
1
2
3
4
8
7
6
5
S
X1
X2
CONTROL
INPUT E
C
W
Z
OUTPUT B
OUTPUT A
AD633JN
C
SIGNAL
INPUT E
Y1
S
R
–V
Y2
S
EC
0.1F
f2
=
(Equation 8)
20V π RC
(
)
–15V
and the rolloff is 6 dB per octave. This output, which is at a
high impedance point, may need to be buffered.
Figure 12. Voltage Controlled High-Pass Filter
Voltage Controlled Quadrature Oscillator
The voltage at output B, the direct output of the AD633, has
same response up to frequency f1, the natural breakpoint of RC
filter,
Figure 13 shows two multipliers being used to form integrators
with controllable time constants in a 2nd order differential
equation feedback loop. R2 and R5 provide controlled current
output operation. The currents are integrated in capacitors C1
and C2, and the resulting voltages at high impedance are applied
to the X inputs of the “next” AD633. The frequency control
input, EC, connected to the Y inputs, varies the integrator gains
with a calibration of 100 Hz/V. The accuracy is limited by the
Y-input offsets. The practical tuning range of this circuit is
100:1. C2 (proportional to C1 and C3), R3, and R4 provide
regenerative feedback to start and maintain oscillation. The
diode bridge, D1 through D4 (1N914s), and Zener diode D5
provide economical temperature stabilization and amplitude
stabilization at ±8.5 V by degenerative damping. The out-
put from the second integrator (10 V sin ωt) has the lowest
distortion.
1
f1 =
(Equation 9)
2 π RC
then levels off to a constant attenuation of f1/f2 = EC/10.
+15V
0.1F
+V
MODULATION
INPUT
1
2
3
4
8
7
6
5
S
X1
X2
E
M
؎E
W
Z
M
W = 1+
E
sin t
C
10V
AD633JN
CARRIER
INPUT
Y1
E
sin t
C
–V
Y2
S
0.1F
–15V
AGC AMPLIFIERS
Figure 14 shows an AGC circuit that uses an rms-dc converter
to measure the amplitude of the output waveform. The AD633
and A1, 1/2 of an AD712 dual op amp, form a voltage con-
trolled amplifier. The rms dc converter, an AD736, measures
the rms value of the output signal. Its output drives A2, an
integrator/comparator, whose output controls the gain of the
voltage controlled amplifier. The 1N4148 diode prevents the
output of A2 from going negative. R8, a 50 kΩ variable resistor,
sets the circuit’s output level. Feedback around the loop forces
the voltages at the inverting and noninverting inputs of A2 to be
equal, thus the AGC.
Figure 10. Linear Amplitude Modulator
For example, if R = 8 kΩ and C = 0.002 µF, then output A has
a pole at frequencies from 100 Hz to 10 kHz for EC ranging
from 100 mV to 10 V. Output B has an additional zero at 10 kHz
(and can be loaded because it is the multiplier’s low impedance
output). The circuit can be changed to a high-pass filter Z inter-
changing the resistor and capacitor as shown in Figure 12 below.
–5–
REV. B
AD633
D5
1N95236
D1
1N914
D3
1N914
(10V) cos t
+15V
0.1F
D2
1N914
D4
1N914
R4
C2
+15V
0.1F
16k⍀
0.01F
+V
1
2
3
4
8
7
6
5
S
X1
X2
R1
1k⍀
R3
330k⍀
+V
W
1
2
3
4
8
7
6
5
S
X1
X2
R2
AD633JN
16k⍀
E
W
Z
(10V) sin t
Y1
C
Z
R5
16k⍀
AD633JN
0.1F
E
C
10V
–V
Y1
Y2
S
f =
kHz
0.1F
C3
–V
Y2
S
0.1F
0.1F
–15V
–15V
Figure 13. Voltage Controlled Quadrature Oscillator
R2
1k⍀
R3
10k⍀
R4
10k⍀
AGC THRESHOLD
ADJUSTMENT
+15V
0.1F
+15V
C1
1F
0.1F
+V
1
2
3
4
8
1/2
S
X1
X2
E
AD712
OUT
W
7
6
5
R5
10k⍀
A1
AD633JN
E
Y1
Z
R6
1k⍀
–V
Y2
S
+15V
1
2
3
4
C
COMMON
8
7
6
5
0.1F
–15V
C
0.1F
V
+V
S
AD736
OUTPUT
IN
C
F
C2
0.02F
0.1F
–V
C
S
AV
C3
0.2F
R10
10k⍀
–15V
C4
33F
A2
R9
10k⍀
1N4148
1/2
AD712
+15V
R8
50k⍀
OUTPUT
LEVEL
ADJUST
0.1F
–15V
Figure 14. Connections for Use in Automatic Gain Control Circuit
–6–
REV. B
Typical Characteristics–AD633
100
0dB = 0.1V rms, R = 2k⍀
L
90
80
70
60
50
40
0
C
= 1000pF
L
TYPICAL
FOR X,Y
INPUTS
C
= 0dB
L
–10
–20
–30
NORMAL
CONNECTION
30
20
100
100k
1M
1k
10k
10k
1M
10M
100k
FREQUENCY – Hz
FREQUENCY – Hz
Figure 15. Frequency Response
Figure 18. CMRR vs. Frequency
1.5
700
600
500
400
1
0.5
300
200
0
10
–60 –40 –20
0
20
40
60
80
100 120 140
100
100k
1k
10k
FREQUENCY – Hz
TEMPERATURE – ؇C
Figure 16. Input Bias Current vs. Temperature (X, Y, or Z
Inputs)
Figure 19. Noise Spectral Density vs. Frequency
14
12
1000
Y-FEEDTHROUGH
100
OUTPUT, R
2k⍀
L
10
8
X- FEEDTHROUGH
10
ALL INPUTS
1
0
6
4
8
20
10
12
14
16
18
10
100
10k
FREQUENCY – Hz
1k
100k
1M
10M
PEAK POSITIVE OR NEGATIVE SUPPLY – Volts
Figure 17. Input and Output Signal Ranges vs. Supply
Voltages
Figure 20. AC Feedthrough vs. Frequency
–7–
REV. B
AD633
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
0.39 (9.91)
MAX
8
5
4
0.25 0.31
(6.35) (7.87)
1
PIN 1
0.30 (7.62)
REF
0.10 (2.54)
TYP
0.035 ؎0.01
(0.89 ؎0.25)
0.165 ؎0.01
(4.19 ؎0.25)
0.18 ؎0.03
(4.57 ؎0.76)
0.125 (3.18)
MIN
0.11 ؎0.003
(0.28 ؎0.08)
0.018 ؎0.003
(0.46 ؎0.03)
SEATING
PLANE
0.033 (0.84)
NOM
0-15؇
8-Lead Plastic SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
BSC
؋
45؇ 0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
8؇
0؇
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
–8–
REV. B
相关型号：
©2020 ICPDF网 联系我们和版权申明