AD633ARZ-R7 [ADI]
Low Cost Analog Multiplier; 低成本模拟乘法器
| 型号： | AD633ARZ-R7 |
| 厂家： | 
ADI |
| 描述： | Low Cost Analog Multiplier |
| 文件： | 总16页 (文件大小：610K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost
Analog Multiplier
AD633
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
X1
4-quadrant multiplication
1
Low cost, 8-lead SOIC and PDIP packages
Complete—no external components required
Laser-trimmed accuracy and stability
Total error within 2% of full scale
X2
A
W
Z
1
10V
Differential high impedance X and Y inputs
High impedance unity-gain summing input
Laser-trimmed 10 V scaling reference
Y1
Y2
1
Figure 1.
APPLICATIONS
Multiplication, division, squaring
Modulation/demodulation, phase detection
Voltage-controlled amplifiers/attenuators/filters
GENERAL DESCRIPTION
The AD633 is a functionally complete, four-quadrant, analog
multiplier. It includes high impedance, differential X and Y inputs,
and a high impedance summing input (Z). The low impedance
output voltage is a nominal 10 V full scale provided by a buried
Zener. The AD633 is the first product to offer these features in
modestly priced 8-lead PDIP and SOIC packages.
The AD633 is available in 8-lead PDIP and SOIC packages. It is
specified to operate over the 0°C to 70°C commercial temperature
range (J Grade) or the −40°C to +85°C industrial temperature
range (A Grade).
PRODUCT HIGHLIGHTS
1. The AD633 is a complete four-quadrant multiplier offered
in low cost 8-lead SOIC and PDIP packages. The result is a
product that is cost effective and easy to apply.
2. No external components or expensive user calibration are
required to apply the AD633.
3. Monolithic construction and laser calibration make the
device stable and reliable.
4. High (10 MΩ) input resistances make signal source
loading negligible.
The AD633 is laser calibrated to a guaranteed total accuracy of
2% of full scale. Nonlinearity for the Y input is typically less
than 0.1% and noise referred to the output is typically less than
100 μV rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz bandwidth,
20 V/μs slew rate, and the ability to drive capacitive loads make
the AD633 useful in a wide variety of applications where
simplicity and cost are key concerns.
The versatility of the AD633 is not compromised by its simplicity.
The Z input provides access to the output buffer amplifier, enabling
the user to sum the outputs of two or more multipliers, increase
the multiplier gain, convert the output voltage to a current, and
configure a variety of applications.
5. Power supply voltages can range from 8 V to 18 V. The
internal scaling voltage is generated by a stable Zener diode;
multiplier accuracy is essentially supply insensitive.
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
AD633
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information.................................................................8
Multiplier Connections ................................................................8
Squaring and Frequency Doubling.............................................8
Generating Inverse Functions .....................................................8
Variable Scale Factor.....................................................................9
Current Output..............................................................................9
Linear Amplitude Modulator ......................................................9
Voltage-Controlled, Low-Pass and High-Pass Filters...............9
Voltage-Controlled Quadrature Oscillator................................... 10
Automatic Gain Control (AGC) Amplifiers........................... 10
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
Typical Performance Characteristics ............................................. 6
Functional Description.................................................................... 7
Error Sources................................................................................. 7
REVISION HISTORY
4/10—Rev. F to Rev. G
2/12—Rev. H to Rev. I
Changes to Equation 1......................................................................6
Changes to Equation 5 and Figure 14.............................................7
Changes to Figure 21.........................................................................9
Changes to Figure 1.......................................................................... 1
Changes to Figure 2.......................................................................... 5
Changes to Generating Inverse Functions Section ...................... 8
Changes to Figure 15........................................................................ 9
Added Evaluation Board Section and Figure 23 to Figure 29,
Renumbered Sequentially.............................................................. 12
Changes to Ordering Guide .......................................................... 15
10/09—Rev. E to Rev. F
Changes to Format .............................................................Universal
Changes to Figure 21.........................................................................9
Updated Outline Dimensions....................................................... 11
Changes to Ordering Guide.......................................................... 12
4/11—Rev. G to Rev. H
Changes to Figure 1, Deleted Figure 2........................................... 1
Added Figure 2, Figure 3, Table 4, Table 5 .................................... 5
Deleted Figure 9, Renumbered Subsequent Figures.................... 6
Changes to Figure 15........................................................................ 9
10/02—Rev. D to Rev. E
Edits to Title of 8-Lead Plastic SOIC Package (RN-8) .................1
Edits to Ordering Guide ...................................................................2
Change to Figure 13 ..........................................................................7
Updated Outline Dimensions..........................................................8
Rev. I | Page 2 of 16
Data Sheet
AD633
SPECIFICATIONS
TA = 25°C, VS = 15 V, RL ≥ 2 kΩ.
Table 1.
AD633J, AD633A
Typ
Parameter
Conditions
Min
Max
Unit
TRANSFER FUNCTION
(
X1 − X2)(Y1 − Y2
)
W =
+ Z
10 V
MULTIPLIER PERFORMANCE
Total Error
−10 V ≤ X, Y ≤ +10 V
±1
±3
±±1
% full scale
% full scale
% full scale
% full scale
% full scale
% full scale
% full scale
% full scale
mV
TMIN to TMAX
Scale Voltage Error
Supply Rejection
Nonlinearity, X
SF = 10.00 V nominal
VS = ±14 V to ±16 V
X = ±10 V, Y = +10 V
Y = ±10 V, X = +10 V
Y nulled, X = ±10 V
X nulled, Y = ±10 V
±0.±5%
±0.01
±0.4
±0.1
±0.3
±0.1
±5
±11
±0.41
±11
±0.41
±501
Nonlinearity, Y
X Feedthrough
Y Feedthrough
Output Offset Voltage
DYNAMICS
Small Signal Bandwidth
Slew Rate
Settling Time to 1%
OUTPUT NOISE
Spectral Density
Wideband Noise
VO = 0.1 V rms
VO = ±0 V p-p
ΔVO = ±0 V
1
±0
±
MHz
V/µs
µs
0.8
1
90
µV/√Hz
mV rms
µV rms
f = 10 Hz to 5 MHz
f = 10 Hz to 10 kHz
OUTPUT
Output Voltage Swing
Short Circuit Current
INPUT AMPLIFIERS
Signal Voltage Range
±111
V
mA
RL = 0 Ω
30
401
Differential
Common mode
±101
±101
V
V
Offset Voltage (X, Y)
CMRR (X, Y)
Bias Current (X, Y, Z)
Differential Resistance
POWER SUPPLY
±5
80
0.8
10
±301
±.01
mV
dB
µA
MΩ
VCM = ±10 V, f = 50 Hz
601
Supply Voltage
Rated Performance
Operating Range
Supply Current
±15
4
V
V
mA
±81
±181
61
Quiescent
1 This specification was tested on all production units at electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum
specifications are guaranteed; however, only this specification was tested on all production units.
Rev. I | Page 3 of 16
AD633
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage
±18 V
Internal Power Dissipation
Input Voltages1
500 mW
±18 V
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
AD633J
Indefinite
−65°C to +150°C
THERMAL RESISTANCE
0°C to 70°C
−40°C to +85°C
300°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
AD633A
Lead Temperature (Soldering, 60 sec)
ESD Rating
1000 V
Table 3.
1 For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.
Package Type
8-Lead PDIP
8-Lead SOIC
θJA
90
155
Unit
°C/W
°C/W
ESD CAUTION
Rev. I | Page 4 of 16
Data Sheet
AD633
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
X1
X2
Y1
Y2
1
2
3
4
8
7
6
5
+V
W
Z
Y1
Y2
1
2
3
4
8
7
6
5
X2
X1
+V
W
S
1
1
1
A
1
10V
1
10V
–V
S
S
A
1
Z
–V
S
AD633JN/AD633AN
AD633JR/AD633AR
(X1 – X2)(Y1 – Y2)
(X1 – X2)(Y1 – Y2)
W =
+ Z
W =
+ Z
10V
10V
Figure 2. 8-Lead PDIP
Figure 3. 8-Lead SOIC
Table 4. 8-Lead PDIP Pin Function Descriptions
Table 5. 8-Lead SOIC Pin Function Descriptions
Pin No. Mnemonic Description
Pin No.
Mnemonic Description
1
±
3
4
5
6
7
8
X1
X±
Y1
Y±
−VS
Z
X Multiplicand Noninverting Input
X Multiplicand Inverting Input
Y Multiplicand Noninverting Input
Y Multiplicand Inverting Input
Negative Supply Rail
Summing Input
Product Output
Positive Supply Rail
1
±
3
4
5
6
7
8
Y1
Y±
−VS
Z
Y Multiplicand Noninverting Input
Y Multiplicand Inverting Input
Negative Supply Rail
Summing Input
Product Output
Positive Supply Rail
X Multiplicand Noninverting Input
X Multiplicand Inverting Input
W
+VS
X1
X±
W
+VS
Rev. I | Page 5 of 16
AD633
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
100
90
80
70
60
50
40
30
20
0dB = 0.1V rms, R = 2kΩ
L
0
–10
–20
C
= 1000pF
L
C
= 0dB
L
TYPICAL
FOR X, Y
INPUTS
NORMAL
CONNECTION
–30
10k
100k
FREQUENCY (Hz)
1M
10M
100
1k
10k
FREQUENCY (Hz)
100k
1M
Figure 7. CMRR vs. Frequency
Figure 4. Frequency Response
1.5
1.0
700
600
500
400
300
200
0.5
0
10
100
1k
10k
100k
–60 –40 –20
0
20
40
60
80
100 120 140
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 5. Input Bias Current vs. Temperature (X, Y, or Z Inputs)
Figure 8. Noise Spectral Density vs. Frequency
14
1k
100
10
Y-FEEDTHROUGH
12
OUTPUT, R ≥ 2kΩ
L
10
8
X-FEEDTHROUGH
ALL INPUTS
1
6
4
0.1
10
8
10
12
14
16
18
20
100
1k
10k
100k
1M
10M
PEAK POSITIVE OR NEGATIVE SUPPLY (V)
FREQUENCY (Hz)
Figure 6. Input and Output Signal Ranges vs. Supply Voltages
Figure 9. AC Feedthrough vs. Frequency
Rev. I | Page 6 of 16
Data Sheet
AD633
FUNCTIONAL DESCRIPTION
The AD633 is a low cost multiplier comprising a translinear
core, a buried Zener reference, and a unity-gain connected
output amplifier with an accessible summing node. Figure 1
shows the functional block diagram. The differential X and Y
inputs are converted to differential currents by voltage-to-
current converters. The product of these currents is generated
by the multiplying core. A buried Zener reference provides an
overall scale factor of 10 V. The sum of (X × Y)/10 + Z is then
applied to the output amplifier. The amplifier summing node Z
allows the user to add two or more multiplier outputs, convert
the output voltage to a current, and configure various analog
computational functions.
ERROR SOURCES
Multiplier errors consist primarily of input and output offsets,
scale factor error, and nonlinearity in the multiplying core. The
input and output offsets can be eliminated by using the optional
trim of Figure 10. This scheme reduces the net error to scale
factor errors (gain error) and an irreducible nonlinearity
component in the multiplying core. The X and Y nonlinearities
are typically 0.4% and 0.1% of full scale, respectively. Scale
factor error is typically 0.25% of full scale. The high impedance
Z input should always reference the ground point of the driven
system, particularly if it is remote. Likewise, the differential X
and Y inputs should reference their respective grounds to
realize the full accuracy of the AD633.
Inspection of the block diagram shows the overall transfer
function is
+V
S
(
X1 − X2)(Y1 − Y2
)
+ Z
±50mV
W =
(1)
300kΩ
TO APPROPRIATE
INPUT TERMINAL
(FOR EXAMPLE, X2, Y2, Z)
50kΩ
10 V
1kΩ
–V
S
Figure 10. Optional Offset Trim Configuration
Rev. I | Page 7 of 16
AD633
Data Sheet
APPLICATIONS INFORMATION
+15V
0.1µF
The AD633 is well suited for such applications as modulation
and demodulation, automatic gain control, power measurement,
voltage-controlled amplifiers, and frequency doublers. These
applications show the pin connections for the AD633JN (8-lead
PDIP), which differs from the AD633JR (8-lead SOIC).
+V
8
E
1
2
3
4
X1
X2
S
2
E
R
C
W =
W
Z
7
6
5
10V
R1
1kΩ
AD633JN
Y1
R2
3kΩ
–V
MULTIPLIER CONNECTIONS
Y2
S
Figure 11 shows the basic connections for multiplication. The X
and Y inputs normally have their negative nodes grounded, but
they are fully differential, and in many applications, the grounded
inputs may be reversed (to facilitate interfacing with signals of a
particular polarity while achieving some desired output polarity),
or both may be driven.
0.1µF
–15V
Figure 13. Bounceless Frequency Doubler
At ωo = 1/CR, the X input leads the input signal by 45° (and is
attenuated by √2), and the Y input lags the X input by 45° (and
is also attenuated by √2). Because the X and Y inputs are 90° out of
phase, the response of the circuit is (satisfying Equation 3)
+15V
0.1µF
+V
8
7
+
–
+
–
1
2
3
4
X1
X2
1
10V
E
2
E
2
S
X
W
sin 0t 45
sin 0t 45
(X1 – X2)(Y1 – Y2)
10V
INPUT
W =
+ Z
W
Z
AD633JN
OPTIONAL SUMMING
INPUT, Z
E2
40 V
Y1
6
5
Y
sin 2 0t
(4)
INPUT
–V
Y2
S
0.1µF
which has no dc component. Resistors R1 and R2 are included
to restore the output amplitude to 10 V for an input amplitude
of 10 V.
–15V
Figure 11. Basic Multiplier Connections
SQUARING AND FREQUENCY DOUBLING
The amplitude of the output is only a weak function of frequency;
the output amplitude is 0.5% too low at ω = 0.9 ω0 and ω0 = 1.1 ω0.
As is shown in Figure 12, squaring of an input signal, E, is
achieved simply by connecting the X and Y inputs in parallel to
produce an output of E2/10 V. The input can have either polarity,
but the output is positive. However, the output polarity can be
reversed by interchanging the X or Y inputs. The Z input can be
used to add a further signal to the output.
GENERATING INVERSE FUNCTIONS
Inverse functions of multiplication, such as division and square
rooting, can be implemented by placing a multiplier in the feedback
loop of an op amp. Figure 14 shows how to implement square
rooting with the transfer function for the condition E < 0.
+15V
0.1µF
The 1N4148 diode is required to prevent latchup, which can
occur in such applications if the input were to change polarity,
even momentarily.
+V
8
E
1
2
3
4
X1
X2
S
2
E
W =
W
Z
7
6
5
10V
AD633JN
Y1
W
10E
V
(5)
–V
Y2
S
10kΩ
0.1µF
+15V
0.1µF
+15V
–15V
+V
8
1
2
3
4
X1
X2
S
Figure 12. Connections for Squaring
0.1µF
6
10kΩ
W
Z
7
6
5
7
When the input is a sine wave E sin ωt, this squarer behaves as a
frequency doubler, because
2
3
E < 0V
1N4148
–15V
0.1µF
AD633JN
AD711
Y1
Y2
4
2
E2
20 V
–V
S
E sin t
10 V
0.1µF
1 cos 2 t
(2)
–15V
W =
10V)E
Equation 2 shows a dc term at the output that varies strongly
with the amplitude of the input, E. This can be avoided using
the connections shown in Figure 13, where an RC network is
Figure 14. Connections for Square Rooting
used to generate two signals whose product has no dc term. It
uses the identity
1
2
cos θ sin θ
sin 2 θ
(3)
Rev. I | Page 8 of 16
Data Sheet
AD633
Likewise, Figure 15 shows how to implement a divider using a
multiplier in a feedback loop. The transfer function for the
divider is
This arrangement forms the basis of voltage-controlled integrators
and oscillators as is shown later in this section. The transfer
function of this circuit has the form
E
EX
1
R
(
X1− X2)(Y1−Y2
10 V
)
′
W = −
(
10 V
)
(6)
IO =
(7)
R
10kΩ
LINEAR AMPLITUDE MODULATOR
The AD633 can be used as a linear amplitude modulator with no
external components. Figure 18 shows the circuit. The carrier
and modulation inputs to the AD633 are multiplied to produce
a double sideband signal. The carrier signal is fed forward to the
Z input of the AD633 where it is summed with the double
sideband signal to produce a double sideband with the carrier
output.
+15V
0.1µF
+15V
0.1µF
+V
8
E
1
2
3
4
X1
X2
S
X
R
10kΩ
W
Z
7
6
5
7
2
3
E
AD633JN
6
Y1
Y2
AD711
0.1µF
4
–V
S
0.1µF
+15V
–15V
W' = –10V
–15V
E
E
X
0.1µF
MODULATION
INPUT
+V
8
+
–
1
2
3
4
X1
X2
S
E
M
±E
Figure 15. Connections for Division
M
W
Z
7
6
5
W = 1+
E sin ωt
C
10V
AD633JN
CARRIER
INPUT
Y1
Y2
VARIABLE SCALE FACTOR
E
sin ωt
C
–V
S
In some instances, it may be desirable to use a scaling voltage
0.1µF
other than 10 V. The connections shown in Figure 16 increase
the gain of the system by the ratio (R1 + R2)/R1. This ratio is
limited to 100 in practical applications. The summing input, S,
can be used to add an additional signal to the output, or it can
be grounded.
–15V
Figure 18. Linear Amplitude Modulator
VOLTAGE-CONTROLLED, LOW-PASS AND HIGH-
PASS FILTERS
+15V
Figure 19 shows a single multiplier used to build a voltage-
controlled, low-pass filter. The voltage at Output A is a result
of filtering, ES. The break frequency is modulated by EC, the control
input. The break frequency, f2, equals
0.1µF
+V
8
7
6
+
–
+
–
1
2
3
4
X1
X2
S
X
INPUT
(X1 – X2)(Y1 – Y2) R1 + R2
W
Z
W =
+ S
10V
R1
AD633JN
R1
R2
1kΩ ≤ R1, R2 ≤ 100kΩ
Y1
Y2
Y
EC
INPUT
–V
5
f2 =
(8)
S
20 V π RC
0.1µF
S
and the roll-off is 6 dB per octave. This output, which is at a
high impedance point, may need to be buffered.
–15V
dB
Figure 16. Connections for Variable Scale Factor
f2 f1
f
0
CURRENT OUTPUT
+15V
0.1µF
–6dB/OCTAVE
The voltage output of the AD633 can be converted to a current
output by the addition of a resistor, R, between the W and Z pins of
the AD633 as shown in Figure 17.
OUTPUT B
OUTPUT A
+V
8
1
2
3
4
X1
X2
S
CONTROL
INPUT E
1 + T P
1
C
OUTPUT B =
W
Z
7
6
5
1 + T P
2
1
+15V
AD633JN
R
SIGNAL
INPUT E
Y1
Y2
OUTPUT A =
1
1 + T P
2
S
0.1µF
C
–V
S
+V
8
+
–
+
–
1
2
3
4
X1
X2
S
T
=
= R
1
C
X
W
1
0.1µF
–15V
R
1
(X1 – X2)(Y1 – Y2)
10V
INPUT
I
=
1
10
W
Z
7
6
5
O
T
=
=
R
2
AD633JN
W
E
R
2
C
C
1kΩ ≤ R ≤ 100kΩ
Y1
Y2
Y
Figure 19. Voltage-Controlled, Low-Pass Filter
INPUT
–V
S
The voltage at Output B, the direct output of the AD633, has the
same response up to frequency f1, the natural breakpoint of RC
filter, and then levels off to a constant attenuation of f1/f2 = EC/10.
0.1µF
–15V
Figure 17. Current Output Connections
1
f1 =
(9)
2 π RC
Rev. I | Page 9 of 16
AD633
Data Sheet
For example, if R = 8 kΩ and C = 0.002 µF, then Output A has a
pole at frequencies from 100 Hz to 10 kHz for EC ranging from
100 mV to 10 V. Output B has an additional 0 at 10 kHz (and
can be loaded because it is the low impedance output of the
multiplier). The circuit can be changed to a high-pass filter Z
interchanging the resistor and capacitor as shown in Figure 20.
EC, connected to the Y inputs, varies the integrator gains with a
calibration of 100 Hz/V. The accuracy is limited by the Y input
offsets. The practical tuning range of this circuit is 100:1. C2
(proportional to C1 and C3), R3, and R4 provide regenerative
feedback to start and maintain oscillation. The diode bridge, D1
through D4 (1N914s), and Zener diode D5 provide economical
temperature stabilization and amplitude stabilization at 8.5 V
by degenerative damping. The output from the second integrator
(10 V sin ωt) has the lowest distortion.
dB
f1 f2
f
0
+15V
0.1µF
OUTPUT B
+6dB/OCTAVE
AUTOMATIC GAIN CONTROL (AGC) AMPLIFIERS
OUTPUT A
+V
8
1
2
3
4
X1
X2
S
CONTROL
INPUT E
Figure 22 shows an AGC circuit that uses an rms-to-dc
converter to measure the amplitude of the output waveform.
The AD633 and A1, ½ of an AD712 dual op amp, form a
voltage-controlled amplifier. The rms-to-dc converter, an
AD736, measures the rms value of the output signal. Its output
drives A2, an integrator/comparator whose output controls the
gain of the voltage-controlled amplifier. The 1N4148 diode
prevents the output of A2 from going negative. R8, a 50 kΩ
variable resistor, sets the output level of the circuit. Feedback
around the loop forces the voltages at the inverting and
noninverting inputs of A2 to be equal, thus the AGC.
C
OUTPUT B
OUTPUT A
W
Z
7
6
5
C
AD633JN
SIGNAL
INPUT E
Y1
Y2
S
R
–V
S
0.1µF
–15V
Figure 20. Voltage-Controlled, High-Pass Filter
VOLTAGE-CONTROLLED QUADRATURE OSCILLATOR
Figure 21 shows two multipliers being used to form integrators
with controllable time constants in second-order differential
equation feedback loop. R2 and R5 provide controlled current
output operation. The currents are integrated in capacitors C1
and C2, and the resulting voltages at high impedance are applied
to the X inputs of the next AD633. The frequency control input,
D5
1N5236
D1
D3
1N914
1N914
(10V) cos ωt
D2
1N914
D4
1N914
+15V
0.1µF
C2
0.01µF
R4
16kΩ
+15V
0.1µF
+V
8
1
2
3
4
X1
X2
S
R1
1kΩ
R3
330kΩ
+V
8
W
Z
7
6
5
1
2
3
4
X1
X2
S
R2
16kΩ
AD633JN
E
C
Y1
Y2
W
Z
7
6
5
(10V) sin ωt
C1
0.01µF
R5
AD633JN
16kΩ
C3
0.01µF
–V
Y1
Y2
S
0.1µF
0.1µF
–15V
–V
S
E
C
f =
= kHz
–15V
10V
Figure 21. Voltage-Controlled Quadrature Oscillator
Rev. I | Page 10 of 16
Data Sheet
AD633
R2
1kΩ
R3
10kΩ
R4
10kΩ
AGC THRESHOLD
ADJUSTMENT
+15V
0.1µF
+15V
C1
1µF
8
0.1µF
2
3
+V
8
1
2
3
4
X1
X2
S
1/2
AD712
1
E
OUT
R5
W
7
6
5
10kΩ
AD633JN
A1
R6
1kΩ
Y1
Y2
Z
E
–V
S
+15V
COMMON
8
7
1
2
3
4
C
V
C
0.1µF
0.1µF
+V
S
IN
–15V
AD736
C
OUTPUT
6
5
C2
0.02µF
F
0.1µF
C
–V
AV
S
C3
0.2µF
R10
10kΩ
–15V
C4
33µF
A2
R9
10kΩ
6
5
1N4148
+15V
1/2
AD712
7
OUTPUT
LEVEL
ADJUST
R8
50kΩ
4
0.1µF
–15V
Figure 22. Connections for Use in Automatic Gain Control Circuit
Rev. I | Page 11 of 16
AD633
Data Sheet
EVALUATION BOARD
The evaluation board of the AD633 enables simple bench-top
experimenting to be performed with easy control of the
AD633. Built-in flexibility allows convenient configuration
to accommodate most operating configurations. Figure 23 is
a photograph of the AD633 evaluation board.
Figure 24. Component Side Copper
Figure 23. AD633 Evaluation Board
Any dual-polarity power supply capable of providing 10 mA
or greater is all that is required, in addition to whatever test
equipment the user wishes to perform the intended tests.
Referring to the schematic in Figure 30, inputs to the multiplier are
differential and dc-coupled. Three-position slide switches enhance
flexibility by enabling the multiplier inputs to be connected to
an active signal source, to ground, or to a test loop connected
directly to the device pin for direct measurements, such as bias
current. Inputs may be connected single ended or differentially,
but must have a dc path to ground for bias current. If an input
source’s impedance is non-zero, an equal value impedance must
be connected to the opposite polarity input to avoid introducing
additional offset voltage.
Figure 25. Circuit Side Copper
The AD633-EVALZ can be configured for multiplier or divider
operation by switch S1. Refer to Figure 15 for divider circuit
connections.
Figure 24 through Figure 27 are the signal, power, and ground-
plane artworks, and Figure 28 shows the component and circuit
side silkscreen. Figure 29 shows the assembly.
Figure 26. Inner Layer Ground Plane
Rev. I | Page 1± of 16
Data Sheet
AD633
Figure 27. Inner Layer Power Plane
Figure 29. AD633-EVALZ Assembly
Figure 28. Component Side Silk Screen
G1
G2
G3
G4
G5
G6
+V
GND
–V
–V
C5
+
C6
10µF
25V
10µF
+
25V
+V
Y1_IN
X2_IN
X2_TP
D
FUNCT(1)
IN
IN
SEL_Y1
SEL_Y2
GND
GND
SEL_X1
M
TEST
TEST
IN
Y1_TP
Y1
Y2_IN
X1_IN (DENOM)
Y2_TP
X1_TP
1
2
8
7
IN
X2
X1
GND
GND
SEL_X2
1
Y2
Z1
TEST
+V
TEST
AD633ARZ
S
R1
100Ω
3
4
6
5
–V
+V
S
–V
S
C3
0.1µF
Z
W
C2
0.1µF
C1
0.1µF
7
3
Z_IN
Z_TP
6
R2
10kΩ
IN
D
2
SEL_Z
GND
TEST
4
MULTIPLICATION:
[(X1-X2)(Y1-Y2)/10V] + Z
DIVISION:
FUNCT(2)
C4
0.1µF
M
R3
10kΩ
NOM_TP
–10V (NUM/DENOM)
D
NUMERATOR
NOTES
1. Z1 TO HAVE DUAL FOOTPRINT FOR
SOLDER MOUNT OR THRUHOLE SOCKET.
FUNCT(3)
OUT
M
OUT_TP
Figure 30. Schematic of the AD633 Evaluation Board
Rev. I | Page 13 of 16
AD633
Data Sheet
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 31. 8-Lead Plastic Dual-in-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 32. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. I | Page 14 of 16
Data Sheet
AD633
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
AD633ANZ
AD633ARZ
AD633ARZ-R7
AD633ARZ-RL
AD633JN
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
8-Lead Plastic Dual-in-Line Package [PDIP]
N-8
R-8
R-8
R-8
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel
8-Lead Plastic Dual-in-Line Package [PDIP]
AD633JNZ
AD633JR
8-Lead Plastic Dual-in-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel
Evaluation Board
AD633JR-REEL
AD633JR-REEL7
AD633JRZ
AD633JRZ-R7
AD633JRZ-RL
AD633-EVALZ
0°C to 70°C
0°C to 70°C
0°C to 70°C
1 Z = RoHS Compliant Part.
Rev. I | Page 15 of 16
AD633
NOTES
Data Sheet
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00786-0-2/12(I)
Rev. I | Page 16 of 16
相关型号：
AD633ARZ-REEL
IC ANALOG MULTIPLIER OR DIVIDER, 1 MHz BAND WIDTH, PDSO8, PLASTIC, MS-012AA, SOIC-8, Analog Computational Function
ADI
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