AD630B [ADI]
Balanced Modulator/Demodulator; 平衡调制器/解调器
| 型号： | AD630B |
| 厂家： | 
ADI |
| 描述： | Balanced Modulator/Demodulator |
| 文件： | 总8页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
Balanced Modulator/Demodulator
AD630
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Recovers Signal from +100 dB Noise
2 MHz Channel Bandwidth
45 V/s Slew Rate
CM OFF
ADJ
6
CM OFF DIFF OFF
DIFF OFF
ADJ
ADJ
5
ADJ
4
3
2.5k⍀
–120 dB Crosstalk @ 1 kHz
1
R
A
AD630
IN
AMP A
AMP B
Pin Programmable Closed Loop Gains of ؎1 and ؎2
0.05% Closed Loop Gain Accuracy and Match
100 V Channel Offset Voltage (AD630BD)
350 kHz Full Power Bandwidth
Chips Available
2
12
11
CHA+
CHA–
COMP
20
+V
S
A
B
2.5k⍀
R
B
17
IN
13
V
OUT
10k⍀
CHB+ 18
CHB– 19
10k⍀
–V
14
15
R
B
F
R
R
5k⍀
16
7
A
PRODUCT DESCRIPTION
CHANNEL
STATUS
B/A
COMP
The AD630 is a high precision balanced modulator which com-
bines a flexible commutating architecture with the accuracy and
temperature stability afforded by laser wafer trimmed thin-film
resistors. Its signal processing applications include balanced
modulation and demodulation, synchronous detection, phase
detection, quadrature detection, phase sensitive detection,
lock-in amplification and square wave multiplication. A network
of on-board applications resistors provides precision closed loop
gains of 1 and 2 with 0.05% accuracy (AD630B). These
resistors may also be used to accurately configure multiplexer
gains of +1, +2, +3 or +4. Alternatively, external feedback may
be employed allowing the designer to implement his own high
gain or complex switched feedback topologies.
9
SEL B
10
SEL A
8
–V
S
PRODUCT HIGHLIGHTS
1. The configuration of the AD630 makes it ideal for signal
processing applications such as: balanced modulation and
demodulation, lock-in amplification, phase detection, and
square wave multiplication.
2. The application flexibility of the AD630 makes it the best
choice for many applications requiring precisely fixed gain,
switched gain, multiplexing, integrating-switching functions,
and high-speed precision amplification.
The AD630 may be thought of as a precision op amp with two
independent differential input stages and a precision comparator
which is used to select the active front end. The rapid response
time of this comparator coupled with the high slew rate and fast
settling of the linear amplifiers minimize switching distortion. In
addition, the AD630 has extremely low crosstalk between chan-
nels of –100 dB @ 10 kHz.
3. The 100 dB dynamic range of the AD630 exceeds that of any
hybrid or IC balanced modulator/demodulator and is compa-
rable to that of costly signal processing instruments.
4. The op-amp format of the AD630 ensures easy implementa-
tion of high gain or complex switched feedback functions.
The application resistors facilitate the implementation of
most common applications with no additional parts.
The AD630 is intended for use in precision signal processing
and instrumentation applications requiring wide dynamic range.
When used as a synchronous demodulator in a lock-in amplifier
configuration, it can recover a small signal from 100 dB of inter-
fering noise (see lock-in amplifier application). Although optimized
for operation up to 1 kHz, the circuit is useful at frequencies up
to several hundred kilohertz.
5. The AD630 can be used as a two channel multiplexer with
gains of +1, +2, +3 or +4. The channel separation of
100 dB @ 10 kHz approaches the limit which is achievable
with an empty IC package.
6. The AD630 has pin-strappable frequency compensation (no
external capacitor required) for stable operation at unity gain
without sacrificing dynamic performance at higher gains.
Other features of the AD630 include pin programmable frequency
compensation, optional input bias current compensation resis-
tors, common-mode and differential-offset voltage adjustment,
and a channel status output which indicates which of the two
differential inputs is active. This device is now available to Stan-
dard Military Drawing (DESC) numbers 5962-8980701RA and
5962-89807012A.
7. Laser trimming of comparator and amplifying channel offsets
eliminates the need for external nulling in most cases.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(@ + 25؇C and ؎V = ؎15 V unless otherwise noted)
AD630–SPECIFICATIONS
S
Model
AD630J/A
AD630K/B
Typ
AD630S
Typ
Min
Typ
Max
Min
100
Max
Min
90
Max
Unit
GAIN
Open Loop Gain
90
110
0.1
0.1
2
120
2
110
0.1
0.1
2
dB
%
%
ppm/°C
1, 2 Closed Loop Gain Error
Closed Loop Gain Match
Closed Loop Gain Drift
0.05
0.05
CHANNEL INPUTS
VIN Operational Limit1
Input Offset Voltage
Input Offset Voltage
TMIN to TMAX
Input Bias Current
Input Offset Current
Channel Separation @ 10 kHz
(–VS + 4 V) to (+VS – 1 V)
(–VS + 4 V) to (+VS – 1 V)
(–VS + 4 V) to (+VS – 1 V)
Volts
µV
500
100
500
800
160
1000
µV
nA
nA
dB
100
10
300
50
100
10
300
50
100
10
300
50
100
100
100
COMPARATOR
VIN Operational Limit1
Switching Window
Switching Window
TMIN to TMAX
Input Bias Current
(–VS + 3 V) to (+VS – 1.5 V) (–VS + 3 V) to (+VS – 1.5 V)
(–VS + 3 V) to (+VS – 1.3 V)
Volts
mV
؎1.5
؎1.5
؎1.5
2
؎2.0
؎2.0
؎2.5
mV
nA
ns
100
200
300
100
200
300
100
200
300
Response Time (–5 mV to +5 mV Step)
Channel Status
I
SINK @ VOL = –VS + 0.4 V3
1.6
1.6
1.6
mA
Pull-Up Voltage
(–VS + 33 V)
(–VS + 33 V)
(–VS + 33 V) Volts
DYNAMIC PERFORMANCE
Unity Gain Bandwidth
Slew Rate4
2
45
3
2
45
3
2
45
3
MHz
V/µs
µs
Settling Time to 0.1% (20 V Step)
OPERATING CHARACTERISTICS
Common-Mode Rejection
Power Supply Rejection
Supply Voltage Range
85
90
؎5
105
110
90
90
؎5
110
110
90
90
؎5
110
110
dB
dB
Volts
mA
16.5
5
16.5
5
16.5
Supply Current
4
4
4
5
OUTPUT VOLTAGE, @ RL = 2 kΩ
2
T
MIN to TMAX
؎10
؎10
10
Volts
mA
Output Short Circuit Current
25
25
25
TEMPERATURE RANGES
Rated Performance–N Package
Rated Performance–D Package
0
–25
+70
+85
0
–25
+70
+85
N/A
°C
°C
–55
+125
NOTES
1If one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply.
2These parameters are guaranteed but not tested for J and K grades. For A, B and S grades they are tested.
3ISINK @ VOL = (–VS + 1) volt is typically 4 mA.
4Pin 12 Open. Slew rate with Pins 12 and 13 shorted is typically 35 V/µs.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 600 mW
Output Short Circuit to Ground . . . . . . . . . . . . . . . . Indefinite
Storage Temperature, Ceramic Package . . . . –65°C to +150°C
Storage Temperature, Plastic Package . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering, 10 sec ) . . . . . . . +300°C
Max Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Temperature
Ranges
Package
Descriptions Options
Package
Model
AD630JN
AD630KN
AD630AD
AD630BD
AD630SD
0°C to +70°C
0°C to +70°C
Plastic DIP
Plastic DIP
N-20
N-20
–25°C to +85°C Side Brazed DIP D-20
–25°C to +85°C Side Brazed DIP D-20
–55°C to +125°C Side Brazed DIP D-20
THERMAL CHARACTERISTICS
AD630SD/883B –55°C to +125°C Side Brazed DIP D-20
5962-8980701RA –55°C to +125°C Side Brazed DIP D-20
θJC
θJA
AD630SE/883B –55°C to +125°C LCC
5962-89807012A –55°C to +125°C LCC
E-20A
E-20A
20-Pin Plastic DIP (N)
20-Pin Ceramic DIP (D)
20-Pin Leadless Chip Carrier (E)
24°C/W
35°C/W
35°C/W
61°C/W
120°C/W
120°C/W
AD630JCHIPS
0°C to +70°C
Chip
AD630SCHIPS –55°C to +125°C Chip
–2–
REV. C
AD630
PIN CONFIGURATIONS
CHIP METALIZATION AND PINOUT
Dimensions shown in inches and (mm).
Contact factory for latest dimensions
20-Lead DIP (D-20 and N-20)
R
A
CH A–
20
1
2
IN
CH A+
19 CH B–
CH B+
3
18
17
16
15
14
13
DIFF OFF ADJ
DIFF OFF ADJ
CM OFF ADJ
4
R
R
B
IN
5
AD630
A
TOP VIEW
6
R
R
CM OFF ADJ
F
(Not to Scale)
7
CHANNEL STATUS B/A
B
–V
8
V
S
OUT
SEL B
SEL A
12 COMP
11
9
10
+V
S
20-Contact LCC (E-20A)
3
2
1 20 19
4
5
DIFF OFF ADJ
CM OFF ADJ
18 CH B+
CHIP AVAILABILITY
17
R
B
IN
The AD630 is available in laser trimmed, passivated chip form.
The figure shows the AD630 metalization pattern, bonding pads
and dimensions. AD630 chips are available; consult factory for
details.
AD630
CM OFF ADJ 6
16
15
R
R
R
A
TOP VIEW
(Not to Scale)
CHANNEL STATUS B/A 7
F
–V
8
14
B
S
9
10 11 12 13
Typical Performance Characteristics
15
10
5
15
10
5
18
5k⍀
5k⍀
V
15
10
5
i
V
O
R
C
= 2k⍀
= 100pF
C
= 100pF
f = 1kHz
L
L
L
2k⍀
100pF
5k⍀
5k⍀
V
i
5k⍀ 5k⍀
V
V
i
O
V
O
2k⍀
100pF
R
L
f = 1kHz
100pF
C
= 100pF
CAP IN
L
0
5
10
15
1
100
1k
10k 100k 1M
1k
10k
100k
1M
10
SUPPLY VOLTAGE – ؎V
RESISTIVE LOAD – ⍀
FREQUENCY – Hz
Figure 2. Output Voltage vs.
Resistive Load
Figure 3. Output Voltage Swing
vs. Supply Voltage
Figure 1. Output Voltage vs.
Frequency
120
100
80
0
120
100
60
UNCOMPENSATED
40
UNCOMPENSATED
45
90
80
60
40
20
20
0
60
COMPENSATED
COMPENSATED
–20
40
135
180
–40
20
0
–60
0
10
100
1k
10k 100k 1M 10M
0
1
2
3
4
5
1
10
100
1k
10k
100k
–5 –4 –3 –2 –1
FREQUENCY – Hz
FREQUENCY – Hz
INPUT VOLTAGE – V
dVO
Figure 4. Common-Mode
Rejection vs. Frequency
Figure 6. Gain and Phase vs.
Frequency
Figure 5.
vs. Input Voltage
dt
–3–
REV. C
AD630
–Typical Performance Characteristics
50mV
1mV
20mV
10V
5s
1mV
100
90
100
90
100
90
50mV/DIV
؎10V 20kHz
(V )
i
(V )
i
20mV/DIV
(V )
o
1mV/DIV
(A)
1mV/DIV
(B)
20mV/DIV
10V/DIV
10
10
10
(V )
0%
(V )
i
0%
0%
o
100mV/DIV
500ns
100mV
(V )
500ns
20mV
10V
TOP TRACE: V
MIDDLE TRACE: SETTLING
ERROR (B)
BOTTOM TRACE: V
o
TOP TRACE: V
TOP TRACE: V
BOTTOM TRACE: V
i
o
i
MIDDLE TRACE: SETTLING
ERROR (A)
BOTTOM TRACE: V
i
15
16
o
o
5k⍀
10k⍀
2
10k⍀
CH
A
10k⍀
20
19
18
V
O
13
12
10k⍀
1k⍀
V
i
TOP
TRACE
15
20
2
14
14
10k⍀
15
20
2
V
O
V
O
13
13
V
i
TOP
TRACE
CH
B
CH A
12
BOTTOM
TRACE
CH A
12
BOTTOM
TRACE
10k⍀
10k⍀
10k⍀
10k⍀
MIDDLE
TRACE
(A)
10k⍀
(B)
MIDDLE
TRACE
14
9
V
i
30pF
HP5082-2811
TEKTRONIX
7A13
10
Figure 9. Large Signal Inverting
Step Response
Figure 7. Channel-to-Channel Switch-
Settling Characteristic
Figure 8. Small Signal Noninverting
Step Response
TWO WAYS TO LOOK AT THE AD630
R
5k⍀
The functional block diagram of the AD630 (see page 1) also
shows the pin connections of the internal functions. An alternative
architectural diagram is shown in Figure 10. In this diagram, the
individual A and B channel preamps, the switch, and the inte-
grator output amplifier are combined in a single op amp. This
amplifier has two differential input channels, only one of which
is active at a time.
A
16
15
V
i
R
10k⍀
F
2
A
B
20
V
O
19
18
13
R
B
10k⍀
+V
S
14
9
11
15
14
16
1
10
R
5k⍀
R
B
10k⍀
A
Figure 11. AD630 Symmetric Gain ( 2)
2.5k⍀
R
2
F
A
B
10k⍀
20
19
18
When channel B is selected, the resistors RA and RF are con-
nected for inverting feedback as shown in the inverting gain
configuration diagram in Figure 12. The amplifier has sufficient
loop gain to minimize the loading effect of RB at the virtual
ground produced by the feedback connection. When the sign of
the comparator input is reversed, input B will be deselected and
A will be selected. The new equivalent circuit will be the nonin-
verting gain configuration shown below. In this case RA will appear
across the op-amp input terminals, but since the amplifier drives
this difference voltage to zero the closed loop gain is unaffected.
13
12
7
2.5k⍀
17
B/A
9
SEL B
SEL A
10
8
–V
S
Figure 10. Architectural Block Diagram
HOW THE AD630 WORKS
The two closed loop gain magnitudes will be equal when RF/RA
= 1 + RF/RB, which will result from making RA equal to RFRB/
(RF + RB) the parallel equivalent resistance of RF and RB.
The basic mode of operation of the AD630 may be more easy to
recognize as two fixed gain stages which may be inserted into the
signal path under the control of a sensitive voltage comparator.
When the circuit is switched between inverting and noninverting
gain, it provides the basic modulation/demodulation function. The
AD630 is unique in that it includes Laser-Wafer-Trimmed thin-
film feedback resistors on the monolithic chip. The configuration
shown in Figure 11 yields a gain of 2 and can be easily changed to
1 by shifting RB from its ground connection to the output.
The 5k and the two 10k resistors on the AD630 chip can be
used to make a gain of two as shown here. By paralleling the
10k resistors to make RF equal 5k and omitting RB the circuit
can be programmed for a gain of 1 (as shown in Figure 18a).
These and other configurations using the on chip resistors
present the inverting inputs with a 2.5k source impedance. The
more complete AD630 diagrams show 2.5k resistors available at
the noninverting inputs which can be conveniently used to mini-
mize errors resulting from input bias currents.
The comparator selects one of the two input stages to complete
an operational feedback connection around the AD630. The
deselected input is off and has negligible effect on the operation.
–4–
REV. C
AD630
R
10k⍀
faster the output signal will move. This feature helps insure
rapid, symmetric settling when switching between inverting and
noninverting closed loop configurations.
F
R
5k⍀
A
V
i
R
R
R
F
B
V
= –
V
The output section of the AD630 includes a current mirror-load
(Q24 and Q25), an integrator-voltage gain stage (Q32), and
complementary output buffer (Q44 and Q74). The outputs of
both transconductance stages are connected in parallel to the
current mirror. Since the deselected input stage produces no
output current and presents a high impedance at its outputs,
there is no conflict. The current mirror translates the differential
output current from the active input transconductance amplifier
into single ended form for the output integrator. The comple-
mentary output driver then buffers the integrator output pro-
duce a low impedance output.
O
i
10k⍀
A
Figure 12. Inverting Gain Configuration
V
i
R
R
F
R
5k⍀
A
V
= (1+
)
V
i
O
B
R
R
B
10k⍀
F
10k⍀
OTHER GAIN CONFIGURATIONS
Figure 13. Noninverting Gain Configuration
CIRCUIT DESCRIPTION
Many applications require switched gains other than the 1 and
2 which the self-contained applications resistors provide. The
AD630 can be readily programmed with three external resistors
over a wide range of positive and negative gain by selecting and
RB and RF to give the noninverting gain 1 + RF/RB and subsequent
RA to give the desired inverting gain. Note that when the inverting
magnitude equals the noninverting magnitude, the value of RA is
found to be RB RF/(RB + RF). That is, RA should equal the parallel
combination of RB and RF to match positive and negative gain.
The simplified schematic of the AD630 is shown in Figure 14.
It has been subdivided into three major sections, the comparator,
the two input stages and the output integrator. The comparator
consists of a front end made up of Q52 and Q53, a flip-flop load
formed by Q3 and Q4, and two current steering switching cells
Q28, Q29 and Q30, Q31. This structure is designed so that a
differential input voltage greater than 1.5 mV in magnitude
applied to the comparator inputs will completely select one the
switching cells. The sign of this input voltage determine which
of the two switching cells is selected.
The feedback synthesis of the AD630 may also include reactive
impedance. The gain magnitudes will match at all frequencies if
the A impedance is made to equal the parallel combination of
the B and F impedances. Essentially the same considerations
apply to the AD630 as to conventional op-amp feedback circuits.
Virtually any function which can be realized with simple nonin-
verting “L network” feedback can be used with the AD630. A
common arrangement is shown in Figure 15. The low frequency
gain of this circuit is 10. The response will have a pole (–3 dB)
at a frequency f Ӎ 1/(2 π 100 kΩC) and a zero (3 dB from the
high frequency asymptote) at about 10 times this frequency.
The 2k resistor in series with each capacitor mitigates the load-
ing effect on circuitry driving this circuit, eliminates stability
problems, and has a minor effect on the pole-zero locations.
CH A+ CH B+
CH A–
CH B–
20
19
2
18
11
+V
S
Q35
Q33
Q36
Q34
i73
i55
Q44
SEL A
10
Q53
Q62
Q52
Q65
Q67
Q70
13
V
O
9
Q74
C121
SEL B
12
Q30
COMP
Q31
C122
Q25
Q28
i22
3
Q32
Q29
As a result of the reactive feedback, the high frequency components
of the switched input signal will be transmitted at unity gain
Q24
i23
Q4
Q3
C
C
2k⍀
2k⍀
8
–V
S
5
4
6
10k⍀
100k⍀
V
i
DIFF
OFF ADJ
DIFF
OFF ADJ
CM
CM
OFF ADJ OFF ADJ
2
Figure 14. AD630 Simplified Schematic
A
B
20
13
V
O
19
18
The collectors of each switching cell connect to an input trans-
conductance stage. The selected cell conveys bias currents i22
and i23 to the input stage it controls, causing it to become active.
The deselected cell blocks the bias to its input stage which, as a
consequence, remains off.
12
11.11k⍀
7
9
10
8
–V
The structure of the transconductance stages is such that they
present a high impedance at their input terminals and draw no
bias current when deselected. The deselected input does not
interfere with the operation of the selected input insuring maxi-
mum channel separation.
S
Figure 15. AD630 with External Feedback
while the low frequency components will be amplified. This
arrangement is useful in demodulators and lock-in amplifiers. It
increases the circuit dynamic range when the modulation or
interference is substantially larger than the desired signal ampli-
tude. The output signal will contain the desired signal multi-
plied by the low frequency gain (which may be several hundred
for large feedback ratios) with the switching signal and interfer-
ence superimposed at unity gain.
Another feature of the input structure is that it enhances the
slew rate of the circuit. The current output of the active stage
follows a quasi-hyperbolic-sine relationship to the differential
input voltage. This means that the greater the input voltage, the
harder this stage will drive the output integrator, and hence, the
REV. C
–5–
AD630
SWITCHED INPUT IMPEDANCE
because the open collector channel status output inverts the
output sense of the internal comparator.
The noninverting mode of operation is a high input impedance
configuration while the inverting mode is a low input impedance
configuration. This means that the input impedance of the
circuit undergoes an abrupt change as the gain is switched un-
der control of the comparator. If gain is switched when the
input signal is not zero, as it is in many practical cases, a tran-
sient will be delivered to the circuitry driving the AD630. In
most applications, this will require the AD630 circuit to be
driven by a low impedance source which remains “stiff “ at high
frequencies. Generally this will be a wideband buffer amplifier.
+5V
100k⍀
1M⍀
100k⍀
9
7
10
8
–15V
100⍀
FREQUENCY COMPENSATION
Figure 16. Comparator Hysteresis
The AD630 combines the convenience of internal frequency
compensation with the flexibility of external compensation by
means of an optional self-contained compensation capacitor.
The channel status output may be interfaced with TTL inputs
as shown in Figure 17. This circuit provides appropriate level
shifting from the open-collector AD630 channel status output to
TTL inputs.
In gain of 2 applications the noise gain which must be addressed
for stability purposes is actually 4. In this circumstance, the
phase margin of the loop will be on the order of 60° without the
optional compensation. This condition provides the maximum
bandwidth and slew-rate for closed-loop gains of |2| and above.
+5V
+15V
100k⍀
22k⍀
6.8k⍀
When the AD630 is used as a multiplexer, or in other configura-
tions where one or both inputs are connected for unity gain
feedback, the phase margin will be reduced to less than 20°.
This may be acceptable in applications where fast slewing is a
first priority, but the transient response will not be optimum.
For these applications, the self-contained compensation capaci-
tor may be added by connecting Pin 12 to Pin 13. This connec-
tion reduces the closed loop bandwidth somewhat, and improves
the phase margin.
IN914's
AD630
7
TTL INPUT
2N2222
8
–15V
Figure 17. Channel Status—TTL Interface
APPLICATIONS: BALANCED MODULATOR
Perhaps the most commonly used configuration of the AD630 is
the balanced modulator. The application resistors provide pre-
cise symmetric gains of 1 and 2. The 1 arrangement is
shown in Figure 18a and the 2 arrangement is shown in Figure
18b. These cases differ only in the connection of the 10k feed-
back resistor (Pin 14) and the compensation capacitor (Pin 12).
Note the use of the 2.5 kΩ bias current compensation resistors
in these examples. These resistors perform the identical function
in the 1 gain case. Figure 19 demonstrates the performance of
the AD630 when used to modulate a 100 kHz square wave
carrier with a 10 kHz sinusoid. The result is the double side-
band suppressed carrier waveform.
For intermediate conditions, such as gain of 1 where loop
attenuation is 2, use of the compensation should be determined
by whether bandwidth or settling response must be optimized.
The optional compensation should also be used when the AD630
is driving capacitive loads or whenever conservative frequency
compensation is desired.
OFFSET VOLTAGE NULLING
The offset voltages of both input stages and the comparator
have been pretrimmed so that external trimming will only be
required in the most demanding applications. The offset adjust-
ment of the two input channels is accomplished by means of a
differential and common-mode scheme. This facilitates fine
adjustment of system errors in switched gain applications. With
system input tied to 0 V, and a switching or carrier waveform
applied to the comparator, a low level square wave will appear at
the output. The differential offset adjustment pot can be used
to null the amplitude of this square wave (Pins 3 and 4). The
common-mode offset adjustment can be used to zero the re-
sidual dc output voltage (Pins 5 and 6). These functions should
be implemented using 10k trim pots with wipers connected
directly to Pin 8 as shown in Figures 18a and 18b.
These balanced modulator topologies accept two inputs, a signal
(or modulation) input applied to the amplifying channels, and a
reference (or carrier) input applied to the comparator.
10k⍀
10k⍀
DIFF
ADJ
CM
ADJ
6
4
3
5
2.5k⍀
2.5k⍀
MODULATION
INPUT
1
2
AMP A
12
11
13
A
+V
S
20
B
CHANNEL STATUS OUTPUT
10k⍀
MODULATED
OUTPUT
SIGNAL
17
18
AMP B
14
15
16
The channel status output, Pin 7, is an open collector output
referenced to –VS which can be used to indicate which of the
two input channels is active. The output will be active (pulled
low) when Channel A is selected. This output can also be used
to supply positive feedback around the comparator. This pro-
duces hysteresis which serves to increase noise immunity. Figure
16 shows an example of how hysteresis may be implemented.
Note that the feedback signal is applied to the inverting (–)
terminal of the comparator to achieve positive feedback. This is
–V
10k⍀
19
AD630
CARRIER
INPUT
5k⍀
COMP
7
9
10
8
–V
S
Figure 18a. AD630 Configured as a Gain-of-One Balanced
Modulator
–6–
REV. C
AD630
LVDT SIGNAL CONDITIONER
10k⍀
10k⍀
DIFF
ADJ
CM
ADJ
Many transducers function by modulating an ac carrier. A Lin-
ear Variable Differential Transformer (LVDT) is a transducer of
this type. The amplitude of the output signal corresponds to
core displacement. Figure 20 shows an accurate synchronous
demodulation system which can be used to produce a dc voltage
which corresponds to the LVDT core position. The inherent
precision and temperature stability of the AD630 reduce de-
modulator drift to a second order effect.
6
4
3
5
2.5k⍀
2.5k⍀
MODULATION
INPUT
1
2
AMP A
12
11
13
A
+V
S
20
B
10k⍀
MODULATED
OUTPUT
SIGNAL
17
18
AMP B
14
15
16
–V
10k⍀
19
AD630
CARRIER
INPUT
E1000
5k⍀
COMP
AD544
SCHAEVITZ
A
7
AD630
؎2 DEMODULATOR
9
FOLLOWER
16
LVDT
5k⍀
B
10
8
15
10k⍀
2.5k⍀
10k⍀
1
2.5kH
Z
A
B
20
19
–V
C
S
100k⍀
1F
2V p-p
13
D
14
17
SINUSOIDAL
EXCITATION
Figure 18b. AD630 Configured as a Gain-of-Two Balanced
Modulator
12
2.5k⍀
9
PHASE
SHIFTER
5V
20s
5V
10
MODULATION
INPUT
Figure 20. LVDT Signal Conditioner
AC BRIDGE
Bridge circuits which use dc excitation are often plagued by
CARRIER
INPUT
errors caused by thermocouple effects, 1/f noise, dc drifts in the
electronics, and line noise pick-up. One way to get around these
problems is to excite the bridge with an ac waveform, amplify
the bridge output with an ac amplifier, and synchronously de-
modulate the resulting signal. The ac phase and amplitude
information from the bridge is recovered as a dc signal at the
output of the synchronous demodulator. The low frequency
system noise, dc drifts, and demodulator noise all get mixed to
the carrier frequency and can be removed by means of a low-pass
filter. Dynamic response of the bridge must be traded off against
the amount of attenuation required to adequately suppress these
residual carrier components in the selection of the filter.
OUTPUT
SIGNAL
10V
Figure 19. Gain-of-Two Balanced Modulator Sample
Waveforms
BALANCED DEMODULATOR
The balanced modulator topology described above will also act as
a balanced demodulator if a double sideband suppressed carrier
waveform is applied to the signal input and the carrier signal is
applied to the reference input. The output under these circum-
stances will be the baseband modulation signal. Higher order
carrier components will also be present which can be removed
with a low-pass filter. Other names for this function are synchro-
nous demodulation and phase-sensitive detection.
Figure 21 is an example of an ac bridge system with the AD630
used as a synchronous demodulator. The oscilloscope photo-
graph shows the results of a 0.05% bridge imbalance caused by
the 1 Meg resistor in parallel with one leg of the bridge. The top
trace represents the bridge excitation, the upper-middle trace is
the amplified bridge output, the lower-middle trace is the out-
put of the synchronous demodulator and the bottom trace is the
filtered dc system output.
PRECISION PHASE COMPARATOR
The balanced modulator topologies of Figures 18a and 18b can
also be used as precision phase comparators. In this case, an ac
waveform of a particular frequency is applied to the signal input
and a waveform of the same frequency is applied to the refer-
ence input. The dc level of the output (obtained by low-pass
filtering) will be proportional to the signal amplitude and phase
difference between the input signals. If the signal amplitude is
held constant, then the output can be used as a direct indication
of the phase. When these input signals are 90° out of phase, they
are said to be in quadrature and the AD630 dc output will be zero.
This system can easily resolve a 0.5 ppm change in bridge im-
pedance. Such a change will produce a 3.2 mV change in the
low-pass filtered dc output, well above the RTO drifts and noise.
1kHz
BRIDGE
EXCITATION
AD630
A
؎2 DEMODULATOR
16
AD524
GAIN 1000
15
1k⍀
1k⍀
1k⍀
10k⍀
5k⍀
FILTER
5k⍀
A
B
20
2
1k⍀
D
B
2.5
5k⍀ 5k⍀
13
12
k⍀
C
1
2F 2F 2F
1M⍀
PRECISION RECTIFIER-ABSOLUTE VALUE
If the input signal is used as its own reference in the balanced
modulator topologies, the AD630 will act as a precision recti-
fier. The high frequency performance will be superior to that
which can be achieved with diode feedback and op amps. There
are no diode drops which the op amp must “leap over” with the
commutating amplifier.
17
2.5
k⍀
10k⍀
14
PHASE
SHIFTER
9
10
Figure 21. AC Bridge System
REV. C
–7–
AD630
to Figure 18b and is shown in the upper trace of Figure 24. It is
attenuated 100,000 times normalized to the output, B, of the
summing amplifier. A noise signal which might represent, for
example, background and detector noise in the chopped radia-
tion case, is added to the modulated signal by the summing
amplifier. This signal is simply band limited clipped white noise.
Figure 24 shows the sum of attenuated signal plus noise in the
center trace. This combined signal is demodulated synchro-
nously using phase information derived from the modulator,
and the result is low-pass filtered using a 2-pole simple filter
which also provides a gain of 100 to the output. This recovered
signal is the lower trace of Figure 24.
20V
200s
5V
BRIDGE EXCITATION
(20V/DIV) (A)
100
0V
90
AMPLIFIED BRIDGE
OUTPUT (5V/DIV) (B)
0V
DEMODULATED BRIDGE
OUTPUT (5V/DIV) (C)
10
0V
0%
FILTER OUTPUT (2V/DIV) (D)
5V
2V
0V
Figure 22. AC Bridge Waveforms
The combined modulated signal and interfering noise used for
this illustration is similar to the signals often requiring a lock-in
amplifier for detection. The precision input performance of the
AD630 provides more than 100 dB of signal range and its dy-
namic response permits it to be used with carrier frequencies
more than two orders of magnitude higher than in this example.
A more sophisticated low-pass output filter will aid in rejecting
wider bandwidth interference.
LOCK-IN AMPLIFIER APPLICATIONS
Lock-in amplification is a technique which is used to separate a
small, narrow band signal from interfering noise. The lock-in
amplifiers acts as a detector and narrow band filter combined.
Very small signals can be detected in the presence of large
amounts of uncorrelated noise when the frequency and phase of
the desired signal are known.
The lock-in amplifier is basically a synchronous demodulator
followed by a low-pass filter. An important measure of perfor-
mance in a lock-in amplifier is the dynamic range of its demodu-
lator. The schematic diagram of a demonstration circuit which
exhibits the dynamic range of an AD630 as it might be used in a
lock-in amplifier is shown in Figure 23. Figure 24 is an oscillo-
scope photo showing the recovery of a signal modulated at
400 Hz from a noise signal approximately 100,000 times larger;
a dynamic range of 100 dB.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Ceramic DIP (D-20)
CLIPPED
C
BAND-LIMITED
WHITE NOISE
AD630
B
5k⍀
16
1
100R
15
10k⍀
AD542
2.5k⍀
AD542
A
B
20
19
13
R
2.5k⍀
17
100R
C
100dB
20-Lead Plastic DIP (N-20)
ATTENUATION
14 10k⍀
OUTPUT
A
10
9
LOW PASS
FILTER
0.1Hz
MODULATED
400Hz
CARRIER
PHASE
CARRIER
REFERENCE
Figure 23. Lock-In Amplifier
5V
5s
5V
100
90
MODULATED SIGNAL (A)
(UNATTENUATED)
LCC (E-20A)
ATTENUATED SIGNAL
PLUS NOISE (B)
0.200 (5.08)
BSC
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.100
(2.54)
BSC
0.015 (0.38)
MIN
10
0%
OUTPUT
0.095 (2.41)
0.075 (1.90)
5mV
0.028 (0.71)
0.022 (0.56)
0.358 (9.09)
0.342 (8.69)
20
1
SQ
0.358
(9.09)
MAX
SQ
0.011 (0.28)
0.007 (0.18)
R TYP
Figure 24. Lock-In Amplifier Waveforms
BOTTOM
VIEW
0.050
(1.27)
BSC
The test signal is produced by modulating a 400 Hz carrier with
a 0.1 Hz sine wave. The signals produced, for example, by
chopped radiation (IR, optical, etc.) detectors may have similar
low frequency components. A sinusoidal modulation is used for
clarity of illustration. This signal is produced by a circuit similar
0.075
(1.91)
REF
13
9
45
TYP
°
0.150
(3.81)
BSC
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
–8–
REV. C
相关型号：
©2020 ICPDF网 联系我们和版权申明