AD5725_技术文档

Quad, 12-Bit, Serial Input,

Unipolar/Bipolar, Voltage Output DAC

AD5726

Bipolar outputs are configured by connecting both V_REFPand

V_REFNto nonzero voltages. This method of setting output voltage

ranges has advantages over the bipolar offsetting methods

because it is not dependent on internal and external resistors

with different temperature coefficients.

FEATURES

+5 V to 15 V operation

Unipolar or bipolar operation

1 ꢀSB maximum INꢀ error, 1 ꢀSB maximum DNꢀ error

Guaranteed monotonic over temperature

Double-buffered inputs

Simultaneous updating via ꢀDAC

Asynchronous CꢀR to zero scale/midscale

Operating temperature range: −40°C to +125°C

iCMOS® process technology¹

The AD5726 uses a serial interface that operates at clock rates up to

30 MHz and is compatible with DꢀP and microcontroller interface

standards. Double buffering allows simultaneous updating of all

CLR

DACs. The asynchronous

function clears all DAC registers

to a user-selectable, zero-scale or midscale output.

The AD5726 is available in 16-lead ꢀꢀOP and 16-lead ꢀOIC

packages. It can be operated from a wide variety of supply and

reference voltages with supplies ranging from single +5 V to

15 V, and references ranging from +2.5 V to 10 V. Power

dissipation is less than 240 mW with 15 V supplies and only

30 mW with a +5 V supply. Operation is specified over the

temperature range of −40°C to +125°C.

APPꢀICATIONS

Industrial automation

Closed-loop servo control, process control

Automotive test and measurement

Programmable logic controllers

GENERAꢀ DESCRIPTION

The AD5726 is a quad, 12-bit, serial input, voltage output

digital-to analog converter that offers guaranteed monotonicity

and integral nonlinearity (INL) of 1 LꢀB maximum.

Table 1. Related Devices

Part No.

Description

AD5725

Quad, 12-bit, parallel input,

Output voltage swing is set by two reference inputs, V_REFPand

unipolar/bipolar, voltage output DAC.

AD5724R/AD5734R/ Complete, quad, 12-/14-/16-bit, serial

V_REFN. The DAC offers a unipolar positive output range when

the V_REFNinput is set to 0 V and the V_REFPinput is set to a positive

voltage. A similar configuration with V_REFPat 0 V and V_REFNat a

negative voltage provides a unipolar negative output range.

AD5754R

input, unipolar/bipolar voltage output

DAC with internal reference.

AD5722R/AD5732R/ Complete, dual, 12-/14-/16-bit, serial

AD5752R

input, unipolar/bipolar voltage output

DAC with internal reference.

FUNCTIONAꢀ BꢀOCK DIAGRAM

AV

V

REFP

SS

DD

12

INPUT

REG A

DAC

DAC A

DAC B

DAC C

DAC D

V

OUTA

OUTB

OUTC

OUTD

I/O

REG A

SDIN

SCLK

CS

REGISTER

AND

CONTROL

LOGIC

INPUT

REG B

DAC

REG B

INPUT

REG C

DAC

REG C

INPUT

REG D

DAC

REG D

AD5726

V

GND

CLR CLRSEL LDAC

REFN

Figure 1.

¹For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology

platform that enables the development of analog ICs capable of 30 V and operating at 15 V supplies while allowing dramatic reductions in power consumption and

package size, and increased ac and dc performance.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

rights of third parties that may result from its use. Specifications subject to change without notice. No

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

AD5726

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 13

DAC Architecture....................................................................... 13

Output Amplifiers...................................................................... 13

Reference Inputs......................................................................... 13

ꢀerial Interface............................................................................ 14

Applications..................................................................................... 15

Power-Up ꢀequence ................................................................... 15

Reference Configuration ........................................................... 15

Power ꢀupply Bypassing and Grounding................................ 16

Galvanically Isolated Interface ................................................. 16

Microprocessor Interfacing....................................................... 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

ꢀpecifications..................................................................................... 3

AC Performance Characteristics................................................ 5

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

EꢀD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 12

REVISION HISTORY

4/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

AD5726

SPECIFICATIONS

AV_DD= +5 V 5%, AV_ꢀꢀ= 0 V/−5 V 5%, V_REFP= +2.5 V, V_REFN= 0 V/−2.5 V, R_LOAD= 2 kΩ.

All specifications T_MINto T_MAX, unless otherwise noted.¹

Table 2.

Parameter

Value

Unit

Test Conditions/Comments

ACCURACY

Resolution

Relative Accuracy (INL)

12

1

6

12

10

Bits

LSB max

LSB typ

LSB max

ppm FSR/°C typ

Y grade, AV_SS= −5 V, outputs unloaded

Y grade, AV_SS= 0 V²

Guaranteed monotonic

Differential Nonlinearity (DNL)

Linearity Matching

Zero-Scale Error

Full-Scale Error

Zero-Scale Error

Full-Scale Error

AV_SS= −5 V

AV_SS= 0 V²

AV_SS= −5 V

Zero-Scale TC³

Full-Scale TC³

REFERENCE INPUT

V_REFP

Reference Input Range⁴

V_REFN+ 2.5

AV_DD− 2.5

0.75

V min

V max

mA max

Input Current

V_REFN

Reference Input Range⁴

Typically 0.25 mA

AV_SS= 0 V

AV_SS

V min

0 V

V min

V_REFP− 2.5

−1.0

160

V max

mA max

kHz typ

Input Current

Large Signal Bandwidth³

OUTPUT CHARACTERISTICS³

Output Current

Typically −0.6 mA, AV_SS= −5 V

−3 dB, V_REFP= 0 V to 10 V p-p

1.25

mA max

AV_SS= −5 V

DIGITAL INPUTS

V_IH, Input High Voltage

V_IL, Input Low Voltage

Input Current³

Input Capacitance³

POWER SUPPLY CHARACTERISTICS

Power Supply Sensitivity³

AI_DD

2.4

0.8

10

5

V min

V max

μA max

pF typ

0.002

1.5

%/% max

Typically 0.0004

mA/channel max

mW max

Outputs unloaded, typically 0.75 mA, V_IL= DGND, V_IH= 5 V

Outputs unloaded, typically 15 mW, AV_SS= 0 V

AI_SS

Power Dissipation

30

¹All supplies can be varied 5% and operation is guaranteed. Device is tested with AVDD = 4.75 V.

²For single-supply operation (V_REFN= 0 V, AV_SS= 0 V), due to internal offset errors, INL and DNL are measured beginning at code 0x005.

³Guaranteed by design and characterization, not production tested.

⁴Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

Rev. 0 | Page 3 of 20

AD5726

AV_DD= +15 V 5%, AV_ꢀꢀ= −15 V 5%, V_REFP= +10 V, V_REFN= −10 V, R_LOAD= 2 kΩ. All specifications T_MINto T_MAX, unless otherwise noted.¹

Table 3.

Parameter

Value

Unit

Test Conditions/Comments

ACCURACY

Resolution

12

0.5

1

3

4

Bits

LSB max

ppm FSR/°C typ

Relative Accuracy (INL)

Differential Nonlinearity (DNL)

Linearity Matching

Zero-Scale Error

Full-Scale Error

Zero-Scale TC²

Y grade

Guaranteed monotonic

Full-Scale TC²

REFERENCE INPUT

V_REFP

Reference Input Range³

V_REFN+ 2.5

AV_DD− 2.5

2

V min

V max

mA max

Input Current

V_REFN

Reference Input Range³

Code 0x000, Code 0x555, typically 1 mA

−10 V

V_REFP− 2.5

−3.5

V min

V max

mA min

kHz typ

Input Current²

Large Signal Bandwidth²

OUTPUT CHARACTERISTICS²

Output Current

Code 0x000, Code 0x555, typically −2 mA

−3 dB, V_REFP= 0 V to 2.5 V p-p

450

5

mA max

DIGITAL INPUTS

V_IH, Input High Voltage

V_IL, Input Low Voltage

Input Current²

Input Capacitance²

POWER SUPPLY CHARACTERISTICS

Power Supply Sensitivity²

AI_DD

2.4

0.8

10

5

V min

V max

μA max

pF typ

0.002

2

%/% max

Typically 0.0004

Outputs unloaded, typically 1.25 mA, V_IL= DGND, V_IH= 5 V

mA/channel max

mW max

AI_SS

Power Dissipation

240

¹All supplies can be varied 5% and operation is guaranteed.

²Guaranteed by design and characterization, not production tested.

³Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

Rev. 0 | Page 4 of 20

AD5726

AC PERFORMANCE CHARACTERISTICS

AV_DD= +5 V 5%/+15 V 5%, AV_ꢀꢀ= −5 V 5%/0 V/−15 V 5%, GND = 0 V, V_REFP= +2.5 V/+10 V, V_REFN= −2.5 V/0 V/−10 V,

_LOAD= 2 kΩ. All specifications T_MINto T_MAX, unless otherwise noted.¹

R

Table 4.

Parameter

A Grade

B Grade

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time (t_S)

13

9

2.3

2

100

0.25

90

30

13

9

2.3

2

100

0.25

90

30

μs typ

V/μs typ

dB

nV-sec

kHz

nV-sec

To 0.01%, 10 V voltage swing

To 0.01%, 2.5 V voltage swing, AV_DD= 5 V

10% to 90%, 10 V voltage swing

10% to 90%, 2.5 V voltage swing

Slew Rate

Analog Crosstalk

Digital Feedthrough

Large Signal Bandwidth

Glitch Impulse

3 dB, V_REFP= 5 V +10 Vp-p, V_REFN= −10 V.

Code transition = 0x7FF to 0x800 and vice versa

¹Guaranteed by design and characterization, not production tested.

Rev. 0 | Page 5 of 20

AD5726

TIMING CHARACTERISTICS

AV_DD= +15 V/+5 V, AV_ꢀꢀ= −15 V/−5 V/0 V, GND = 0 V; V_REFP= +10 V/+2.5 V; V_REFN= −10 V/−2.5 V/0 V, V_L= 5 V, R_LOAD= 2 kΩ,

C_L= 200 pF. All specifications T_MINto T_MAX, unless otherwise noted.^{1, 2}

Table 5.

Parameter

ꢀimit at T_MIN, T_MAX

Unit

ns

Description

t_DS

t_DH

t_CH

t_CL

t_CSS

t_CSH

t_LD1

t_LD2

5

Data setup time.

Data hold time.

Clock pulse width high.

Clock pulse width low.

Select time.

Deselect delay.

Load disable time.

Load delay.

13

20

t_LDW

t_CLRW

Load pulse width.

Clear pulse width.

¹Guaranteed by design and characterization, not production tested.

²All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

t_CSH

CS

t_CSS

SDIN

A1

A0

X

D11

D10

D9

D8

D4

D3

D2

D1

D0

SCLK

t_LD1

t_LD2

LDAC

Figure 2. Data Load Sequence

t_DS

t_DH

SDIN

SCLK

CS

t_CH

t_CSH

t_CL

CLRSEL

t_CLRW

t_LD2

t_LDW

CLR

LDAC

t_S

±1LSB

V

OUT

V

±1LSB

OUT

Figure 4. Clear Timing

Figure 3. Data Load Timing

Rev. 0 | Page 6 of 20

AD5726

ABSOLUTE MAXIMUM RATINGS

THERMAꢀ RESISTANCE

T_A= 25°C unless otherwise noted.

Transient currents up to 100 mA do not cause ꢀCR latch-up.

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 6.

Table 7. Thermal Resistance

Parameter

Rating

AV_SSto GND

AV_DDto GND

AV_SSto AV_DD

AV_SSto V_REFN

Current into Any Pin

Digital Input Voltage to GND

Digital Output Voltage to GND

Operating Temperature Range

Industrial

Storage Temperature Range

Junction Temperature (T_Jmax)

Lead Temperature

Soldering

+0.3 V to −17 V

−0.3 V to +17 V

−0.3 V to +34 V

−0.3 V to +AV_SS− 2 V

15 mA

Package Type

16-Lead SSOP

16-Lead SOIC

θ_JA

θ_JC

Unit

°C/W

151

124.9

28

42.9

ESD CAUTION

−0.3 V to +7 V

−40°C to +85°C

−65°C to +150°C

105°C

JEDEC industry standard

J-STD-020

ꢀtresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 7 of 20

AD5726

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AV

1

2

3

4

5

6

7

8

16 CLRSEL

15 CLR

14 LDAC

13 NC

DD

V

OUTD

OUTC

V

AD5726

TOP VIEW

(Not to Scale)

V

REFN

V

12 CS

REFP

11 SCLK

10 SDIN

OUTB

OUTA

V

AV

9

GND

SS

NC = NO CONNECT

Figure 5. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

3

4

AV_DD

V_OUTD

V_OUTC

V_REFN

Positive Analog Supply Pin. Voltage ranges from 5 V to 15 V

Buffered Analog Output Voltage of DAC D.

Buffered Analog Output Voltage of DAC C.

Negative DAC Reference Input. The voltage applied to this pin defines the zero-scale output.

Allowable range is AV_SSto V_REFP− 2.5 V.

5

V_REFP

Positive DAC Reference Input. The voltage applied to this pin defines the full-scale output voltage.

Allowable range is A_VDD− 2.5 V to V_REFN+ 2.5 V.

6

7

8

9

10

11

12

V_OUTB

V_OUTA

AV_SS

GND

SDIN

SCLK

CS

Buffered Analog Output Voltage of DAC B.

Buffered Analog Output Voltage of DAC A.

Negative Analog Supply Pin. Voltage ranges from 0 V to −15 V.

Ground Reference Pin.

Serial Data Input. Data must be valid on the rising edge of SCLK. This input is ignored when CS is high.

Serial Clock Input. Data is clocked into the input register on the rising edge of SCLK.

Active Low Chip Select Pin. This pin must be active for data to be clocked in. This pin is logically OR’ed with

the SCLK input and disables the serial data input when high.

13

14

NC

LDAC

No Internal Connection.

Active Low, Asynchronous Load DAC Input. The data currently contained in the serial input register is

transferred out to the DAC data registers on the falling edge of LDAC, independent of CS. Input data must

remain stable while LDAC is low.

15

16

CLR

Active Low Input. Sets input register and DAC registers to zero-scale (0x000) or midscale (0x800),

depending on the state of CLRSEL. The data in the serial input register is unaffected by this control.

Determines the action of CLR. If high, a clear command sets the internal DAC registers to midscale (0x800).

If low, the registers are set to zero (0x000).

CLRSEL

Rev. 0 | Page 8 of 20

AD5726

TYPICAL PERFORMANCE CHARACTERISTICS

0.4

0.05

0

0.3

+85°C

+25°C

0.2

–40°C

–0.05

–0.10

–0.15

–0.20

–0.25

0.1

0

–0.1

–0.2

AV

= +15V

AV

= 5V

DD

AV = –15V

DD

AV = 0V

SS

–0.3

–0.4

V

= +10V

= –10V

V

T

= 0V

REFP

REFN

= 25°C

A

0

500

1000 1500 2000 2500 3000 3500

DAC (Code)

4000

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

V

(V)

REFP

Figure 6. INL Error vs. DAC Code, V_SUPPLY

=

15 V, V_REFP/V_REFN= 10 V

Figure 9. DNL Error vs. V_REFP, V_SUPPLY= +5 V, V_REFN= 0 V

0.20

0.15

0.10

0.05

0

1.0

0.8

AV

= +15V

+85°C

+25°C

–40°C

DD

AV = –15V

SS

V

= –10V

REFN

= 25°C

A

T

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.05

–0.10

AV

= +15V

DD

AV = –15V

SS

–0.15

–0.20

V

= +10V

= –10V

REFP

REFN

0

500

1000 1500 2000 2500 3000 3500

DAC (Code)

4000

6

7

8

9

10

11

12

V

(V)

REFP

Figure 7. DNL Error vs. DAC Code, V_SUPPLY

= 15 V, V_REFP/V_REFN= 10 V

Figure 10. INL Error vs. V_REFP, V_SUPPLY

=

15 V, V_REFN= −10 V

1.0

0.5

0.4

AV

= +15V

AV

AV = 0V

= 5V

DD

AV = –15V

DD

SS

0.8

0.6

SS

V

T

= –10V

V

T

= 0V

= 25°C

REFN

= 25°C

REFN

A

0.3

0.4

0.2

0.1

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.1

–0.2

–0.3

–0.4

6

7

8

9

10

11

12

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

V

(V)

V

(V)

REFP

Figure 8. DNL Error vs. V_REFP, V_SUPPLY

= 15 V, V_REFN= −10 V

Figure 11. INL Error vs. V_REFP, V_SUPPLY= +5 V, V_REFN= 0 V

Rev. 0 | Page 9 of 20

AD5726

0

0.3

0.2

AV

= +15V

DD

AV = –15V

SS

V

= +10V

= –10V

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

DAC A

DAC B

DAC C

DAC D

REFP

REFN

2kΩ LOAD

0.1

DAC D

0

–0.1

–0.2

–0.3

–0.4

AV

= 5V

DAC C

DD

AV = 0V

DAC B

SS

V

= 2.5V

= 0V

= 25°C

REFP

REFN

DAC A

20

T

A

–40

–20

0

40

60

80

0

500

1000 1500 2000 2500 3000 3500 4000

DAC (Code)

TEMPERATURE (°C)

Figure 12. Full-Scale Error vs. Temperature

Figure 15. Channel-to-Channel Matching, V_SUPPLY= +5 V, V_REFP= 2.5 V, V_REFN= 0 V

0.3

0.2

16

14

12

10

8

AV

= +15V

DD

AV = –15V

SS

V

= +10V

= –10V

REFP

REFN

2kΩ LOAD

0.1

0

DAC A

6

–0.1

–0.2

–0.3

DAC D

4

2

0

AV

= +15V

DD

AV = –15V

DAC C

SS

V

= –10V

REFN

DIGITAL INPUTS HIGH

DAC B

T

= 25°C

A

–40

–20

0

20

40

60

80

–7

–5

–3

–1

1

3

5

7

9

11

13

TEMPERATURE (°C)

V

(V)

REFP

Figure 13. Zero-Scale Error vs. Temperature

Figure 16. AI_DDvs. V_REFP, All DACs Loaded with Full-Scale Code

0.3

0.2

1.7995

1.5995

1.3995

1.1995

0.9995

0.7995

0.5995

0.3995

0.1995

–0.0005

AV

= +15V

V

= +10V

V

= –10V

T = 25°C

A

DD

REFP

REFN

AV = –15V

SS

DAC A

DAC B

DAC C

DAC D

0.1

0

–0.1

–0.2

–0.3

AV

= +15V

DD

AV = –15V

SS

V

= +10V

= –10V

= 25°C

REFP

REFN

T

A

0

500

1000 1500 2000 2500 3000 3500 4000

DAC (Code)

0

500

1000 1500 2000 2500 3000 3500 4000

DAC (Code)

Figure 14. Channel-to-Channel Matching, V_SUPPLY

=

15 V, V_REFP/V_REFN

=

10 V

Figure 17. IV_REFPvs. DAC Code

Rev. 0 | Page 10 of 20

AD5726

2

0

25

20

15

10

5

AV

= 15V

DD

AV = 0V

SS

V

= 10V

= 0V

= 25°C

REFP

REFN

–2

T

A

DATA = 0x800

–4

–6

–8

–10

–12

–14

–16

AV

= +15V

0

DD

AV = –15V

SS

V

= 0V ± 100mV

= –10V

REFP

–5

–10

REFN

FULL-SCALE CODE LOADED

= 25°C

T

A

10

100

1k

10k

100k

1M

10M

0

1

2

3

4

5

6

7

8

9

10

FREQUENCY (Hz)

V

(V)

OUT

Figure 18. Small Signal Response, V_SUPPLY

= 15 V, V_REFN= −10 V

Figure 20. Output Current vs. Output Voltage, V_SUPPLY

=

15 V, V_REFP/V_REFN= 10 V

8

12

AV

= +15V

DD

AV = –15V

I

DD

SS

6

V

= +10V

= –10V

REFP

REFN

10

8

AV

= +15V

DD

AV = –15V

T = 25°C

A

4

2

SS

0

6

–2

–4

–6

–8

4

I

SS

2

0

0.01

–35

–15

5

25

45

65

85

0.1

1

10

100

TEMPERATURE (°C)

LOAD RESISTANCE (kꢀ)

Figure 21. Output Swing vs. Load Resistance, V_SUPPLY

= 15 V, V_REFP/V_REFN= 10 V

Figure 19. Power Supply Currents vs. Temperature,

V_SUPPLY15 V, V_REFP/V_REFN10 V

=

Rev. 0 | Page 11 of 20

AD5726

TERMINOLOGY

Zero-Scale Error TC

Relative Accuracy or Integral Nonlinearity (INL)

This is a measure of the change in zero-scale error with a

change in temperature. Zero-scale error TC is expressed in

ppm FꢀR/°C.

For the DAC, relative accuracy or integral nonlinearity (INL) is

a measure of the maximum deviation, in LꢀBs, from a straight

line passing through the endpoints of the DAC transfer

function. A typical INL vs. code plot can be seen in Figure 6.

Output Voltage Settling Time

Output voltage settling time is the amount of time it takes for the

output to settle to a specified level for a full-scale input change.

Differential Nonlinearity (DNL)

Differential nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LꢀB change between any two

adjacent codes. A specified differential nonlinearity of 1 LꢀB

maximum ensures monotonicity. This DAC is guaranteed

monotonic by design. A typical DNL vs. code plot can be seen

in Figure 7.

Slew Rate

The slew rate of a device is a limitation in the rate of change of

the output voltage. The output slewing speed of a voltage-

output DAC converter is usually limited by the slew rate of the

amplifier used at its output. ꢀlew rate is measured from 10% to

90% of the output signal and is given in V/μs.

Monotonicity

A DAC is monotonic if the output either increases or remains

constant for increasing digital input code. The AD5726 is

monotonic over its full operating temperature range

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital inputs of the

DAC, but is measured when the DAC output is not updated. It

is specified in nV-sec and measured with a full-scale code

change on the data bus.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale

code is loaded to the DAC register. Ideally, the output should be

V_REFP− 1 LꢀB. Full-scale error is expressed in LꢀBs. A plot of

Power Supply Sensitivity

full-scale error vs. temperature can be seen in Figure 12.

Power supply sensitivity indicates how the output of the DAC is

affected by changes in the power supply voltage.

Zero-Scale Error

Zero-scale error is the error in the DAC output voltage when

0x0000 (straight binary coding) is loaded to the DAC register.

Ideally, the output voltage should be V_REFN. A plot of zero-scale

error vs. temperature can be seen in Figure 13.

Analog Crosstalk

This is the dc change in the output level of one DAC in response

to a change in the output of another DAC. It is measured with a

full-scale output change on one DAC while monitoring another

DAC. It is expressed in dB.

Rev. 0 | Page 12 of 20

AD5726

THEORY OF OPERATION

The AD5726 is a quad, 12-bit, serial input, unipolar/bipolar

voltage output DAC. It operates from single-supply voltages of

+5 V to +15 V or dual supply voltages of 5 V to 15 V. The

four outputs are buffered and capable of driving a 2 kΩ load.

Data is written to the AD5726 in a 16-bit word format via a

3-wire serial interface.

symmetric bipolar waveforms, which require an accurate, low

drift bipolar reference. The AD588 provides both voltages and

needs no external components. Additionally, the part is

trimmed in production for 12-bit accuracy over the full

temperature range without user calibration.

AV

DD

DAC ARCHITECTURE

2.5V MIN

V

VREFP

Each of the four DACs is a voltage switched, high impedance

(50 kΩ), R-2R ladder configuration. Each 2R resistor is driven by a

pair of switches that connect the resistor to either V_REFPor V_REFN

0xFFF

.

OUTPUT AMPꢀIFIERS

2.5V MIN

The AD5726 features buffered analog voltage outputs capable of

sourcing and sinking up to 5 mA when operating from 15 V

supplies, eliminating the need for external buffer amplifiers in

most applications while maintaining specified accuracy over the

rated operating conditions. The output amplifiers are short-

circuit protected. The designer should verify that the output

load meets the capabilities of the device, in terms of both output

current and load capacitance. The AD5726 is stable with

capacitive loads up to 2 nF typically. However, any capacitance

load increases the settling time and should be minimized if

speed is a concern.

1 LSB

0x000

–10V MIN

V

VREFN

0V MIN

AV

SS

Figure 22. Output Voltage Range Programming

When driving the reference input, it is important to note that

_REFPboth sinks and sources current, and that the input currents

of both are code dependent. Many voltage reference products

have limited current sinking capabilities and must be buffered

with an amplifier to drive V_REFPto maintain overall system

accuracy. The input V_REFN, however, has no such requirement.

The output stage includes a P-channel MOꢀFET to pull the

output voltage down to the negative supply. This is very

important in single-supply systems where V_REFNusually has the

same potential as the negative supply. With no load, the zero-

scale output voltage in these applications are less than 500 μV

typically, or less than 1 LꢀB when V_REFP= 2.5 V. However, when

sinking current, this voltage does increase because of the finite

impedance of the output stage. The effective value of the pull-

down resistor in the output stage is typically 320 Ω. With a

100 kΩ resistor connected to 5 V, the resulting zero-scale output

voltage is 16 mV. Thus, the best single-supply operation is

obtained with the output load connected to ground, so the

output stage does not have to sink current.

V

For a single 5 V supply, V_REFPis limited to 2.5 V at the most, and

must always be at least 2.5 V less than the positive supply to

ensure linearity of the device. For these applications, the AD780

is an excellent low drift 2.5 V reference. It works well with the

AD5726 in a single 5 V system, as shown in Figure 26.

It is recommended that the reference inputs be bypassed with

0.2 μF capacitors when operating with 10 V references. This

limits the reference bandwidth.

Like all amplifiers, the AD5726 output buffers do generate

voltage noise, 5 nV/rtHz typically. This is easily reduced by

adding a simple RC low-pass filter on each output.

V_REFPInput Requirements

The AD5726 uses a DAC switch driver circuit that compensates

for different supply, reference voltage, and digital code inputs.

This ensures that all DAC ladder switches are always biased

equally, ensuring excellent linearity under all conditions. Thus,

as indicated in the specifications, the V_REFPinput of the AD5726

requires both sourcing and sinking current capability from the

reference voltage source. Many positive voltage references are

intended as current sources only and offer little sinking capability.

The user should consider references such as the AD584, AD586,

AD587, AD588, AD780, and REF43 for such an application.

REFERENCE INPUTS

The two reference inputs of the AD5726 allow a great deal of

flexibility in circuit design. The user must take care, however, to

observe the minimum voltage input levels on V_REFPand V_REFNto

maintain the accuracy shown in the data sheet. These input

voltages can be set anywhere across a wide range within the

supplies, but must be a minimum of 2.5 V apart in any case (see

Figure 22). A wide output voltage range can be obtained with

5 V references that can be provided by the AD588 as shown in

Figure 24. Many applications utilize the DACs to synthesize

Rev. 0 | Page 13 of 20

AD5726

LOAD DAC (

)

LDAC

SERIAꢀ INTERFACE

The AD5726 is controlled over a versatile 3-wire serial interface

that operates at clock rates up to 30 MHz and is compatible with

ꢀPI, QꢀPI™, MICROWIRE™, and DꢀP standards.

LDAC

When asserted, the

pin is an asynchronous, active low,

digital input that transfers the contents of the input register to

the internal data bus, updating the addressed DAC output. New

LDAC

data must not be programmed to the AD5726 while the

pin is low.

Input Shift Register

The input shift register is 16 bits wide. Data is loaded into the

device MꢀB first as a 16-bit word under the control of a serial

clock input ꢀCLK. The input register consists of two address

bits, two don’t care bits, and 12 data bits as shown in Table 11.

The timing diagram for this operation is shown in Figure 2.

and CLRSEL

CLR

The

control allows the user to perform an asynchronous

CLR

clear function. Asserting

loads all four DAC registers,

forcing the DAC outputs to either zero-scale (0x000) or

Cꢀ

When

is low, the data presented to the input ꢀDIN is shifted

midscale (0x800), depending on the state of CLRꢀEL as shown

MꢀB first into the internal shift register on the rising edge of

ꢀCLK. Once all 16 bits of the serial data-word have been input,

the load control LDAC is strobed, and the word is latched onto

the internal data bus. The two address bits are decoded and used to

route the 12-bit data-word to the appropriate DAC data register.

CLR

Cꢀ CLR

of . When

clear value until

registers with either the data held in the input register prior to

the clear or with new data loaded through the serial interface.

in Table 9. The

function is asynchronous and independent

returns high, the DAC outputs remain at the

LDAC

is strobed, reloading the individual DAC

Operation of and SCLK

CS

CLR

Table 9.

CꢀR

/CLRSEL Truth Table

Cꢀ

The

and ꢀCLK pins are internally fed to the same logical OR

CꢀRSEꢀ

DAC Registers

gate and, therefore, require careful attention during a load cycle

to avoid clocking in false data bits. As shown in the timing

diagram in Figure 2, ꢀCLK must be halted high, or

brought high, during the last high portion of ꢀCLK following

the rising edge that clocked in the last data bit. Otherwise, an

0

1

0

1

0

1

Zero-Scale (0x000)

Midscale (0x800)

No Change

Cꢀ

must be

No Change

Cꢀ

additional rising edge is generated by

rising while ꢀCLK is

to act as the clock and allowing a false data bit

Table 10. DAC Address Word Decode Table

Cꢀ

low, causing

A1

A0

DAC Addressed

into the input shift register. The same must also be considered

for the beginning of the data load sequence.

0

1

DAC A

DAC B

1

0

1

DAC C

DAC D

Coding

The AD5726 uses binary coding. The output voltage can be

calculated from the following equation:

(

V_REFP−V_REFN× D

)

V_OUT= V_REFN

+

4096

where D is the digital code in decimal.

Table 11. Input Register Format

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10 DB11 DB12 DB13 DB14 DB15

D5 D4 D3 D2 D1 D0

A1

A0

X

D11

D10

D9

D8

D7

D6

Rev. 0 | Page 14 of 20

AD5726

APPLICATIONS

Figure 24 (symmetrical bipolar operation) shows the AD5726

configured for 10 V operation. ꢀee the AD688 datasheet for a

full explanation of the reference operation.

POWER-UP SEQUENCE

To prevent CMOꢀ latch-up conditions, powering AV_DD, AV_ꢀꢀ,

and GND prior to any reference voltages is recommended. The

ideal power-up sequence is GND, AV_ꢀꢀ, AV_DD, V_REFP, V_REFN, and

the digital inputs. Noncompliance with the power-up sequence

over an extended period can elevate the reference currents and

eventually damage the device. On the other hand, if the non-

compliant power-up sequence condition is as short as a few

milliseconds, the device can resume normal operation without

damage once AV_DD/AV_ꢀꢀare powered up.

Adjustments may not be necessary for many applications

because the AD688 is a very high accuracy reference. However,

if additional adjustments are required, adjust the AD5726 full-

scale first. Begin by loading the digital full-scale code (0xFFF).

Then, modify the gain adjust potentiometer to attain a DAC

output voltage of 9.9976 V. Next, alter the balance adjust to set

the midscale output voltage to 0.000 V.

The 0.2 μF bypass capacitors shown at their reference inputs in

Figure 24 should be used whenever 10 V references are used.

Applications with single references or references to 5 V may

not require the 0.2 μF bypassing. The 6.2 Ω resistor in series

with the output of the reference amplifier keeps the amplifier

from oscillating with the capacitive load. This has been found to

be large enough to stabilize this circuit. Larger resistor values

are acceptable if the drop across the resistor does not exceed a V_BE.

Assuming a minimum V_BEof 0.6 V and a maximum current of

2.75 mA, the resistor should be under 200 Ω for the loading of a

single AD5726.

REFERENCE CONFIGURATION

Output voltage ranges can be configured as either unipolar or

bipolar, and within these choices, a wide variety of options

exists. The unipolar configuration can be either a positive (as

shown in Figure 23) or a negative voltage output. The bipolar

configuration can be either symmetrical (as shown in Figure 24)

or nonsymmetrical.

+15V

+

V

REFP

AV

INPUT

DD

OP1177

Using two separate references is not recommended. Having two

references may cause different drifts with time and temperature,

whereas with a single reference, most drifts track.

OUTPUT

TRIM

0.2µF

AD5726

ADR01

0.1µF║10µF

10kꢀ

V

REFN

Unipolar positive full-scale operation can usually be set by a

reference with the correct output voltage. This is preferable to

using a reference and dividing down to the required value. For a

10 V full-scale output, the circuit can be configured as shown in

Figure 25. In this configuration, the full-scale value is first set by

adjusting the 10 kΩ resistor for a full-scale output of 9.9976 V.

AV

SS

+10V OPERATION

–15V

Figure 23. Unipolar +10 V Operation

+15V

U1

39kꢀ

V

OUT

+15V

IN

+15V

ADR01

TEMP TRIM

6

4

AV

DD

3

1

AV

DD

V

REFP

6.2ꢀ

V

BALANCE

REFP

+15V

12

5

GND

100kꢀ

0.2µF

AD5726

0.1µF║10µF

AD688 FOR ±10V

AD588 FOR ±5V

AD5726

U2

V+

OP1177

V–

0.1µF║10µF

14

15

V

GAIN

100kꢀ

REFN

6.2ꢀ

AV

SS

0.2µF

V

REFN

AV

0.2µF

SS

8

13

7

–15V

0V TO –10V OPERATION

1µF

–15V

±5 OR ±10V OPERATION

Figure 25. Unipolar −10 V Operation

Figure 25 shows the AD5726 configured for −10 V to 0 V opera-

tion. An ADR01 and OP1177 are configured to produce a −10 V

output that is connected directly to V_REFPfor the reference voltage.

Figure 24. Symmetrical Bipolar Operation

Rev. 0 | Page 15 of 20

AD5726

Single +5 V Supply Operation

The ground path (circuit board trace) should be as wide as

possible to reduce any effects of parasitic inductance and ohmic

drops. A ground plane is recommended if possible. The noise

immunity of the on-board digital circuitry, typically in the

hundreds of millivolts, is well able to reject the common-mode

noise typically seen between system analog and digital grounds.

Finally, the analog and digital ground should be connected to

each other at a single point in the system to provide a common

reference. This is preferably done at the power supply

For operation with a 5 V supply, the reference voltage should be

set between 1.0 V and 2.5 V for optimum linearity. Figure 26

shows an AD780 used to supply a 2.5 V reference voltage. The

headroom of the reference and DAC are both sufficient to support

a 5 V supply with 5 V tolerance. AV_DDand V_Lshould be

connected to the same supply. ꢀeparate bypassing to each pin

should be used.

5V

Good grounding practice is essential to maintain analog perform-

ance in the surrounding analog support circuitry as well. With

two reference inputs and four analog outputs capable of moderate

bandwidth and output current, there is a significant potential

for ground loops. Again, a ground plane is recommended as

the most effective solution to minimize errors due to noise and

ground offsets.

10µF

0.01µF

INPUT

AV

DD

V

OUTPUT

TRIM

REFP

0.2µF

AD780

0.1µF║10µF

10kꢀ

AD5726

GND

V

REFN

The AD5726 should have ample supply bypassing located as

close to the package as possible. Recommended capacitor values

are 10 μF in parallel with 0.1 μF. The 0.1 μF capacitor should

have low effective series resistance (EꢀR) and effective series

inductance (EꢀI), such as the common ceramic types, which

provide a low impedance path to ground at high frequencies to

handle transient currents due to internal logic switching.

AV

SS

0V TO 2.5V OPERATION

SINGLE 5V SUPPLY

Figure 26. 5 V Single-Supply Operation

POWER SUPPꢀY BYPASSING AND GROUNDING

In any circuit where accuracy is important, careful consideration

to the power supply and ground return layout helps to ensure

the rated performance. The AD5726 has a single ground pin

that is internally connected to the digital section as the logic

reference level. The user’s first instinct may be to connect this

pin to the digital ground; however, in large systems, the digital

ground is often noisy because of the switching currents of other

digital circuitry. Any noise introduced at the ground pin could

couple into the analog output. Thus, to avoid error-causing

digital noise in the sensitive analog circuitry, the ground pin

should be connected to the system analog ground.

GAꢀVANICAꢀꢀY ISOꢀATED INTERFACE

In many process control applications, it is necessary to provide

an isolation barrier between the controller and the unit being

controlled to protect and isolate the controlling circuitry from any

hazardous common-mode voltages that may occur. Isocouplers

provide voltage isolation in excess of 2.5 kV. The serial loading

structure of the AD5726 makes it ideal for isolated interfaces

because the number of interface lines is kept to a minimum.

Figure 27 shows a 4-channel isolated interface connected to the

AD5726 using an ADuM1400.

MICROCONTROLLER

ADuM1400*

V

IA

OA

OB

OC

OD

TO SCLK

TO SDIN

TO CS

SERIAL CLOCK OUT

SERIAL DATA OUT

ENCODE

DECODE

IB

V

IC

ID

SYNC OUT

V

TO LDAC

CONTROL OUT

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 27. Isolated Interface

Rev. 0 | Page 16 of 20

AD5726

The 8xC51 transmits data in 8-bit bytes with only eight falling

clock edges occurring in the transmit cycle. Because the DAC

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5726 is via a serial bus

that uses standard protocol compatible with microcontrollers

and DꢀP processors. The communications channel is a 3-wire

interface (minimum) consisting of a clock signal, a data signal,

and a synchronization signal. The AD5726 requires a 16-bit

data-word with data valid on the falling edge of ꢀCLK.

Cꢀ

expects a 16-bit word,

(P3.3) must be left low after the first

eight bits are transferred. After the second byte has been

transferred, the P3.3 line is taken high. The DAC can be

LDAC

updated using

via P3.4 of the 8xC51

8xC51*

RxD

AD5726*

SDIN

For all the interfaces, the DAC output update can be done

automatically when all the data is clocked in, or it can be done

TxD

P3.3

P3.4

SCLK

CS

LDAC

under the control of

.

LDAC

MC68HC11 Interface

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 28 shows an example of a serial interface between the

AD5726 and the MC68HC11 microcontroller. The serial

peripheral interface (ꢀPI) on the MC68HC11 is configured for

master mode (MꢀTR = 1); clock polarity bit (CPOL = 0), and

the clock phase bit (CPHA = 1). The ꢀPI is configured by writing

to the ꢀPI control register (ꢀPCR); see the 68HC11 User Manual.

ꢀCK of the MC68HC11 drives the ꢀCLK of the AD5726, the

MOꢀI output drives the serial data line (ꢀDIN) of the AD5726.

Figure 29. 8xC51 to AD5726 Interface

PIC16C6x/7x Interface

The PIC16C6x/7x synchronous serial port (ꢀꢀP) is configured as

an ꢀPI master with the clock polarity bit set to 0. This is done by

writing to the synchronous serial port control register (ꢀꢀPCON).

ꢀee the PIC16/17 Microcontroller User Manual. In this example,

Cꢀ

I/O port RA1 is being used to pulse

and enable the serial

Cꢀ

The

is driven from one of the port lines, in this case PC7.

port of the AD5726. This microcontroller transfers only eight

bits of data during each serial transfer operation; therefore, two

consecutive write operations are needed. Figure 30 shows the

connection diagram.

Cꢀ

When data is being transmitted to the AD5726, the

line

(PC7) is taken low and data is transmitted MꢀB first. Data

appearing on the MOꢀI output is valid on the falling edge of

ꢀCK. Eight falling clock edges occur in the transmit cycle; thus,

to load the required 16-bit word, PC7 is not brought high until

the second 8-bit word has been transferred to the DACs input

shift register.

PIC16C6x/7x*

AD5726*

SDO/RC5

SCLK/RC3

RA1

SDIN

SCLK

CS

MC68HC11*

MOSI

AD5726*

SDIN

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 30. PIC16C6x/7x to AD5726 Interface

SCK

PC7

SCLK

CS

Blackfin® DSP interface

Figure 31 shows how the AD5726 can be interfaced to the

Analog Devices Blackfin DꢀP. The Blackfin has an integrated

ꢀPI port that can be connected directly to the ꢀPI pins of the

AD5726. It also has programmable I/O pins that can be used to

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 28. MC68HC11 to AD5726 Interface

8xC51 Interface

LDAC

set the state of a digital input such as the

pin.

The AD5726 requires a clock synchronized to the serial data.

For this reason, the 8xC51 must be operated in Mode 0. In this

mode, serial data is transferred through RxD, and a shift clock

is output on TxD.

ADSP-BF531

AD5726*

SPISELx

SCK

CS

SCLK

SDIN

LDAC

P3.3 and P3.4 are bit-programmable pins on the serial port and

MOSI

PF10

Cꢀ

LDAC

are used to drive

and , respectively. The 8Cx51 provides

the LꢀB of its ꢀBUF register as the first bit in the data stream. The

user must ensure that the data in the ꢀBUF register is arranged

correctly because the DAC expects MꢀB first. When data is to

be transmitted to the DAC, P3.3 is taken low. Data on RxD is

clocked out of the microcontroller on the rising edge of TxD

and is valid on the falling edge. As a result, no glue logic is

required between this DAC and the microcontroller interface.

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 31. Blackfin DSP to AD5726 Interface

Rev. 0 | Page 17 of 20

AD5726

OUTLINE DIMENSIONS

6.50

6.20

5.90

9

8

16

5.60

5.30

5.00

8.20

7.80

7.40

1

0.25

0.09

1.85

1.75

1.65

2.00 MAX

8°

4°

0°

0.95

0.75

0.55

0.38

0.22

0.05 MIN

SEATING

PLANE

COPLANARITY

0.10

0.65 BSC

COMPLIANT TO JEDEC STANDARDS MO-150-AC

Figure 32. 16-Lead Shrink Small Outline Package [SSOP]

(RS-16)

Dimensions shown in millimeters

10.50 (0.4134)

10.10 (0.3976)

16

9

8

7.60 (0.2992)

7.40 (0.2913)

1

10.65 (0.4193)

10.00 (0.3937)

0.75 (0.0295)

0.25 (0.

0098)

1.27 (0.0500)

BSC

45°

2.65 (0.1043)

2.35 (0.0925)

0.30 (0.0118)

0.10 (0.0039)

8°

0°

COPLANARITY

0.10

SEATING

PLANE

0.51 (0.0201)

0.31 (0.0122)

1.27 (0.0500)

0.40 (0.0157)

0.33 (0.0130)

0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 33. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model

AD5726YRSZ-500RL7¹

AD5726YRSZ-REEL¹

AD5726YRWZ-REEL¹

AD5726YRWZ-REEL7¹

Temperature Range

−40°C to +125°C

Package Description

16-Lead SSOP

16-Lead SOIC_W

Package Option

RS-16

RW-16

¹Z = RoHS Compliant Part.

Rev. 0 | Page 18 of 20

AD5726

NOTES

Rev. 0 | Page 19 of 20

AD5726

NOTES

registered trademarks are the property of their respective owners.

D06469-0-4/07(0)

Rev. 0 | Page 20 of 20


型号：	AD5725
厂家：	ADI
描述：	Quad 12-Bit Serial Input Unipolar/Bipolar Voltage Output DAC 四通道12位串行输入，单极性/双极性电压输出DAC
文件：	总20页 (文件大小：518K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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