AD5721RBRUZ [ADI]
Multiple Range, 12-Bit, Unipolar Voltage Output DACs with 2 PPM/⁰C Reference;
| 型号： | AD5721RBRUZ |
| 厂家： | 
ADI |
| 描述： | Multiple Range, 12-Bit, Unipolar Voltage Output DACs with 2 PPM/⁰C Reference 光电二极管 转换器 |
| 文件： | 总36页 (文件大小：1504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multiple Range, 16-/12-Bit, Bipolar/Unipolar
Voltage Output DACs with 2 ppm/°C Reference
Data Sheet
AD5761R/AD5721R
FEATURES
GENERAL DESCRIPTION
8 software-programmable output ranges: 0 V to +5 V, 0 V to
+10 V, 0 V to +16 V, 0 V to +20 V, 3 V, 5 V, 10 V, and −2.5 V
to +7.5 V; 5% overrange
Low drift 2.5 V reference: 2 ppm/°C typical
Total unadjusted error (TUE): 0.1% FSR maximum
16-bit resolution: 2 LSB maximum INL
Guaranteed monotonicity: 1 LSB maximum
Single channel, 16-/12-bit DACs
The AD5761R/AD5721R are single channel, 16-/12-bit serial
input, voltage output, digital-to-analog converters (DACs).
They operate from single supply voltages from +4.75 V to
+30 V or dual supply voltages from −16.5 V to 0 V VSS and
+4.75 V to +16.5 V VDD. The integrated output amplifier,
reference buffer, and reference provide a very easy to use,
universal solution.
The devices offer guaranteed monotonicity, integral nonlinearity
(INL) of 2 LSB maximum, 35 nV/√Hz noise, and 7.5 μs settling
time on selected ranges.
Settling time: 7.5 μs typical
Integrated reference buffers
Low noise: 35 nV/√Hz
The AD5761R/AD5721R use a serial interface that operates at
clock rates of up to 50 MHz and are compatible with DSP and
microcontroller interface standards. Double buffering allows the
asynchronous updating of the DAC output. The input coding
is user-selectable twos complement or straight binary. The
asynchronous reset function resets all registers to their default
state. The output range is user selectable, via the RA[2:0] bits
in the control register.
Low glitch: 1 nV-sec (0 V to 5 V range)
1.7 V to 5.5 V digital supply range
Asynchronous updating via LDAC
Asynchronous RESET to zero scale/midscale
DSP-/microcontroller-compatible serial interface
Robust 4 kV HBM ESD rating
16-lead, 3 mm × 3 mm LFCSP package
16-lead TSSOP package
Operating temperature range: −40°C to +125°C
The devices available in a 3 mm × 3 mm LFCSP package and a
16-lead TSSOP package offer guaranteed specifications over the
−40°C to +125°C industrial temperature range.
APPLICATIONS
Industrial automation
Instrumentation, data acquisition
Open-/closed-loop servo control, process control
Programmable logic controllers
FUNCTIONAL BLOCK DIAGRAM
V
V
/V
DD
REFIN REFOUT
AD5761R/AD5721R
2.5V
REFERENCE
REFERENCE
BUFFERS
DV
CC
0V TO 5V
0V TO 10V
0V TO 16V
0V TO 20V
±3V
±5V
±10V
−2.5V TO +7.5V
ALERT
SDI
SCLK
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
12/16
12/16
12-BIT/
16-BIT
DAC
INPUT
REG
DAC
REG
V
OUT
SYNC
SDO
RESET
CLEAR
DNC
DGND
V
LDAC
AGND
SS
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 1.
Rev. C
Document Feedback
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Tel: 781.329.4700 ©2014–2018 Analog Devices, Inc. All rights reserved.
Technical Support
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AD5761R/AD5721R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Hysteresis .................................................................... 27
Register Details ............................................................................... 28
Input Shift Register .................................................................... 28
Control Register ......................................................................... 29
Readback Control Register ....................................................... 30
Update DAC Register from Input Register............................. 31
Readback DAC Register ............................................................ 31
Write and Update DAC Register .............................................. 31
Readback Input Register............................................................ 32
Disable Daisy-Chain Functionality.......................................... 32
Software Data Reset ................................................................... 32
Software Full Reset..................................................................... 33
No Operation Registers ............................................................. 33
Applications Information.............................................................. 34
Typical Operating Circuit ......................................................... 34
Power Supply Considerations................................................... 34
Evaluation Board........................................................................ 34
Outline Dimensions....................................................................... 35
Ordering Guide .......................................................................... 36
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Performance Characteristics................................................ 6
Timing Characteristics ................................................................ 7
Timing Diagrams.......................................................................... 7
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characterstics............................................. 12
Terminology .................................................................................... 23
Theory of Operation ...................................................................... 25
Digital-to-Analog Converter .................................................... 25
Transfer Function....................................................................... 25
DAC Architecture....................................................................... 25
Serial Interface ............................................................................ 26
Hardware Control Pins.............................................................. 26
REVISION HISTORY
1/2018—Rev. B to Rev. C
Changes to Figure 35...................................................................... 16
Changes to Figure 37...................................................................... 17
Changes to Figure 50...................................................................... 19
Changes to Figure 58 to Figure 60................................................ 20
Changes to Figure 61 to Figure 66................................................ 21
Changes to Figure 69...................................................................... 22
Added Figure 71 ............................................................................. 22
Changes to Terminology Section ................................................. 23
Changes to Digital-to-Analog Converter Section and Internal
Reference Section ........................................................................... 25
Changes to Transfer Function Section......................................... 25
Moved DAC Output Amplifier Section....................................... 26
Change to DB[15:11] Column, Table 11 and RA[2:0]
Description Column, Table 12...................................................... 29
Change to DB[15:13] Column, Table 15 ..................................... 30
Updated Outline Dimensions....................................................... 35
Moved Ordering Guide Section.................................................... 36
Changes to Ordering Guide .......................................................... 36
10/2016—Rev. A to Rev. B
CLEAR
Changes to Asynchronous Clear Function (
) Section .......27
Changes to Features Section ........................................................... 1
Changes to Table 12 ....................................................................... 29
Changes to Power Supply Considerations Section and
Figure 77 .......................................................................................... 34
Added Figure 79 ............................................................................. 35
Updated Outline Dimensions....................................................... 35
Changes to Ordering Guide.......................................................... 35
5/2015—Rev. 0 to Rev. A
Added LFCSP Package.......................................................Universal
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 6
Changes to Table 4............................................................................ 9
Added Figure 6 and Table 6; Renumbered Sequentially ........... 11
Changes to Figure 21 to Figure 24................................................ 14
11/2014—Revision 0: Initial Version
Rev. C | Page 2 of 36
Data Sheet
AD5761R/AD5721R
SPECIFICATIONS
VDD1 = 4.75 V to 30 V, VSS1 = −16.5 V to 0 V, AGND = DGND = 0 V, VREFIN/VREFOUT = 2.5 V external, DVCC = 1.7 V to 5.5 V, RLOAD = 1 kΩ
for all ranges except 0 V to 16 V and 0 V to 20 V for which RLOAD = 2 kΩ, CLOAD = 200 pF, all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter2
Min
Typ
Max
Unit
Test Conditions/Comments
External reference3 and internal reference, outputs
unloaded
STATIC PERFORMANCE
Programmable Output Ranges
0
0
0
0
−2.5
−3
−5
−10
5
10
16
20
+7.5
+3
+5
+10
V
V
V
V
V
V
V
V
AD5761R
Resolution
Relative Accuracy, INL
A Grade
16
Bits
−8
−2
+8
+2
LSB
LSB
External reference3 and internal reference
All ranges except 0 V to 16 V and 0 V to 20 V,
B Grade4
VREFIN/VREFOUT = 2.5 V external and internal reference
Differential Nonlinearity, DNL
AD5721R
Resolution
−1
12
+1
LSB
Bits
Relative Accuracy, INL
B Grade
Differential Nonlinearity, DNL
Zero-Scale Error
−0.5
−0.5
−6
+0.5
+0.5
+6
LSB
LSB
mV
External reference3 and internal reference
All ranges except 10 V and 0 V to 20 V, external
reference3
0 V to 20 V, 10 V ranges, external reference3
All ranges except 5 V, 10 V and 0 V to 20 V,
internal reference
−10
−6
+10
+6
mV
mV
−8
−9
−13
+8
+9
+13
mV
mV
mV
5 V range, internal reference
0 V to 20 V range, internal reference
10 V range, internal reference
Zero-Scale Temperature
Coefficient (TC)5
5
µV/°C
Unipolar ranges, external reference3 and internal
reference
15
µV/°C
Bipolar ranges, external reference3 and internal
reference
Bipolar Zero Error
Bipolar Zero TC5
−5
−7
+5
+7
mV
mV
µV/°C
All bipolar ranges except 10 V
10 V output range
3 V range, external reference3 and internal
reference
All bipolar ranges except 3 V range, external
reference3 and internal reference
2
5
µV/°C
mV
Offset Error
−6
+6
All ranges except 10 V and 0 V to 20 V, external
reference3
−10
−6
+10
+6
mV
mV
0 V to 20 V, 10 V ranges, external reference3
All ranges except 5 V, 10 V, and 0 V to 20 V;
internal reference
−8
−9
−13
+8
+9
+13
mV
mV
mV
5 V range, internal reference
0 V to 20 V range, internal reference
10 V range, internal reference
Rev. C | Page 3 of 36
AD5761R/AD5721R
Data Sheet
Parameter2
Offset Error TC5
Min
Typ
Max
Unit
Test Conditions/Comments
Unipolar ranges, external reference3 and internal
reference
5
µV/°C
15
µV/°C
Bipolar ranges, external reference3 and internal
reference
Gain Error
−0.1
+0.1
+0.15
% FSR
% FSR
External reference3
−0.15
Internal reference
Gain Error TC5
TUE
1.5
ppm FSR/°C External reference3 and internal reference
% FSR
% FSR
−0.1
+0.1
+0.15
External reference3
Internal reference
−0.15
REFERENCE INPUT (EXTERNAL)5
Reference Input Voltage (VREF
Input Current
)
2.5
0.5
V
µA
V
1% for specified performance
3 mV, at ambient temperature
−2
2
+2
3
Reference Range
REFERENCE OUTPUT (INTERNAL)5
Output Voltage
Voltage Reference TC
Output Impedance
Output Voltage Noise
Noise Spectral Density
Line Regulation
2.5
2
25
6
10
6
80
3.5
V
5
ppm/°C
kΩ
µV p-p
nV/√Hz
µV/V
ppm
ms
0.1 Hz to 10 Hz
At ambient; f = 10 kHz
At ambient
Thermal Hysteresis
Start-Up Time
First temperature cycle
Coming out of power-down mode with a 10 nF
capacitor on the VREFIN/VREFOUT pin to improve noise
performance; outputs unloaded
OUTPUT CHARACTERISTICS5
Output Voltage Range
−VOUT
+VOUT
See Table 7 for the different output voltage ranges
available
−10
−10.5
+10
+10.5
V
V
VDD/VSS
VDD/VSS
=
=
11 V, 10 V output range
11 V, 10 V output range with 5%
overrange
Capacitive Load Stability
Headroom
1
1
nF
V
0.5
RLOAD = 1 kΩ for all ranges except 0 V to16 V and 0 V
to 20 V ranges (RLOAD = 2 kΩ)
Output Voltage TC
Short-Circuit Current
Resistive Load
3
25
ppm FSR/°C
mA
kΩ
kΩ
mV/mA
Ω
10 V range, external reference
Short on the VOUT pin
All ranges except 0 V to16 V and 0 V to 20 V
0 V to 16 V, 0 V to 20 V ranges
Outputs unloaded
1
2
Load Regulation
DC Output Impedance
LOGIC INPUTS5
Input Voltage
High, VIH
0.3
0.5
Outputs unloaded
DVCC = 1.7 V to 5.5 V, JEDEC compliant
0.7 × DVCC
V
V
Low, VIL
0.3 × DVCC
Input Current
Leakage Current
−1
+1
+1
µA
µA
µA
pF
SDI, SCLK, SYNC
−1
LDAC, CLEAR, RESET pins held high
LDAC, CLEAR, RESET pins held low
Per pin, outputs unloaded
−55
Pin Capacitance
5
Rev. C | Page 4 of 36
Data Sheet
AD5761R/AD5721R
Parameter2
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC OUTPUTS (SDO, ALERT)5
Output Voltage
Low, VOL
High, VOH
High Impedance, SDO Pin
Leakage Current
0.4
+1
V
V
DVCC = 1.7 V to 5.5 V, sinking 200 µA
DVCC = 1.7 V to 5.5 V, sourcing 200 µA
DVCC − 0.5
−1
µA
pF
Pin Capacitance
5
POWER REQUIREMENTS
VDD
VSS
DVCC
IDD
ISS
DICC
4.75
−16.5
1.7
30
0
5.5
6.5
3
V
V
V
5.1
1
0.005
67.1
0.1
mA
mA
µA
mW
mV/V
Outputs unloaded, external reference
Outputs unloaded
VIH = DVCC, VIL = DGND
11 V operation, outputs unloaded, TSSOP package
VDD 10%, VSS = −15 V
1
Power Dissipation
DC Power Supply Rejection
Ratio (PSRR)5
0.1
65
mV/V
dB
VSS 10%, VDD = +15 V
VDD 200 mV, 50 Hz/60 Hz, VSS = −15 V, internal
reference, CLOAD = 100 nF
AC PSRR5
65
80
80
dB
dB
dB
VSS 200 mV, 50 Hz/60 Hz, VDD = +15 V, internal
reference, CLOAD = 100 nF
VDD 200 mV, 50 Hz/60 Hz, VSS = −15 V, external
reference, CLOAD = unloaded
VSS 200 mV, 50 Hz/60 Hz, VDD = +15 V, external
reference, CLOAD = unloaded
1 For specified performance, headroom requirement is 1 V.
2 Temperature range: −40°C to +125°C, typical at +25°C.
3 External reference means 2 V to 2.85 V with overrange and 2 V to 3 V without overrange.
4 Integral nonlinearity error is specified at 4 LSB (min/max) for 16 V and 20 V ranges with VREFIN/VREFOUT = 2.5 V external and internal, and for all ranges with VREFIN/VREFOUT
2 V to 2.85 V with overrange and 2 V to 3 V without overrange.
=
5 Guaranteed by design and characterization, not production tested.
Rev. C | Page 5 of 36
AD5761R/AD5721R
Data Sheet
AC PERFORMANCE CHARACTERISTICS
VDD1 = 4.75 V to 30 V, VSS1 = −16.5 V to 0 V, AGND = DGND = 0 V, VREFIN/VREFOUT = 2.5 V external, DVCC = 1.7 V to 5.5 V, RLOAD = 1 kΩ
for all ranges except 0 V to 16 V and 0 V to 20 V for which RLOAD = 2 kΩ, CLOAD = 200 pF, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2
DYNAMIC PERFORMANCE3
Min Typ Max Unit
Test Conditions/Comments
Output Voltage Settling Time
9
7.5
12.5 µs
20 V step to 1 LSB at 16-bit resolution
10 V step to 1 LSB at 16-bit resolution
512 LSB step to 1 LSB at 16-bit resolution
10 V range
0 V to 5 V range
10 V range
8.5
5
µs
µs
Digital-to-Analog Glitch Impulse
Glitch Impulse Peak Amplitude
8
1
15
10
100
0.6
nV-sec
nV-sec
mV
mV
mV p-p
nV-sec
0 V to 5 V range
Power-On Glitch
Digital Feedthrough
Output Noise
0.1 Hz to 10 Hz Bandwidth
100 kHz Bandwidth
15
45
35
25
15
80
µV p-p
µV rms
µV rms
µV rms
µV rms
nV/√Hz
0 V to 20 V and 0 V to 16 V ranges, 2.5 V external reference
0 V to 10 V, 10 V, and −2.5 V to +7.5 V ranges, 2.5 V external reference
5 V range, 2.5 V external reference
0 V to 5 V and 3 V ranges, 2.5 V external reference
10 V range, 2.5 V external reference
Output Noise Spectral Density,
at 10 kHz
35
70
nV/√Hz
nV/√Hz
3 V range, 2.5 V external reference
5 V, 0 V to 10 V, and −2.5 V to +7.5 V ranges, 2.5 V external reference
110
90
45
nV/√Hz 0 V to 20 V range, 2.5 V external reference
nV/√Hz 0 V to 16 V range, 2.5 V external reference
nV/√Hz 0 V to 5 V range, 2.5 V external reference
Total Harmonic Distortion (THD)4
Signal-to-Noise Ratio (SNR)
Peak Harmonic or Spurious
Noise (SFDR)
−87
92
92
dB
dB
dB
2.5 V external reference, 1 kHz tone
At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz
At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz
Signal-to-Noise-and-Distortion
(SINAD) Ratio
85
dB
At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz
1 For specified performance, headroom requirement is 1 V.
2 Temperature range: −40°C to +125°C, typical at +25°C.
3 Guaranteed by design and characterization, not production tested.
4 Digitally generated sine wave at 1 kHz.
Rev. C | Page 6 of 36
Data Sheet
AD5761R/AD5721R
TIMING CHARACTERISTICS
DVCC = 1.7 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Description
1
t1
t2
t3
t4
20
10
10
15
10
20
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs typ
µs typ
ns min
ns typ
ns min
ns max
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge time
Minimum SYNC high time (write mode)
Data setup time
t5
t6
t7
t8
t9
5
Data hold time
10
20
20
9
7.5
20
200
10
40
50
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
t10
t11
t12
DAC output settling time, 20 V step to 1 LSB at 16-bit resolution (see Table 2)
DAC output settling time, 10 V step to 1 LSB at 16-bit resolution
CLEAR pulse width low
t13
t14
t15
t16
t17
CLEAR pulse activation time
SYNC rising edge to SCLK falling edge
SCLK rising edge to SDO valid (CL_SDO2 = 15 pF)
Minimum SYNC high time (readback/daisy-chain mode)
1 Maximum SCLK frequency is 50 MHz for write mode and 33 MHz for readback mode.
2 CL_SDO is the capacitive load on the SDO output.
TIMING DIAGRAMS
t1
SCLK
1
2
24
t3
t2
t6
t5
t4
SYNC
SDI
t8
t7
DB23
DB0
t11
t9
t10
LDAC
t12
V
OUT
OUT
t12
V
t13
CLEAR
t14
V
OUT
Figure 2. Serial Interface Timing Diagram
Rev. C | Page 7 of 36
AD5761R/AD5721R
Data Sheet
t1
SCLK
24
48
t3
t2
t5
t17
t15
t4
SYNC
SDI
t8
t7
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N – 1
INPUT WORD FOR DAC N
t16
DB23
DB0
SDO
t10
UNDEFINED
t11
LDAC
Figure 3. Daisy-Chain Timing Diagram
SCLK
1
1
24
24
t17
SYNC
DB23
DB0
DB23
DB0
SDI
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
DB23
DB0
DB23
DB0
SDO
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
Figure 4. Readback Timing Diagram
Rev. C | Page 8 of 36
Data Sheet
AD5761R/AD5721R
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
200 mA do not cause silicon controlled rectifier (SCR) latch-up.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 4.
Parameter
Rating
VDD to AGND
VSS to AGND
VDD to VSS
DVCC to DGND
Digital Inputs to DGND
−0.3 V to +34 V
+0.3 V to −17 V
−0.3 V to +34 V
−0.3 V to +7 V
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
ESD CAUTION
Digital Outputs to DGND
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
VREFIN/VREFOUT to DGND
VOUT to AGND
−0.3 V to +7 V
VSS to VDD
AGND to DGND
Operating Temperature Range,
TA Industrial
−0.3 V to +0.3 V
−40°C to +125°C
Storage Temperature Range
Junction Temperature, TJ MAX
16-Lead TSSOP Package
θJA Thermal Impedance
θJC Thermal Impedance
16-Lead LFCSP Package
θJA Thermal Impedance
θJC Thermal Impedance
Power Dissipation
−65°C to +150°C
150°C
113°C/W1
28°C/W
75°C/W1
4.5°C/W2
(TJ MAX − TA)/θJA
JEDEC industry standard
J-STD-020
Lead Temperature
Soldering
ESD (Human Body Model)
4 kV
1 JEDEC 2S2P test board, still air (0 m/sec airflow).
2 Measured to exposed paddle, with infinite heat sink on package top surface.
Rev. C | Page 9 of 36
AD5761R/AD5721R
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ALERT
CLEAR
RESET
DGND
DV
CC
SCLK
SYNC
SDI
AD5761R/
AD5721R
V
V
REFIN/ REFOUT
TOP VIEW
AGND
(Not to Scale)
V
LDAC
SDO
DNC
SS
V
OUT
V
DD
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT
TO THIS PIN.
Figure 5. 16-Lead TSSOP Pin Configuration
Table 5. 16-Lead TSSOP Pin Function Descriptions
Pin No.
Mnemonic Description
1
ALERT
Active Low Alert. This pin is asserted low when the die temperature exceeds approximately 150°C, or when an
output short circuit or a brownout occurs. This pin is also asserted low during power-up, a full software reset, or
a hardware reset, for which a write to the control register asserts the pin high.
2
3
CLEAR
RESET
Falling Edge Clear Input. Asserting this pin sets the DAC register to zero scale, midscale, or full-scale code (user
selectable) and updates the DAC output. This pin can be left floating because there is an internal pull-up resistor.
Active Low Reset Input. Asserting this pin returns the AD5761R/AD5721R to their default power-on status
where the output is clamped to ground and the output buffer is powered down. This pin can be left floating
because there is an internal pull-up resistor.
4
VREFIN/VREFOUT Internal Reference Voltage Output and External Reference Voltage Input. For specified performance,
VREFIN/VREFOUT = 2.5 V. Connect a 10 nF capacitor with the internal reference to minimize the noise.
5
6
AGND
VSS
Ground Reference Pin for Analog Circuitry.
Negative Analog Supply Connection. A voltage in the range of −16.5 V to 0 V can be connected to this pin. For
unipolar output ranges, connect this pin to 0 V. VSS must be decoupled to AGND.
7
8
VOUT
VDD
Analog Output Voltage of the DAC. The output amplifier is capable of directly driving a 2 kΩ, 1 nF load.
Positive Analog Supply Connection. A voltage in the range of 4.75 V to 30 V can be connected to this pin for
unipolar output ranges. Bipolar output ranges accept a voltage in the range of 4.75 V to 16.5 V. VDD must be
decoupled to AGND.
9
10
DNC
SDO
Do Not Connect. Do not connect to this pin.
Serial Data Output. This pin clocks data from the serial register in daisy-chain or readback mode. Data is clocked
out on the rising edge of SCLK and is valid on the falling edge of SCLK.
11
LDAC
Load DAC. This logic input updates the DAC register and, consequently, the analog output. When tied
permanently low, the DAC register is updated when the input register is updated. If LDAC is held high during
the write to the input register, the DAC output register is not updated, and the DAC output update is held off
until the falling edge of LDAC. This pin can be left floating because there is an internal pull-up resistor.
12
13
SDI
SYNC
Serial Data Input. Data must be valid on the falling edge of SCLK.
Active Low Synchronization Input. This pin is the frame synchronization signal for the serial interface. While
SYNC is low, data is transferred in on the falling edge of SCLK. Data is latched on the rising edge of SYNC.
14
15
16
SCLK
DVCC
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This pin operates at
clock speeds of up to 50 MHz.
Digital Supply. The voltage range is from 1.7 V to 5.5 V. The applied voltage sets the voltage at which the digital
interface operates.
DGND
Digital Ground.
Rev. C | Page 10 of 36
Data Sheet
AD5761R/AD5721R
RESET
1
2
3
4
12 SCLK
11 SYNC
AD5761R/
AD5721R
V
/V
REFIN REFOUT
TOP VIEW
10
9
AGND
SDI
(Not to Scale)
V
LDAC
SS
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED PAD MUST BE MECHANICALLY CONNECTED TO THE PCB
COPPER PLANE FOR OPTIMAL THERMAL PERFORMANCE. THE EXPOSED PAD
CAN BE LEFT ELECTRICALLY FLOATING.
Figure 6. 16-Lead LFCSP Pin Configuration
Table 6. 16-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RESET
Active Low Reset Input. Asserting this pin returns the AD5761R/AD5721R to their default power-on status
where the output is clamped to ground and the output buffer is powered down. This pin can be left floating
because there is an internal pull-up resistor.
2
VREFIN/VREFOUT Internal Reference Voltage Output and External Reference Voltage Input. For specified performance,
VREFIN/VREFOUT = 2.5 V. Connect a 10 nF capacitor with the internal reference to minimize the noise.
3
4
AGND
VSS
Ground Reference Pin for Analog Circuitry.
Negative Analog Supply Connection. A voltage in the range of −16.5 V to 0 V can be connected to this pin. For
unipolar output ranges, connect this pin to 0 V. VSS must be decoupled to AGND.
5
6
VOUT
VDD
Analog Output Voltage of the DAC. The output amplifier is capable of directly driving a 2 kΩ, 1 nF load.
Positive Analog Supply Connection. A voltage in the range of 4.75 V to 30 V can be connected to this pin for
unipolar output ranges. Bipolar output ranges accept a voltage in the range of 4.75 V to 16.5 V. VDD must be
decoupled to AGND.
7
8
DNC
SDO
Do Not Connect. Do not connect to this pin.
Serial Data Output. This pin clocks data from the serial register in daisy-chain or readback mode. Data is clocked
out on the rising edge of SCLK and is valid on the falling edge of SCLK.
9
LDAC
Load DAC. This logic input updates the DAC register and, consequently, the analog output. When tied
permanently low, the DAC register is updated when the input register is updated. If LDAC is held high during
the write to the input register, the DAC output register is not updated, and the DAC output update is held off
until the falling edge of LDAC. This pin can be left floating because there is an internal pull-up resistor.
10
11
SDI
SYNC
Serial Data Input. Data must be valid on the falling edge of SCLK.
Active Low Synchronization Input. This pin is the frame synchronization signal for the serial interface. While
SYNC is low, data is transferred in on the falling edge of SCLK. Data is latched on the rising edge of SYNC.
12
13
SCLK
DVCC
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This pin operates at
clock speeds of up to 50 MHz.
Digital Supply. The voltage range is from 1.7 V to 5.5 V. The applied voltage sets the voltage at which the digital
interface operates.
14
15
DGND
ALERT
Digital Ground.
Active Low Alert. This pin is asserted low when the die temperature exceeds approximately 150°C, or when an
output short circuit or a brownout occurs. This pin is also asserted low during power-up, a full software reset, or
a hardware reset, for which a write to the control register asserts the pin high.
16
CLEAR
EPAD
Falling Edge Clear Input. Asserting this pin sets the DAC register to zero scale, midscale, or full-scale code (user
selectable) and updates the DAC output. This pin can be left floating because there is an internal pull-up resistor.
Exposed Pad. The exposed pad must be mechanically connected to the PCB copper plane for optimal thermal
performance. The exposed pad can be left electrically floating.
Rev. C | Page 11 of 36
AD5761R/AD5721R
Data Sheet
TYPICAL PERFORMANCE CHARACTERSTICS
2.0
0.5
0.4
V
V
= +21V
= –11V
+5V SPAN
+10V SPAN
+16V SPAN
+20V SPAN
±3V SPAN
V
V
= +21V
= –11V
DD
SS
DD
SS
±5V SPAN
±10V SPAN
–2.5V TO +7.5V SPAN
1.5
1.0
0.3
0.2
0.5
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.5
–1.0
–1.5
–2.0
0
10000
20000
30000
40000
50000
60000
0
500
1000 1500 2000 2500 3000 3500 4000
DAC CODE
DAC CODE
Figure 7. AD5761R INL Error vs. DAC Code, Unipolar Output
Figure 10. AD5721R INL Error vs. DAC Code, Bipolar Output
0.5
1.0
+5V SPAN
+10V SPAN
+16V SPAN
+20V SPAN
V
V
= +21V
= –11V
+5V SPAN
+10V SPAN
+16V SPAN
+20V SPAN
V
V
= +21V
= –11V
DD
SS
DD
SS
0.4
0.3
0.8
0.6
0.2
0.4
0.1
0.2
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.2
–0.4
–0.6
–0.8
–1.0
0
500
1000 1500 2000 2500 3000 3500 4000
DAC CODE
0
10000
20000
30000
40000
50000
60000
DAC CODE
Figure 8. AD5721R INL Error vs. DAC Code, Unipolar Output
Figure 11. AD5761R DNL Error vs. DAC Code, Unipolar Output
2.0
0.5
V
V
= +21V
= –11V
±3V SPAN
DD
SS
+5V SPAN
+10V SPAN
+16V SPAN
+20V SPAN
V
V
= +21V
= –11V
DD
SS
±5V SPAN
0.4
0.3
±10V SPAN
–2.5V TO +7.5V SPAN
1.5
1.0
0.2
0.5
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.5
–1.0
–1.5
–2.0
0
10000
20000
30000
40000
50000
60000
0
500
1000 1500 2000 2500 3000 3500 4000
DAC CODE
DAC CODE
Figure 9. AD5761R INL Error vs. DAC Code, Bipolar Output
Figure 12. AD5721R DNL Error vs. DAC Code, Unipolar Output
Rev. C | Page 12 of 36
Data Sheet
AD5761R/AD5721R
1.0
1.0
0.8
±3V SPAN
V
V
= +21V
= –11V
DD
SS
±5V SPAN
0.8
0.6
±10V SPAN
–2.5V TO +7.5V SPAN
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
+5V U2 EXT MIN DNL
±10V U2 EXT MIN DNL
+5V U1 INT MIN DNL
±10V U1 INT MIN DNL
+5V U2 EXT MAX DNL
±10V U2 EXT MAX DNL
+5V U1 INT MAX DNL
±10V U1 INT MAX DNL
V
V
= +21V
DD
SS
= –11V
0
10000
20000
30000
40000
50000
60000
–40
–20
0
25
50
85
105
125
DAC CODE
TEMPERATURE (°C)
Figure 13. AD5761R DNL Error vs. DAC Code, Bipolar Output
Figure 16. DNL Error vs. Temperature
0.5
0.4
2.0
1.5
+5V U2 EXT MAX INL
+5V U1 INT MAX INL
±10V U2 EXT MAX INL
±10V U1 NT MAX INL
+5V U2 EXT MIN INL
+5V U1 INT MIN INL
±10V U2 EXT MIN INL
±10V U1 INT MIN INL
V
V
= +21V
= –11V
V
V
T
= +21V
±3V SPAN
DD
SS
DD
SS
A
= –11V
±5V SPAN
= 25°C
±10V SPAN
–2.5V TO +7.5V SPAN
NO LOAD
0.3
1.0
0.2
0.5
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.5
–1.0
–1.5
–2.0
+5V SPAN VDD/VSS = +6V/–1V
V
DD/VSS = +10V/–1V
V
DD/VSS = +16.5V/–1V
0
500
1000 1500 2000 2500 3000 3500 4000
DAC CODE
±10V SPAN VDD/VSS = +11V/–11V
V
DD/VSS = +13.5V/–13.5V
VDD/VSS = +16.5V/–16.5V
VDD/VSS = +7.5V/–1V
V
DD/VSS = +12.5V/–1V
V
DD/VSS = +12.5V/–12.5V
VDD/VSS = +14.5V/–14.5V
SUPPLY VOLTAGE (V)
Figure 14. AD5721R DNL Error vs. DAC Code, Bipolar Output
Figure 17. INL Error vs. Supply Voltage
1.5
1.0
1.0
0.8
+5V U2 EXT MAX DNL
+5V U1 INT MAX DNL
±10V U2 EXT MAX DNL
±10V U1 NT MAX DNL
+5V U2 EXT MIN DNL
+5V U1 INT MIN DNL
±10V U2 EXT MIN DNL
±10V U1 INT MIN DNL
+5V U1 INT MAX INL
+5V U2 EXT MAX INL
±10V U1 INT MAX INL
±10V U2 EXT MAX INL
+5V U1 INT MIN INL
+5V U2 EXT MIN INL
±10V U1 INT MIN INL
±10V U2 EXT MIN INL
V
V
A
= +21V
= –11V
DD
SS
T
= 25°C
NO LOAD
0.6
0.4
0.5
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
V
V
= +21V
= –11V
DD
SS
+5V SPAN VDD/VSS = +6V/–1V
V
DD/VSS = +10V/–1V
V
DD/VSS = +16.5V/–1V
–40
–20
0
25
50
85
105
125
±10V SPAN VDD/VSS = +11V/–11V
VDD/VSS = +13.5V/–13.5V
VDD/VSS = +16.5V/–16.5V
VDD/VSS = +7.5V/–1V
VDD/VSS = +12.5V/–12.5V
VDD/VSS = +12.5V/–1V
VDD/VSS = +14.5V/–14.5V
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 15. INL Error vs. Temperature
Figure 18. DNL Error vs. Supply Voltage
Rev. C | Page 13 of 36
AD5761R/AD5721R
Data Sheet
3
0.006
0.004
0.002
0
MAX INL, +5V SPAN
MAX INL, ±10V SPAN
MIN INL, +5V SPAN
V
V
= +21V
= –11V
V
V
= +21V
= –11V
DD
SS
DD
SS
+5V U1 EXT
+5V U2 INT
±10V U1 EXT
±10V U2 INT
MIN INL, ±10V SPAN
2
1
0
–1
–2
–3
–0.002
–0.004
–0.006
2.00
2.25
2.50
REFERENCE VOLTAGE (V)
2.75
3.00
–40
–20
0
25
50
85
105
125
TEMPERATURE (°C)
Figure 19. INL Error vs. Reference Voltage
Figure 22. Midscale Error vs. Temperature
1.0
0.8
0.010
0.008
0.006
0.004
0.002
0
MAX DNL, ±10V SPAN
MAX DNL, +5V SPAN
MIN DNL, ±10V SPAN
MIN DNL, +5V SPAN
V
V
= +21V
= –11V
V
V
= +21V
= –11V
DD
SS
DD
SS
+5V U1 EXT
+5V U2 INT
±10V U1 EXT
±10V U2 INT
0.6
0.4
0.2
0
–0.002
–0.004
–0.006
–0.008
–0.010
–0.2
–0.4
–0.6
–0.8
–1.0
–40
–20
0
25
50
85
105
125
2.00
2.25
2.50
2.75
3.00
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
Figure 20. DNL Error vs. Reference Voltage
Figure 23. Full-Scale Error vs. Temperature
0.15
0.10
0.05
0
0.010
0.008
0.006
0.004
0.002
0
V
V
= +21V
= –11V
V
V
= +21V
= –11V
DD
SS
DD
SS
+5V U1 EXT
+5V U2 INT
±10V U1 EXT
±10V U2 INT
+5V U1 EXT
+5V U2 INT
±10V U1 EXT
±10V U2 INT
–0.002
–0.004
–0.006
–0.008
–0.010
–0.05
–0.10
–0.15
–40
–20
0
25
50
85
105
125
–40
–20
0
25
50
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 24. Gain Error vs. Temperature
Figure 21. Zero-Scale Error vs. Temperature
Rev. C | Page 14 of 36
Data Sheet
AD5761R/AD5721R
0.0010
0.030
0.025
0.020
0.015
0.010
0.005
0
T
V
= 25°C
T
V
= 25°C
A
A
0.0005
0
= 2.5V
= 2.5V
REF
REF
+5V U2 EXT
+5V U1 INT
±10V U2 EXT
±10V U1 INT
–0.0005
–0.0010
–0.0015
–0.0020
–0.0025
–0.0030
–0.0035
–0.0040
–0.0045
–0.0050
+5V U2 EXT
+5V U1 INT
±10V U2 EXT
±10V U1 INT
–0.005
–0.010
–0.015
–0.020
–0.025
–0.030
+5V SPAN VDD/VSS = +6V/–1V
V
DD/VSS = +10V/–1V
VDD/VSS = +16.5V/–1V
+5V SPAN VDD/VSS = +6V/–1V
V
DD/VSS = +10V/–1V
VDD/VSS = +16.5V/–1V
±10V SPAN VDD/VSS = +11V/–11V
V
DD/VSS = +13.5V/–13.5V
V
DD/VSS = +16.5V/–16.5V
±10V SPAN VDD/VSS = +11V/–11V
V
DD/VSS = +13.5V/–13.5V
VDD/VSS = +16.5V/–16.5V
V
DD/VSS = +7.5V/–1V
V
DD/VSS = +12.5V/–1V
V
DD/VSS = +7.5V/–1V
VDD/VSS = +12.5V/–1V
V
DD/VSS = +12.5V/–12.5V
V
DD/VSS = +14.5V/–14.5V
VDD/VSS = +12.5V/–12.5V
VDD/VSS = +14.5V/–14.5V
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 25. Zero-Scale Error vs. Supply Voltage
Figure 28. Gain Error vs. Supply Voltage
0.005
0.003
0.0005
0
V
V
A
= +21V
= –11V
+5V SPAN
±10V SPAN
DD
SS
T
V
= 25°C
A
= 2.5V
REF
T
= 25⁰C
–0.0005
–0.0010
–0.0015
–0.0020
–0.0025
–0.0030
0.001
+5V U2 EXT
+5V U1 INT
±10V U2 EXT
±10V U1 INT
–0.001
–0.003
–0.005
2.0
2.5
3.0
+5V SPAN VDD/VSS = +6V/–1V
V
DD/VSS = +10V/–1V
V
DD/VSS = +16.5V/–1V
±10V SPAN VDD/VSS = +11V/–11V
V
DD/VSS = +13.5V/–13.5V
V
DD/VSS = +16.5V/–16.5V
REFERENCE VOLTAGE (V)
VDD/VSS = +7.5V/–1V
V
DD/VSS = +12.5V/–1V
V
DD/VSS = +12.5V/–12.5V
VDD/VSS = +14.5V/–14.5V
SUPPLY VOLTAGE (V)
Figure 26. Midscale Error vs. Supply Voltage
Figure 29. Zero-Scale Error vs. Reference Voltage
0.0010
0.0008
0.0006
0.0004
0.0002
0
0.0010
0.0005
0
+5V SPAN
±10V SPAN
V
V
A
= +21V
DD
SS
T
V
= 25°C
= 2.5V
A
= –11V
REF
T
= 25°C
–0.0005
–0.0010
–0.0015
–0.0020
–0.0002
–0.0004
–0.0006
–0.0008
–0.0010
+5V U2 EXT
+5V U1 INT
±10V U2 EXT
±10V U1 INT
2.0
2.5
3.0
+5V SPAN VDD/VSS = +6V/–1V
±10V SPAN VDD/VSS = +11V/–11V
VDD/VSS = +10V/–1V
VDD/VSS = +13.5V/–13.5V
VDD/VSS = +16.5V/–1V
VDD/VSS = +16.5V/–16.5V
REFERENCE VOLTAGE (V)
VDD/VSS = +7.5V/–1V
VDD/VSS = +12.5V/–12.5V
VDD/VSS = +12.5V/–1V
VDD/VSS = +14.5V/–14.5V
SUPPLY VOLTAGE (V)
Figure 30. Midscale Error vs. Reference Voltage
Figure 27. Full-Scale Error vs. Supply Voltage
Rev. C | Page 15 of 36
AD5761R/AD5721R
Data Sheet
0.05
0.03
0.005
T
= 25°C
+5V SPAN
±10V SPAN
V
V
A
= +21V
= –11V
A
DD
SS
T
= 25°C
0.003
0.001
0.01
–0.01
–0.03
–0.05
–0.001
–0.003
± 5V SPAN_INT
–2.5V TO +7.5V SPAN_INT
±5V SPAN_EXT
±10V SPAN_INT
±3V SPAN_INT
±10V SPAN_EXT
±3V SPAN_EXT
–2.5V TO +7.5V SPAN_EXT
–0.005
2.0
0
10000
20000
30000
CODE
40000
50000
60000
2.5
REFERENCE VOLTAGE (V)
3.0
Figure 31. Full-Scale Error vs. Reference Voltage
Figure 34. TUE vs. Code, Bipolar Output
0.05
0.03
0.06
0.05
0.04
0.03
0.02
0.01
0
+5V SPAN
±10V SPAN
+5V_U1_EXTREF
+5V_U2_INTREF
+5V_U3_INTREF
±10V_U1_EXTREF
±10V_U2_INTREF
±10V_U3_INTREF
V
V
= +21V
= –11V
V
V
T
= +21V
= –11V
DD
SS
DD
SS
A
= 25°C
0.01
–0.01
–0.03
–0.05
2.0
2.5
3.0
–40
–20
0
20
40
60
80
100
120
REFERENCE VOLTAGE (V)
TEMPERATURE (⁰C)
Figure 35. TUE vs. Temperature
Figure 32. Gain Error vs. Reference Voltage
0.030
0.028
0.026
0.024
0.022
0.020
0.018
0.016
0.014
0.012
0.01
0.05
0.03
+5V SPAN_INT
+16V SPAN_INT
+5V SPAN_EXT
+16V SPAN_EXT
+10V SPAN_INT
+20V SPAN_INT
+10V SPAN_EXT
+20V SPAN_EXT
T
V
= 25°C
T
= 25°C
A
A
= 2.5V
REF
0.01
–0.01
–0.03
–0.05
0.008
0.006
0.004
0.002
0
+5V U2 EXT
+5V U1 INT
±10V U2 EXT
±10V U1 INT
+5V SPAN VDD/VSS = +6V/–1V
±10V SPAN VDD/VSS = +11V/–11V
VDD/VSS = +10V/–1V
VDD/VSS = +16.5V/–1V
0
10000
20000
30000
CODE
40000
50000
60000
V
DD/VSS = +13.5V/–13.5V
V
DD/VSS = +16.5V/–16.5V
VDD/VSS = +7.5V/–1V
V
DD/VSS = +12.5V/–1V
V
DD/VSS = +12.5V/–12.5V
VDD/VSS = +14.5V/–14.5V
SUPPLY VOLTAGE (V)
Figure 36. TUE vs. Supply Voltage
Figure 33. TUE vs. Code, Unipolar Output
Rev. C | Page 16 of 36
Data Sheet
AD5761R/AD5721R
0.00001
0.000001
V
REF
V
OUT
0.0000001
0.00000001
0.000000001
500mV
AV
= 21V
SYNC
DD
5V
5V
AV = –11V
DV
LOAD = 2kΩ||200pF
CAP ON V = 10nF
SS
= 5V
CC
REF
10
100
1k
10k
100k
1M
200µs/DIV
FREQUENCY (Hz)
Figure 37. Reference Output Voltage Turn On Transient
Figure 40. Reference Output Noise Spectral Density vs. Frequency
10
8
2.5014
2.5012
2.5010
2.5008
2.5006
2.5004
2.5002
2.5000
V
V
A
= +21V
= –11V
DD
SS
T
= 25⁰C
6
4
2
0
–2
–4
–6
–8
–10
2.4998
VSS –13.50 –13.75 –14.00 –14.25 –14.50 –14.75 –15.00 –15.25 –15.50 –15.75 –16.00 –16.25
VDD
13.50 13.75 14.00 14.25 14.50 14.75 15.00 15.25 15.50 15.75 16.00 16.25
–2.0 –1.6 –1.2 –0.8 –0.4
0
0.4
0.8
1.2
1.6
2.0
SUPPLY VOLTAGE (V)
TIME (Seconds)
Figure 38. Internal Reference Noise (100 kHz Bandwidth)
Figure 41. Reference Output Voltage (VREFOUT) vs. Supply Voltage
10
8
3.0
V
V
T
= +21V
= –11V
V
V
T
= +21V
= –11V
DD
SS
A
DD
SS
A
= 25°C
= 25⁰C
6
4
2.5
2.0
1.5
2
0
–2
–4
–6
–8
–10
BIPOLAR 10V
UNIPOLAR 10V
BIPOLAR 5V
UNIPOLAR 5V
–2.5V TO 7.5V
BIPOLAR 3V
UNIPOLAR 16V
UNIPOLAR 20V
–2.0 –1.6 –1.2 –0.8 –0.4
0
0.4
0.8
1.2
1.6 2.0
–10
–8
–6
–4
–2
0
2
4
6
8
10
TIME (Second)
LOAD CURRENT (µA)
Figure 39. Internal Reference Noise (0.1 Hz to 10 Hz Bandwidth)
Figure 42. Internal Reference vs. Load Current
Rev. C | Page 17 of 36
AD5761R/AD5721R
Data Sheet
2.50200
2.50175
2.50150
2.50125
2.50100
2.50075
2.50050
2.50025
2.50000
15000
10000
5000
±10V
+10V
±5V
+5V
–2.5V TO +7.5V
±3V
+16V
+20V
0
–5000
–10000
–15000
–20000
V
V
A
= +21V
DD
SS
= –11V
T
= 25°C
–40
–20
0
25
55
85
105
125
–30
–20
–10
0
10
20
30
TEMPERATURE (°C)
SOURCE/SINK CURRENT (mA)
Figure 43. Reference Output Voltage vs. Temperature
Figure 46. Source and Sink Capability of Output Amplifier with
Negative Full Scale Loaded
0.0010
70
60
50
40
30
20
10
0
IDV 3V
CC
V
V
= +21V
= –11V
= 25⁰C
DD
SS
IDV 5V
CC
0.0009
0.0008
0.0007
0.0006
0.0005
0.0004
0.0003
0.0002
0.0001
0
T
A
LOAD = 2kΩ || 200pF
INTERNAL REFERENCE
0
1
2
3
4
5
LOGIC INPUT VOLTAGE (V)
TEMPERATURE DRIFT (ppm/°C)
Figure 44. Reference Output TC
Figure 47. Supply Current vs. Logic Input Voltage
6
4
30000
25000
20000
15000
10000
5000
V
V
A
= +21V
= –11V
DD
SS
±10V
+10V
T
= 25°C
±5V
+5V
LOAD = 2kΩ||200pF
–2.5V TO +7.5V
±3V
+16V
+20V
2
0
–2
–4
–6
0
–5000
–10000
–15000
V
V
A
= +21V
DD
SS
SYNC
= –11V
±5V, ZERO SCALE TO FULL SCALE
T
= 25°C
–8.0 –6.0 –4.0 –2.0
0
2.0 4.0 6.0 8.0 10.0 12.0 14.0
TIME (µs)
–30
–20
–10
0
10
20
30
40
SOURCE/SINK CURRENT (mA)
Figure 45. Source and Sink Capability of Output Amplifier with
Positive Full Scale Loaded
Figure 48. Full-Scale Settling Time (Rising Voltage Step), 5 V Range
Rev. C | Page 18 of 36
Data Sheet
AD5761R/AD5721R
6
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
SYNC
500-CODE STEP, ±5V SPAN
4
2
V
V
A
=+21V
= –11V
DD
SS
T
= 25°C
LOAD = 2kΩ||200pF
0
–2
V
V
A
= +21V
= –11V
DD
SS
–4
T
= 25°C
LOAD = 2kΩ||200pF
SYNC
–0.01
±5V, FULL SCALE TO ZERO SCALE
–2
–1
0
1
2
3
4
5
–6
–8.0 –6.0 –4.0 –2.0
0
2.0 4.0 6.0 8.0 10.0 12.0 14.0
TIME (µs)
TIME (µs)
Figure 52. 500-Code Step Settling Time, 5 V Range
Figure 49. Full-Scale Settling Time (Falling Voltage Step), 5 V Range
0.20
0.19
0.18
0.17
0.16
0.15
0.14
0.13
0.12
0.11
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
12
V
V
A
= +21V
= –11V
SYNC
DD
SS
500-CODE STEP, ±10V SPAN
10
8
T
= 25°C
LOAD = 2kΩ||200pF
6
4
2
0
–2
–4
–6
–8
–10
–12
V
V
= +21V
= –11V
DD
SS
T
= 25°C
A
SYNC
LOAD = 2kΩ||200pF
±10V, ZERO SCALE TO FULL SCALE
–0.01
–2
–1
0
1
2
3
4
5
–3 –2 –1
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
TIME (µs)
TIME (µs)
Figure 53. 500-Code Step Settling Time, 10 V Range
Figure 50. Full-Scale Settling Time (Rising Voltage Step), 10 V Range
12
10
8
12
0nF
1nF
5nF
7nF
10nF
SYNC
10
8
±10V, FULLSCALE TO ZERO SCALE
6
6
4
4
2
2
0
0
–2
–4
–6
–8
–10
–12
–2
–4
–6
–8
–10
–12
V
V
=+21V
= –11V
= 25°C
V
V
T
= +21V
= –11V
DD
SS
DD
SS
A
= 25°C
T
A
LOAD = 2kΩ||200pF
LOAD = 2kΩ
–5
0
5
10
15
20
–3.0 –1.0
1.0 3.0
5.0
7.0
9.0
11.0 13.0 15.0
TIME (µs)
TIME (µs)
Figure 54. Full-Scale Settling Time at Various Capacitive Loads, 10 V Range
Figure 51. Full-Scale Settling Time (Falling Voltage Step), 10 V Range
Rev. C | Page 19 of 36
AD5761R/AD5721R
Data Sheet
6.0
0nF
1nF
5nF
7nF
10nF
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10V
V
DD
10V
5V
V
SS
V
/V
REFIN REFOUT
V
OUT
20mV
V
V
T
= +21V
= –11V
DD
SS
A
= 25⁰C
LOAD = 2kΩ
2
–3 –2 –1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
20ms/DIV
TIME (µs)
Figure 58. Power-Up Glitch
Figure 55. Full-Scale Settling Time at Various Capacitive Loads,
0 V to 5 V Range
0.005
0.004
0.003
0.002
0.001
0
5V
SCLK
SDI
5V
5V
SYNC
–0.001
–0.002
–0.003
–0.004
–0.005
–0.006
1V
–0.007
–0.008
–0.009
–0.010
V
V
= 21V
= –11V
DD
SS
V
OUT
LOAD = 2kΩ||200pF
T
= 25°C
A
0
0.5
1.0
1.5
2.0
2.5
3.0 3.5
200µs/DIV
TIME (µs)
Figure 59. Software Full Reset Glitch from Full Scale with Output Loaded,
0 V to 5 V Range
Figure 56. Digital-to-Analog Glitch Energy, 5 V Range
0.004
0.002
0
5V
SCLK
5V
5V
SYNC
SDI
–0.002
–0.004
–0.006
–0.008
–0.010
500mV
V
V
= 21V
= –11V
DD
V
OUT
SS
LOAD = 2kΩ||200pF
T
= 25°C
A
200µs/DIV
0
0.5
1.0
1.5
2.0
2.5
3.0 3.5
TIME (µs)
Figure 57. Digital-to-Analog Glitch Energy, 10 V Range
Figure 60. Software Full Reset Glitch from Midscale with Output Loaded,
5 V Range
Rev. C | Page 20 of 36
Data Sheet
AD5761R/AD5721R
5V
5V
SCLK
SCLK
SDI
5V
5V
5V
5V
SYNC
SYNC
SDI
200mV
V
2V
OUT
V
OUT
200µs/DIV
200µs/DIV
Figure 64. Software Full Reset Glitch from Zero Scale with Output Loaded,
10 V Range
Figure 61. Software Full Reset Glitch from Zero Scale with Output Loaded,
0 V to 5 V Range
5V
SCLK
SDI
5V
SCLK
5V
5V
5V
SYNC
SYNC
5V
1V
SDI
V
OUT
2V
V
OUT
200µs/DIV
200µs/DIV
Figure 62. Software Full Reset Glitch from Full Scale with Output Loaded,
10 V Range
Figure 65. Output Range Change Glitch, 0 V to 5 V Range
5V
5V
SCLK
SCLK
SYNC
5V
5V
SYNC
5V
SDI
5V
SDI
V
OUT
200mV
500mV
V
OUT
200µs/DIV
200µs/DIV
Figure 66. Output Range Change Glitch, 10 V Range
Figure 63. Software Full Reset Glitch from Midscale with Output Loaded,
10 V Range
Rev. C | Page 21 of 36
AD5761R/AD5721R
Data Sheet
10
0.0015
0.0010
0.0005
0
V
V
V
T
= +21V
= –11V
NOISE INT REF
NOISE EXT REF
DD
SS
= 2.5V
8
6
REFIN
= 25⁰C
A
4
2
T
V
V
DV
= 25°C
0
A
= 21V
= –11V
= 5V
DD
SS
–0.0005
–0.0010
–2
–4
CC
2.5V EXT REF
LOAD = 2kΩ||200pF
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
TIME (Seconds)
TIME (µs)
Figure 70. Digital Feedthrough
Figure 67. Peak-to-Peak Noise (Voltage Output Noise), 0.1 Hz to 10 Hz
Bandwidth
0
–20
30
NOISE EXT REF
NOISE INT REF
20
–40
10
0
–60
–80
–100
–120
–140
–160
–10
V
V
V
= +21V
= –11V
DD
SS
–20
= 2.5V
REFIN
T
= 25°C
A
–30
–2.0
0
2
4
6
8
10
12
14
16
18
20
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
FREQUENCY (kHz)
TIME (Seconds)
Figure 71. Total Harmonic Distortion
Figure 68. Peak-to-Peak Noise (Voltage Output Noise), 100 kHz Bandwidth
1600
V
V
A
= +21V
= –11V
DD
SS
1400
1200
1000
800
600
400
200
0
T
= 25°C
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 69. DAC Output Noise Spectral Density (NSD) vs. Frequency,
10 V Range
Rev. C | Page 22 of 36
Data Sheet
AD5761R/AD5721R
TERMINOLOGY
Total Unadjusted Error (TUE)
Gain Error
Total unadjusted error is a measure of the output error taking
all the various errors into account, namely INL error, offset
error, gain error, and output drift over supplies, temperature,
and time. TUE is expressed in % FSR.
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed in % FSR. A plot of gain error vs. temperature is
shown in Figure 24.
Relative Accuracy or Integral Nonlinearity (INL)
Gain Error Temperature Coefficient (TC)
For the DAC, relative accuracy, or integral nonlinearity, is a
measure of the maximum deviation, in LSB, from a straight line
passing through the endpoints of the DAC transfer function.
A typical INL error vs. DAC code plot is shown in Figure 7.
Gain error TC is a measure of the change in gain error with
changes in temperature. It is expressed in ppm FSR/°C.
DC Power Supply Rejection Ratio (DC PSRR)
DC power supply rejection ratio is a measure of the rejection of
the output voltage to dc changes in the power supplies applied
to the DAC. It is measured for a given dc change in power
supply voltage and is expressed in mV / V.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent codes.
A specified differential nonlinearity of 1 LSB maximum ensures
monotonicity. The AD5761R/AD5721R are guaranteed monotonic.
A typical DNL error vs. code plot is shown in Figure 11.
AC Power Supply Rejection Ratio (AC PSRR)
AC power supply rejection ratio is a measure of the rejection of
the output voltage to ac changes in the power supplies applied
to the DAC. It is measured for a given amplitude and frequency
change in power supply voltage and is expressed in decibels.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5761R/AD5721R
are monotonic over their full operating temperature range.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a full-scale input
change. Full-scale settling time is shown in Figure 48 to Figure 51.
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x8000 (straight binary coding) or 0x0000 (twos complement
coding) for the AD5761R/AD5721R.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by 1 LSB at
the major carry transition (see Figure 56 and Figure 57).
Bipolar Zero Temperature Coefficient (TC)
Bipolar zero TC is a measure of the change in the bipolar zero
error with a change in temperature. It is expressed in µV/°C.
Zero-Scale Error
Glitch Impulse Peak Amplitude
Zero-scale error is the error in the DAC output voltage when
0x0000 (straight binary coding) or 0x8000 (twos complement
coding) is loaded to the DAC register. Ideally, the output voltage
is negative full scale. A plot of zero-scale error vs. temperature is
shown in Figure 21.
Glitch impulse peak amplitude is the peak amplitude of the
impulse injected into the analog output when the input code in
the DAC register changes state. It is specified as the amplitude
of the glitch in mV and is measured when the digital input code
is changed by 1 LSB at the major carry transition.
Zero-Scale Error Temperature Coefficient (TC)
Digital Feedthrough
Zero-scale error TC is a measure of the change in zero-scale
error with a change in temperature. It is expressed in µV/°C.
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function.
Noise Spectral Density (NSD)
Noise spectral density is a measurement of the internally
generated random noise characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to full scale and
measuring noise at the output. It is measured in nV/√Hz. A plot
of noise spectral density is shown in Figure 69.
Offset Error Temperature Coefficient (TC)
Offset error TC is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
Rev. C | Page 23 of 36
AD5761R/AD5721R
Data Sheet
Voltage Reference Temperature Coefficient (TC)
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental.
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given
temperature range expressed in ppm/°C as follows:
For the AD5761R/AD5721R, it is defined as
V22 +V32 +V42 +V52 +V62
THD (dB) = 20× log
V
1
VREF _ MAX −VREF _ MIN
×Temp Range
where:
TC =
×106
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
V
REF _ NOM
where:
REF_MAX is the maximum reference output measured over the
total temperature range.
REF_MIN is the minimum reference output measured over the
total temperature range.
REF_NOM is the nominal reference output voltage, 2.5 V.
V
V
V
Temp Range is the specified temperature range, −40°C to
+125°C.
Rev. C | Page 24 of 36
Data Sheet
AD5761R/AD5721R
THEORY OF OPERATION
V
REFIN
DIGITAL-TO-ANALOG CONVERTER
The AD5761R/AD5721R are single channel, 16-/12-bit voltage
output DACs. The AD5761R/AD5721R output ranges are
software selectable and can be configured as follows:
V
/
REFIN
V
REFOUT
DAC REGISTER
R-2R
V
OUT
Unipolar output voltage: 0 V to 5 V, 0 V to 10 V, 0 V to
16 V, 0 V to 20 V
Bipolar output voltage: −2.5 V to +7.5 V, ±± V, ±5 V, ±10 V
CONFIGURABLE
OUTPUT
AMPLIFIER
AGND
AGND
OUTPUT
Data is written to the AD5761R/AD5721R in a 24-bit word
format via a 4-wire, serial peripheral interface (SPI) compatible,
digital interface. The devices also offer an SDO pin to facilitate
daisy-chaining and readback.
RANGE CONTROL
Figure 72. DAC Architecture
R-2R DAC
The architecture of the AD5761R consists of two matched DAC
sections. A simplified circuit diagram is shown in Figure 7±. The
6 MSBs of the 16-bit data-word are decoded to drive 6± switches,
E0 to E62, while the remaining 10 bits of the data-word drive
the S0 to S9 switches of a 10-bit voltage mode R-2R ladder
network.
TRANSFER FUNCTION
The internal reference is on by default. The input coding to the
DAC can be straight binary or twos complement (bipolar ranges
case only). Therefore, the transfer function is given by
D
VOUT VREF M
C
2N
The code loaded into the DAC register determines which arms
of the ladder are switched between VREF and ground (AGND).
The output voltage is taken from the end of the ladder and
amplified afterwards to provide the selected output voltage.
where:
REF is 2.5 V.
V
M is the slope for a given output range.
D is the decimal equivalent of the code loaded to the DAC
register as follows:
R
R
R
V
OUT
2R
2R
S0
2R ...
2R
S9
2R
2R ... 2R
...
0 to 4095 for the 12-bit device.
...
S1
E62
E61
E0
0 to 65,5±5 for the 16-bit device.
N is the number of bits. N is 12 for the AD5721R and 16 for the
AD5761R.
V
REF
AGND
10-BIT R-2R LADDER
6 MSBs DECODED INTO
63 EQUAL SEGMENTS
C is the offset for a given output range.
Figure 73. DAC Ladder Structure
The values for M and C are as shown in Table 7.
Internal Reference
Table 7. M and C Values for Various Output Ranges
The AD5761R/AD5721R feature an on-chip reference. The
on-chip reference is on at power-up, and this reference can be
turned off by setting the software-programmable bit, DB5, in
the control register. Table 12 shows how the state of the bit
corresponds to the mode of operation.
Range
M
C
±±1 ꢀ
±5 ꢀ
±3 ꢀ
−2.5 ꢀ to +7.5 ꢀ
1 ꢀ to 21 ꢀ
1 ꢀ to ±6 ꢀ
1 ꢀ to ±1 ꢀ
1 ꢀ to 5 ꢀ
8
4
2.4
4
8
6.4
4
2
4
2
±.2
±
1
1
1
1
The internal reference is available at the VRFEFIN/VREFOUT pin.
A buffer is required if the reference output is used to drive
external loads. Place a capacitor in the range of 1 nF to 100 nF
between the reference output and DGND to improve the noise
performance.
DAC ARCHITECTURE
Reference Buffer
The DAC architecture consists of an R-2R DAC followed by an
output buffer amplifier. Figure 72 shows a block diagram of the
DAC architecture. Note that the reference input is buffered
prior to being applied to the DAC. The AD5761R/AD5721R
offer a 2.5 V, 5 ppm/°C maximum internal reference on chip.
The AD5761R/AD5721R can operate with either an external or
internal reference. The reference input has an input range of 2 V
to ± V with 2.5 V for specified performance. This input voltage
is then buffered before it is applied to the DAC core.
The output voltage range obtained from the configurable output
amplifier is selected by writing to the ± LSBs (RA[2:0]) in the
control register.
Rev. C | Page 25 of 36
AD5761R/AD5721R
Data Sheet
DAC Output Amplifier
Daisy-Chain Operation
The output amplifier is capable of generating both unipolar and
bipolar output voltages. It is capable of driving a load of 2 kΩ in
parallel with 1 nF to AGND. The source and sink capabilities of
the output amplifier are shown in Figure 45.
For systems that contain several devices, use the SDO pin to
daisy chain several devices together. Daisy-chain mode is useful
in system diagnostics and in reducing the number of serial
SYNC
interface lines. The first falling edge of
cycle. SCLK is continuously applied to the input shift register
SYNC
starts the write
SERIAL INTERFACE
when
is low. If more than 24 clock pulses are applied, the
SYNC
The AD5761R/AD5721R 4-wire digital interface (
SDI, and SDO) is SPI compatible. The write sequence begins
SYNC
, SCLK,
data ripples out of the shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge.
after bringing the
line low, and maintaining this line low
until the complete data-word is loaded from the SDI pin. Data
is loaded in at the SCLK falling edge transition (see Figure 2).
By connecting the SDO of the first device to the SDI input of
the next device in the chain, a multidevice interface is constructed.
Each device in the system requires 24 clock pulses. Therefore,
the total number of clock cycles must equal 24 × N, where N is
the total number of AD5761R/AD5721R devices in the chain.
SYNC
When
is brought high again, the serial data-word is
decoded according to the instructions in Table 10. The
AD5761R/AD5721R contain an SDO pin to allow the user
to daisy-chain multiple devices together or to read back the
contents of the registers.
SYNC
When the serial transfer to all devices is complete,
is
taken high, which latches the input data in each device in the
daisy chain and prevents any further data from being clocked
into the input shift register.
Standalone Operation
The serial interface works with both a continuous and
noncontinuous serial clock. A continuous SCLK source can
CONTROLLER
AD5761R/
SYNC
be used only when
of clock cycles.
is held low for the correct number
AD5721R*
SDI
DATA OUT
SERIAL CLOCK
CONTROL OUT
DATA IN
In gated clock mode, a burst clock containing the exact number
SYNC
SCLK
SYNC
of clock cycles must be used, and
must be taken high
after the final clock to latch the data. The first falling edge of
SDO
SYNC
starts the write cycle. Exactly 24 falling clock edges must
SYNC
be applied to SCLK before
is brought high again. If
SDI
SYNC
is brought high before the 24th falling SCLK edge, the
data written is invalid. If more than 24 falling SCLK edges are
AD5761R/
AD5721R*
SYNC
applied before
invalid.
is brought high, the input data is also
SCLK
SYNC
SDO
SYNC
must be brought
The input shift register is updated on the rising edge of
SYNC
.
For another serial transfer to take place,
low again. After the end of the serial data transfer, data is
automatically transferred from the input shift register to the
addressed register. When the write cycle is complete, the output
SDI
AD5761R/
AD5721R*
LDAC
SYNC
can be updated by taking
low while
is high.
SCLK
Readback Operation
SYNC
SDO
The contents of the input, DAC, and control registers can be
read back via the SDO pin. Figure 4 shows how the registers are
decoded. After a register has been addressed for a read, the next
24 clock cycles clock the data out on the SDO pin. The clocks
*
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 74. Daisy-Chain Block Diagram
SYNC
SYNC
must be applied while
is low. When
is returned
HARDWARE CONTROL PINS
LDAC
high, the SDO pin is placed in tristate. For a read of a single
register, the no operation (NOP) function clocks out the data.
Alternatively, if more than one register is to be read, the data of
the first register to be addressed clocks out at the same time that
the second register to be read is being addressed. The SDO pin
must be enabled to complete a readback operation. The SDO pin
is enabled by default.
Load DAC Function (
)
After data transfers into the input register of the DAC, there are
two ways to update the DAC register and DAC output. Depend-
SYNC
LDAC
ing on the status of both
and
, one of two update
modes is selected: synchronous DAC update or asynchronous
DAC update.
Rev. C | Page 26 of 36
Data Sheet
AD5761R/AD5721R
In the event of the die temperature exceeding approximately
Synchronous DAC Update
ALERT
150°C, the
pin is low and the value of the ETS bit
LDAC
In synchronous DAC update mode,
is held low while
determines the state of the digital supply of the device, whether
the internal digital supply is powered on or powered down. If
the ETS bit is set to 0, the internal digital supply is powered on
when the internal die temperature exceeds approximately
150°C. If the ETS bit is set to 1, the internal digital supply is
powered down when the internal die temperature exceeds
approximately 150°C, and the device becomes nonfunctional
(see Table 11 and Table 12).
data is being clocked into the input shift register. The DAC
SYNC
output is updated on the rising edge of
.
Asynchronous DAC Update
LDAC
In asynchronous DAC update mode,
data is being clocked into the input shift register. The DAC output
LDAC SYNC
is held high while
is asynchronously updated by taking
taken high. The update then occurs on the falling edge of
RESET
low after
is
LDAC
.
The AD5761R/AD5721R temperature at power-up must be less
than 150°C for proper operation of the devices.
Reset Function (
The AD5761R/AD5721R can be reset to their power-on state
RESET
)
THERMAL HYSTERESIS
by two means: either by asserting the
software full reset registers (see Table 26).
CLEAR
pin or by using the
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient to
cold, to hot, and then back to ambient. Thermal hysteresis data
was tested for the AD5761R as shown in Figure 75. It is measured
by sweeping the temperature from ambient to −40°C, then to
125°C, and returning to ambient. The VREF delta is then
measured between the two ambient measurements (shown in
Figure 75).
Asynchronous Clear Function (
CLEAR
)
The
pin is a falling edge active input that allows the
output to be cleared to a user defined value. The clear code
value is programmed by writing to Bit 10 and Bit 9 in the
CLEAR
control register (see Table 11 and Table 12). Maintain
low for the minimum time of 20 ns to complete the operation
5
CLEAR
(see Figure 2). When the
signal is returned high, the
output remains at the clear value until a new value is loaded to
the DAC register.
4
3
2
1
0
ALERT
Alert Function (
)
ALERT
When the
pin is asserted low, a readback from the control
register is required to clarify whether a short-circuit or brownout
condition occurred, depending on the values of Bit 12 and Bit 11,
the SC and BO bits, respectively (see Table 15 and Table 16). If
neither of these conditions occurred, the temperature exceeded
approximately 150°C.
ALERT
The
a hardware reset. After the first write to the control register to
ALERT
pin is low during power-up, a software full reset, or
–120
–100
–80
–60
–40
–20
DISTORTION (ppm)
configure the DAC, the
pin is asserted high.
Figure 75. Thermal Hysteresis
Rev. C | Page 27 of 36
AD5761R/AD5721R
Data Sheet
REGISTER DETAILS
INPUT SHIFT REGISTER
The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input,
SCLK, which can operate at rates of up to 50 MHz. The input shift register consists of three don’t care bits, one fixed value bit (DB20 = 0),
four address bits, and a 16-bit or 12-bit data-word as shown in Table 8 and Table 9, respectively.
Table 8. AD5761R 16-Bit Input Shift Register Format
MSB
DB23
X1
LSB
DB22
X1
DB21
X1
DB20
DB19
DB18
DB17
DB16
DB[15:0]
0
Register address
Register data
1 X is don’t care.
Table 9. AD5721R 12-Bit Input Shift Register Format
MSB
LSB
DB23
X1
DB22
X1
DB21
X1
DB20
DB19
DB18
DB17
DB16
DB[15:4]
DB[3:0]
XXXX1
0
Register address
Register data
1 X is don’t care.
Table 10. Input Shift Register Commands
Register Address
DB19 DB18 DB17 DB16 Command
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No operation
Write to input register (no update)
Update DAC register from input register
Write and update DAC register
Write to control register
No operation
No operation
Software data reset
Reserved
Disable daisy-chain functionality
Readback input register
Readback DAC register
Readback control register
No operation
No operation
Software full reset
Rev. C | Page 28 of 36
Data Sheet
AD5761R/AD5721R
CONTROL REGISTER
The control register controls the mode of operation of the AD5761R/AD5721R. The control register options are shown in Table 11 and
Table 12.
On power-up, after a full reset, or after a hardware reset, the output of the DAC is clamped to ground through a 1 kΩ resistor and the
output buffer remains in power-down mode. A write to the control register is required to configure the device, remove the clamp to
ground, and power up the output buffer.
When the DAC output range is reconfigured during operation, a software full reset command (see Table 26) must be written to the device
before writing to the control register.
Table 11. Write to Control Register
MSB
LSB
DB[23:21]
DB20
DB[19:16]
Register address
0100
DB[15:11]
DB[10:9]
DB8
DB7
Register data
B2C ETS
DB6
DB5
DB[4:3]
DB[2:0]
XXX1
0
XXXXX1
CV[1:0]
OVR
IRO
PV[1:0]
RA[2:0]
1 X is don’t care.
Table 12. Control Register Functions
Bit Name
Description
CV[1:0]
CLEAR voltage selection.
00: zero scale
01: midscale
10, 11: full scale
OVR
B2C
ETS
5% overrange.
0: 5% overrange disabled
1: 5% overrange enabled
Bipolar range.
0: DAC input for bipolar output range is straight binary coded
1: DAC input for bipolar output range is twos complement coded
Thermal shutdown alert. The alert may not work correctly if the device powers on with temperature conditions >150°C
(greater than the maximum rating of the device).
0: internal digital supply does not power down if die temperature exceeds 150°C.
1: internal digital supply powers down if die temperature exceeds 150°C.
IRO
Internal reference.
0: internal reference turned off
1: internal reference turned on
PV[1:0]
Power up voltage.
00: zero scale
01: midscale
10, 11: full scale
RA[2:0]
Output range. Before an output range configuration, the device must be reset.
000: −10 V to +10 V
001: 0 V to +10 V
010: −5 V to +5 V
011: 0 V to 5 V
100: −2.5 V to +7.5 V
101: −3 V to +3 V
110: 0 V to 16 V
111: 0 V to 20 V
Rev. C | Page 29 of 36
AD5761R/AD5721R
Data Sheet
Table 13. Bipolar Output Range Possible Codes
Straight Binary
Decimal Code
Twos Complement
0111
1111
7
1110
6
0110
1101
5
0101
1100
4
0100
1011
3
0011
1010
2
0010
1001
1
0001
1000
0
0000
0111
0110
0101
0100
0011
0010
0001
0000
−1
−2
−3
−4
−5
−6
−7
−8
1111
1110
1101
1100
1011
1010
1001
1000
READBACK CONTROL REGISTER
The readback control register operation provides the contents of the control register by setting the register address to 1100. Table 14
outlines the 24-bit shift register for this command, where the last 16 bits are don’t care bits.
During the next command, the control register contents are shifted out of the SDO pin with the MSB shifted out first. Table 15 outlines
the 24-bit data read from the SDO pin, where DB23 is the first bit shifted out.
Table 14. Readback Control Register, 24-Bit Shift Register to the SDI Pin
MSB
LSB
DB[23:21]
DB20
DB[19:16]
Register address
1100
DB[15:0]
Register data
Don’t care
XXX1
0
1 X is don’t care.
Table 15. Readback Control Register, 24-Bit Data Read from the SDO Pin
MSB
LSB
DB8 DB7 DB6 DB5 DB[4:3] DB[2:0]
Register data
OVR B2C
DB[23:21] DB20 DB[19:16]
Register address
1100
DB[15:13] DB12 DB11 DB[10:9]
XXXX1
SC BO CV[1:0]
XXX1
0
ETS
IRO
PV[1:0]
RA[2:0]
1 X is don’t care.
Table 16. Readback Control Register Bit Descriptions
Bit Name
Description
SC
Short-circuit condition. The SC bit is reset at every control register write.
0: no short-circuit condition detected
1: short-circuit condition detected
BO
Brownout condition. The BO bit is reset at every control register write.
0: no brownout condition detected
1: brownout condition detected
Rev. C | Page 30 of 36
Data Sheet
AD5761R/AD5721R
UPDATE DAC REGISTER FROM INPUT REGISTER
The update DAC register function loads the DAC register with the data saved in the input register and updates the DAC output voltage.
LDAC
This operation is equivalent to a software
. Table 17 outlines how data is written to the DAC register.
Table 17. Update DAC Register from Input Register
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB[15:0]
Register address
0010
Register data
Don’t care
X1
X1
X1
0
1 X is don’t care.
READBACK DAC REGISTER
The readback DAC register operation provides the contents of the DAC register by setting the register address to 1011. Table 18 outlines
the 24-bit shift register for this command. During the next command, the DAC register contents are shifted out of the SDO pin with the
MSB shifted out first. Table 19 outlines the 24-bit data read from the SDO pin, where DB23 is the first bit shifted out.
Table 18. Readback DAC Register, 24-Bit Shift Register to SDI Pin
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB[15:0]
Register address
1011
Register data
Don’t care
X1
X1
X1
0
1 X is don’t care.
Table 19. Readback DAC Register, 24-Bit Data Read from SDO Pin
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
Register address
1011
DB17
DB16
DB[15:0]
Register data
X1
X1
X1
0
Data read from DAC register
1 X is don’t care.
WRITE AND UPDATE DAC REGISTER
The write and update DAC register (Register Address 0011) updates the input register and the DAC register with the entered data-word
LDAC
from the input shift register, irrespective of the state of
.
Setting the register address to 0001 writes the input register with the data from the input shift register, clocked in MSB first on the SDI pin.
Table 20. Write and Update DAC Register
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB[15:0]
Register address
0001
Register data
Data loaded
Data loaded
X1
X1
X1
X1
X1
X1
0
0
0011
1 X is don’t care.
Rev. C | Page 31 of 36
AD5761R/AD5721R
Data Sheet
READBACK INPUT REGISTER
The readback input register operation provides the contents of the input register by setting the register address to 1010. Table 21 outlines
the 24-bit shift register for this command. During the next command, the input register contents are shifted out of the SDO pin with the
MSB shifted out first. Table 22 outlines the 24-bit data read from the SDO pin, where DB23 is the first bit shifted out.
Table 21. Readback Input Register, 24-Bit Shift Register to the SDI Pin
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB[15:0]
Register address
1010
Register data
Don’t care
X1
X1
X1
0
1 X is don’t care.
Table 22. Readback Input Register, 24-Bit Data Read from the SDO Pin
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
Register address
1010
DB17
DB16
DB[15:0]
Register data
X1
X1
X1
0
Data read from input register
1 X is don’t care.
DISABLE DAISY-CHAIN FUNCTIONALITY
The daisy-chain feature can be disabled to save the power consumed by the SDO buffer when this functionality is not required (see Table 23).
When disabled, a readback request is not accepted because the SDO pin remains in tristate.
Table 23. Disable Daisy-Chain Functionality Register
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB[15:1]
DB0
Register address
1001
Register data
X1
X1
X1
0
Don’t care
DDC
1 X is don’t care.
Table 24. Disable Daisy-Chain Bit Description
Bit Name Description
DDC
DDC decides whether daisy-chain functionality is enabled or disabled for the device. By default, daisy-chain functionality is
enabled.
0: daisy-chain functionality is enabled for the device.
1: daisy-chain functionality is disabled for the device.
SOFTWARE DATA RESET
The AD5761R/AD5721R can be reset via software to zero scale, midscale, or full scale (see Table 25). The value to which the device is
reset is specified by the PV[1:0] bits, which are set in the write to control register command (see Table 11 and Table 12).
Table 25. Software Data Reset Register
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB[15:0]
Register address
0111
Register data
Don’t care
X1
X1
X1
0
1 X is don’t care.
Rev. C | Page 32 of 36
Data Sheet
AD5761R/AD5721R
SOFTWARE FULL RESET
The device can also be reset completely via software (see Table 26). When the register address is set to 1111, the device behaves in a
power-up state, where the output is clamped to AGND and the output buffer is powered down. The user must write to the control register
to configure the device, remove the 1 kΩ resistor clamp to ground, and power up the output buffer.
The software full reset command is also issued when the DAC output range is reconfigured during normal operation.
Table 26. Software Full Reset Register
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB[15:0]
Register address
1111
Register data
Don’t care
X1
X1
X1
0
1 X is don’t care.
NO OPERATION REGISTERS
The no operation registers are ignored and do not vary the state of the device (see Table 27).
Table 27. No Operation Registers
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB[15:0]
Register address
Register data
Don’t care
X1
X1
X1
0
0000/0101/0110/1101/1110
1 X is don’t care.
Rev. C | Page 33 of 36
AD5761R/AD5721R
Data Sheet
APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
POWER SUPPLY CONSIDERATIONS
Figure 76 shows the typical operating circuit for the AD5761R/
AD5721R. The only external components needed for this
precision 16-/12-bit DAC are decoupling capacitors on the
supply pins and supply voltage. Because the AD5761R/AD5721R
incorporate a voltage reference and reference buffers, they
eliminate the need for an external bipolar reference and
associated buffers, resulting in overall savings in both cost and
board space.
The AD5761R/AD5721R must be powered by the following
three supplies to provide any of the eight output voltage ranges
available on the DAC: VDD = 21 V, VSS = −11 V, and DVCC = 5 V.
For applications requiring optimal high power efficiency and
low noise performance, it is recommended to use the ADP5070
switching regulator to convert the 5 V input rail into two
intermediate rails (+23 V and −13 V). These intermediate rails
are then postregulated by very low noise, low dropout (LDO)
regulators (ADP7142 and ADP7182). Figure 77 shows the
recommended method.
In Figure 76, VDD is connected to 15 V and VSS is connected to
−15 V, but VDD and VSS can operate with supplies from 4.75 V to
30 V and from −16.5 V to 0 V, respectively.
ADP5070
+23V
DC-TO-DC
SWITCHING
REGULATOR
AD5761R/
AD5721R
ADP7142
LDO
+5V INPUT
+21V: VDD
+5V: DVCC
100nF
1
2
3
4
5
6
7
8
ALERT
CLEAR
RESET
16
15
14
13
12
11
10
9
ALERT
CLEAR
RESET
DGND
DV
+
ADP7142
LDO
10µF
+5V
CC
SCLK
SYNC
SDI
SCLK
SYNC
SDI
ADP5070
DC-TO-DC
SWITCHING
REGULATOR
V
V
/
REFIN
REFOUT
–13V
V
ADP7182
LDO
REFIN
–11V: VSS
+5V INPUT
AGND
100nF
100nF
–15V
V
LDAC
SDO
LDAC
SDO
SS
10µF
10µF
Figure 77. Postregulation by ADP7142 and ADP7182
V
V
V
OUT
OUT
DD
EVALUATION BOARD
+15V
DNC
An evaluation board is available for the AD5761R to aid
designers in evaluating the high performance of the device
with minimum effort. The AD5761R evaluation kit includes a
populated and tested AD5761R printed circuit board (PCB).
The evaluation board interfaces to the USB port of a PC. Software
is available with the evaluation board to allow the user to easily
program the AD5761R. The EVAL-AD5761RSDZ user guide
provides full details on the operation of the evaluation board.
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 76. Typical Operating Circuit
Rev. C | Page 34 of 36
Data Sheet
AD5761R/AD5721R
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 78. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
DETAIL A
(JEDEC 95)
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
13
16
TIONS
INDICATOR AREA OP
(SEE DETAIL A)
0.50
BSC
12
1
1.75
1.60 SQ
1.45
EXPOSED
PAD
9
4
8
5
0.50
0.40
0.30
0.20 MIN
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TOJEDEC STANDARDS MO-220-WEED-6.
Figure 79. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-22)
Dimensions shown in millimeters
Rev. C | Page 35 of 36
AD5761R/AD5721R
Data Sheet
ORDERING GUIDE
Resolution
(Bits)
Internal
Reference (V)
Temperature
Range
INL
(LSB)
Package
Description
Package
Option
Marking
Code
Model1, 2
AD5721RBRUZ
12
12
12
16
16
16
16
16
16
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
0.5
0.5
0.5
8
8
2
2
8
2
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP
16-Lead LFCSP
Evaluation Board
SDP Controller Board
RU-16
RU-16
CP-16-22
RU-16
RU-16
RU-16
RU-16
CP-16-22
CP-16-22
AD5721RBRUZ-RL7
AD5721RBCPZ-RL7
AD5761RARUZ
AD5761RARUZ-RL7
AD5761RBRUZ
AD5761RBRUZ-RL7
AD5761RACPZ-RL7
AD5761RBCPZ-RL7
EVAL-AD5761RSDZ
EVAL-SDP-CB1Z
DHN
DJ5
DJ6
1 Z = RoHS Compliant Part.
2 The EVAL-AD5761RSDZ can be used to evaluate the AD5721R.
©2014–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12355-0-1/18(C)
Rev. C | Page 36 of 36
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