AD5694BRUZ [ADI]
Quad 16-/12-Bit nanoDAC I2C Interface;
| 型号： | AD5694BRUZ |
| 厂家： | 
ADI |
| 描述： | Quad 16-/12-Bit nanoDAC I2C Interface 光电二极管 转换器 |
| 文件： | 总24页 (文件大小：748K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad, 16-/12-Bit nanoDAC+
with I2C Interface
Data Sheet
AD5696/AD5694
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High relative accuracy (INL): 2 LSB maximum at 16 bits
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): 0.1% of FSR maximum
Offset error: 1.5 mV maximum
Gain error: 0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User-selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
400 kHz I2C-compatible serial interface
4 I2C addresses available
V
GND
V
REF
DD
AD5696/AD5694
V
LOGIC
SCL
STRING
DAC A
INPUT
REGISTER
DAC
REGISTER
V
V
V
V
A
B
C
D
OUT
OUT
OUT
OUT
BUFFER
BUFFER
BUFFER
BUFFER
STRING
DAC B
INPUT
DAC
REGISTER
REGISTER
SDA
A1
STRING
DAC C
INPUT
REGISTER
DAC
REGISTER
A0
STRING
DAC D
INPUT
REGISTER
DAC
REGISTER
Low glitch: 0.5 nV-sec
Low power: 1.8 mW at 3 V
2.7 V to 5.5 V power supply
POWER-ON
RESET
GAIN =
×1/×2
POWER-
DOWN
LOGIC
−40°C to +105°C temperature range
LDAC RESET
RSTSEL
GAIN
APPLICATIONS
Figure 1.
Digital gain and offset adjustment
Programmable attenuators
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5696 and AD5694, members of the nanoDAC+™ family,
are low power, quad, 16-/12-bit buffered voltage output DACs.
The devices include a gain select pin giving a full-scale output
of 2.5 V (gain = 1) or 5 V (gain = 2). The devices operate from
a single 2.7 V to 5.5 V supply, are guaranteed monotonic by
design, and exhibit less than 0.1% FSR gain error and 1.5 mV
offset error performance. The devices are available in a 3 mm ×
3 mm LFCSP package and in a TSSOP package.
Table 1. Quad nanoDAC+ Devices
Interface
Reference 16-Bit
14-Bit
12-Bit
SPI
Internal
External
Internal
External
AD5686R
AD5685R
AD5684R
AD5684
AD5694R
AD5694
AD5686
AD5696R
AD5696
I2C
AD5695R
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5696 (16-bit): 2 LSB maximum
AD5694 (12-bit): 1 LSB maximum
2. Excellent DC Performance.
Total unadjusted error: 0.1% of FSR maximum
Offset error: 1.5 mV maximum
Gain error: 0.1% of FSR maximum
3. Two Package Options.
The AD5696/AD5694 incorporate a power-on reset circuit and a
RSTSEL pin; the RSTSEL pin ensures that the DAC outputs power
up to zero scale or midscale and remain at that level until a valid
write takes place. The parts contain a per-channel power-down
feature that reduces the current consumption of the device in
power-down mode to 4 µA at 3 V.
The AD5696/AD5694 use a versatile 2-wire serial interface that
operates at clock rates up to 400 kHz and include a VLOGIC pin
intended for 1.8 V/3 V/5 V logic.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. B
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Tel: 781.329.4700 ©2012–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5696/AD5694
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Serial Interface ............................................................................ 17
Write and Update Commands.................................................. 18
I2C Slave Address........................................................................ 18
Serial Operation ......................................................................... 18
Write Operation.......................................................................... 18
Read Operation........................................................................... 19
Multiple DAC Readback Sequence.......................................... 19
Power-Down Operation............................................................ 20
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 16
Digital-to-Analog Converter .................................................... 16
Transfer Function ....................................................................... 16
DAC Architecture....................................................................... 16
LDAC
Load DAC (Hardware
Pin)........................................... 20
LDAC
Mask Register ................................................................. 21
RESET
Hardware Reset Pin (
) ................................................... 21
Reset Select Pin (RSTSEL) ........................................................ 21
Applications Information .............................................................. 22
Microprocessor Interfacing....................................................... 22
AD5696/AD5694 to ADSP-BF531 Interface.......................... 22
Layout Guidelines....................................................................... 22
Galvanically Isolated Interface ................................................. 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 24
REVISION HISTORY
11/2016—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to Specifications Section.................................................. 3
Changes to VLOGIC Parameter, Table 1 ............................................ 4
Changes to AC Characteristics Section ......................................... 5
Changes to Timing Characteristics Section.................................. 6
Changes to Table 5............................................................................ 7
RESET
Changes to VLOGIC Pin Description and
Pin Description,
Table 7 ................................................................................................ 8
Changes to Figure 9.......................................................................... 9
Changes to Figure 11 to Figure 16................................................ 10
Changes to Figure 17, Figure 19, and Figure 22......................... 11
Changes to Figure 24...................................................................... 12
Changes to Figure 29...................................................................... 13
Changes to Figure 38...................................................................... 19
RESET
Changes to Hardware Reset Pin (
) Section..................... 21
6/2013—Rev. 0 to Rev. A
Changes to Pin GAIN and Pin RSTSEL Descriptions; Table 7....... 8
7/2012—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
AD5696/AD5694
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.62 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A Grade
Typ
B Grade
Typ
Parameter
STATIC PERFORMANCE2
Min
Max
Min
Max
Unit
Test Conditions/Comments1
AD5696
Resolution
Relative Accuracy
16
16
Bits
LSB
LSB
LSB
2
2
8
8
1
1
1
2
3
1
Gain = 2
Gain = 1
Guaranteed monotonic by
design
Differential Nonlinearity
AD5694
Resolution
Relative Accuracy
Differential Nonlinearity
12
12
Bits
LSB
LSB
0.12
2
1
0.12
1
1
Guaranteed monotonic by
design
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
0.4
4
0.4
1.5
1.5
0.1
0.1
0.1
0.2
mV
mV
All 0s loaded to DAC register
+0.1
+0.01
0.02
0.01
4
0.2
0.2
0.25
0.25
+0.1
+0.01
0.02
0.01
% of FSR All 1s loaded to DAC register
% of FSR
% of FSR Gain = 2
% of FSR Gain = 1
µV/°C
ppm
mV/V
µV
Total Unadjusted Error
Offset Error Drift3
Gain Temperature
Coefficient3
1
1
1
1
Of FSR/°C
DC Power Supply Rejection
0.15
2
0.15
2
DAC code = midscale; VDD
5 V 10%
=
Ratio3
DC Crosstalk3
Due to single channel, full-
scale output change
3
2
3
2
µV/mA
µV
Due to load current change
Due to power-down (per
channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
0
VREF
2 × VREF
0
0
VREF
2 × VREF
V
V
nF
nF
kΩ
Gain = 1
Gain = 2 (see Figure 20)
RL = ∞
Capacitive Load Stability
2
10
2
10
RL = 1 kΩ
Resistive Load4
Load Regulation
1
1
DAC code = midscale
80
80
80
80
µV/mA
µV/mA
5 V 10%; −30 mA ≤ IOUT
+30 mA
3 V 10%; −20 mA ≤ IOUT
+20 mA
≤
≤
Short-Circuit Current5
Load Impedance at Rails6
Power-Up Time
40
25
2.5
40
25
2.5
mA
Ω
µs
See Figure 20
Coming out of power-down
mode; VDD = 5 V
REFERENCE INPUT
Reference Current
90
180
90
180
µA
µA
V
VREF = VDD = 5.5 V, gain = 1
VREF = VDD = 5.5 V, gain = 2
Gain = 1
Reference Input Range
1
1
VDD
VDD/2
1
1
VDD
VDD/2
V
Gain = 2
Reference Input Impedance
16
32
16
32
kΩ
kΩ
Gain = 2
Gain = 1
Rev. B | Page 3 of 24
AD5696/AD5694
Data Sheet
A Grade
Typ
B Grade
Typ
Parameter
LOGIC INPUTS3
Min
Max
Min
Max
Unit
Test Conditions/Comments1
Input Current
2
2
µA
V
V
Per pin
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
LOGIC OUTPUTS (SDA)3
Output Low Voltage, VOL
Output High Voltage, VOH
0.3 × VLOGIC
0.3 × VLOGIC
0.7 × VLOGIC
0.7 × VLOGIC
2
4
2
4
pF
0.4
0.4
V
V
pF
ISINK = 3 mA
ISOURCE = 3 mA
VLOGIC − 0.4
VLOGIC − 0.4
Floating State Output
Capacitance
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
1.62
5.5
3
5.5
5.5
1.62
5.5
3
5.5
5.5
V
µA
V
2.7
VREF + 1.5
2.7
VREF + 1.5
Gain = 1
Gain = 2
V
IDD
VIH = VDD, VIL = GND, VDD
2.7 V to 5.5 V
=
Normal Mode7
All Power-Down Modes8
0.59
1
0.7
4
6
0.59
1
0.7
4
6
mA
µA
µA
−40°C to +85°C
−40°C to +105°C
1 Temperature range is −40°C to +105°C.
2 DC specifications are tested with the outputs unloaded, unless otherwise noted. Upper dead band (10 mV) exists only when VREF = VDD with gain = 1 or when VREF/2 = VDD
with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5696) or 12 to 4080 (AD5694).
3 Guaranteed by design and characterization; not production tested.
4 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to 30 mA
up to a junction temperature of 110°C.
5 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum junction temperature may impair device reliability.
6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices.
For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 20).
7 Interface inactive. All DACs active. DAC outputs unloaded.
8 All DACs powered down.
Rev. B | Page 4 of 24
Data Sheet
AD5696/AD5694
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.62 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2
Min
Typ
Max
Unit
Test Conditions/Comments3
Output Voltage Settling Time
AD5696
AD5694
¼ to ¾ scale settling to 2 LSB
5
5
8
7
µs
µs
Slew Rate
0.8
0.5
0.13
500
0.1
0.2
0.3
−80
100
6
V/µs
nV-sec
nV-sec
kHz
nV-sec
nV-sec
nV-sec
dB
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Multiplying Bandwidth
Digital Crosstalk
1 LSB change around major carry transition
Analog Crosstalk
DAC-to-DAC Crosstalk
Total Harmonic Distortion4
Output Noise Spectral Density
Output Noise
Signal-to-Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
DAC code = midscale, 10 kHz, gain = 2
0.1 Hz to 10 Hz
nV/√Hz
µV p-p
dB
90
83
At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
dB
Signal-to-Noise-and-Distortion Ratio
(SINAD)
80
dB
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +105°C; typical at 25°C.
4 Digitally generated sine wave at 1 kHz.
Rev. B | Page 5 of 24
AD5696/AD5694
Data Sheet
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; 1.62 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1, 2 Min
Max
Unit
µs
µs
µs
µs
ns
µs
µs
µs
µs
ns
ns
ns
ns
ns
pF
Description
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
tSP
2.5
0.6
1.3
0.6
100
0
0.6
0.6
1.3
0
20 + 0.1CB
20
400
0
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start hold time
tSU,DAT, data setup time
tHD,DAT, data hold time
tSU,STA, repeated start setup time
tSU,STO, stop condition setup time
tBUF, bus free time between a stop condition and a start condition
tR, rise time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting/receiving
LDAC pulse width
3
0.9
4
300
300
4, 5
SCL rising edge to LDAC rising edge
6
50
400
Pulse width of suppressed spike
Capacitive load for each bus line
5
CB
1 See Figure 2.
2 Guaranteed by design and characterization; not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the SCL
falling edge.
4 tR and tF are measured from 0.3 × VDD to 0.7 × VDD
5 CB is the total capacitance of one bus line in pF.
.
6 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.
Timing Diagram
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
SDA
t9
t10
t11
t4
t3
SCL
t4
t2
t1
t6
t5
t7
t8
t12
1
2
t13
LDAC
LDAC
t12
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
2
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. B | Page 6 of 24
Data Sheet
AD5696/AD5694
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. This
value was measured using a JEDEC standard 4-layer board with
zero airflow. For the LFCSP package, the exposed pad must be
tied to GND.
Table 5.
Parameter
Rating
VDD to GND
VLOGIC to GND
VOUT to GND
VREF to GND
Digital Input Voltage to GND1
SDA and SCL to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−0.3 V to +7 V
−40°C to +105°C
−65°C to +150°C
125°C
Table 6. Thermal Resistance
Package Type
16-Lead LFCSP
16-Lead TSSOP
θJA
Unit
°C/W
°C/W
70
112.6
Reflow Soldering Peak Temperature,
Pb Free (J-STD-020)
260°C
ESD CAUTION
1 Excluding SDA and SCL.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 7 of 24
AD5696/AD5694
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5696/AD5694
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
RSTSEL
RESET
A1
REF
V
V
B
A
OUT
OUT
V
V
A 1
OUT
12 A1
11 SCL
10 A0
AD5696/
AD5694
TOP VIEW
(Not to Scale)
GND 2
GND
SCL
V
3
4
DD
V
A0
DD
9
V
LOGIC
C
OUT
V
V
C
D
V
LOGIC
OUT
OUT
GAIN
LDAC
SDA
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD MUST BE TIED TO GND.
Figure 3. Pin Configuration, 16-Lead LFCSP
Figure 4. Pin Configuration, 16-Lead TSSOP
Table 7. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
VOUT
Description
1
2
3
3
4
5
A
GND
VDD
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Power Supply Input. The parts can be operated from 2.7 V to 5.5 V. The supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4
5
6
6
7
8
VOUT
VOUT
SDA
C
D
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the
24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the
supply with an external pull-up resistor.
7
8
9
LDAC
GAIN
LDAC can be operated in two modes, asynchronous update mode and synchronous update mode.
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new
data; all DAC outputs are simultaneously updated. This pin can also be tied permanently low.
10
Gain Select Pin. When this pin is tied to GND, all four DAC outputs have a span of 0 V to VREF.
When this pin is tied to VLOGIC, all four DAC outputs have a span of 0 V to 2 × VREF
.
9
10
11
11
12
13
VLOGIC
A0
SCL
Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V.
Address Input. Sets the first LSB of the 7-bit slave address.
Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the
24-bit input shift register.
12
13
14
15
A1
RESET
Address Input. Sets the second LSB of the 7-bit slave address.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is activated
(low), the input register and the DAC register are updated with zero scale or midscale, depending
on the state of the RSTSEL pin. When RESET is low, all LDAC pulses are ignored. If the pin is forced
low at power-up, the POR circuit does not initialize correctly until the pin is released.
14
16
RSTSEL
VREF
Power-On Reset Pin. When this pin is tied to GND, all four DACs are powered up to zero scale.
When this pin is tied to VLOGIC, all four DACs are powered up to midscale.
Reference Input Voltage.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Exposed Pad. The exposed pad must be tied to GND.
15
16
17
1
2
N/A
VOUT
B
EPAD
Rev. B | Page 8 of 24
Data Sheet
AD5696/AD5694
TYPICAL PERFORMANCE CHARACTERISTICS
10
8
1.0
0.8
6
0.6
4
0.4
2
0.2
0
0
–2
–4
–6
–0.2
–0.4
–0.6
–0.8
–1.0
V
= 5V
= 25°C
V
= 5V
DD
DD
–8
T
T = 25°C
A
A
REFERENCE = 2.5V
REFERENCE = 2.5V
–10
0
10000
20000
30000
CODE
40000
50000
60000
0
625
1250
1875
CODE
2500
3125
3750 4096
Figure 5. AD5696 INL
Figure 8. AD5694 DNL
10
8
10
8
6
6
4
4
2
2
INL
0
0
DNL
–2
–4
–6
–8
–2
–4
–6
–8
–10
V
= 5V
= 25°C
DD
T
V
= 5V
DD
A
REFERENCE = 2.5V
REFERENCE = 2.5V
–10
0
625
1250
1875
CODE
2500
3125
3750 4096
–40 10
60
110
TEMPERATURE (°C)
Figure 6. AD5694 INL
Figure 9. INL Error and DNL Error vs. Temperature
1.0
0.8
10
8
0.6
6
0.4
4
0.2
2
INL
0
0
DNL
–2
–4
–6
–8
–10
–0.2
–0.4
–0.6
–0.8
–1.0
V
= 5V
= 25°C
DD
V
= 5V
DD
= 25°C
T
A
T
A
REFERENCE = 2.5V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
10000 20000
30000
CODE
40000
50000
60000
V
(V)
REF
Figure 7. AD5696 DNL
Figure 10. INL Error and DNL Error vs. VREF
Rev. B | Page 9 of 24
AD5696/AD5694
Data Sheet
0.10
0.08
0.06
0.04
0.02
0
10
8
6
4
2
GAIN ERROR
INL
0
DNL
FULL-SCALE ERROR
–2
–4
–6
–8
–0.02
–0.04
–0.06
–0.08
–0.10
T
= 25°C
T
= 25°C
A
A
REFERENCE = 2.5V
REFERENCE = 2.5V
–10
2.7
3.2
3.7
4.2
4.7
5.2
2.7 3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 11. INL Error and DNL Error vs. Supply Voltage
Figure 14. Gain Error and Full-Scale Error vs. Supply Voltage
0.10
0.08
0.06
0.04
0.02
0
1.5
1.0
0.5
ZERO-CODE ERROR
FULL-SCALE ERROR
GAIN ERROR
0
OFFSET ERROR
–0.02
–0.04
–0.06
–0.08
–0.10
–0.5
–1.0
–1.5
V
= 5V
T
= 25°C
DD
A
REFERENCE = 2.5V
REFERENCE = 2.5V
–40 –20
0
20
40
60
80
100
120
2.7 3.2
3.7
4.2
4.7
5.2
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 12. Gain Error and Full-Scale Error vs. Temperature
Figure 15. Zero-Code Error and Offset Error vs. Supply Voltage
0.10
V
= 5V
DD
V
= 5V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
DD
REFERENCE = 2.5V
REFERENCE = 2.5V
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
ZERO-CODE ERROR
OFFSET ERROR
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. TUE vs. Temperature
Figure 13. Zero-Code Error and Offset Error vs. Temperature
Rev. B | Page 10 of 24
Data Sheet
AD5696/AD5694
0.10
0.08
0.06
0.04
0.02
0
1.0
0.8
0.6
0.4
SINKING, 2.7V
0.2
SINKING, 5V
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.02
–0.04
–0.06
–0.08
SOURCING, 5V
SOURCING, 2.7V
15
T
= 25°C
A
REFERENCE = 2.5V
–0.10
2.7
0
5
10
20
25
30
3.2
3.7
4.2
4.7
5.2
LOAD CURRENT (mA)
SUPPLY VOLTAGE (V)
Figure 20. Headroom/Footroom vs. Load Current
Figure 17. TUE vs. Supply Voltage, Gain = 1
7
6
0
–0.01
V
= 5V
= 25°C
DD
T
A
REFERENCE = 2.5V
GAIN = 2
0xFFFF
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
–0.09
–0.10
5
4
0xC000
0x8000
0x4000
0x0000
3
2
1
0
V
= 5V
= 25°C
DD
–1
–2
T
A
REFERENCE = 2.5V
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0
10000
20000
30000
CODE
40000
50000
60000 65535
LOAD CURRENT (A)
Figure 21. Source and Sink Capability at 5 V
Figure 18. TUE vs. Code, AD5696
5
4
V
= 5V
= 25°C
DD
V
= 3V
= 25°C
DD
25
T
A
T
A
REFERENCE = 2.5V
GAIN = 1
EXTERNAL
REFERENCE = 2.5V
20
15
10
5
3
0xFFFF
0xC000
0x8000
0x4000
2
1
0x0000
0
–1
0
–2
–60
540
560
580
600
620
640
–40
–20
0
20
40
60
I
(µA)
DD
I
(mA)
OUT
Figure 19. IDD Histogram at 5 V
Figure 22. Source and Sink Capability at 3 V
Rev. B | Page 11 of 24
AD5696/AD5694
Data Sheet
3
2
1
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
V
V
V
A
B
C
D
OUT
OUT
OUT
OUT
GAIN = 2
GAIN = 1
FULL-SCALE
V
= 5V
= 25°C
REFERENCE = 2.5V
DD
T
A
–40
10
60
TEMPERATURE (°C)
110
–5
0
5
10
TIME (µs)
Figure 23. Supply Current vs. Temperature
Figure 26. Exiting Power-Down to Midscale
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.5008
2.5003
2.4998
2.4993
2.4988
V
V
V
V
A
B
C
D
OUT
OUT
OUT
OUT
CHANNEL B
T
= 25°C
A
V
= 5V
= 25°C
REFERENCE = 2.5V
¼ TO ¾ SCALE
V
= 5.25V
DD
DD
T
REFERENCE = 2.5V
CODE = 0x7FFF TO 0x8000
ENERGY = 0.227206nV-sec
A
0
20
40
80
160
320
0
2
4
6
8
10
12
TIME (µs)
TIME (µs)
Figure 24. Settling Time
Figure 27. Digital-to-Analog Glitch Impulse
0.06
6
0.003
0.002
0.001
0
V
V
V
V
V
A
B
C
D
OUT
OUT
OUT
OUT
DD
V
V
V
B
C
D
OUT
OUT
OUT
0.05
0.04
0.03
0.02
0.01
0
5
4
3
2
1
–0.001
–0.002
0
T
= 25°C
REFERENCE = 2.5V
A
–0.01
–1
15
–10
–5
0
5
10
0
5
10
15
20
25
TIME (µs)
TIME (µs)
Figure 28. Analog Crosstalk, VOUTA
Figure 25. Power-On Reset to 0 V
Rev. B | Page 12 of 24
Data Sheet
AD5696/AD5694
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
0nF
V
= 5V
= 25°C
DD
T
0.1nF
0.22nF
4.7nF
10nF
T
A
REFERENCE = 2.5V
1
V
= 5V
= 25°C
DD
T
A
REFERENCE = 2.5V
1.590 1.595 1.600 1.605 1.610 1.615 1.620 1.625 1.630
CH1 2µV
M1.0s
A CH1
802mV
TIME (ms)
Figure 29. 0.1 Hz to 10 Hz Output Noise Plot
Figure 31. Settling Time vs. Capacitive Load
20
0
0
V
= 5V
= 25°C
DD
T
A
REFERENCE = 2.5V
–10
–20
–40
–20
–30
–40
–50
–60
–60
–80
–100
–120
–140
–160
–180
V
= 5V
DD
T
= 25°C
A
REFERENCE = 2.5V, ±0.1V p-p
10k 100k
FREQUENCY (Hz)
0
2000 4000 6000 8000 10000 12000 14000 16000 18000 20000
FREQUENCY (Hz)
1M
10M
Figure 30. Total Harmonic Distortion at 1 kHz
Figure 32. Multiplying Bandwidth
Rev. B | Page 13 of 24
AD5696/AD5694
Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
Relative accuracy or integral nonlinearity is a measurement of
the maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function. Figure 5
and Figure 6 show typical INL vs. code plots.
Output Voltage Settling Time
The output voltage settling time is the amount of time it takes
for the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change.
Digital-to-Analog Glitch Impulse
Differential Nonlinearity (DNL)
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by 1 LSB
at the major carry transition (0x7FFF to 0x8000) (see Figure 27).
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent codes.
A specified differential nonlinearity of 1 LSB maximum ensures
monotonicity. The AD5696/AD5694 are guaranteed monotonic
by design. Figure 7 and Figure 8 show typical DNL vs. code plots.
Digital Feedthrough
Zero-Code Error
Digital feedthrough is a measurement of the impulse injected into
the analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5696/AD5694 because the output of the DAC cannot go
below 0 V due to a combination of the offset errors in the DAC
and the output amplifier. Zero-code error is expressed in mV.
Figure 13 shows a plot of zero-code error vs. temperature.
Noise Spectral Density (NSD)
Noise spectral density is a measurement of the internally gener-
ated random noise. Random noise is characterized as a spectral
density (nV/√Hz) and is measured by loading the DAC to mid-
scale and measuring noise at the output. It is measured in nV/√Hz.
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range (% of FSR). Figure 12 shows a
plot of full-scale error vs. temperature.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC
in response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC
kept at midscale. It is expressed in μV.
Gain Error
Gain error is a measurement of the span error of the DAC. It is
the deviation in slope of the DAC transfer characteristic from
the ideal expressed in % of FSR.
DC crosstalk due to load current change is a measurement
of the impact that a change in load current on one DAC has
on another DAC kept at midscale. It is expressed in μV/mA.
Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in ppm
of FSR/°C.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output of
one DAC at midscale in response to a full-scale code change (all
0s to all 1s and vice versa) in the input register of another DAC.
It is expressed in nV-sec.
Offset Error
Offset error is a measurement of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV in the linear region
of the transfer function. It can be negative or positive.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC in response to a change in the output of another DAC.
To measure analog crosstalk, load one of the input registers with
a full-scale code change (all 0s to all 1s and vice versa), and then
execute a software LDAC and monitor the output of the DAC
whose digital code was not changed. The area of the glitch is
expressed in nV-sec.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with changes in temperature. It is expressed in µV/°C.
DC Power Supply Rejection Ratio (PSRR)
DC PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
VOUT to a change in VDD for midscale output of the DAC. It is mea-
sured in mV/V. VREF is held at 2.5 V, and VDD is varied by 10%.
Rev. B | Page 14 of 24
Data Sheet
AD5696/AD5694
DAC-to-DAC Crosstalk
Total Harmonic Distortion (THD)
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC in response to a digital code change and
subsequent analog output change of another DAC. It is measured
by loading one channel with a full-scale code change (all 0s to
all 1s and vice versa) using the write to and update commands
while monitoring the output of another channel that is at mid-
scale. The energy of the glitch is expressed in nV-sec.
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC; THD is a measurement of the harmonics
present on the DAC output. It is measured in dB.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Rev. B | Page 15 of 24
AD5696/AD5694
Data Sheet
THEORY OF OPERATION
The resistor string structure is shown in Figure 34. Each resistor
in the string has a value R. The code loaded to the DAC register
determines the node on the string from which the voltage is
tapped off and fed into the output amplifier. The voltage is tapped
off by closing one of the switches that connect the string to the
amplifier. Because the AD5696/AD5694 are a string of resistors,
they are guaranteed monotonic.
DIGITAL-TO-ANALOG CONVERTER
The AD5696/AD5694 are quad, 16-/12-bit, serial input, voltage
output DACs that operate from supply voltages of 2.7 V to 5.5 V.
Data is written to the AD5696/AD5694 in a 24-bit word format
via a 2-wire serial interface. The AD5696/AD5694 incorporate a
power-on reset circuit to ensure that the DAC output powers up
to a known output state. The devices also have a software power-
down mode that reduces the current consumption to 4 µA.
V
REF
R
TRANSFER FUNCTION
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
R
R
D
VOUT = VREF × Gain
TO OUTPUT
AMPLIFIER
N
2
where:
REF is the value of the external reference.
V
Gain is the gain of the output amplifier and is set to 1 by default.
The gain can be set to 1 or 2 using the gain select pin. When the
GAIN pin is tied to GND, all four DAC outputs have a span of
0 V to VREF. When this pin is tied to VDD, all four DAC outputs
R
R
have a span of 0 V to 2 × VREF
.
D is the decimal equivalent of the binary code that is loaded to
the DAC register as follows: 0 to 4095 for the 12-bit AD5694,
and 0 to 65,535 for the 16-bit AD5696.
Figure 34. Resistor String Structure
N is the DAC resolution (12 bits or 16 bits).
Output Amplifiers
The output buffer amplifier can generate rail-to-rail voltages on
its output for an output range of 0 V to VDD. The actual range
depends on the value of VREF, the GAIN pin, the offset error,
and the gain error. The GAIN pin selects the gain of the output.
DAC ARCHITECTURE
The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 33 shows a block diagram of the DAC
architecture.
V
•
When this pin is tied to GND, all four outputs have a gain
of 1, and the output range is from 0 V to VREF
When this pin is tied to VDD, all four outputs have a gain
of 2, and the output range is from 0 V to 2 × VREF
REF
.
•
REF (+)
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
.
V
X
OUT
REF (–)
The output amplifiers are capable of driving a load of 1 kΩ in
parallel with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼
to ¾ scale settling time of 5 µs.
GAIN
(GAIN = 1 OR 2)
GND
Figure 33. Single DAC Channel Architecture Block Diagram
Rev. B | Page 16 of 24
Data Sheet
AD5696/AD5694
Table 8. Command Definitions
SERIAL INTERFACE
Command Bits
The AD5696/AD5694 have a 2-wire, I2C-compatible serial
interface (see the I2C-Bus Specification, Version 2.1, January
2000, available from Philips Semiconductor). See Figure 2 for a
timing diagram of a typical write sequence. The AD5696/AD5694
can be connected to an I2C bus as slave devices, under the control
of a master device. The AD5696/AD5694 support standard
(100 kHz) and fast (400 kHz) data transfer modes. Support is
not provided for 10-bit addressing or general call addressing.
C3
0
C2
0
C1
0
C0
0
Command
No operation
0
0
0
1
Write to Input Register n (dependent
on LDAC)
0
0
1
0
Update DAC Register n with contents
of Input Register n
0
0
0
0
0
1
0
1
1
1
0
0
1
0
1
Write to and update DAC Channel n
Power down/power up DAC
Hardware LDAC mask register
Software reset (power-on reset)
Reserved
Input Shift Register
The input shift register of the AD5696/AD5694 is 24 bits wide.
Data is loaded into the device, MSB first, as a 24-bit word under
the control of the serial clock input, SCL. The first eight MSBs
make up the command byte (see Figure 35 and Figure 36).
1
1
X1
1
1
X1
0
1
X1
Reserved
1 X = don’t care.
The first four bits of the command byte are the command
bits (C3, C2, C1, and C0), which control the mode of oper-
ation of the device (see Table 8).
The last four bits of the command byte are the address bits
(DAC D, DAC C, DAC B, and DAC A), which select the
DAC that is operated on by the command (see Table 9).
Table 9. Address Bits and Selected DACs
Address Bits
DAC D DAC C DAC B DAC A Selected DAC Channels1
0
0
0
0
0
0
0
1
1
…
1
0
0
0
1
1
1
1
0
0
…
1
0
1
1
0
0
1
1
0
0
…
1
1
0
1
0
1
0
1
0
1
…
1
DAC A
DAC B
DAC A and DAC B
DAC C
DAC A and DAC C
DAC B and DAC C
DAC A, DAC B, and DAC C
DAC D
DAC A and DAC D
…
All DACs
The 8-bit command byte is followed by two data bytes, which
contain the data-word. For the AD5696, the data-word comprises
the 16-bit input code (see Figure 35); for the AD5694, the data-
word comprises the 12-bit input code followed by four don’t care
bits (see Figure 36). The data bits are transferred to the input
shift register on the 24 falling edges of SCL.
Commands can be executed on one DAC channel, any two or
three DAC channels, or on all four DAC channels, depending
on the address bits selected (see Table 9).
1 Any combination of DAC channels can be selected using the address bits.
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3
C2
C1
C0 DAC D DAC C DAC B DAC A D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND
DAC ADDRESS
DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 35. Input Shift Register Contents, AD5696
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3
C2
C1
C0 DAC D DAC C DAC B DAC A D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
COMMAND
DAC ADDRESS
DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 36. Input Shift Register Contents, AD5694
Rev. B | Page 17 of 24
AD5696/AD5694
Data Sheet
WRITE AND UPDATE COMMANDS
SERIAL OPERATION
The 2-wire I2C serial bus protocol operates as follows:
LDAC
Pin) section.
For more information about the
LDAC
function, see the Load
DAC (Hardware
1. The master initiates a data transfer by establishing a start
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address.
2. The slave device with the transmitted address responds by
pulling SDA low during the 9th clock pulse (this is called
the acknowledge bit). At this stage, all other devices on the
bus remain idle while the selected device waits for data to
be written to, or read from, its input shift register.
3. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
Transitions on the SDA line must occur during the low period
of SCL; SDA must remain stable during the high period of SCL.
4. After all data bits are read or written, a stop condition is
established. In write mode, the master pulls the SDA line high
during the 10th clock pulse to establish a stop condition. In
read mode, the master issues a no acknowledge for the 9th
clock pulse (that is, the SDA line remains high). The master
then brings the SDA line low before the 10th clock pulse and
then high again during the 10th clock pulse to establish a
stop condition.
Write to Input Register n (Dependent on
)
LDAC
Command 0001 allows the user to write to each DAC’s
LDAC
dedicated input register individually. When
is low, the
LDAC
input register is transparent (if not controlled by the
mask register).
Update DAC Register n with Contents of Input Register n
Command 0010 loads the DAC registers/outputs with the
contents of the input registers selected by the address bits
(see Table 9) and updates the DAC outputs directly.
Write to and Update DAC Channel n (Independent of
)
LDAC
Command 0011 allows the user to write to the DAC registers
and update the DAC outputs directly, independent of the state
LDAC
of the
pin.
I2C SLAVE ADDRESS
The AD5696/AD5694 have a 7-bit I2C slave address. The five
MSBs are 00011, and the two LSBs (A1 and A0) are set by the
state of the A1 and A0 address pins. The ability to make hard-
wired changes to A1 and A0 allows the user to incorporate up
to four AD5696/AD5694 devices on one bus (see Table 10).
WRITE OPERATION
When writing to the AD5696/AD5694, the user must begin with
Table 10. Device Address Selection
W
a start command followed by an address byte (R/ = 0), after
A1 Pin Connection
A0 Pin Connection
A1 Bit
A0 Bit
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. The AD5696/AD5694 require two bytes of
data for the DAC and a command byte that controls various DAC
functions. Three bytes of data must, therefore, be written to the
DAC with the command byte followed by the most significant
data byte and the least significant data byte, as shown in Figure 37.
All these data bytes are acknowledged by the AD5696/AD5694.
A stop condition follows.
GND
GND
VLOGIC
VLOGIC
GND
VLOGIC
GND
VLOGIC
0
0
1
1
0
1
0
1
1
9
1
9
SCL
0
0
0
1
1
A1
A0
R/W
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
ACK BY
SDA
ACK BY
AD5696/AD5694
START BY
MASTER
AD5696/AD5694
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB7
DB6 DB5 DB4
DB3
DB2
DB1
DB0
DB8
ACK BY
AD5696/AD5694
ACK BY
STOP BY
AD5696/AD5694 MASTER
FRAME 3
MOST SIGNIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 37. I2C Write Operation
Rev. B | Page 18 of 24
Data Sheet
AD5696/AD5694
READ OPERATION
MULTIPLE DAC READBACK SEQUENCE
When reading data back from the AD5696/AD5694, the user
must begin with a start command followed by an address byte
When reading data back from multiple AD5696/AD5694 DACs,
W
the user begins with an address byte (R/ = 0), after which the
W
(R/ = 0), after which the DAC acknowledges that it is prepared
DAC acknowledges that it is prepared to receive data by pulling
SDA low. The address byte must be followed by the command
byte, which is also acknowledged by the DAC. The user selects
the first channel to read back using the command byte.
to receive data by pulling SDA low. The address byte must be
followed by the command byte, which determines both the read
command that is to follow and the pointer address to read from;
the command byte is also acknowledged by the DAC. The user
configures the channel to read back the contents of one or more
DAC registers and sets the readback command to active using
the command byte.
Following this, the master establishes a repeated start condition,
W
and the address is resent with R/ = 1. This byte is acknowledged
by the DAC, indicating that it is prepared to transmit data. The
first two bytes of data are then read from DAC Input Register n
(selected using the command byte), most significant byte first, as
shown in Figure 38. The next two bytes read back are the contents
of DAC Input Register n + 1, and the next bytes read back are
the contents of DAC Input Register n + 2. Data is read from the
DAC input registers in this auto-incremented fashion until a
NACK followed by a stop condition follows. If the contents of
DAC Input Register D are read out, the next two bytes of data
that are read are the contents of DAC Input Register A.
Following this, the master establishes a repeated start condition,
and the address is resent with R/ = 1. This byte is acknowledged
by the DAC, indicating that it is prepared to transmit data. Two
bytes of data are then read from the DAC, as shown in Figure 38.
A NACK condition from the master, followed by a stop condition,
completes the read sequence. If more than one DAC is selected,
Channel A is read back by default.
W
1
9
1
9
SCL
0
0
0
1
1
A1
A0
R/W
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
ACK BY
SDA
ACK BY
AD5696/AD5694
START BY
MASTER
AD5696/AD5694
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
SDA
0
0
0
1
1
A1
A0
R/W
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
REPEATED START BY
MASTER
ACK BY
AD5696/AD5694
ACK BY
MASTER
FRAME 3
SLAVE ADDRESS
FRAME 4
MOST SIGNIFICANT
DATA BYTE n
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB7 DB6
DB5 DB4
DB3 DB2
DB1
DB0
NACK BY STOP BY
MASTER MASTER
FRAME 5
LEAST SIGNIFICANT
DATA BYTE n
Figure 38. I2C Read Operation
Rev. B | Page 19 of 24
AD5696/AD5694
Data Sheet
POWER-DOWN OPERATION
AMPLIFIER
Command 0100 is designated for the power-down function. The
AD5696/AD5694 provide three separate power-down modes
(see Table 11). These power-down modes are software program-
mable by setting Bit DB7 to Bit DB0 in the input shift register
(see Table 12). Two bits are associated with each DAC channel.
Table 11 shows how the state of these two bits corresponds to
the mode of operation of the device.
V
X
DAC
OUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 39. Output Stage During Power-Down
Table 11. Modes of Operation
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when power-down
mode is activated. However, the contents of the DAC registers
are unaffected in power-down mode, and the DAC registers can
be updated while the device is in power-down mode. The time
required to exit power-down is typically 2.5 µs for VDD = 5 V.
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
100 kΩ to GND
Three-State
PDx1
PDx0
0
0
0
1
1
1
0
1
LOAD DAC (HARDWARE LDAC PIN)
Any or all DACs (DAC A to DAC D) can be powered down
to the selected mode by setting the corresponding bits in the
input shift register. See Table 12 for the contents of the input
shift register during the power-down/power-up operation.
The AD5696/AD5694 DACs have double buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The user can write to any combination of the input
registers (see Table 9). Updates to the DAC registers are con-
When both Bit PDx1 and Bit PDx0 (where x is the DAC selected)
in the input shift register are set to 0, the parts work normally
with their normal power consumption of 0.59 mA at 5 V. When
Bit PDx1, Bit PDx0, or both Bit PDx1 and Bit PDx0 are set to 1,
the part is in power-down mode. In power-down mode, the
supply current falls to 4 μA at 5 V.
LDAC
trolled by the
pin.
OUTPUT
AMPLIFIER
12-/16-BIT
DAC
V
V
X
REF
OUT
DAC
REGISTER
LDAC
In power-down mode, the output stage is internally switched
from the output of the amplifier to a resistor network of known
values. In this way, the output impedance of the part is known
when the part is in power-down mode.
INPUT
REGISTER
Table 11 lists the three power-down options. The output is
connected internally to GND through either a 1 kΩ or a 100 kΩ
resistor, or it is left open-circuited (three-state). The output stage
is illustrated in Figure 39.
SCL
SDA
INPUT SHIFT
REGISTER
Figure 40. Simplified Diagram of Input Loading Circuitry for a Single DAC
Table 12. 24-Bit Input Shift Register Contents for Power-Down/Power-Up Operation1
DB23
(MSB) DB22
DB15
DB0
(LSB)
DB21
DB20
DB19 to DB16 to DB8 DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
1
0
0
X
X
PDD1
PDD0
PDC1
PDC0
PDB1
PDB0
PDA1
PDA0
Command bits (C3 to C0)
Address bits
(don’t care)
Don’t
care
Power-down
select, DAC D
Power-down
select, DAC C
Power-down
select, DAC B
Power-down
select, DAC A
1 X = don’t care.
Rev. B | Page 20 of 24
Data Sheet
AD5696/AD5694
LDAC
LDAC
Instantaneous DAC Updating (
Held Low)
Table 13.
Overwrite Definition
Load
Register
LDAC
LDAC
For instantaneous updating of the DACs,
is held low while
Bit
LDAC
data is clocked into the input register using Command 0001. Both
the addressed input register and the DAC register are updated on
the 24th clock, and the output begins to change (see Table 14).
Pin
Operation
LDAC
LDAC
1 or 0
X1
(DB3 to DB0)
0
1
Determined by the LDAC pin.
DAC channels are updated. (DAC
channels see LDAC pin as 1.)
LDAC
Deferred DAC Updating (
For deferred updating of the DACs,
is clocked into the input register using Command 0001. All DAC
Pulsed Low)
LDAC
is held high while data
1 X = don’t care.
HARDWARE RESET PIN (RESET)
LDAC
outputs are asynchronously updated by pulling
low after the
LDAC
th
RESET
is an active low reset that allows the outputs to be cleared
24 clock. The update occurs on the falling edge of
.
to either zero scale or midscale. The clear code value is user select-
able via the reset select pin (RSTSEL). It is necessary to
LDAC MASK REGISTER
LDAC
Command 0101 is reserved for the software
When this command is executed, the address bits are ignored.
LDAC
function.
RESET
keep
low for a minimum of 30 ns to complete the
operation.
When writing to the DAC using Command 0101, the 4-bit
LDAC
RESET
When the
signal is returned high, the output remains at
mask register (DB3 to DB0) is loaded. Bit DB3 of the
mask
the cleared value until a new value is programmed. The outputs
RESET
register corresponds to DAC D; Bit DB2 corresponds to DAC C;
Bit DB1 corresponds to DAC B; and Bit DB0 corresponds to
DAC A.
cannot be updated with a new value while the
pin is low.
There is also a software executable reset function that resets the
DAC to the power-on reset code. Command 0110 is designated
for this software reset function (see Table 8). Any events
LDAC
The default value of these bits is 0; that is, the
normally. Setting any of these bits to 1 forces the selected DAC
LDAC
pin works
LDAC
RESET
on
during a power-on reset are ignored. If the
pin
channel to ignore transitions on the
pin, regardless of the
pin. This flexibility is useful in appli-
cations where the user wishes to select which channels respond
LDAC
is pulled low at power-up, the device does not initialize correctly
until the pin is released.
LDAC
state of the hardware
RESET SELECT PIN (RSTSEL)
to the
pin.
The AD5696/AD5694 contain a power-on reset circuit that
controls the output voltage during power-up. When the RSTSEL
pin is tied to GND, the outputs power up to zero scale (note
that this is outside the linear region of the DAC). When the
RSTSEL pin is tied to VDD, the outputs power up to midscale.
The outputs remain powered up at the level set by the RSTSEL
pin until a valid write sequence is made to the DAC.
LDAC
control over the hardware
The
mask register allows the user extra flexibility and
LDAC
pin (see Table 13). Setting
LDAC
the
bit (DB3 to DB0) to 0 for a DAC channel allows the
LDAC
hard-ware
pin to control the updating of that channel.
1
LDAC
Table 14. Write Commands and
Pin Truth Table
Hardware
Pin State
LDAC
Input Register
Contents
Command
Description
DAC Register Contents
No change (no update)
Data update
0001
Write to Input Register n (dependent on LDAC)
VLOGIC
GND2
Data update
Data update
No change
0010
Update DAC Register n with contents of Input
Register n
VLOGIC
Updated with input register
contents
GND
No change
Updated with input register
contents
0011
Write to and update DAC Channel n
VLOGIC
GND
Data update
Data update
Data update
Data update
1 A high to low transition on the hardware
pin always updates the contents of the DAC register with the contents of the input register on channels that are not
LDAC
masked (blocked) by the
mask register.
LDAC
pin is permanently tied low, the
2 When the
mask bits are ignored.
LDAC
LDAC
Rev. B | Page 21 of 24
AD5696/AD5694
Data Sheet
APPLICATIONS INFORMATION
For enhanced thermal, electrical, and board level performance,
solder the exposed pad on the bottom of the LFCSP package to
the corresponding thermal land paddle on the PCB. Design
thermal vias into the PCB land paddle area to further improve
heat dissipation.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5696/AD5694 is via a
serial bus that uses a standard protocol that is compatible with
DSP processors and microcontrollers. The communications
channel requires a 2-wire interface consisting of a clock signal
and a data signal.
The GND plane on the device can be increased (as shown in
Figure 42) to provide a natural heat sinking effect.
AD5696/AD5694 TO ADSP-BF531 INTERFACE
AD5696/
AD5694
The I2C interface of the AD5696/AD5694 is designed for easy
connection to industry-standard DSPs and microcontrollers.
Figure 41 shows the AD5696/AD5694 connected to the Analog
Devices, Inc., Blackfin® processor. The Blackfin processor has
an integrated I2C port that can be connected directly to the I2C
pins of the AD5696/AD5694.
GND
PLANE
AD5696/
AD5694
BOARD
ADSP-BF531
Figure 42. Paddle Connection to Board
GPIO1
GPIO2
SCL
SDA
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur.
PF9
PF8
LDAC
RESET
Figure 41. AD5696/AD5694 to ADSP-BF531 Interface
LAYOUT GUIDELINES
The Analog Devices iCoupler® products provide voltage iso-
lation in excess of 2.5 kV. The serial loading structure of the
AD5696/AD5694 makes the part ideal for isolated interfaces
because the number of interface lines is kept to a minimum.
Figure 43 shows a 4-channel isolated interface to the AD5696/
AD5694 using the ADuM1400. For more information, visit
www.analog.com/icouplers.
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure the
rated performance. The PCB on which the AD5696/AD5694
are mounted should be designed so that the AD5696/AD5694
lie on the analog plane.
The AD5696/AD5694 should have ample supply bypassing of
10 µF in parallel with 0.1 µF on each supply, located as close to
the package as possible, ideally right up against the device. The
10 µF capacitor is the tantalum bead type. The 0.1 µF capacitor
should have low effective series resistance (ESR) and low effective
series inductance (ESI), such as the common ceramic types; these
capacitors provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
CONTROLLER
ADuM1400
V
V
V
V
V
V
V
V
IA
IB
IC
ID
OA
OB
OC
OD
TO
SERIAL
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
SCL
CLOCK IN
TO
SDA
SERIAL
DATA OUT
TO
RESET
RESET OUT
In systems where many devices are on one board, it is often
useful to provide some heat sinking capability to allow the
power to dissipate easily.
LOAD DAC
OUT
TO
LDAC
Figure 43. Isolated Interface
The AD5696/AD5694 LFCSP models have an exposed pad
beneath the device. Connect this pad to the GND supply for
the part. For optimum performance, use special considerations
to design the motherboard and to mount the package.
Rev. B | Page 22 of 24
Data Sheet
AD5696/AD5694
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
1
4
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
8
5
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 44. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 45. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. B | Page 23 of 24
AD5696/AD5694
Data Sheet
ORDERING GUIDE
Accuracy
(INL)
Package
Model1
Resolution Temperature Range
Package Description
16-Lead LFCꢀP_WQ
16-Lead LFCꢀP_WQ
16-Lead TꢀꢀOP
16-Lead TꢀꢀOP
16-Lead TꢀꢀOP
Option
CP-16-22
CP-16-22
RU-16
RU-16
RU-16
Branding
DJ±
DJ9
AD5696ACPZ-RL7
AD5696BCPZ-RL7
AD5696ARUZ
AD5696ARUZ-RL7
AD5696BRUZ
AD5696BRUZ-RL7
AD5694BCPZ-RL7
AD5694ARUZ
AD5694ARUZ-RL7
AD5694BRUZ
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
±± LꢀB
±2 LꢀB
±± LꢀB
±± LꢀB
±2 LꢀB
±2 LꢀB
±1 LꢀB
±2 LꢀB
±2 LꢀB
±1 LꢀB
±1 LꢀB
16-Lead TꢀꢀOP
RU-16
16-Lead LFCꢀP_WQ
16-Lead TꢀꢀOP
16-Lead TꢀꢀOP
16-Lead TꢀꢀOP
16-Lead TꢀꢀOP
CP-16-22
RU-16
RU-16
RU-16
RU-16
DJQ
AD5694BRUZ-RL7
EVAL-AD5696RꢀDZ
EVAL-AD5694RꢀDZ
AD5696 TꢀꢀOP Evaluation Board
AD5694 TꢀꢀOP Evaluation Board
1 Z = RoHꢀ Compliant Part.
I2C refers to a communications protocol originally developed by Philips ꢀemiconductors (now NXP ꢀemiconductors).
©2012–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10799-0-11/16(B)
Rev. B | Page 24 of 24
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