AD5583_15 [ADI]
Quad, Parallel Input, Voltage Output, 12-/10-Bit Digital-to-Analog Converters;
| 型号： | AD5583_15 |
| 厂家： | 
ADI |
| 描述： | Quad, Parallel Input, Voltage Output, 12-/10-Bit Digital-to-Analog Converters |
| 文件： | 总20页 (文件大小：449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad, Parallel Input, Voltage Output,
12-/10-Bit Digital-to-Analog Converters
a
AD5582/AD5583
FEATURES
AD5582 FUNCTIONAL BLOCK DIAGRAM
12-Bit Linearity and Monotonic AD5582
10-Bit Linearity and Monotonic AD5583
Wide Operating Range: Single 5 V to 15 V or
Dual ꢀ5 V Supply
V
V
V
V
V
V
REFHB
DD3
38
REFLA
10
SS3
37
REFHA
REFLB
9
7
8
3
4
5
V
DD1
33
32
AD5582
A1
A0
ADDR
V
DECODE
SS1
Unipolar or Bipolar Operation
+
VOA
VOB
Double Buffered Registers Enable Independent or
Simultaneous Multichannel Update
4 Independent Rail-to-Rail Reference Inputs
20 mA High Current Output Drive
Parallel Interface
–
31
30
29
28
26
25
24
23
21
20
19
18
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
2
I
N
T
E
R
F
A
C
E
D
11 R1
O
DAC
REG
Data Readback Capability
5 ꢁs Settling Time
IN
REG
20kꢅ
20kꢅ
D
12
RCT
I
Built-In Matching Resistor Simplifies
Negative Reference
Unconditionally Stable Under Any Capacitive Loading
Compact Footprint: TSSOP-48
Extended Temperature Range: ꢂ40ꢃC to ꢄ125ꢃC
13
1
R2
AGND1
AGND2
4
4
48
47
OE
VOC
APPLICATIONS
34
35
14
17
CS
Process Control Equipment
Closed-Loop Servo Control
Data Acquisition Systems
Digitally Controlled Calibration
Optical Network Control Loops
4 m to 20 mA Current Transmitter
R/W
CONTROL
LOGIC
DV
DD
–
+
44
VOD
MSB
46
45
V
DD2
16
15
RS
V
SS2
LDAC
22
27
36
40
39
41
42
GENERAL DESCRIPTION
DGND1 DGND2 DGND3
V
V
V
V
REFLC
REFHD
REFLD
REFHC
The AD5582/AD5583 family of quad, 12-/10-bit, voltage output
digital-to-analog converters is designed to operate from a single
5 V to 15 V or dual ±5 V supply. It offers the user ease of use in
single- or dual-supply systems. Built using an advance BiCMOS
process, this high performance DAC is dynamically stable, capable
of high current drive, and in small form factor.
AD5582/AD5583
ꢄ2.5V
ADR421
REF
V
REFHA
ꢀ2.5V
DAC A
V
REFHB
V
REFHC
V
ꢀ2.5V
DAC B
REFHD
The applied external reference VREF determines the full-scale out-
put voltage ranges from VSS to VDD, resulting in a wide selection
of full-scale outputs. For multiplying and wide dynamic appli-
cations, ac reference inputs can be as high as |VDD – VSS|. Two
built-in precision trimmed resistors are available and can be
configured easily to provide four-quadrant multiplications.
R1
R2
RCT
ꢀ2.5V
ꢀ2.5V
DAC C
DAC D
V
REFLA
–
V
REFLB
V
+
REFLC
ꢂ2.5V
V
REFLD
A doubled-buffered parallel interface offers a fast settling time.
A common level sensitive load DAC strobe (LDAC) input allows
additional simultaneous update of all DAC outputs. An external
asynchronous reset (RS) forces all registers to the zero code state
when the MSB = 0 or to midscale when the MSB = 1.
DIGITAL CIRCUITRY OMITTED FOR CLARITY
Figure 1. Using Built-In Matching Resistors
to Generate a Negative Voltage Reference
Both parts are offered in the same pinout and package to allow
users to select the appropriate resolution for a given application
without PCB layout changes.
The AD5582 is well suited for DAC8412 replacement in medium
voltage applications in new designs, as well as any other general
purpose multichannel 10- to 12-bit applications.
The AD5582/AD5583 are specified over the extended industrial
(–40∞C to +125∞C) temperature range and offered in a thin and
compact 1.1 mm TSSOP-48 package.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD5582/AD5583–SPECIFICATIONS
(VDD = +5 V, VSS = –5 V, DVDD = +5 V ꢀ 10%, VREFH = +2.5 V, VREFL = –2.5 V,
ELECTRICAL CHARACTERISTICS –40ꢃC < TA < +125ꢃC, unless otherwise noted.)
Parameter
Symbol
Condition
Min
Typ1 Max
Unit
STATIC PERFORMANCE
Resolution2
N
AD5582
AD5583
12
10
+1
Bits
Bits
LSB
LSB
LSB
Relative Accuracy3
Differential Nonlinearity3
Zero-Scale Error
INL
DNL
VZSE
–1
–1
–2
Monotonic
Data = 000H for AD5582
and AD5583
+2
Gain Error
VGE
VGE
VGE
TCVFS
Data = 0xFFFH for AD5582
Data = 0x3FFH for AD5583
VDD = 2.7 V to 4.5 V
–2
–4
–4
+2
+4
+4
LSB
LSB
LSB
ppm/∞C
Gain Error
Full-Scale Tempco4
1.5
REFERENCE INPUT
VREFH Input Range
VREFL Input Range5
Input Resistance
VREFH
VREFL
RREF
VREFL + 0.5
VSS
12
VDD
VREFH – 0.5
V
V
Data = 555H (Minimum RREF
for AD5582 and 155H for AD5583
)
20
80
kW1
Input Capacitance4
REF Input Current
REF Multiplying Bandwidth BWREF
CREF
IREF
pF
mA
MHz
%
Data = 555H for AD5582
Code = Full Scale
AD5582
500
1.3
±0.025
±0.100
R1–R2 Matching
R1/R2
AD5583
%
ANALOG OUTPUT
Output Current6
IOUT
IOUT
Data = 800H for AD5582 and
200H for AD5583, ꢀVOUT £ 2 mV
Data = 800H for AD5582 and
200H for AD5583, ꢀVOUT £ |–8 mV|
ꢀVOUT £ ±15 mV
±2
mA
Output Current6
+20
–20
mA
mA
pF
Capacitive Load4, 7
CL
No Oscillation
Note 7
LOGIC INPUTS
Logic Input Low Voltage
VIL
VIH
DVDD = 5 V ± 10%
DVDD = 3 V ± 10%
DVDD = 5 V ± 10%
DVDD = 3 V ± 10%
0.8
0.4
V
V
V
V
mA
pF
V
Logic Input High Voltage
2.4
2.1
Input Leakage Current
Input Capacitance4
Output Voltage High
Output Voltage Low
IIL
0.01
5
1
CIL
VOH
VOL
IOH = –0.8 mA
IOL = 1.2 mA, TA = 85∞C,
IOL = 0.6 mA, DVDD = 3 V
2.4
0.4
0.4
V
I
OL = 1.0 mA, TA = 125∞C,
V
IOL = 0.5 mA, DVDD = 3 V
AC CHARACTERISTICS
Output Slew Rate
SR
Data = Zero Scale to Full Scale
to Zero Scale
To ±0.1% of Full Scale
Code 7FFH to 800H to 7FFH
for AD5582 and 1FFH to 200H
to 1FFH for AD5583
2
V/ms
Settling Time8
DAC Glitch
tS
Q
5
100
ms
nV-s
Digital Feedthrough
Analog Crosstalk
Output Noise
V
OUT/tCS
Data = Midscale, CS Toggles at
f = 16 MHz
5
nV-s
dB
VOUT/VREF VREF = 1.5 V dc + 1 V p-p,
Data = 000H, f = 100 kHz
eN
–80
33
f = 1 kHz
nV/÷Hz
–2–
REV. A
AD5582/AD5583
Parameter
Symbol
Condition
Min
Typ1
Max
Unit
SUPPLY CHARACTERISTICS
Single-Supply Voltage Range VDD
Dual-Supply Voltage Range
VSS = 0 V
VDD = +2.7 V to +6.5 V,
VSS = –6.5 V to –2.7 V
3
–9
18
+9
V
V
VDD/VSS
Digital Logic Supply
Positive Supply Current6
Negative Supply Current
Power Dissipation
DVDD
IDD
ISS
PDISS
PSS
2.7
8
3
3
30
V
mA
mA
mW
ppm/V
VIL = 0 V, No Load
VIL = 0 V, No Load
VIL = 0 V, No Load
ꢀVDD = ±5%
1.7
1.5
16
Power Supply Sensitivity
30
NOTES
1Typical specifications represent average readings measured at 25∞C.
2DAC Output Equation: VOUT = VREFL + [(VREFH – VREFL) ꢁ D/2N], where D = data loaded in corresponding DAC Register A, B, C, D, and N equals the number of bits;
AD5582 = 12 bits, AD5583 = 10 bits. One LSB step voltage = (VREFH – VREFL)/4096 V and (VREFH – VREFL)/1024 V for AD5582 and AD5583, respectively.
3The first two codes (000H, 001H) of the AD5583 and the first four codes (000H, 001H, 002H, 003H) of the AD5582 are excluded from the linearity error measurement
in single-supply operation.
4These parameters are guaranteed by design and not subject to production testing.
5Dual-supply operation, VREFL = VSS, exclude the lowest eight codes for the AD5582 and two codes for the AD5583 for INL and DNL errors.
6Short circuit output and supply currents are 24 mA and 25 mA, respectively.
7Part is stable under any capacitive loading conditions.
8The settling time specification does not apply for negative-going transitions within the last 3 LSBs of ground in single-supply operation.
Specifications subject to change without notice.
(VDD = 15 V, VSS = 0 V, DVDD = 5 V ꢀ 10%, VREFH = 10 V, VREFL = 0 V,
ELECTRICAL CHARACTERISTICS
–40ꢃC < TA < +125ꢃC, unless otherwise noted.)
Parameter
Symbol
Condition
Min
Typ1 Max
Unit
STATIC PERFORMANCE
Resolution2
N
AD5582
AD5583
12
10
+1
Bits
Bits
LSB
LSB
LSB
Relative Accuracy3
Differential Nonlinearity3
Zero-Scale Error
INL
DNL
VZSE
–1
–1
–2
Monotonic
Data = 000H for AD5582
and AD5583
+2
Gain Error
VGE
VGE
TCVFS
Data = 0xFFFH for AD5582
Data = 0x3FFH for AD5583
–2
–4
+2
+4
LSB
LSB
ppm/∞C
Full-Scale Tempco4
1.5
REFERENCE INPUT
VREFH Input Range
VREFL Input Range5
Input Resistance
VREFH
VREFL
RREF
VREFL + 0.5
VSS
12
VDD
VREFH – 0.5
V
V
Data = 555H (Minimum RREF
for AD5582 and 155H for AD5583
)
20
80
kW1
Input Capacitance4
REF Input Current
REF Multiplying Bandwidth BWREF
CREF
IREF
pF
mA
MHz
%
Data = 555H for AD5582
Code = Full Scale
AD5582
1000
1.3
±0.025
±0.100
R1–R2 Matching
R1/R2
AD5583
%
ANALOG OUTPUT
Output Current6
IOUT
IOUT
Data = 800H for AD5582 and
200H for AD5583, ꢀVOUT £ 2 mV
Data = 800H for AD5582 and
200H for AD5583, ꢀVOUT £ |–8 mV|
ꢀVOUT £ 15 mV
2
mA
Output Current6
+20
–20
mA
mA
pF
Capacitive Load4, 7
CL
No Oscillation
Note 7
REV. A
–3–
AD5582/AD5583
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Symbol
Condition
Min
Typ1 Max
Unit
LOGIC INPUTS/OUTPUTS
Logic Input Low Voltage
VIL
VIH
0.8
0.4
V
V
V
V
mA
pF
V
DVDD = 3 V ± 10%
DVDD = 3 V ± 10%
Logic Input High Voltage
2.4
2.1
Input Leakage Current
Input Capacitance4
Output Voltage High
Output Voltage Low
IIL
CIL
VOH
VOL
IOH = –0.8 mA
2.4
IOL = 1.2 mA, TA = 85ꢂC,
IOL = 0.6 mA, DVDD = 3 V
IOL = 1.0 mA, TA = 125ꢂC,
IOL = 0.5 mA, DVDD = 3 V
0.4
0.4
V
VOL
V
AC CHARACTERISTICS
Output Slew Rate
SR
Data = Zero Scale to Full Scale
to Zero Scale
To ±0.1% of Full Scale
Code 7FFH to 800H to 7FFH for
AD5582 and 1FFH to 200H to
1FFH for AD5583
2
V/ms
Settling Time8
DAC Glitch
tS
Q
14
100
ms
nV-s
Digital Feedthrough
Analog Crosstalk
Output Noise
V
OUT/tCS
VOUT/VREF
eN
Data = Midscale, CS Toggles at
f = 16 MHz
VREF = 1.5 V dc + 1 V p-p,
Data = 000H, f = 100 kHz
f = 1 kHz
5
nV-s
dB
–80
33
nV/÷Hz
SUPPLY CHARACTERISTICS
Single-Supply Voltage Range
Dual-Supply Voltage Range
VDD
VDD/VSS
VSS = 0 V
VDD = +2.7 V to +6.5 V,
VSS = –6.5 V to –2.7 V
3
–6.5
16.5
+6.5
V
V
Digital Logic Supply
Positive Supply Current6
Power Dissipation
DVDD
IDD
PDISS
PSS
2.7
6.5
3.5
52.5
V
mA
mW
ppm/V
VIL = 0 V, No Load
VIL = 0 V, No Load
ꢀVDD = ±5%
2.3
34.5
30
Power Supply Sensitivity
NOTES
1Typical specifications represent average readings measured at 25∞C.
2DAC Output Equation: VOUT = VREFL + [(VREFH – VREFL) ꢁ D/2N], where D = data in decimal loaded in corresponding DAC Register A, B, C, D, and N equals the number of
bits; AD5582 = 12 bits, AD5583 = 10 bits. One LSB step voltage = (VREFH – VREFL)/4096 V and = (VREFH – VREFL)/1024 V for AD5582 and AD5583, respectively.
3The first two codes (000H, 001H) of the AD5583 and the first four codes (000H, 001H, 002H, 003H) of the AD5582 are excluded from the linearity error measurement
in single-supply operation.
4These parameters are guaranteed by design and not subject to production testing.
5Dual-supply operation, VREFL = VSS, exclude the lowest eight codes for the AD5582 and two codes for the AD5583 for INL and DNL errors.
6Short circuit output and supply currents are 24 mA and 25 mA, respectively.
7Part is stable under any capacitive loading conditions.
8The settling time specification does not apply for negative-going transitions within the last 3 LSBs of ground in single-supply operation.
Specifications subject to change without notice.
–4–
REV. A
AD5582/AD5583
(VDD = 15 V or 5 V, VSS = 0 V, DVDD = 5 V ꢀ 10%, VREFH = 10 V, VREFL = 0 V, –40ꢃC < TA < +125ꢃC,
TIMING CHARACTERISTICS unless otherwise noted.)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
INTERFACE TIMING*
Chip Select Write Pulse Width
Chip Select Read Pulse Width
Write Setup
Write Hold
Address Setup
Address Hold
Load Setup
Load Hold
Write Data Setup
tWCS
tRCS
tWS
tWH
tAS
tAH
tLS
tLH
tWDS
tWDH
tLDW
tRESET
tRDH
tRDS
tDZ
tCSD
tCSP
tLDS
tLDH
20
130
35
0
35
0
0
0
35
0
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Data Hold
Load Data Pulse Width
Reset Pulse Width
Read Data Hold
Read Data Setup
Data to Hi-Z
Chip Select to Data
Chip Select Repetitive Pulse Width
Load Setup in Double Buffer Mode
Load Data Hold
0
CL = 10 pF
CL = 10 pF
100
100
10
20
0
*All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Specifications subject to change without notice.
(VDD = 15 V or 5 V, VSS = 0 V, DVDD = 3 V ꢀ 10%, VREFH = 10 V, VREFL = 0 V, –40ꢃC < TA < +125ꢃC,
TIMING CHARACTERISTICS
unless otherwise noted.)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
INTERFACE TIMING*
Chip Select Write Pulse Width
Chip Select Read Pulse Width
Write Setup
Write Hold
Address Setup
Address Hold
Load Setup
Load Hold
Write Data Setup
tWCS
tRCS
tWS
tWH
tAS
tAH
tLS
tLH
tWDS
tWDH
tLDW
tRESET
tRDH
tRDS
tDZ
tCSD
tCSP
tLDS
tLDH
35
130
50
0
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
50
0
35
35
0
Write Data Hold
Load Data Pulse Width
Reset Pulse Width
Read Data Hold
Read Data Setup
Data to Hi-Z
Chip Select to Data
Chip Select Repetitive Pulse Width
Load Setup in Double Buffer Mode
Load Data Hold
0
CL = 10 pF
CL = 10 pF
80
80
20
35
0
100
100
*All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Specifications subject to change without notice.
REV. A
–5–
AD5582/AD5583
ABSOLUTE MAXIMUM RATINGS*
Thermal Resistance Junction to Case, ꢃJC . . . . . . . . . . 42∞C/W
Maximum Junction Temperature (TJ Max) . . . . . . . . . . 150∞C
Package Power Dissipation = (TJ Max – TA)/ꢃJA
Operating Temperature Range . . . . . . . . . . –40∞C to +125∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –9 V
VDD to VREF+ . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
VREF– to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
VREFH to VREFL . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
DVDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Logic Inputs to GND . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
VOUT to GND . . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 24 mA
Thermal Resistance Junction to Ambient, ꢃJA . . . . . . 115∞C/W
RV-48 (Soldering, 60 secs) . . . . . . . . . . . . . . . . . . . . 300∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE1
Resolution
(Bits)
Temperature
Range
Package
Description
Package
Option
Container
Quantity
Top
Model
Marking2
AD5582YRV-REEL1 12
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
TSSOP-48
TSSOP-48
TSSOP-48
TSSOP-48
RV-48
RV-48
RV-48
RV-48
2500
2500
39
AD5582Y
AD5583Y
AD5582Y
AD5583Y
AD5583YRV-REEL
10
12
10
AD5582YRV1
AD5583YRV
39
NOTES
1The AD5582 contains 4116 transistors. The die size measures 108 mil ꢁ 144 mil.
2First row marking is shown in the table above. Second row marking contains date code in YYWW format. Third row marking contains the lot number.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5582/AD5583 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6–
REV. A
AD5582/AD5583
AD5582 PIN CONFIGURATION
AGND1
VOB
1
2
48 AGND2
47 VOC
V
3
46
45
V
DD2
DD1
V
4
V
SS2
SS1
VOA
NC
5
44 VOD
43 NC
6
V
7
42
41
40
39
38
37
V
REFLC
REFLB
V
8
V
REFHC
REFHB
V
9
V
REFHD
REFHA
V
10
V
REFLD
REFLA
AD5582
TOP VIEW
(Not to Scale)
R1 11
RCT 12
R2 13
V
DD3
V
SS3
36 DGND3
DV
14
15
16
35
34
R/W
DD
LDAC
CS
33 A1
RS
MSB 17
DB0 18
32 A0
31 DB11
30 DB10
29 DB9
28 DB8
27 DGND2
26 DB7
25 DB6
DB1 19
DB2 20
DB3 21
DGND1 22
DB4 23
DB5 24
NC = NO CONNECT
AD5582 PIN FUNCTION DESCRIPTIONS*
Pin
Pin
No. Mnemonic Description
No. Mnemonic Description
1
2
3
4
5
6
7
8
9
AGND1
VOB
VDD1
VSS1
VOA
Analog Ground for DAC A and B
DAC B Output
Positive Power Supply for DAC A and B
Negative Power Supply for DAC A and B
DAC A Output
25 DB6
26 DB7
27 DGND2
28 DB8
29 DB9
30 DB10
31 DB11
32 A0
Data Bit 6
Data Bit 7
Digital Ground 2
Data Bit 8
Data Bit 9
Data Bit 10
Data Bit 11
Address Input 0
Address Input 1
Chip Select, Active Low
Read/Write Mode Select
Digital Ground 3
Negative Power Supply for Analog Switches
Positive Power Supply for Analog Switches
DAC D Voltage Reference Low Terminal
DAC D Voltage Reference High Terminal
DAC C Voltage Reference High Terminal
DAC C Voltage Reference Low Terminal
No Connect
NC
No Connect
VREFLB
VREFHB
VREFHA
DAC B Voltage Reference Low Terminal
DAC B Voltage Reference High Terminal
DAC A Voltage Reference High Terminal
DAC A Voltage Reference Low Terminal
R1 Terminal (for Negative Reference)
Center Tap Terminal (for Negative Reference)
R2 Terminal (for Negative Reference)
Power Supply for Digital Circuits
DAC Register Load, Active Low Level Sensitive
Reset Strobe
33 A1
34 CS
10 VREFLA
11 R1
12 RCT
13 R2
14 DVDD
15 LDAC
16 RS
35 R/W
36 DGND3
37 VSS3
38 VDD3
39 VREFLD
40 VREFHD
41 VREFHC
42 VREFLC
43 NC
44 VOD
45 VSS2
46 VDD2
47 VOC
48 AGND2
17 MSB
MSB = 0, Reset to 000H.
MSB = 1, Reset to 800H.
18 DB0
19 DB1
20 DB2
21 DB3
22 DGND1
23 DB4
24 DB5
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Digital Ground 1
Data Bit 4
Data Bit 5
DAC D Output
Negative Power Supply for DAC C and D
Positive Power Supply for DAC C and D
DAC C Output
Analog Ground for DAC C and D
*AD5582 optimizes internal layout design to reduce die area so that all supply voltage pins are required to be connected externally. See Figure 5.
REV. A
–7–
AD5582/AD5583
AD5583 PIN CONFIGURATION
AGND1
VOB
1
2
48 AGND2
47 VOC
V
3
46
45
V
DD2
DD1
V
4
V
SS2
SS1
VOA
NC
5
44 VOD
43 NC
6
V
7
42
41
40
39
38
37
V
REFLC
REFLB
V
8
V
REFHB
REFHC
VREFHD
V
9
REFHA
V
10
V
REFLD
REFLA
AD5583
TOP VIEW
(Not to Scale)
R1 11
RCT 12
R2 13
V
DD3
V
SS3
36 DGND3
DV
14
15
16
35
34
R/W
DD
LDAC
RS
CS
33 A1
MSB 17
NC 18
32 A0
31 DB9
30 DB8
29 DB7
28 DB6
27 DGND2
26 DB5
25 DB4
NC 19
DB0 20
DB1 21
DGND1 22
DB2 23
DB3 24
NC = NO CONNECT
AD5583 PIN FUNCTION DESCRIPTIONS*
Pin
Pin
No. Mnemonic Description
No. Mnemonic Description
1
2
3
4
5
6
AGND1
VOB
VDD1
VSS1
VOA
NC
Analog Ground for DAC A and B
DAC B Output
Positive Power Supply for DAC A and B
Negative Power Supply for DAC A and B
DAC A Output
25 DB4
26 DB5
27 DGND2
28 DB6
29 DB7
30 DB8
31 DB9
32 A0
Data Bit 4
Data Bit 5
Digital Ground 2
Data Bit 6
Data Bit 7
Data Bit 8
Data Bit 9
Address Input 0
No Connect (Do Not Connect Anything
other than Dummy Pad)
7
8
9
VREFLB
VREFHB
VREFHA
DAC B Voltage Reference Low Terminal
DAC B Voltage Reference High Terminal
DAC A Voltage Reference High Terminal
DAC A Voltage Reference Low Terminal
R1 Terminal (for Negative Reference)
Center Tap Terminal (for Negative Reference)
R2 Terminal (for Negative Reference)
Power Supply for Digital Circuits
DAC Register Load, Active Low Level Sensitive
Reset Strobe
MSB = 0, Reset to 000H.
MSB = 1, Reset to 200H.
No Connect (Do Not Connect Anything
other than Dummy Pad)
No Connect (Do Not Connect Anything
other than Dummy Pad)
33 A1
34 CS
Address Input 1
Chip Select, Active Low
Read/Write Mode Select
Digital Ground 3
10 VREFLA
11 R1
12 RCT
13 R2
14 DVDD
15 LDAC
16 RS
35 R/W
36 DGND3
37 VSS3
38 VDD3
39 VREFLD
40 VREFHD
41 VREFHC
42 VREFLC
43 NC
Negative Power Supply for Analog Switches
Positive Power Supply for Analog Switches
DAC D Voltage Reference Low Terminal
DAC D Voltage Reference High Terminal
DAC C Voltage Reference High Terminal
DAC C Voltage Reference Low Terminal
No Connect (Do Not Connect Anything
other than Dummy Pad)
DAC D Output
17 MSB
18 NC
19 NC
44 VOD
45 VSS2
46 VDD2
47 VOC
48 AGND2
Negative Power Supply for DAC C and D
Positive Power Supply for DAC C and D
DAC C Output
20 DB0
21 DB1
22 DGND1
23 DB2
24 DB3
Data Bit 0
Data Bit 1
Digital Ground 1
Data Bit 2
Analog Ground for DAC C and D
Data Bit 3
*AD5583 optimizes internal layout design to reduce die area so that all supply voltage pins are required to be connected externally. See Figure 5.
–8–
REV. A
AD5582/AD5583
TIMING DIAGRAMS
tCSP = 10ns
tWCS = 20ns
CS
tWS = 35ns
tWH = 0ns
R/W
tAS = 35ns
ADDRESS
ONE
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
ADDRESS
tLS = 0ns
tLH = 0ns
LDAC
tWDH = 0ns
tWDS = 35ns
DATA1
VALID
DATA2
VALID
DATA3
VALID
DATA4
VALID
DATA IN
Figure 2a. Single Buffer Mode, Output Updated Individually, DVDD = 5 V
tCSP = 10ns
tWCS = 20ns
CS
tWH = 0ns
tWS = 35ns
R/W
tAS = 35ns
ADDRESS
ONE
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
ADDRESS
tLDH = 0ns
tLDS = 0ns
LDAC
tLDW = 20ns
tWDS = 35ns
tWDH = 0ns
DATA1
VALID
DATA2
VALID
DATA3
VALID
DATA4
VALID
DATA IN
Figure 2b. Double Buffer Mode, Output Updated Simultaneously, DVDD = 5 V
REV. A
–9–
AD5582/AD5583
tWCS = 20ns
CS
tWS = 35ns
tWH = 0ns
R/W
tAH = 0ns
tAS = 35ns
A0/A1
tLDW = 20ns
tLH = 0ns
tLS = 0ns
LDAC
tWDH = 0ns
tWDS = 35ns
DATA IN
tRESET= 20ns
RS
Figure 2c. Data Write (Input and Output Registers) Timing
tRCS = 130ns
CS
tRDS = 35ns
tRDH = 0ns
R/W
tAS = 35ns
tAH = 0ns
A0/A1
tCSD = 100ns MAX
HI-Z
tDZ = 100ns MAX
HI-Z
DATA OUT
DATAVALID
Figure 2d. Data Output (Read Timing)
–10–
REV. A
Typical Performance Characteristics–AD5582/AD5583
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
512
1024
1536
2048
2560
3072
3584
4096
0
128
256
384
512
640
768
896
1024
CODE (Decimal)
CODE (Decimal)
TPC 1. AD5582 Integral Nonlinearity Error
TPC 4. AD5583 Differential Nonlinearity Error
1.0
0.8
0.6
0.4
0.2
0
6
V
SS
= 5V
= 0V
DD
V
V
= 0V
REFL
4
2
NO LOAD
INL
GE
ZSE
DNL
0
–0.2
–2
–4
–6
–0.4
–0.6
–0.8
–1.0
0
512
1024
1536
2048
2560
3072
3584
4096
0
5
10
15
20
25
30
CODE (Decimal)
V
–V
(mV)
REFH
DD
TPC 2. AD5582 Differential Nonlinearity Error
TPC 5. AD5582 INL, DNL, ZSE, and GE at Positive
Rail-to-Rail Operation
1.0
0.8
0.6
0.4
0.2
4
V
SS
= +5V
= –5V
DD
V
3
2
V
= +4V
REFH
ZSE
NO LOAD
1
DNL
DAC-A
DAC-C
DAC-B
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
–1
–2
–3
–4
INL
DAC-D
GE
0
128
256
384
512
640
768
896
1024
0
5
10
15
20
(mV)
25
30
35
CODE (Decimal)
V
–V
SS
REFL
TPC 3. AD5583 Integral Nonlinearity Error
TPC 6. AD5582 INL, DNL, GE, and ZSE at Negative
Rail-to-Rail Operation
REV. A
–11–
AD5582/AD5583
1.0
40
30
V
= ꢄ5V
= ꢂ5V
DD
ZERO
SCALE
ERROR
ZERO
SCALE
ERROR
0.8
0.6
V
SS
V
= ꢄ4V
= 0V
REFH
V
REFL
20
R
= NO LOAD
L
0.4
V
>V
SS
V
=V
SS
REFL
REFL
R
= 260ꢅ
L
10
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–10
–20
–30
–40
R
= 790ꢅ
L
R
= 390ꢅ
L
GAIN
GAIN
ERROR
ERROR
RESISTIVE LOAD R IS BETWEEN
L
PULL-UP RESISTIVE LOAD R
IS BETWEENV
L
V
AND GND
OUT
ANDV
DD
OUT
100
1k
10k
R _PU (ꢅ)
100k
1M
0
512
1024
1536
2048
2560
3072
3584
4096
L
CODE (Decimal)
TPC 7. AD5582 INL at Various Resistive Loads
TPC 10. AD5582 Gain and Zero-Scale Error vs.
Pull-Up Resistive Loads
0.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
V
= ꢄ5V
= ꢂ5V
= ꢄ4V
DD
0.4
0.3
V
SS
V
REFH
V
= 0V
REFL
0.2
R
= NO LOAD
L
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
R
= 260ꢅ
L
1.5
INL
1.0
RESISTIVE LOAD R IS BETWEEN
V
L
DNL
AND GND
0.5
OUT
0
512
1024
1536
2048
2560
3072
3584 4096
0
0
2
4
6
8
10
12
CODE (Decimal)
V
–V
(V)
REFL
REFH
TPC 8. AD5582 DNL at Various Resistive Loads
TPC 11. AD5582 Linearity Errors vs. Differential
Reference Ranges
0
2.00
1.95
1.90
–2
V
= +5V OR +15V
= –5V OR 0V
= +4V
= 0V
DD
V
SS
–4
–6
V
= 0V
SS
V
REFH
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
V
= +4V
REFH
V
REFL
V
= 0V
REFL
V
= +5V
= –5V
DD
–8
V
SS
V
= +15V
= 0V
= +10V
DD
V
= +4V
REFH
V
SS
–10
–12
–14
–16
V
REFH
V
= 0V
REFL
RESISTIVE LOAD R IS BETWEEN
L
V
AND GND
OUT
100
1k
10k
100k
0
2
4
6
8
10
12
14
16
R
(ꢅ)
L
V
(V)
DD
TPC 9. AD5582 Gain Error vs. Resistive Load
TPC 12. AD5582 Supply Current vs. Supply Voltage
–12–
REV. A
AD5582/AD5583
300
250
200
150
100
50
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 5V
= 0V
= 4V
DD
V
SS
V
REFH
V
= 0V
REFL
V
= +15V
= 0V
DD
V
= +5V
= –5V
DD
V
SS
V
SS
V
= 0V
REFL
V
= –5V
REFL
V
= +5V
= 0V
DD
V
SS
V
= 0V
REFL
0
0
512
1024
1536
2048
2560
3072
3584
4096
–10
–5
0
5
10
15
20
CODE (Decimal)
V
(V)
REFH
TPC 13. AD5582 Supply Current vs. Reference Voltage
TPC 16. AD5582 Reference Current
4.0
140
120
100
80
V
= ꢄ15V
= 0V
= ꢄ10V
= 0V
DD
V
SS
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
REFH
V
REFL
60
V
= ꢄ5V
= ꢂ5V
= ꢄ4V
DD
V
SS
40
V
REFH
V
= 0V
REFL
20
0
–60 –40 –20
0
20
40
60
80
100 120 140
0
512
1024
1536
2048
2560
3072
3584
4096
TEMPERATURE (ꢃC)
CODE (Decimal)
TPC 14. AD5582 Supply Current vs. Temperature
TPC 17. AD5582 Referenced Input Resistance
20
6
V
= 5V OR 15V
DD
= 0V
DD
V
= 5V 0.5V
= 0V
= 4V
DD
18
16
14
12
10
8
DV = 3V
V
SS
V
SS
V
5
4
3
2
1
0
REF
DATA = 800
H
V
= 5V OR 15V
DD
= 0V
DD
DV = 5V
V
SS
6
4
2
0
0
1
2
3
4
5
10k
100k
1M
10M
100M
V
(V)
CLOCK FREQUENCY (Hz)
IH
TPC 15. AD5582 Supply Current vs. Logic Input Voltage
TPC 18. AD5582 Supply Current vs. Clock Frequency
REV. A
–13–
AD5582/AD5583
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
V
= ꢄ5V ꢀ 0.5V
= 0V
= ꢄ4V
DD
DATA 5V/DIV
V
SS
V
REF
DATA = 800
100
90
H
V
= 5V
= 0V
= 2.5V
DD
V
SS
V
REFH
10
0
5ꢁs/DIV
V
0.5V/DIV
OUT
1
10
100
1k
10k
100k
1M
GRAPH <1>
: C = 0
L
GRAPH <2> w/RINGING : C = 10nF
FREQUENCY (Hz)
L
TPC 19. AD5582 PSRR vs. Frequency
TPC 22. Large Signal Settling When Loaded
(See Test Circuit 1)
V
200mV/DIV
OUT
V
200mV/DIV
2ꢁs/DIV
V
0.1V/DIV
5ꢁs/DIV
REF
OUT
TPC 20. Small Signal Response Operating
at Near Rail, CL = 2 nF (See Test Circuit 1)
TPC 23. Midscale Transition Glitch
–
3980
1260
398
V
V
= 15V
= 0V
R
= 30Hz
DD
BW
33nV/ Hz @ 1kHz
–
SS
100
90
V
= 10V
–
REFH
23004
7285
2300
730
230
73
126
V
2V/DIV
OUT
39.90
12.60
4.00
1.26
0.40
0.13
10
0
23
5ꢁs/DIV
DATA 5V/DIV
0.04
7.3
2kHz
1Hz
TPC 21. Large Signal Settling
TPC 24. AD5582 Output Noise Density
–14–
REV. A
AD5582/AD5583
FFF
0
0.8
0.6
H
800
V
= +5V
= –5V
H
DD
400
H
V
SS
200
H
V
= +4V
= –4V
REFH
100
–24
–48
–72
–96
H
V
REFL
080
0.4
H
040
H
ZSE DRIFT
020
H
0.2
010
+3ꢆ
H
008
H
004
0
H
–3ꢆ
002
H
001
H
–0.2
–0.4
–0.6
–0.8
+3ꢆ
–3ꢆ
000
H
GE DRIFT
100
1k
10k
100k
1M
10M
0
100
200
300
400
500
600
FREQUENCY (Hz)
HOURS OF OPERATION AT 150ꢃC
TPC 25. AD5582 Multiplying Bandwidth
TPC 26. AD5582 Long-Term Drift
Test Circuit
V
DD
1kꢅ
V
OUT
DAC
C
1kꢅ
L
Test Circuit 1
THEORY OF OPERATION
The AD5582/AD5583 are quad, voltage output, 12-/10-bit parallel
input DACs in compact TSSOP-48 packages.
These DACs feature double buffers, which allow both synchro-
nous and asynchronous channels update with additional data
readback capability. These parts can be reset to zero scale or mid-
scale controlled by the RS and MSB pins. When RS is activated,
the MSB of 0 resets the DACs to zero scale and the MSB of 1
resets the DACs to midscale. The ability to operate from wide
supply voltages, +5 V to +15 V or ±5 V, with multiplying bipolar
references is another key feature of these DACs.
Each DAC is a voltage switching, high impedance (R = 20 kW),
R-2R ladder configuration with segmentation to optimize die
area and precision. Figure 3 shows a simplified R-2R structure
without the segmentation. The 2R resistances are switched
between VREFH and VREFL, and the output is obtained from
the rightmost ladder node. As the code is sequenced through
all possible states, the voltage of this node changes in steps of
(2/3 VREFH – VREFL)/(2N – 1) starting from the lowest VREFL and
going to the highest VREFH – DUTLSB. Buffering it with an
amplifier with a gain of 1.5 brings the output to:
R
R
R
+
–
V
O
2R
2R
2R
2R
2R
2R
R
2R
SW0
SW1
SW2
SWn–3
SWn–1
D
2N – 1
VOUT
=
V
–VREFL + V
(1)
(
)
(
)
REFH
REFL
V
V
+
REFL
+
–
REFH
where D is the decimal equivalent of the data bits and N is the
numbers of bits.
b0
b1
b2
bn–2
bn–1
–
If –VREFL is equal to VREFH as VREF, VOUT is simplified to:
Figure 3. Simplified R-2R Architecture
(Segmentation Not Shown)
Ê 2D
ˆ
Power Supplies
There are three separate power supplies needed for the opera-
VOUT
=
– 1 V
Á
˜
(For AD5582) (2)
REF
Ë
¯
4095
tion of the DACs. For dual supply, VSS can be set from –6.5 V
to –2.7 V and VDD can be set from +2.7 V to +6.5 V. For single
supply, VSS should be set at 0 V while VDD is set from 3 V to
16.5 V. However, setting the single supply of VDD below 4.5 V
can impact the overall accuracy of the device.
Ê 2D
ˆ
¯
VOUT
=
– 1 V
Á
˜
(For AD5583) (3)
REF
Ë
1023
The advantage of this scheme is that it allows the DAC to inter-
polate between two voltages for differential references or
single-ended reference.
REV. A
–15–
AD5582/AD5583
Since these DACs can be operated at high voltages, the digital
signal levels are therefore controlled separately by the provision
of DVDD. DVDD can be set as low as 2.7 V but no greater than
6.5 V. This allows the DAC to be operable from low level digital
signals generated from a wide range of microcontrollers, FPGA,
and signal processors.
Reset
The RS function can be used either at power-up or at any time
during operation. The RS function has priority over any other
digital inputs. This pin is active low and sets the DAC output
registers to either zero scale or midscale, determined by the state
of the MSB. The reset to midscale is useful when the DAC is
configured for bipolar references and the output will be reset to 0 V.
Reference Input
All four channels of DACs allow independent and differential
reference voltages. The flexibility of independent references
allows users to apply a unique reference voltage to each channel.
Similarly, bipolar references can be applied across the differential
references. To maintain optimum accuracy, the difference between
VREFH and VREFL should be greater than 1 V. See TPC 11.
Output Amplifiers
Unlike many voltage output DACs, the AD5582/AD5583 feature
buffered voltage outputs with high output current driving capa-
bility. Each output is capable of both sourcing and sinking ±20 mA,
eliminating the need for external buffers when driving any capaci-
tive loads without oscillation. These amplifiers also have short
circuit protection.
The voltages applied to these reference inputs set the output
voltage limits of all four channels of the DACs, and VREFH must
always be higher than VREFL. VREFH can be set at any voltage from
VREFL + 0.5 V to VDD, while VREFL can be set at any voltage from
VSS to VREFH – 0.5 V. In addition, a symmetrical negative reference
can be generated easily by an external op amp in an inverting
mode with a pair of built-in precision resistors, R1 and R2. These
resistors are matched within ±0.025% for the AD5582 and 0.1%
for the AD5583, which is equivalent to less than 1 LSB mis-
match. Figure 4 shows a simple configuration.
Glitch
The worst-case glitch of the AD5582 occurs at the transitions
between midscale (1000 0000 0000B) to midscale minus 1
(0111 1111 1111B), or vice versa. The glitch energy is mea-
sured as 100 mV ꢁ 1 ms or equivalent to 100 nV-s. Such glitch
occurs in a shorter duration than the settling time and therefore
most applications will be immune to such an effect without a
deglitcher.
Layout and Power Supply Bypassing
Common reference or references can be applied to all four chan-
nels, but each reference pin should be decoupled with a 0.1 mF
ceramic capacitor mounted close to the pin.
It is a good practice to employ compact, minimum lead length
PCB layout design. The leads to the input should be as short as
possible to minimize IR drop and stray inductance.
It is also essential to bypass the power supplies with quality capaci-
tors for optimum stability. Supply leads to the device should be
bypassed with 0.01 mF to 0.1 mF disc or chip ceramics capacitors.
Low ESR 1 mF to 10 mF tantalum or electrolytic capacitors should
also be applied at the supplies to minimize transient disturbance.
The AD5582/AD5583 optimize internal layout design to reduce
die area so that all analog supply pins are required to be con-
nected externally. See Figure 5.
AD5582
+2.5V
ADR421
V
REFHA
REF
ꢀ2.5V
ꢀ2.5V
DAC A
V
REFHB
V
REFHC
V
DAC B
REFHD
R1
R2
RCT
ꢀ2.5V
ꢀ2.5V
DAC C
DAC D
V
REFLA
–
V
REFLB
AD5582/
AD5583
V
+
REFLC
–2.5V
V
REFLD
V
V
DD
DD1
+
+
V
C1
C2
DD2
Figure 4. Using On-Board Matching Resistors
to Generate a Negative Voltage REF
10ꢁF
0.1ꢁF
V
DD3
AGND1
AGND2
C3
10ꢁF
C4
0.1ꢁF
Digital I/O
V
V
SS
SS1
Digital I/O consists of a 12-/10-bit bidirectional data bus, two
register select inputs, A0 and A1, an R/W input, a Reset (RS), a
Chip Select (CS), and a Load DAC (LDAC) input. Control of
the DACs and the bus direction is determined by these inputs
as shown in Table I. All digital pins are TTL/CMOS compat-
ible and all internal registers are level triggered.
V
SS2
V
SS3
DV
DD
C5
0.1ꢁF
DGND
Figure 5. Power Supply Configurations
APPLICATIONS
The register selects inputs A0 and A1. Decoding of the registers
is enabled by the CS input. When CS is high, no decoding is
taking place and neither the writing nor the reading of the input
registers is enabled. The loading of the second bank of registers
is controlled by the asynchronous LDAC input. By taking LDAC
low while CS is enabled, the individual channel is updated as
single buffer mode, Figure 2a. If CS is enabled sequentially to
load data into all input registers, then a subsequent LDAC pulse
will allow all channels to be updated simultaneously as double
buffer mode, Figure 2b.
Programmable Current Source
AD5582/AD5583 high current capability allow them to be used
directly in programmable current source applications, such as
4 m to 20 mA current transmitter and other general purpose
applications. For higher compliance voltage that is higher than
15 V, Figure 6 shows a versatile V-I conversion circuit using an
improved Howland Current Pump. In addition to the precision
current conversion it provides, this circuit enables a bidirec-
tional current flow and high voltage compliance. The voltage
R/W controls the writing to and reading from the input register.
–16–
REV. A
AD5582/AD5583
Table I. AD5582/AD5583 Logic Table
INPUT
REGISTER
DAC
REGISTER
OPERATION
MODE
SELECTED
DAC
A1
A0
R/W
CS
LDAC
RS
0
0
1
1
0
0
1
1
0
0
1
1
X
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
X
1
0
0
0
0
1
1
1
1
1
1
1
1
0
1
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
≠
Write
Write
Write
Write
Write
Write
Write
Write
Read
Read
Read
Read
Hold
Hold
Transparent
Transparent
Transparent
Transparent
Hold
Hold
Hold
Hold
Hold
Transparent
Transparent
Transparent
Transparent
Write Input
Write Input
Write Input
Write Input
Readback to D0 to DN
Readback to D0 to DN
Readback to D0 to DN
Readback to D0 to DN
Update All Registers
Hold
A
B
C
D
A
B
C
D
A
B
Hold
Hold
Hold
C
D
All
All
All
All
Update All Registers
Hold
All registers reset to midscale or zero scale.
All registers latched to midscale or zero scale.
MSB = 0 resets to zero scale, MSB = 1 resets to midscale. X: Don’t Care. Input and output registers are transparent when asserted.
This circuit is versatile, but users must pay attention to the
compensation. Without C1, it can be shown that the output
impedance becomes:
compliance is mainly limited by the op amp supply voltages.
This circuit can be used in 4 to 20 mA current transmitters with
up to 500 W of load.
R1'R3 R1 + R2
(
)
R1'
R2'
ZO
=
(5)
150kꢅ
15kꢅ
R1 R2'+ R3' – R1' R2 + R3
(
)
(
)
C1
10pF
If the resistors are perfectly matched, ZO is infinite, which is
highly desirable. On the other hand, if they are not matched, ZO
can either be positive or negative. The latter, because of the
pole in the right S-plane, can cause oscillation. As a result, C1
in the range of a few pF is needed to prevent the oscillation. For
critical applications, C1 should be found empirically without
overcompensating.
+15V
R3'
50ꢅ
–
U4
AD8510
+
U1
ADR421
+2.5V
+5V
+5V
R3
50ꢅ
V
DAC
V
V
DD
REFH
–15V
R1
RCT
R2
V
Boosted Programmable Voltage Source
ADU52582
VL
IL
For users who need higher than 20 mA current driving capabil-
ity, they can add an external op amp and power transistors. The
capacitive loading capability will change, but it can still drive
100 nF capacitive load without oscillation in this circuit. Figure 7
shows a programmable power supply with 200 mA capability.
R1
150kꢅ
R2
15kꢅ
V
SS
REFL
+5V
–
LOAD
–5V
OP1177
+
–2.5V
FDV30IN
V
V
O
DD
DECOUPLING CAPS ARE OMITTED FOR CLARITY
+5V
–5V
N1
+4.096V
V
U1
REF198
+15V
U3
Figure 6. Programmable Current Source with Bidirectional
Current Control and High Voltage Compliance Capabilities
V
REFH
DD
LOAD
ADU52582
C1
1ꢁF
+
Figure 6 shows that if the resistor network is matched, the load
current is:
OP1177
–
V
V
REFL
SS
R2 + R3 / R1
(
)
IL
=
VDAC
(4)
DECOUPLING CAPS ARE OMITTED FOR CLARITY
R3
Figure 7. Boosted Programmable Voltage Source
R3 in theory can be made small to achieve the current needed
within the U4 output current driving capability. In this circuit,
the AD8510 can deliver ±20 mA in both directions and the
voltage compliance approaches ±15 V.
REV. A
–17–
AD5582/AD5583
V
V
DD
DD
+10V
FDBK
+10V
FDBK
G+
VINP
G–
G+
VINP
G–
V+
U5
AD603
V–
V+
U6
AD603
V–
C1
C2
C3
V
V
IN
DD
OUT
OUT
V
O
0.1ꢁF
0.1ꢁF
0.1ꢁF
R3
50kꢅ
R1
100ꢅ
COMM
COMM
+
U4
AD8565
–
R4
50kꢅ
V
DD
V
DD
VOA VOB
V
1-TO-3 VOC VOD
DD
R2
10kꢅ
R1
V
REFHA
DV
DD
10kꢅ
2.0V
1.0V
V
REFHB
V
REFHC
+IN
V
REFHD
U1
AD5582
U2
ADR510
V
REFLA
–IN
V
REFLB
V
REFLC
+IN
V
REFLD
V
1-TO-3
SS
U3
ADR510
–IN
DECOUPLING CAPS ARE OMITTED FOR CLARITY
Figure 8. Programmable PGA
In this circuit, the inverting input of the op amp forces the VO to
be equal to the DAC output. The load current is then delivered by
the supply via the N-Ch FET N1. U3 needs to be a rail-to-rail
input type. With a VDD of 5 V, this circuit can source a maximum
of 200 mA at 4.096 V full scale, 100 mA at midscale, and 50 mA
near zero-scale outputs. Higher current can be achieved with N1
in a larger package mounted on a heat sink.
The decibel gain is linear in dB, accurately calibrated, and stable
over temperature and supply. The gain is controlled at a high
impedance (50 MW), low bias (200 nA) differential input; the
scaling is 25 mV/dB, requiring a gain control voltage of only 1 V
to span the central 40 dB of the gain range. An overrange and
underrange of 1 dB is provided whatever the selected range. The
gain control response time is less than 1 ms for a 40 dB change.
Programmable PGA
The differential gain control interface allows the use of either
differential or single-ended positive or negative control voltages,
where the common-mode range is –1.2 V to +2.0 V. The
AD5582/AD5583 is ideally suited to provide the differential
input range of 1 V within the common-mode range of 0 V to 2 V.
To accomplish this, place VREFH at 2.0 V and VREFL at 1.0 V,
then all 4096 V levels of the AD5582 will fall within the gain
control range of the AD603. Please refer to the AD603 data
sheet for further information regarding gain control, layout, and
general operation.
The AD603 is a low noise, voltage controlled amplifier for use in
RF and IF AGC (automatic gain control) systems. It provides
accurate, pin selectable gains of –11 dB to +31 dB with a band-
width of 90 MHz, or 9 dB to 51 dB with a bandwidth of 9 MHz.
Any intermediate gain range may be arranged using one external
resistor between Pin 5 and Pin 7. The input referred noise spectral
density is only 1.3 nV/÷Hz and power consumption is 125 mW
at the recommended ±5 V supplies.
–18–
REV. A
AD5582/AD5583
OUTLINE DIMENSIONS
48-Lead Thin Shrink Small Outline Package [TSSOP]
(RV-48)
Dimensions shown in millimeters
12.60
12.50
12.40
48
25
6.20
6.10
6.00
8.10 BSC
1
24
PIN 1
1.20 MAX
0.15
0.05
0.75
8ꢃ
0ꢃ
0.60
0.45
0.5
BSC
0.27
0.17
SEATING
PLANE
0.20
0.09
COMPLIANT TO JEDEC STANDARDS MO-153ED
REV. A
–19–
AD5582/AD5583
Revision History
Location
Page
8/03—Data Sheet changed from REV. 0 to REV. A.
Change to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Changes to Figures 2a, 2b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
–20–
REV. A
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