AD5564 [ADI]
IC SAMPLE AND HOLD AMPLIFIER, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119, Sample and Hold Circuit;
| 型号： | AD5564 |
| 厂家： | 
ADI |
| 描述： | IC SAMPLE AND HOLD AMPLIFIER, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119, Sample and Hold Circuit 放大器 |
| 文件： | 总12页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32/64-Channel Infinite
Sample-and-Hold
a
Preliminary Technical Data
AD5532/64
FEATURES
GENERAL DESCRIPTION
Infinite Hold Capability with No Droop
Single Input, 32/64 channels of Output
Input/Output Transfer Function Linearity of
The AD5532/64 combines a 32/64 channel voltage translation
function with an infinite output hold capability. An analog
input voltage on the common input pin, VIN, is sampled and
its digital representation transferred to a chosen DAC register.
The output of this DAC is updated to reflect the new contents
of the DAC register. Channel selection is accomplished via
the parallel address inputs A5-A0 or via the serial input port.
The device is operated from +5V, ± 12V to ± 15V
supplies and requires a stable +3V reference on REF IN
pins as well as an offset voltage on OFFS_IN. The
AD5532/64 is available in a 119-lead BGA package.
±
0.012% max
Per-Channel Acquisition time of 16 µs max
Input Voltage: 0 to +3V
Output Voltage Span: 10.5V
e.g. -3V to +7.5V
-2.5V to +7V
Power-OnReset
APPLICATIONS
LevelSetting
Instrumentation
AutomaticTestEquipment
ControlSystems
DataAcquisition
Low Cost I/O
PRODUCT HIGHLIGHTS
1. No Droop; Infinite Hold Capability
2. Typically
±0.006% transfer function linearity betwen
Input and Output.
3. 32/64 14-bit DACs in one package, guaranteed
monotonic with 9-bit linearity.
3. The AD5532/64 is available in a 119-lead BGA package
with a bump pitch of 1.27mm and a body size of 14mm by
22mm.
FUNCTIONAL BLOCK DIAGRAM
V
V
DD
DV
AV
CC
OFFS_IN
SS
REF IN 1
REF IN 2
CC
AD5532/64
-
V
1
OUT
+
V
DAC
ADC
IN
TRACK
BUSY
-
V
64
OUT
DAC
DAC
+
DAC_GND
AGND
OFFS_OUT
DGND
INTERFACE
CONTROL
LOGIC
SER/PAR
ADDRESS INPUT REGISTER
WR
CAL
OFFSET_SEL
SCLK
D
D
A5-A0
SYNC/CS
IN
OUT
Patents Applied For
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106,USA
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its use,
nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under
any patent or patent rights of Analog Devices.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web: www.analog.com
Prelim D3 7/98
VDD = +10.8V to +16.5V, VSS = -10.8V to -16.5V; AVCC = +4.75V to +5.25V;
DVCC = +2.7V to +5.25V; AGND = DGND = DAC_GND = 0V; All specifica-
tions TMIN to TMAX unless otherwise noted.
AD5532/64-SPECIFICATIONS
Mode 1 - SHA Mode
Parameter1
B Version2
Units
Conditions/Comments
ANALOG CHANNEL
VIN to VOUT Linearity
± 0.012
% max
Typically ±0.006% (after gain and offset
adjustment)
Offset Error
Gain Error
Channel-to-Channel Matching
± 60
± 3
TBD
mV max
% max
% typ
See Figure 1 (page 8)
ANALOG INPUT (VIN)
Input Voltage Range
Input Current
0 to +3
100
6.4
V
Nominal Input Range
nA max
µA max
VIN being acquired on one channel
VIN being acquired on all 64 channels
simultaneously - Cal Mode
Input Capacitance
50
pF typ
ANALOG INPUT (OFFS_IN)
Input Current
100
nA max
REFERENCE INPUTS
Nominal Input Voltage
Input Voltage Range
Input Current
+3.0
+2.85/+3.15
50
V
V min/max
nA max
ANALOG OUTPUTS (VOUT 1-64)
Output Temp Coeff
25
750
ppm/°C typ
Ω typ
Output Impedance
Output Range
VSS + 3 /VDD - 3
500
15
250
10
-70
-70
TBD
V min/max
µA typ
nF max
µV rms
mA typ
dB
Maximum Output Current
Maximum Capacitive Load
Output Noise
Short-Circuit Current
Output PSRR
1MHz Bandwidth
VDD varied ±5%.
VSS varied ±5%
dB
µV typ
DC Crosstalk
ANALOG OUTPUT (OFFS_OUT)
Output Temp Coeff
Output Impedance
Output Range
20
1.0
ppm/°C typ
kΩ typ
V min/max
µV rms
µA typ
pF typ
mA typ
dB typ
0 / +REF IN
100
10
100
10
-70
TBD
Output Noise
1MHz Bandwidth
Source Current
Maximum Output Current
Maximum Capacitive Load
Short-Circuit Current
Output PSRR
Sink Current
AVCC varied ±5%
DC Crosstalk
µV typ
DIGITAL INPUTS
Input Current
±10
0.8
0.4
2.0
200
10
µA max
V max
V max
V min
mV typ
pF max
Input Low Voltage
DVCC = 5V±5%
DVCC = 3V±10%
Input High Voltage
Input Hysteresis (SCLK only)
Input Capacitance
-2-
Prelim D3 7/98
VDD = +10.8V to +16.5V, VSS = -10.8V to -16.5V; AVCC = +4.75V to +5.25V;
DVCC = +2.7V to +5.25V; AGND = DGND = DAC_GND = 0V; All specifica-
tions TMIN to TMAX unless otherwise noted.
AD5532/64-SPECIFICATIONS
Mode 1 - SHA Mode (cont.)
Parameter1
B Version2
Units
Conditions/Comments
DIGITAL OUTPUTS (BUSY, DOUT
)
Output Low Voltage
Output High Voltage
Output Low Voltage
0.4
4.0
0.4
2.4
TBD
TBD
V max
V min
V max
V min
µA max
pF max
DVCC = 5V. Sinking TBD mA
DVCC = 5V. Sourcing TBD µA
DVCC = 3V. Sinking TBD mA
DVCC = 3V. Sourcing TBD µA
Output High Voltage
Floating-State Leakage Current4
Floating-State Input Capacitance4
POWER REQUIREMENTS
Power-Supply Voltages
VDD
VSS
AVCC
+10.8/+16.5
-10.8/-16.5
+4.75/+5.25
+2.7/+5.25
V min/max
V min/max
V min/max
V min/max
DVCC
Power-Supply Currents5
IDD
ISS
AICC
22
22
44
< 1
880
mA typ
mA typ
mA typ
mA max
mW typ
DICC
Power Dissipation5
AC CHARACTERISTICS
AC Crosstalk
TBD
1
16
nV-s typ
µs typ
µs max
V/µs typ
nV-s typ
nV-s typ
Output Settling Time
Acquisition Time
Slew Rate
Digital Feedthrough
Digital Crosstalk
Low Capacitive load
Acquire VIN to ± 0.012% accuracy
1
TBD
TBD
TRACK MODE
Output PSRR
TBD
TBD
TBD
dB
dB
kHz typ
VDD varied ±5%.
VSS varied ±5%
Bandwidth
NOTES:
1See Terminology
2B Version: Industrial temperature range -40°C. to +85°C.
3Guaranteed by design and characterisation, not production tested
4DOUT only
5Outputs Unloaded. All figures are for the AD5564. The numbers for AD5532 are approx 50% of these.
Specifications subject to change without notice
-3-
Prelim D3 7/98
VDD = +10.8V to +16.5V, VSS = -10.8V to -16.5V; AVCC = +4.75V to +5.25V;
DVCC = +2.7V to +5.25V; AGND = DGND = DAC_GND = 0V; All specifica-
tions TMIN to TMAX unless otherwise noted.
AD5532/64-SPECIFICATIONS
Mode 2 - DAC Mode
Parameter1
B Version2
Units
Conditions/Comments
DC PERFORMANCE
Resolution
14
Bits
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
Gain Error
Full-Scale Error
Offset Error Temp Coeff
Gain Error Temp Coeff
Channel-to-Channel Matching
TBD
±1
% of FSR typ
LSB max
mV max
% max
mV max
µV/°C typ
µV/°C typ
% max
Guaranteed Monotonic
TBD
TBD
TBD
TBD
TBD
TBD
AC CHARACTERISTICS
Output Settling Time
TBD
TBD
TBD
TBD
TBD
TBD
TBD
µs typ
µs typ
OFFS_IN Settling Time
Digital-to-Analog Glitch Impulse
Digital Crosstalk
Analog Crosstalk
Total Harmonic Distortion (THD)
Output Noise Spectral Density
nV-s typ
nV-s typ
nV-s typ
dB typ
nV/(Hz)1/2 typ
NOTES:
1See Terminology
2B version: Industrial temperature range -40°C. to +85°C.
3Guaranteed by design and characterisation, not production tested
Specifications subject to change without notice
Timing Characteristics
Serial Interface
Limit at TMIN, TMAX
Parameter1
(B Version)
Units
Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
25
25
5
TBD
10
5
5
10
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
SCLK High Pulse Width
SCLK Low Pulse Width
SYNC Falling Edge to SCLK Falling Edge Setup Time
SYNC Low Time
DIN Setup Time
DIN Hold Time
SYNC Falling Edge to SCLK Rising Edge Setup Time
SCLK Rising Edge to DOUT Valid
SCLK Falling Edge to DOUT High Impedance
2
t8
t9
2
NOTES:
1See Interface Timing Diagrams on following pages
2These numbers are measured with the load circuit of Figure x
Prelim D3 7/98
AD5532/64 Prelim Technical Information
Parallel Interface
Limit at TMIN, TMAX
(B Version)
Parameter1
Units
Conditions/Comments
t1
t2
t3
t4
t5
t6
0
0
50
50
20
0
ns min
ns min
ns min
ns min
ns min
ns min
CS to WR Setup Time
CS to WR Hold Time
CS Pulse Width Low
WR Pulse Width Low
A5-A0, CAL, OFFS_SEL to WR Setup Time
A5-A0, CAL, OFFS_SEL to WR Hold Time
NOTES:
1See Interface Timing Diagrams below
Parallel Interface Timing Diagram
t
t
2
1
t
3
CS
t
4
WR
t
t
6
5
A5-A0, C AL ,
OFFS_SEL
Serial Interface Timing Diagrams
t
1
6
7
9
10
1
2
3
4
5
8
SC LK
S YN C
t
2
t
3
t
4
t
5
t
6
D
IN
M S B
L SB
10-Bit Write (SHA Mode and Both Readback Modes)
Prelim D3 7/98
5
AD5532/64 Prelim Technical Information
Serial Interface Timing Diagrams
t
1
21
23
24
4
5
22
1
2
3
SCLK
t
2
t
3
SYNC
t
4
t
5
t
6
D
IN
MSB
LSB
24-Bit Write (DAC Mode)
t
1
6
7
9
10
12
13
14
4
5
8
11
1
2
3
SCLK
SYNC
t
2
t
7
t
4
t
9
t
8
D
OUT
MSB
LSB
14-Bit Read(Both Readback Modes)
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
Short-Circuit Current............................................TBD mA
Operating Temperature Range
VDD to AGND................................................-0.3V to +17V
VSS to AGND.................................................+0.3V to -17V
AVCC to AGND, DAC_GND............................-0.3V to +7V
DVCC to DGND...............................................-0.3V to +7V
Digital Inputs to DGND........................-0.3V to DVCC+0.3V
Digital Outputs to DGND.....................-0.3V to DVCC+0.3V
REF IN to AGND, DAC_GND.......................-0.3V to +7V
VIN to AGND, DAC_GND...............................-0.3V to +7V
VOUT1-64, OFFS_OUT to AGND........VSS-0.3V to VDD+0.3V
AGND to DGND........................................................TBD
Industrial (B Version)..............................-40°C to +85°C
Storage Temperature Range........................-65°C to +150°C
Junction Temperature (TJ max).........................+150°C
BGA Package,
Power Dissipation......................(TJ max - TA)/θJA mW
θJA Thermal Impedance.............................TBD°C /W
θJC Thermal Impedance.............................TBD°C /W
Solder Ball Temperature, Soldering.................TBD °C.
NOTES:
1Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Transient currents of up to 100mA will not cause SCR latch-up
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5532/64 devices feature proprietary ESD protection circuitry, permanent damage may still
occur on these devices if they are subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
6
Prelim D3 7/98
AD5532/64 Prelim Technical Information
Digital Feeedthrough
Terminology
SHA Mode
This is a measure of the impulse injected into the analog
outputs from the digital control inputs when the part is not
being written to, i.e. CS/SYNC is high. The digital inputs are
toggled between all 0s and all 1s. The area of the glitch is
expressed in nV-secs.
VIN to VOUT Linearity
This is a measure of the maximum deviation from a straight
line passing through the endpoints of the VIN vs. VOUT transfer
function. It is expressed as a percent of the full-scale span.
Digital Crosstalk
This is the glitch impulse transferred to the analog output
while a digital word is being written to the part. The area of
the glitch is expressed in nV-secs.
Offset Error
This is a measure of the output error when VIN = 100mV.
Ideally, with VIN=100mV:
VOUT= 350mV-2.5*VOFFSET
Offset error is a measure of the difference between VOUT
(actual) and VOUT (ideal). It is expressed in mV.
TRACK Mode Bandwidth
When TRACK input is brought low, the input is not ac-
quired. It is connected to the output buffer and the output
voltage is:
Full-Scale Error
VOUT= 3.5*VIN-2.5*VOFFSET
This is a measure of the output error when VIN = VREF. Ideally,
VIN can, of course, be an AC waveform in which case the
TRACK mode has a finite bandwidth. The bandwidth is the
frequency at which the sinusoidal component at the output
falls to 3dB below the sine wave at the input (ignoring the gain
factor).
with VIN=VREF
:
VOUT= 3.5*VREF-2.5*VOFFSET
Full-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal). It is expressed in mV.
Gain Error
This is a measure of the span error of the analog channel. It is
the deviation in slope of the transfer function expressed as a
percent of the full-scale span. It is calculated as:
Full-Scale error - Offset Error
DAC Mode
Gain Error = ------------------------------------* 100
Full-scale span
Integral Nonlinearity (INL)
This is a measure of the maximum deviation from a
straight line passing through the endpoints of the DAC
transfer function. It is expressed as a percentage of Full-
Scale span.
Channel-to-Channel Matching
This is a measure of the difference between VOUT on any two
channels if they acquire the same VIN. It is expressed as a
percent of the Full-scale span.
Differential Nonlinearity (DNL)
Output Temp Coefficient
This is a measure of the change in output with changes in
temperature. It is expressed in µV/°C.
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any
two adjacent codes. A specified DNL of ±1 LSB maximum
ensures monotonicity.
Output PSRR
Power-Supply Rejection Ratio (PSRR) is a measure of the
change in output for a change in supply voltage (VDD and VSS).
It is expressed as percent change of output per percent change
of supply. VDD and VSS are varied ± 5%. For the PSRR
measurement of OFFS_OUT, the AVCC supply is varied ±
5%.
Offset Error
This is a measure of the output error with all zeroes loaded to
the DAC. Ideally the output should be:
VOUT= 350mV-2.5*VOFFSET
Offset error is ameasure of the difference between VOUT
(actual) and VOUT (ideal). It is expressed in mV.
DC Crosstalk
Full-Scale Error
This the DC change in the output level of one channel in
response to a full-scale change in the output of another
channel. It is expressed in µV.
This is a measure of the output error with all ones loaded to
the DAC. Ideally, the output should be:
VOUT= 3.5*VREF-2.5*VOFFSET
Full-scale error is a measure of the difference between
VOUT (actual) and VOUT (ideal). It is expressed in mV.
AC Crosstalk
This is the glitch that occurs on the output of one channel
while another channel is acquiring. It is expressed in nV-secs.
Gain Error
This is a measure of the span error of the DAC. It is the
deviation in slope of the transfer function expressed as a
percent of the full-scale span. It is calculated as:
Full-Scale error - Offset Error
Output Settling Time
This is the time taken from when BUSY goes high to when
the output has settled to ± 0.012% (± 0.5 LSB at 12 bits).
Acquisition Time
This is the time taken for the VIN input to be acquired. It is the
length of time that BUSY stays low.
Gain Error = ------------------------------------* 100
Full-scale span
Prelim D3 7/98
7
AD5532/64 Prelim Technical Information
Channel-to-Channel Matching
This is a measure of the difference between VOUT on any
two DACs if they have the same coded loaded to them. It
is expressed as a percent of the Full-scale span.
Output Settling Time
This is the time taken from when the last data bit is clocked
into the DAC until the output has settled to within ± 0.012%
(± 0.5 LSB at 12 bits).
OFFS_IN Settling Time
This is the time taken from a step change in input voltage on
OFFS_IN until the output has settled to within ± 0.012% (±
0.5 LSB at 12 bits).
Digital-to-Analog Glitch Impulse
This is the impulse injected into the analog output when the
code in the DAC register changes state. It is specified as the
area of the glitch in nV-secs when the digital code is changed
by 1 LSB at the major carry transition (01 1111 1111 1111 to
10 0000 0000 0000).
Digital Crosstalk
This is the glitch impulse transferred to the analog output
while a DAC code is being written to the part. The area of the
glitch is expressed in nV-secs.
Analog Crosstalk
This the glitch impulse transferred to the output of one DAC
due to a full-scale change in the output of another DAC. The
area of the glitch is expressed in nV-secs.
Total Harmonic Distortion
This is the difference between an ideal sine-wave and a
digitally constructed one using the DAC. The THD is a
measure of the harmonics and noise present on the DAC
output. It is measured in dBs.
Gain Error
+
Offset Error
Ideal
Transfer
Function
VOUT
Dead Band (10m V m ax)
Actual
Transfer
Function
Offset Error
0V
VIN
3V
Dead Band (100m V m ax)
Figure 1. SHA Transfer Function
8
Prelim D3 7/98
AD5532/64 Prelim Technical Information
PIN FUNCTION DESCRIPTION
PIN NUMBERS
Pin
No.
Mnemonic
Function
AGND (1-4)
AVCC (1-4)
VDD (1-8)
4 Analog GND pins.
4 Analog supply pins. Voltage range from +4.75V to +5.25V.
8 VDD supply pins. Voltage range from +10.8V to +16.5V.
8 VSS supply pins. Voltage range from +10.8V to +16.5V.
2 Digital GND pins
VSS (1-8)
DGND (1-2)
DVCC (1-2)
2 Digital supply pins. Voltage range from +2.7V to +5.25V.
DAC_GND (1-4) Reference GND supply for all the DACs.
REF IN 1
REF IN 2
VOUT (1-64)
VIN
Reference voltage for channels 1-32
Reference voltage for channels 33-64
Analog output voltages from the 64 channels.
Analog input voltage
A5-A0
CAL
CS / SYNC
Parallel Interface: 6 address pins for the 64 channels. A5=MSB of channel address, A0=LSB.
Parallel Interface: Control input which allows all 64 channels to acquire VIN simultaneously
This pin is both the active low Chip Select pin for the parallel interface and the Frame
Synchronisation pin for the serial interface.
WR
Parallel Interface. Write pin. Active low. This is used in conjunction with the CS pin to
address the device using the parallel interface.
OFFSET_SEL
Offset Select pin. This is activated when writing to the DAC which will provide its output
at OFFS_OUT pin.
SCLK
DIN
Serial Clock input for serial interface
Data input for serial interface
DOUT
Output from the DAC registers for readback.
SER/PAR
This pin allows the user to select whether the serial or parallel interface will beused. If the pin is
tied low, the parallel interface will be used. If it is tied high, the serial interface will be used.
Offset input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be
tied to this pin if the user wants to drive this pin with the Offset Channel.
Offset output. This is the acquired offset voltage which can be tied to OFFS_IN to offset the span.
This output tells the user when the input voltage is being acquired. It goes low during acquisition
and returns high when the acquisition operation is complete.
OFFS_IN
OFFS_OUT
BUSY
TRACK
If this input is held high, VIN is acquired once the channel is addressed. While it
is held low, the input to the gain/offset stage is switched directly to VIN. The addressed channel
begins to acquire VIN on the rising edge of TRACK. See TRACK Input section for further infor
mation.
Prelim D3 7/98
9
AD5532/64 Prelim Technical Information
complete at which point the DAC assumes control of the
voltage to the output buffer and VIN is free to change again
without affecting this output value.
Circuit Description
The AD5532/64 can be thought of as consisting of an ADC
and 64 DACs in a single package. The input voltage VIN is
sampled and converted into a digital word. The digital result
is loaded into one of the DAC registers and is converted (after
the gain and offset in the output buffer) into an analog output
voltage (VOUT1 - VOUT 64). Since the channel output voltage is
effectively the output of a DAC there is no droop associated
with it. As long as power is maintained to the device the
output voltage will remain constant until this channel is
addressed again.
This is useful in an application where the user wants to
ramp up VIN until VOUT reaches a particular level (Figure
1). VIN doesn't need to be acquired continuously while it
is ramping up. TRACK can be kept low and only when
VOUT has reached its desired voltage is TRACK brought
high. At this stage, the acquisition of VIN begins.
In the example shown, a desired voltage is required on
the output of the pin driver. This voltage is represented
by one input to a comparator. The microcontroller/
microprocessor ramps up the input voltage on VIN
through a DAC. TRACK is kept low while the voltage
on VIN ramps up so that VIN is not continually acquired.
When the desired voltage is reached on the output of the
pin driver, the comparator output switches. The µC/µP
then knows what code is required to be input in order to
get the desired voltage at the DUT. The TRACK input
is now brought high and the part begins to acquire VIN.
At this stage BUSY goes low until VIN has been acquired.
Then the output buffer is switched from VIN to the output
of the DAC.
To update a single channel's output voltage the required new
voltage level is set up on the common input pin, VIN. The
desired channel is then addressed via the parallel port or the
serial port. When the channel address has been loaded,
provided TRACK is high, the circuit begins to acquire the
correct code to load to the DAC in order that the DAC
output matches the voltage on VIN. At this stage the BUSY
pin goes low and remains so until the acquistion is complete.
The non-inverting input to the output buffer (gain and offset
stage) is tied to VIN during the acquisition period to avoid
spurious outputs while the DAC acquires the correct code.
This is completed in 16 us max. The BUSY pin goes high at
this stage. Also at this time the updated DAC output assumes
control of the output voltage. The output voltage of the DAC
is connected to the non-inverting input of the output buffer.
The held voltage will remain on the output pin indefinitely,
without drooping, as long as power is maintained to the
device.
Output Buffer Stage - Gain and Offset
The function of the output buffer stage is to translate the 0-
3V output of the DAC to a useful range for ATE applications.
This is done by gaining up the DAC output by 3.5 and
offsetting the voltage by the voltage on OFFS_IN pin. The
following table shows how the output range relates to the
Offset voltage supplied by the user.
On power-on, all the DACs, including the offset channel, are
loaded with zeroes. The outputs of the DACs are at 0V and
the outputs of the output buffers are at negative full-scale. If
the OFFS_IN pin is driven by the on-board offset channel,
the outputs VOUT1 to VOUT64 are also at 0V on power-on since
OFFS_IN is 0V.
VOUT = 3.5*VDAC - 2.5*VOFFSET
VDAC is the output of the DAC and its range is 0-VREF. VOFFSET
is the voltage at the OFFS_IN pin.
SAMPLE OUTPUT RANGES
TRACK Input
In normal mode of operation, TRACK is held high and the
VOFFSET (V)
VDAC (V)
VOUT (V)
channel begins to acquire when it is addressed. However, if
TRACK is low when the channel is addressed then VIN is
switched to the output buffer and an acquisition on the
channel will not occur until a rising edge of TRACK. At this
stage the BUSY pin will go low until the acquisition is
1
0.5
0 to 3
0 to 3
-2.5 to 8
-1.25 to 9.25
VOUT is limited only by the headroom of the output
amplifiers.
Vin
ACQUISITION
CIRCUIT
OUTPUT
STAGE
PIN
DRIVER
DAC
CONTROLLER
+
-
DEVICE
UNDER
TEST
Vout
1
BUSY
TRACK
Threshold Voltage
*Only one channel shown for simplicity
Typical ATE circuit using TRACK Input
10
Prelim D3 7/98
AD5532/64 Prelim Technical Information
Offset Voltage Channel
However, on the next falling edge of SYNC, the data in
the relevant DAC register is clocked out onto the DOUT
line in a 14-bit serial format.
The offset voltage can be supplied externally by the user or it
can be supplied by an additional DAC on the part. The offset
voltage channel is used just like any other channel. The
required offset voltage is set up on VIN and it is acquired by
the DAC. The DAC output is connected directly to
OFFS_OUT. This offset voltage is used as the offset voltage
for the 64 output amplifiers.
4) Readback
Again, this is a readback mode but no acquisition is per-
formed. The relevant DAC is addressed (10-bit write) and on
the next falling edge of SYNC, the data in the relevant DAC
register is clocked out onto the DOUT line in a 14-bit
serial format.
Serial Interface
The serial interface is controlled by 4 pins.
SYNC, DIN, SCLK: Standard 3-wire SPI interface pins.
The SYNC pin is shared with the CS function of the
parallel interface.
DOUT: Data Out pin for reading back the contents of the
DAC registers.
The serial write and read words can be seen in the figures
below.
Digital Readback
This feature allows the user to readback the DAC register
code of any of the DACs. This is useful if the system has been
calibrated and the user wants to know what code in the DAC
corresponds to a desired voltage on VOUT. If the user requires
this voltage again, all he needs to do is to input the code
directly to the DAC register without going through the
acquisition sequence. The user can readback the DAC
register contents through the serial interface and can write
directly to the DAC, again through the serial interface.
The SER/PAR pin must also be tied high to enable the serial
interface and to disable the parallel interface.
Mode bits: There are 4 different modes of operation. See
below for descriptions.
Cal bit: This is used as a calibration instruction. When this is
active, all 64 channels acquire VIN simultaneously.
Parallel Interface
Offset_Sel bit: Used to address the offset voltage control
channel.
The parallel interface is controlled by 10 pins.
CS: Active low package select pin. This pin is shared with the
SYNC function for the serial interface.
WR: Active low Write pin. The values on the address pins are
latched on a rising edge of WR.
A5-A0: 6 Address pins (A5=MSB of address, A0=LSB).
These are used to address the relevant channel (out of a
possible 64).
Offset_Sel: Offset select pin. This has the same function as
the Offset_Sel bit in the serial interface. When it is activated,
the offset voltage control channel is addressed. The address
on A5-A0 is ignored in this case.
A5-A0: Used to address any one of the 64 channels (A5 =
MSB of address, A0=LSB).
DB13-DB0: These are used to write a 14-bit word into
the addressed DAC register. Clearly, this is only valid
when in DAC mode.
The AD5532/64 can be used in 4 different modes of
operation. These modes are set by two Mode bits, the
first 2 bits in the serial word.
MODES OF OPERATION
Cal:Same functionality as the Cal bit in the serial interface
(calibration instruction). When this pin is active, all 64
channels acquire VIN simultaneously.
Mode Bit 1 Mode Bit 2 Operating Mode
0
0
1
1
0
1
0
1
SHA Mode
DAC Mode
Acquire and Readback
Readback
The SER/PAR bit must be tied low to enable the parallel
interface and disable the serial interface.
1) SHA Mode:
Standard mode where a channel is addressed and that channel
acquires the voltage on VIN. This mode requires a 10-bit write
(see figure below) to address the relevant channel (VOUT1-
VOUT64, Offset Channel or all channels).
2) DAC Mode:
In this mode, a particular DAC register can be written to
directly. This mode requires the 10-bit write from the SHA
mode plus an extra 14 bits to write to the 14-bit register of the
DAC. Any one of the 64 DAC registers may be written to
individually or they can all be loaded simultaneously.
3)Acquire and Readback Mode:
This mode allows the user to read back the data in a
particular DAC register. The relevant DAC is addressed
(10-bit write as with SHA mode) and VIN is acquired.
Prelim D3 7/98
11
AD5532/64 Prelim Technical Information
MSB
LSB
0
0
C al
Offset_Sel
A5-A0
Mode Bits
10-Bit Input Serial Write Word (SHA Mode)
M S B
LSB
0
1
Cal
Offset_Sel
A5-A0
D B13-DB0
M od e B its
24-Bit Input Serial Write Word (DAC Mode)
MSB
LSB
MSB
LSB
DB13-DB0
1
0
Cal
Offset_Sel
A5-A0
+
M ode Bits
10-Bit Serial word
written to part
14-Bit Data read from part after
next falling edge of SYNC
(DB13=MSB of DAC W ord)
Input Serial Interface (Acquire and Readback Mode)
M SB
LSB
M SB
LSB
DB13-DB0
1
1
0
O ffs et_Sel
A5-A0
+
M ode Bits
10-Bit Serial word
written to part
14-Bit D ata read from part after
n ext falling ed ge of S YN C
(DB13=MSB of D AC W ord)
Input Serial Interface (Readback Mode)
12
Prelim D3 7/98
相关型号：
AD5570BRSZ-REEL
SERIAL INPUT LOADING, 12us SETTLING TIME, 16-BIT DAC, PDSO16, ROHS COMPLIANT, PLASTIC, MO-150AC, SSOP-16
ADI
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