AD5522 [ADI]
Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs; 四参数测量单元，集成16位电平设置DAC
| 型号： | AD5522 |
| 厂家： | 
ADI |
| 描述： | Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs |
| 文件： | 总45页 (文件大小：550K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad Parametric Measurement Unit With
Integrated 16-Bit Level Setting DACs
AD5522
Preliminary Technical Data
FEATURES
PRODUCT OVERVIEW
Quad Parametric Measurement Unit
FV, FI, FN, MV, MI Functions
4 Programmable Current Ranges (Internal RSENSE
The AD5522 is a high performance, highly integrated parametric
measurement unit consisting of four independent channels. Each
PPMU channel includes five, 16-bit, voltage out DACs setting the
programmable inputs levels for the force voltage input, clamp and
comparator inputs (high and low). Five programmable force and
measure current ranges are available ranging from 5µA to 64mA.
Four of these ranges use on chip sense resistors, while a high
current range up to 64mA is available per channel using off chip
sense resistors. Currents in excess of 64mA require an external
amplifier. Low capacitance DUT connections (FOH, EXT FOH)
ensure the device is suited to relay less test systems.
)
5uA, 20uA, 200uA and 2mA
1 Programmable Current Range up to 64mA (external RSENSE
22.5 V FV Range with Asymmetrical Operation
Integrated 16-Bit DACs Provide Programmable Levels
Offset and Gain Correction on Chip
Low Capacitance Outputs Suited to Relay Less Systems
On-chip Comparators Per Channel
)
FI Voltage Clamps & FV Current Clamps
Guard Drive Amplifier
System PMU connections
Programmable Temperature Shutdown Feature
SPI/Microwire/DSP & LVDS Compatible Interfaces
Compact 80 lead TQFP Package with Exposed Pad (Top Or
Bottom)
The PMU functions are controlled via a simple three wire serial
interface compatible with SPI/QSPI/Microwire and DSP interface
standards. Interface clocks of 50MHz allow fast updating of modes.
LVDS (Low Voltage Differential Signaling) interface protocol at
100MHz is also supported. Comparator outputs are provided per
channel for device go no-go testing and characterization. Control
registers provide easy way of changing force or measure conditions,
DAC levels and selected current ranges. SDO (serial data out)
allows the user to readback information for diagnostic purposes.
APPLICATIONS
Automatic Test Equipment (ATE)
per pin Parametric Measurement Unit
Continuity & Leakage Testing
Device Power Supply
Instrumentation
SMU (Source Measure Unit)
Precision Measurement
DV
DGND
C
(0-3)
SYS_FORCE
AV (0-4) AV (0-4)
SS DD
SYS_SENSE
AGND
CC
COMP
EN
EXTFOH(0-3)
VREF
16-Bit
CLH DAC
x4
16
16
16
16
X1 REG
M REG
C REG
CLH
SW 3
C
(0-3)
FF
X2 REG
*2
REFGND
*2
OFFSET DAC
*6
INTERNAL RANGE SELECT
(5uA, 20uA, 200uA, 2mA)
16
60Ω
1kΩ
FIN
16
16
SW 1
16-Bit
16 FIN DAC
X1 REG
M REG
C REG
+
FOH(0-3)
X2 REG
FORCE
AGNDx
AMPLIFER
*6
SW 5
-
RSENSE
SW 2
SW 6
SW 7
SW 4
16-Bit
CLL DAC
16
16
16
16
EXTMEASIH(0-3)
EXTMEASIL(0-3)
CLL
+
X1 REG
M REG
C REG
X2 REG
OFFSET DAC
BIAS TO
CENTER
+
-
*2
SW 8
EXTERNAL
RSENSE
(CURRENTS
SW 10
*2
IRANGE
10kΩ
x5 or x10
UP TO 64mA)
MEASOUT
MUX & GAIN
x1/x0.2
+
-
-
SW 9
MEASOUT (0-3)
AGND (0-3)
SW 12
TEMP
SENSOR
MEASURE
CURRENT
IN AMP
16
16
16
SW 11
MEASVH (0-3)
GUARD (0-3)
*6
*6
+
-
X1 REG
M REG
C REG
16-Bit
CPH DAC
16
X2 REG
SW 13
SW 14
DUT
AGNDx
+
SW 16
GUARD AMP
x1
GUARDIN (0-3)/
DUTGND (0-3)
16
16
16
DUTGND
CPH
+
-
-
*6
*6
CPL
16-Bit
CPL DAC
X1 REG
M REG
C REG
16
DUTGND
MEASURE
VOLTAGE
IN AMP
X2 REG
-
+
-
+
SW 15
COMPARATOR
10kΩ
AGNDx
16-Bit
OFFSET
DAC
TO ALL DAC
OUTPUT
AMPLIFIERS
16
TEMP
SENSOR
TO
MEASOUT
MUX
TMPALM
16
SERIAL
INTERFACE
CLAMP &
GUARD
ALARM
POWER ON
RESET
CGALM
CPOH2
/CPO1
CPOH3
/CPO3
CPOL2
/CPO0
CPOL3
/CPO2
CPOH0/
SDI
CPOL0/
SCLK
CPOL1/
SYNC
CPOH1/
SDO
LVDS/
SPI
SDO
SDI
RESET
SCLK
SYNC BUSY
LOAD
Figure 1. Functional Block Diagram
Rev.PrL
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD5522
Preliminary Technical Data
TABLE OF CONTENTS
Features..................................................................................................................... 1
Force Voltage, FV.............................................................................................23
Force Current, FI..............................................................................................24
SPI INTERFACE ..............................................................................................25
LVDS INTERFACE..........................................................................................25
Serial Interface Write Mode ...........................................................................25
Revision History...................................................................................................... 2
Specifications........................................................................................................... 4
Table 2. TIMING Characteristics .................................................................... 8
Absolute Maximum Ratings................................................................................11
Thermal Resistance..........................................................................................11
ESD Caution .....................................................................................................11
Pin Configuration and Function Descriptions.................................................12
TERMINOLOGY..................................................................................................15
Functional Description ........................................................................................16
Force Amplifier ................................................................................................16
Comparators .....................................................................................................16
Clamps...............................................................................................................16
Current Range selection..................................................................................17
High Current ranges........................................................................................17
Device under test ground (DUTGND) ........................................................17
Guard amplifer .................................................................................................18
Compensation Capacitors ..............................................................................18
System Force Sense Switches..........................................................................19
Temperature Sensor.........................................................................................19
Measure Output (MEASOUT) ......................................................................19
DAC Levels.............................................................................................................20
Offset DAC........................................................................................................20
Offset and Gain registers ................................................................................20
Cached x2 registers..........................................................................................20
RESET
Function...............................................................................................25
LOAD
BUSY
and
Function ............................................................................25
Register Update Rates......................................................................................26
Register Selection.............................................................................................27
Write System Control Register.......................................................................28
Write PMU Register ........................................................................................30
Write DAC Register.........................................................................................32
Read Registers...................................................................................................34
Readback of System Control Register...........................................................35
Readback of PMU Register.............................................................................36
Readback of Comparator Status Register.....................................................36
Readback of Alarm Status Register ...............................................................37
Readback of DAC Register .............................................................................37
Power On Default ............................................................................................38
Setting up the device on power on ................................................................39
Changing Modes..............................................................................................39
Required external components......................................................................40
Typical Application for the AD5522 .............................................................42
Outline Dimensions .............................................................................................43
Ordering Guide ................................................................................................44
Notes .......................................................................................................................45
VREF.....................................................................................................................21
Reference Selection..........................................................................................21
Calibration ........................................................................................................22
System Level Calibration ................................................................................22
REVISION HISTORY
5th Sept, Update to block diagram, timing and READ functions. .
Rev. PrL | Page 2 of 45
Preliminary Technical Data
AD5522
DV
DGND
C
0
AV (0-4) AV (0-4)
SS DD
AGND
CC
COMP
EN
EXTFOH 0
VREF
CH0
16-Bit
CLH DAC
16
16
16
16
CLH
SW 3
C
0
X1 REG
M REG
C REG
X2 REG
*2
FF
*2
OFFSET DAC
REFGND
INTERNAL RANGE SELECT
(5uA, 20uA, 200uA, 2mA)
16
FIN
16
16
SW 1
*6
16-Bit
16 FIN DAC
X1 REG
M REG
C REG
+
FOH 0
FORCE
X2 REG
AGND
AMPLIFER
*6
SW
4
-
RSENSE
SW
2
SW 6
SW 7
SW 5
16-Bit
CLL DAC
16
16
16
16
EXTMEASIH 0
EXTMEASIL 0
CLL
+
X1 REG
M REG
C REG
X2 REG
OFFSET DAC
BIAS TO
CENTER
+
*2
SW 8
10kΩ
EXTERNAL
RSENSE
(CURRENTS
UP TO 64mA)
SW 10
-
*2
IRANGE
x5 or x10
MEASOUT
MUX & GAIN
x1/x0.2
+
-
-
SW 9
MEASOUT 0
SW 12
TEMP
SENSOR
MEASURE
CURRENT
IN AMP
AGND
16
16
16
MEASVH 0
GUARD 0
SW 11
*6
+
-
X1 REG
M REG
C REG
16-Bit
16 CPH DAC
X2 REG
DUT
DUTGND
AGND
SW 13
+
SW 16
*6
GUARD AMP
x1
DUTGND
16
16
16
CPH
+
-
-
*6
GUARDIN 0/
DUTGND 0
CPL
SW 14
16-Bit
CPL DAC
X1 REG
M REG
C REG
16
SW 15
MEASURE
VOLTAGE
IN AMP
X2 REG
-
+
-
+
10kΩ
COMPARATOR
CPOL0/ SCLK
CPOH0/ SDI
AGNDx
EXTFOH 1
C
1
FF
C
1
COMP
FOH 1
MEASOUT 1
CPOL1/ SYNC
EXTMEASIH 1
EXTMEASIL 1
MEASVH 1
GUARD 1
CPOH1/ SDO
CH1
CH2
CH3
AGND
GUARDIN 1/DUTGND 1
SYS_SENSE
MUX
SYS_FORCE
MUX
EXTFOH 2
C
2
FF
C
2
COMP
FOH 2
MEASOUT 2
EXTMEASIH 2
EXTMEASIL 2
MEASVH 2
GUARD 2
GUARDIN 2/DUTGND 2
CPOL2/CPO0
CPOH2/CPO1
AGND
EN
C
3
COMP
EXTFOH 3
16-Bit
CLH DAC
16
16
16
16
X1 REG
M REG
C REG
CLH
SW 3
C
3
FF
X2 REG
*2
*2
OFFSET DAC
INTERNAL RANGE SELECT
(5uA, 20uA, 200uA, 2mA)
16
FIN
16
16
*6
SW 1
16-Bit
16 FIN DAC
X1 REG
M REG
C REG
+
FOH 3
X2 REG
FORCE
AGND
AMPLIFER
*6
SW 4
-
RSENSE
SW 6
SW 2
SW 7
16-Bit
CLL DAC
16
SW 5
16
16
16
EXTMEASIH 3
EXTMEASIL 3
X1 REG
M REG
C REG
CLL
X2 REG
OFFSET DAC
BIAS TO
CENTER
*2
+
-
SW 8
10kΩ
EXTERNAL
RSENSE
(CURRENTS
UP TO 64mA)
SW 10
*2
IRANGE
+
x5 or x10
MEASOUT
MUX & GAIN
x1/x0.2
+
-
-
SW
9
MEASOUT 3
AGND
SW 12
TEMP
SENSOR
MEASURE
CURRENT
IN AMP
16
16
16
SW 11
MEASVH 3
GUARD 3
*6
+
-
X1 REG
M REG
C REG
16-Bit
SW 16
16 CPH DAC
X2 REG
SW 13
AGND
+
*6
DUTGND
SW 14
GUARD AMP
x1
16
16
16
DUT
CPH
+
-
-
GUARDIN 3/
DUTGND 3
*6
CPL
16-Bit
CPL DAC
X1 REG
M REG
C REG
SW 15
16
MEASURE
VOLTAGE
IN AMP
X2 REG
-
-
+
+
10kΩ
COMPARATOR
AGND
DUTGND
16-Bit
OFFSET
DAC
DUTGND
TO ALL DAC
OUTPUT
AMPLIFIERS
16
TO
MEASOUT
MUX
TEMP
SENSOR
SW 15a
TMPALM
16
SERIAL
INTERFACE
10kΩ
CLAMP &
GUARD
ALARM
POWER ON
RESET
CGALM
AGND
CPOH3
/CPO3
LVDS/
SPI
CPOL3
/CPO2
SDO
SDI
RESET
SCLK
LOAD
BUSY
SYNC
Figure 2. Detailed Block Diagram
Rev. PrL | Page 3 of 45
AD5522
Preliminary Technical Data
SPECIFICATIONS
Table 1. AVDD ≥ 10V, AVSS ≤ −5V, |AVDD –AVSS| ≥ 20V and ≤ 33V, DVCC = 2.3V to 5.25V, VREF=5V, Gain (m), Offset (c) and DAC Offset
registers at default values (TJ = +25 to +90oC, max specs unless otherwise noted.)
Parameter
Min
Typ1
Max
Units
Test Conditions/Comments
FORCE VOLTAGE
All current ranges from FOH at full scale current. Includes
±±V dropped across sense resistor
FOH Output Voltage Range
AVSS+4
AVSS+3
AVDD-4
AVDD-3
V
V
External high current range at full scale current. Does not
include ±±V dropped across sense resistor
EXTFOH Output Voltage Range
Output Voltage Span
Offset Error
22.5
±00
V
-±00
-0.5
mV
µV/oC
Offset Error Tempco2
±±00
±±0
Gain Error
Gain Error Tempco2
0.5
%
ppm/oC
FSR = Fullscale Range. ±±0 V range, Gain and offset errors
calibrated out.
Linearity Error
-0.02
0.02
% FSR
Short Circuit Current Limit2
-±20
-±0
±20
±0
mA
mA
On 64mA range.
In all other ranges.
MEASURE CURRENT
Offset Error
MEASURE = (IDUT X RSENSE x GAIN)
V(Rsense)= ±±V
-±
-±
±
±
%
Offset Error Tempco2
±±0
25
µV/oC
Gain Error
%
Instrumentation Amp Gain = 5 or ±0
Offset and Gain errors calibrated out
Gain Error Tempco2
Linearity Error
ppm/oC
% FSCR
V
-0.0±
0.0±
22.5
Output Voltage Span2
% of FS Change at measure output per V change in DUT
voltage
CM Error
-0.005
0.005
%FSCR/V
Measure Current Ranges
±5
±20
±200
±2
µA
µA
µA
mA
Set using internal sense resistor
Set using internal sense resistor
Set using internal sense resistor
Set using internal sense resistor
Set using external sense resistor, internal amplifier can
drive to 64mA
Up to ±64
mA
FORCE CURRENT
Voltage Compliance, FOH
Voltage Compliance, EXTFOH
Offset Error
AVSS+4
AVSS+3
-2
AVDD-4
AVDD-3
2
V
V
%FSCR
ppm FS/
oC
Offset Error Tempco2
±±0
±25
Gain Error
Gain Error Tempco2
-0.5
0.5
%
Gain = ±
ppm/oC
Linearity Error
-0.02
0.02
% FSCR
% of FS Change at measure output per V change in DUT
voltage
CM Error
-0.005
0.005
%FSCR/V
Force Current Ranges
±5
±20
±200
±2
µA
µA
µA
mA
Set using internal sense resistor, 200kΩ
Set using internal sense resistor, 50kΩ
Set using internal sense resistor, 5kΩ
Set using internal sense resistor, 500Ω
Set using external sense resistor, internal amplifier can
drive to 64mA
Up to ±64
mA
MEASURE VOLTAGE
Measure Voltage Range
AVDD-4
±0
V
AVSS+4
-±0
V
Offset Error
Offset Error Tempco2
mV
±±0
±±0
µV/oC
% FSR
ppm/oC
% FSR
Gain Error
-0.5
0.5
Gain = ±
Gain Error Tempco2
Linearity Error
-0.0±
0.0±
Rev. PrL | Page 4 of 45
Preliminary Technical Data
AD5522
Parameter
Min
Typ1
Max
Units
Test Conditions/Comments
COMPARATOR
Comparator Span
Offset Error
Propagation delay2
VOLTAGE CLAMPS
Clamp Span
22.5
±0
V
-±0
mV
μs
±
TBD
22.5
±50
V
Positive Clamp Accuracy
Negative Clamp Accuracy
Recovery Time2
mV
mV
μs
-±50
TBD
TBD
TBD
TBD
Activation Time2
μs
CURRENT CLAMPS
Prog’d
Clamp
value
Programmed
Clamp value
+±5
% of FSC
range
Clamp Accuracy
Clamp current scales with selected range
Recovery Time2
Activation Time2
TBD
TBD
TBD
TBD
μs
μs
FOH, EXTFOH, EXTMEASIL,
EXTMEASIH, CFF
Pin Capacitance2
3
TBD
3
pF
Leakage Current
-3
-3
nA
nA/oC
On or off switch leakage
Leakage Current Tempco2
MEASVH
±0.±
3
Pin Capacitance2
TBD
3
pF
Leakage/Bias Current
Leakage Current Tempco2
SYS_SENSE
nA
nA/oC
±0.±
SYS_Sense Connected, Force Amplifier Inhibited
SYS_Force Connected, Force Amplifier Inhibited
Pin Capacitance2
3
±
TBD
±.3
3
pF
SYS_SENSE Impedance
kΩ
Leakage Current
-3
nA
nA/oC
Leakage Current Tempco2
SYS_FORCE
±0.±
Pin Capacitance2
3
TBD
80
3
pF
SYS_FORCE Impedance
60
Ω
Leakage Current
Leakage Current Tempco2
-3
nA
nA/oC
±0.±
±0.5
Includes FOH, MEASVH, SYS_SENSE, SYS_FORCE,
EXTMEASIL
COMBINED LEAKAGE at DUT
Leakage Current
Leakage Current Tempco2
-±5
±5
nA
nA/oC typ
DUTGND
Voltage Range
-500
-±
500
±
mV
μA
Leakage Current
MEASURE OUTPUT (MEASOUT)
Measure Output Voltage Span
Measure Pin output Impedance
Output leakage current
Output Capacitance2
Short Circuit Current2
MEASOUT enable time
MEASOUT disable time
MEASOUT MI to MV switching time
GUARD OUTPUT
With respect to AGND
22.5
±00
3
V
Software Programmable output range
Ω
-3
nA
pF
mA
ns
ns
ns
With SW±2 off
±5
-±0
±0
TBD
TBD
TBD
TBD
TBD
TBD
Closing SW±2
Opening SW±2
Guard Output Voltage Span
Guard Output Offset
Short Circuit Current2
Load Capacitance2
22.5
±0
V
-±0
-±0
mV
mA
nF
±0
50
Guard Output Impedance
Slew Rate2
±00
3
Ω
V/μs
CLOAD = TBD pf
Rev. PrL | Page 5 of 45
AD5522
Preliminary Technical Data
Parameter
Min
Typ1
Max
Units
Test Conditions/Comments
FORCE AMPLIFIER
Slew Rate2
0.4
±
V/us
MHz
pF
Ccomp=±00pF, Cff=220pF, Cload=200pF
Ccomp=±00pF, Cff=220pF, Cload=200pF
CCOMP = ±00pF. Larger Load cap requires larger CCOMP
FS step
Gain Bandwidth2
Max stable load Capacitance2
FV SETTLING TIME TO 0.05% OF FSVR
64mA Range2
±0,000
TBD
TBD
TBD
TBD
TBD
40
40
µs
µs
µs
µs
µs
Ccomp=±00pF, Cff=220pF, Cload=200pF
Ccomp=±00pF, Cff=220pF, Cload=200pF
Ccomp=±00pF, Cff=220pF, Cload=200pF
Ccomp=±00pF, Cff=220pF, Cload=200pF
Ccomp=±00pF, Cff=220pF, Cload=200pF
FS step
2mA range2
200µA range2
40
20µA range2
80
5µA range2
300
MI SETTLING TIME TO 0.05% OF FSCR
64mA Range2
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
µs
µs
µs
µs
µs
Ccomp=±00pF, Cff=220pF, Cload=200pF
Ccomp=±00pF, Cff=220pF, Cload=200pF
Ccomp=±00pF, Cff=220pF, Cload=200pF
Ccomp=±00pF, Cff=220pF, Cload=200pF
Ccomp=±00pF, Cff=220pF, Cload=200pF
FS step
2mA range2
200µA range2
20µA range2
5µA range2
FI SETTLING TIME TO 0.05% OF FSCR
64mA Range2
30
30
TBD
TBD
TBD
TBD
TBD
µs
µs
µs
µs
µs
Ccomp=±00pF, Cload=200pF
Ccomp=±00pF, Cload=200pF
Ccomp=±00pF, Cload=200pF
Ccomp=±00pF, Cload=200pF
Ccomp=±00pF, Cload=200pF
FS step
2mA range2
200µA range2
80
20µA range2
680
3000
5µA range2
MV SETTLING TIME TO .05% OF FSVR
64mA Range2
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
µs
µs
µs
µs
µs
Ccomp=±00pF, Cload=200pF
Ccomp=±00pF, Cload=200pF
Ccomp=±00pF, Cload=200pF
Ccomp=±00pF, Cload=200pF
Ccomp=±00pF, Cload=200pF
2mA range2
200µA range2
20µA range2
5µA range2
DAC SPECIFICATIONS
Resolution
Voltage Output Span2
Differential Nonlinearity2
±6
22.5
±
Bits
V
VREF=5V, within a range of -±6.25 to 22.5V
-±
LSB
Guaranteed monotonic by design over temperature.
COMPARATOR DAC DYNAMIC
SPECIFICATIONS
Output Voltage Settling Time2
Slew Rate2
Digital-to-Analog Glitch Energy2
Glitch Impulse Peak Amplitude2
REFERENCE INPUT
±.5
±5
µs
±V change to ±± LSB.
5
V/µs
nV-s
mV
20
VREF DC Input Impedance
VREF Input Current
±
-±0
2
MΩ
µA
V
Typically ±00 MΩ.
±0
5
Per input. Typically ±30 nA.
VREF Range
DIE TEMPERATURE SENSOR
Accuracy
±ꢀ
±.5
5
°C
Output Voltage at 25°C
Output Scale Factor
V
mV/°C
V
Output Voltage Range
INTERACTION & CROSSTALK
Crosstalk (VM)2
0
3
-0.0±
0.0±
% FSR
% FSR
mV
All channels in FIMV mode, measure the voltage for one
channel in the highest current force range, once when all
three other channels are at FI = 0mA and once when
they are at 2mA
Crosstalk (MI)2
-0.0±
0.0±
0.5
All channels in FVMI mode, measure the current for one
channel in the lowest current measure range, once when
all three other channels are at FV = -±0V and once when
they are at +±0V
Crosstalk within a channel2
All channels in FVMI mode, one channel at midscale,
measure the current for one channel in the lowest
current range, for a change in comparator or clamp DAC
Rev. PrL | Page 6 of 45
Preliminary Technical Data
AD5522
Parameter
Shorted DUT Crosstalk2
Min
Typ1
Max
Units
Test Conditions/Comments
levels for that PMU.
TBD
TBD
S/C applied to one PMU channel, measure effect on
other channels.
SPI INTERFACE LOGIC
LOGIC INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance2
CMOS LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
Tristate leakage current
Output Capacitance2
OPEN DRAIN LOGIC OUTPUTS
VOL, Output Low Voltage
Output Capacitance2
LVDS INTERFACE LOGIC
LOGIC INPUTS – Reduced Range Link
Input Voltage Range
Input Differential Threshold
External Termination Resistance
Differential Input Voltage
LOGIC OUTPUTS – Reduced Range Link
Output Offset Voltage
Output Differential Voltage
NOISE PERFORMANCE
NSD of Measure Voltage In-Amp
NSD of Measure Current In-Amp
NSD of Force Amplifier
POWER SUPPLIES
±.ꢀ/2.0
-±
V
(2.3 to 2.ꢀ)/(2.ꢀ to 5.25V) Jedec Compliant Input Levels
(2.3 to 2.ꢀ)/(2.ꢀ to 5.25V) Jedec Compliant Input Levels
0.ꢀ/0.8
V
±
µA
pF
±0
SDO, CPOX
IOL = 500 µA
DVCC – 0.4
-±
V
0.4
±
V
µA
pF
±0
BUSY
, TMPALM, CGALM
0.4
±0
V
IOL = 500 µA, CL = 50pF, RPULLUP = ±kΩ
pF
8ꢀ5
-±00
80
±5ꢀ5
±00
mV
mV
Ω
±00
±20
±00
mV
±200
400
mV
mV
TBD
TBD
TBD
nV/√Hz
nV/√Hz
nV/√Hz
@ ±kHz, measured at MEASOUT
@ ±kHz, measured at MEASOUT
@ ±kHz, measured at FOH
AVDD
±0
-5
28
-23
5.25
25
25
3
V
| AVDD –AVSS| ≤ 33V
AVSS
V
DVCC
2.3
V
AIDD
mA
mA
mA
W
Excluding Load Conditions
Excluding Load Conditions
AISS
DICC
Max Power Dissipation2
Power Supply Sensitivity2
∆Forced Voltage/∆AVDD
∆Forced Voltage/∆AVSS
∆Measured Current/∆AVDD
∆Measured Current/∆AVSS
∆Forced Current/∆AVDD
∆Forced Current/∆AVSS
∆Measured Voltage/∆AVDD
∆Measured Voltage/∆AVSS
∆Forced Voltage/∆DVCC
∆Measured Current/∆DVCC
∆Forced Voltage/∆DVCC
∆Measured Current/∆DVCC
ꢀ
From DC to ±kHz
-ꢀ5
-ꢀ5
-ꢀ5
-ꢀ5
-ꢀ5
-ꢀ5
-ꢀ5
-ꢀ5
-90
-90
-90
-90
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
± Typical specifications are at 25°C and nominal supply, ±±5.25V, unless otherwise noted.
2 Guaranteed by design and characterization, not production tested.
FV = Force Voltage, FI = Force Current, MV = Measure Voltage, MI = Measure Current
FSR = Full Scale Range, FSCR = Full Scale Current Range, FS = Full Scale.
Specifications subject to change without notice.
Rev. PrL | Page ꢀ of 45
AD5522
Preliminary Technical Data
TABLE 2. TIMING CHARACTERISTICS
AVDD ≥ 10V, AVSS ≤ −5V, |AVDD –AVSS| ≥ 20V and ≤ 33V, DVCC = 2.3V to 5.25V, VREF=5V
(TJ = +25 to +90oC, max specs unless otherwise noted.)
SPI INTERFACE (Figure 5 and Figure 6)
Parameter1, 2, 3 Limit at TMIN, TMAX
Unit
Description
t±
t2
t3
t4
t5
t6
tꢀ
t8
t9
20
8
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
µs max
ns min
ns min
ns min
ns min
SCLK Cycle Time.
SCLK High Time.
SCLK Low Time.
8
±0
±5
5
SYNC Falling Edge to SCLK Falling Edge Setup Time.
Minimum SYNC High Time.
29th SCLK Falling Edge to SYNC Rising Edge.
Data Setup Time.
5
4.5
30
±.2
20
20
±50
0
Data Hold Time.
3
SYNC Rising Edge to BUSY Falling Edge.
t±0
t±±
t±2
t±3
t±4
t±5
t±6
t±ꢀ
t±8
t±9
BUSY Pulse Width Low
th
LOAD
29 SLCK Falling EDGE to
Falling Edge
LOAD
pulse width low
BUSY rising edge to FOH Output Response time
LOAD
BUSY rising edge to
falling edge
rising edge to FOH Output Response time
±00
±0
ns max
ns min
µs max
LOAD
RESET Pulse Width Low.
300
RESET Time Indicated by BUSY Low.
Minimum SYNC High Time in Readback Mode.
SCLK Rising Edge to SDO Valid.
±00
25
ns min
ns max
ns min
4
595
Single channel write time
LVDS INTERFACE (Figure ꢀ)
Parameter1, 2, 3 Limit at TMIN, TMAX
Unit
Description
t±
t2
t3
t4
t5
t6
tꢀ
t8
±0
4
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Time.
SCLK Pulse Width High and Low Time.
SYNC to SCLK Setup Time.
Data Setup Time.
2
2
2
Data Hold Time.
2
SCLK to SYNC Hold Time.
SCLK Rising Edge to SDO Valid.
SYNC high time
TBD
TBD
± Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 2 ns (±0% to 90% of VCC) and timed from a voltage level of ±.2 V.
3 See Figure 5 and Figure 6
4 This is measured with circuit the load circuit of Figure 4
V
CC
I
200µA
OL
R
2.2kΩ
L
TO
OUTPUT
PIN
V
(min) - V
2
(max)
OL
OH
TO
OUTPUT
PIN
C
L
50pF
V
OL
50pF
C
I
L
200µA
OL
CGALM TMPALM
BUSY
Timing Diagram
Figure 3.. Load Circuit for
,
Figure 4. Load Circuit for SDO,
Rev. PrL | Page 8 of 45
Preliminary Technical Data
AD5522
t1
SCLK
1
29
t6
24
2
t2
t3
t4
t5
SYNC
SDI
t7
t8
DB0
DB28
t9
t10
BUSY
t11
t12
LOAD1
FOH1
t13
t14
t12
LOAD2
FOH2
t15
t16
RESET
BUSY
t17
1LOAD ACTIVE DURING BUSY
2LOAD ACTIVE AFTER BUSY
Figure 5. SPI Write Timing (Write word contains 29 bits)
SCLK
58
29
t
19
t
18
SYNC
DB23/
DB28
SDI
DB28
DB0
DB0
INPUT WORD SPECIFIES
NOP CONDITION
REGISTER TO BE READ
DB23/
DB28
DB0
SDO
SELECTED REGISTER DATA
CLOCKED OUT
UNDEFINED
Figure 6. SPI Read Timing (Readback word contains 24 bits and can be clocked out with a minimum of 24 clock edges)
Rev. PrL | Page 9 of 45
AD5522
Preliminary Technical Data
t8
SYNC
SYNC
t6
t1
t3
SCLK
SCLK
t4
MSB
D23/D28
LSB
D0
MSB
D28
t2
SDI
SDI
LSB
D0
t7
t5
SDO
SDO
MSB
DB23/
DB28
LSB
DB0
UNDEFINED
SELECTED REGISTER DATA CLOCK OUT
Figure ꢀ. LVDS Read and Write Timing, (Readback word contains 24 bits and can be clocked out with a minimum of 24 clock edges)
Rev. PrL | Page ±0 of 45
Preliminary Technical Data
AD5522
ABSOLUTE MAXIMUM RATINGS
Table 3. AD5522 Absolute Maximum Ratings
THERMAL RESISTANCE3
Parameter
Rating
Thermal resistance values are specified for the worst-case
conditions, i.e., specified for device soldered in circuit board for
surface mount packages.
Supply Voltage AVDD to AVSS
AVDD to AGND
34V
-0.3V to 34V
AVSS to AGND
0.3V to -34V
Table 4. Thermal Resistance (JEDEC 4 layer (1S2P) board)
VREF to AGND
-0.3 V, +ꢀV
Air Flow (LFPM)
0
200
22.3 ±ꢀ.2 ±5.± °C/W
0.3 °C/W
TBD TBD TBD °C/W
4.8 °C/W
500
Unit
DUTGND, REFGND, AGND
DVCC to DGND
AVDD +0.3V to AVSS -0.3V
- 0.3V to ꢀV
TQFP Exposed Pad Down
θJA
θJC
θJA
θJC
Digital Inputs to DGND
Analog Inputs to AGND
Storage Temperature
- 0.3V to DVCC +0.3V
AVSS - 0.3V to AVDD +0.3V
–65°C to +±25°C
TQFP Exposed Pad Up
Operating Junction Temperature +25 to +90°C
Reflow Soldering
Table 5. Thermal Resistance (JEDEC 4 layer (1S2P) board
with cooling plate4 at 45°C, natural convection at 55°C
ambient)
Peak Temperature
230°C
Time at Peak Temperature
Junction Temperature
±0s to 40s
±50°C max
Package Thermals
Unit
°C/W
°C/W
θJA
5.4
3.0
θJA
4.8
0.3
TQFP Exposed Pad Down
TQFP Exposed Pad Up
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
3 Simulated Thermal information.
4 Assumes perfect thermal contact between cooling plate and exposed
paddle
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrL | Page ±± of 45
AD5522
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVDD
CFF0
1
2
AVDD
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
CFF1
CCOMP0
EXTMEASIH0
EXTMEASIL0
FOH0
3
CCOMP1
EXTMEASIH1
4
5
EXTMEASIL1
6
FOH1
GUARD0
7
GUARD1
GUARDIN0
/DUTGND0
8
GUARDIN1
/DUTGND1
MEASVH0
9
AD5522
TOP VIEW
EXPOSED PAD ON BOTTOM
MEASVH1
AGND
AGND
10
11
12
13
14
15
16
17
18
19
20
AGND
AGND
MEASVH2
MEASVH3
(Not to Scale)
GUARDIN2
/DUTGND2
GUARDIN3
/DUTGND3
GUARD2
FOH2
GUARD3
FOH3
EXTMEASIL2
EXTMEASIL3
EXTMEASIH3
CCOMP3
EXTMEASIH2
CCOMP2
CFF2
AVDD
CFF3
AVDD
Figure 8. Pin Configuration (Exposed Pad on bottom of package)
Table 6. Pin Function Descriptions
Pin No.
Pin No.
Mnemonic
Description
Exposed Pad
The exposed pad is electrically connected to AVSS.
Bottom
Top
TQFP with exposed pad on BOTTOM: For enhanced thermal, electrical and board level
performance, the exposed paddle on the bottom of the package should be soldered to a
corresponding thermal land paddle on the PCB.
22, 39, 62,
6ꢀ, ꢀ9,
2, ±4, ±9,
42,59,
AVSS(0-4)
AVDD(0-4)
LOAD
Negative analog supply voltage
±, 20, 4±, 60, ꢀ, 2±, 40,
ꢀ4
Positive analog supply voltage
6±, 80
33
48
Active low logic input used for synchronizing updates within one device or across a group
of devices. If synchronization is not required, LOAD may be tied low and updates to DAC
channels or PMU modes will happen as they are presented to the device. See the BUSY and
LOAD FUNCTIONS section for detailed information.
34
4ꢀ
DVCC
Digital supply voltage
±0, ±±, 50,
5±, 69
±2, 30, 3±,
ꢀ0, ꢀ±
AGND
Analog ground, reference points for force and measure circuitry
30
23
24
25
26
2ꢀ
28
29
3±
5±
58
5ꢀ
56
55
54
53
52
50
DGND
Digital ground reference point.
BUSY
Open Drain active low input/output indicating the status of interface.
Clock input, active falling edge
SCLK
CPOL0/ SCLK
CPOH0/ SDI
SDI
Comparator output low in SPI mode and SCLK in LVDS interface mode
Comparator output high in SPI mode and SDI in LVDS interface mode
Serial data input
SYNC
Frame sync, active low
CPOL±/ SYNC
CPOH±/SDO
Comparator output low in SPI mode and SYNC in LVDS interface mode
Comparator output high in SPI mode and SDO in LVDS interface mode
Rev. PrL | Page ±2 of 45
Preliminary Technical Data
AD5522
32
35
36
3ꢀ
38
49
46
45
44
43
SDO
Serial data out, for readback and diagnostic purposes
CPOL2/CPO0
CPOH2/CPO±
CPOL3/CPO2
CPOH3/CPO3
MEASOUT(0-3)
Comparator output Low, comparator window in LVDS interface mode
Comparator output Low, comparator window in LVDS interface mode
Comparator output Low, comparator window in LVDS interface mode
Comparator output Low, comparator window in LVDS interface mode
66, 65, 64,
63
±5, ±6, ±ꢀ,
±8
Multiplexed DUT voltage/Current sense output/temperature sensor voltage per channel,
referenced to AGND.
68
ꢀ0
ꢀ±
ꢀ2
ꢀ5
±3
±±
±0
9
SYS_FORCE
SYS_SENSE
REFGND
VREF
External FORCE signal input, enables connection of system PMU.
External SENSE signal output, enables connection of system PMU.
Accurate analog reference input ground.
Reference Input for DAC channels, 5V for specified performance.
6
SPI/LVDS
Interface select pin. Logic low selects SPI interface compatible mode, logic high selects
LVDS interface mode. In LVDS mode the CPOH(0-3) pins default to differential interface
pins.
ꢀ6
5
CGALM
CGALM is an open drain pin providing shared Alarm information for Guard amplifier and
Clamp circuitry.
By default, this output pin is disabled. The System Control Register allows user to enable
this function and to set the open drain output as a latched output, or to configure either
the Guard or Clamp function or both flagging the alarm pin.
When this pin flags an alarm, the origins of the alarm may be determined by reading back
the Alarm Status Register. Two flags per channel in this word (one latched, one unlatched)
indicate which function caused the alarm and if the alarm is still present.
ꢀꢀ
ꢀ8
4
3
TMPALM
The function of this pin is to flag a Temperature Alarm. It is a latched active low open drain
output indicating the junction temperature has exceeded either the programmed or
default (±30degC) temperature setting.
Two flags in the Alarm Status Register (one latched, one unlatched) indicate if the
temperature has dropped below ±30degC or still above. User action is required to clear this
latched alarm flag, by writing to the “CLEAR”bit in any of the PMU registers.
RESET
Active low, level sensitive input used to reset all internal nodes on the device to their
power-on reset value.
3, ±8, 43, 58 ꢀ8, 63, 38,
23
CCOMP(0-3)
CFF (0-3)
Compensation capacitor Input per channel. See section on compensation capacitors..
2, ±9, 42, 59 ꢀ9, 62, 39,
22
External capacitor optimizing the stability performance of the force amplifier (per
channel).. See section on Compensation Capacitors
80, 2±, 40,
6±
±, 60, 4±,
20
EXTFOH(0-3)
FOH(0-3)
Per channel, Force output for high current range. Use external resistor here for current
range up to 64mA.
6, ±5, 46, 55 ꢀ5, 66, 35,
26
Per channel force output for all other ranges.
4, ±ꢀ, 44, 5ꢀ ꢀꢀ, 64, 3ꢀ,
24
EXTMEASIH(0-3) Per channel sense input (high sense) for high current range.
EXTMEASIL(0-3) Per channel sense input (Low sense) for high current range.
5, ±6, 45, 56 ꢀ6, 65, 36,
25
9, ±2, 49, 52 ꢀ2, 69, 32,
29
MEASVH(0-3)
DUTGND
Per channel DUT voltage sense input (high sense)
ꢀ3
8
DUT voltage sense input (low sense). By default, DUTGND is shared between all four PMU
channels. If user requires a DUTGND input per channel, the GUARDIN (0-3)/DUTGND(0-3)
pin may be configured to be a DUTGND input per each PMU channel.
ꢀ, ±4 , 4ꢀ, 54 ꢀ4, 6ꢀ, 34,
2ꢀ
GUARD (0-3)
Guard output drive.
8, ±3, 48, 53 ꢀ3, 68, 33,
28
This pin has dual functionality; it may be either a Guard input per channel or DUTGND per
channel.
GUARDIN(0-3)
/DUTGND(0-3)
Its function is determined via the serial interface. The power on default is GUARDIN, where
it functions as the input to the Guard Amplifier. Alternatively, it may be configured to be a
DUTGND input per channel. If selected as DUTGND via the interface, it now provides a
DUTGND per Channel function and the input to the Guard amplifier is internally connected
to MEASVH. See section on Guard Amplifier
Rev. PrL | Page ±3 of 45
AD5522
Preliminary Technical Data
EXTFOH0
AVSS
1
2
EXTFOH2
AVSS
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RESET
3
BUSY
SCLK
TMPALM
CGALM
SPI/LVDS
4
5
CPOL0/SCLK
6
CPOH0/SDI
SDI
AVDD
7
DUTGND
8
SYNC
VREF
REFGND
9
AD5522
TOP VIEW
EXPOSED PAD ON TOP
CPOL1/SYNC
DGND
10
11
12
13
14
15
16
17
18
19
20
SYS_SENSE
AGND
CPOH1/SDO
SDO
(Not to Scale)
SYS_FORCE
LOAD
DVCC
AVSS
MEASOUT0
MEASOUT1
CPOL2/CPO0
CPOH2/CPO1
CPOL3/CPO2
CPOH3/CPO3
AVSS
MEASOUT2
MEASOUT3
AVSS
EXTFOH1
EXTFOH3
Figure 9. Pin Configuration (Exposed Pad on Top of package)
Rev. PrL | Page ±4 of 45
Preliminary Technical Data
AD5522
DAC SPECIFIC TERMS
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1LSB maximum
ensures monotonicity.
Output Voltage Settling Time
The amount of time it takes for the output of a DAC to settle to
a specified level for a full-scale input change.
TERMINOLOGY
Offset Error
Offset error is a measure of the difference between actual and
ideal voltage expressed in mV.
Gain Error Gain error is the difference between full-scale error
and zero-scale error. It is expressed in %.
Gain Error = Full-Scale Error − Zero-Scale Error
Linearity Error
Relative accuracy, or endpoint linearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the full-scale range. It is measured after adjusting
for offset error and gain error and is expressed in % FSR.
CM Error
Common Mode Error is the error at the output of the amplifier
due to the common mode input voltage. It is expressed in % of
FSR/V.
Digital-to-Analog Glitch Energy
The amount of energy injected into the analog output at the
major code transition. The area of the glitch in is specified in
nV-s. It is measured by toggling the DAC register data between
0x1FFF and 0x2000.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in the DAC register code of another converter
is defined as the digital crosstalk and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the
VOUT pins. It can also be coupled along the supply and
ground lines. This noise is digital feedthrough.
Clamp Accuracy
Clamp accuracy is a measure of where the clamps begin to
function fully and limit the clamped voltage or current.
Leakage Current
Current measured at an output pin, when that function is off or
high impedance.
Pin Capacitance
Capacitance measured at a pin when that function is off or high
impedance.
Slew Rate
The rate of change of output voltage, expressed in V/μs.
Rev. PrL | Page ±5 of 45
AD5522
Preliminary Technical Data
FUNCTIONAL DESCRIPTION
comparator output available CPO (0-3) provides information
on whether the measured voltage or current is inside or outside
the set CPH and CPL window. Information of whether the
measurement was high or low is available via the serial
interfaces (Comparator Status Register).
The AD5522 is a highly integrated quad per pin parametric
measurement unit (PPMU) for use in semiconductor automatic
test equipment. It contains programmable modes to force a pin
voltage and measure the corresponding current (FVMI), force
current measure voltage (FIMV), force current measure current
(FIMI), force voltage measure voltage (FVMV) and force
nothing measure voltage (FNMV) or measure current (FNMI).
The PPMU can force or measure a voltage range of 22.5 V. It
can force or measure currents ranging up to 64mA per channel
using the internal amplifier, while the addition of an external
amplifier enables higher current ranges. On Chip are all the
DAC levels required for each PMU channel.
Table 8. Comparator Output Function using LVDS interface
CPO Output
TEST CONDITION
CPL < VDUT And IDUT < CPH
CPL > VDUT or IDUT > CPH
1
0
CLAMPS
FORCE AMPLIFIER
Current and voltage clamps are included on chip per PMU
channel. They protect the DUT in the event of an open or a
short. Internal DAC levels set the CLL and CLH (low and high)
levels and the clamps work to limit the force amplifier in the
event of a voltage or current at the DUT exceeding the set levels.
The clamps also function to protect the DUT when a transient
voltage or current spike occurs when changing to a different
operating mode or when programming the device to a different
current range.
The force amplifier drives the analog output FOH, which drives
a programmed current or voltage to the DUT (device under
test). Headroom and footroom requirements for this amplifier
is 3V on either end. An additional 1V is dropped across the
sense resistor when maximum current is flowing through it.
This amplifier is designed to drive DUT capacitances up to
10nF, with a compensation value of 100pF. Larger DUT
capacitive load will require larger compensation capacitances.
The voltage clamps are active while forcing current and the
current clamps are active while forcing voltage. By default, the
current clamps are off. Simply set them up via the status register
through the serial interface.
Local feedback ensures the amplifiers are stable when disabled.
A disabled channel reduces power consumption by
2.5mA/channel.
COMPARATORS
If a clamp level has been hit, this will be flagged via the
CGALM
Per channel, the DUT measured value is monitored by two
comparators configured as window comparators. Internal DAC
levels set the CPL and CPH (low and high) threshold values.
There are no restrictions on the voltage settings of the
comparator high and lows. CPL going higher than CPH is not a
useful operation; however, it will not cause any problems to the
device. CPOL and CPOH are continuous time comparator
outputs.
open drain output and the resulting alarm information may be
read back via the SPI or LVDS interface. CLL should never be
greater than CLH.
Table 7. Comparator Output Function
TEST CONDITION
VDUT or IDUT > CPH
VDUT or IDUT < CPH
VDUT or IDUT > CPL
VDUT or IDUT < CPL
CPH > VDUT or IDUT > CPL
CPOL CPOH
0
1
1
0
1
1
When using SPI interface, full comparator functionality is
available. When using the LVDS interface, the comparator
function is limited to one output per comparator, due to the
large pin count requirement of the LVDS interface. In this case,
Rev. PrL | Page ±6 of 45
Preliminary Technical Data
AD5522
HIGH CURRENT
BUFFER
EN
EXTFOH
CURRENT RANGE SELECTION
C
FF
Integrated thin film resistors minimize external components
and allow easy selection of current ranges from 5 µA (200kΩ),
20μA (50kΩ), 200μA (5kΩ) and 2mA (500Ω). Per channel, one
current range up to 64mA may be accommodated by
connecting an external sense resistor. For current ranges in
excess of 64mA, it is recommended an external amplifier be
used.
INTERNAL RANGE SELECT
(5uA, 20uA, 200uA, 2mA)
FIN
DAC
+
-
FOH
Rsense
EXTMEASIH
EXTMEASIL
OFFSET DAC
BIAS TO
CENTER
+
-
IRANGE
Rsense
10kΩ
+
x5 or x10
x1/x0.2
+
-
MEASOUT
-
MEASVH
DUTGND
AGND
+
-
DUT
+
For the suggested current ranges, the maximum voltage drop
across the sense resistors is 1V, however, to allow for
correction of errors, there is some over range available in the
current ranges. The full-scale voltage range that can be loaded
to the DAC is 11.5V; the forced current may be calculated as
follows:
x1
+
-
-
Figure 10. Addition of high current amplifier for wider current range(>64mA)
DEVICE UNDER TEST GROUND (DUTGND)
By default, there is one DUTGND input available for all four
PMU channels. In some applications of a PMU, it is necessary
that each channel operate from its own DUTGND level. There
VFIN
FI =
RSENSE ×Gain
GUARDIN(0-3)
is a shared pin in the form of the
/DUTGND(0-
Where:
FI = Forced Current
VFIN = Voltage of the FIN DAC, See VOUT for DAC levels.
RSENSE = Selected Sense Resistor
Gain of Current Measure Instrumentation amplifier, it may be
set (via the serial interface) to 5 or 10.
3) which may be shared as either the input to the GUARD
amplifier (GUARDIN), or as a DUTGND per channel function.
This should be configured through the serial interface on power
on as per required operation. The default connection is SW13b
and SW14b. When configured as DUTGND per channel, this
multifunction pin is no longer connected to the input of the
guard amplifier, it is instead connected to the low end of the
instrumentation amplifier (SW14a), and the input of the Guard
amplifier is not connected internally to MEASVH (SW13a).
Using the 5kΩ sense resistor and ISENSE gain of 10, the
maximum current range possible is 225μA. Similarly for the
other current ranges, there is an over range of 12.5% to allow for
correction.
DUT
MEASVH (0-3)
+
-
Also, the forced current range will only be the quoted full scale
range with an applied reference of 5V or 2.5V (with ISENSE
AMP gain = 5). The ISENSE amplifier is biased by the Offset
DAC output voltage, in such as way as to center the Measure
current output irrespective of the voltage span used.
GUARD AMP
a
b
SW 16
SW 13
AGNDx
+
-
GUARD (0-3)
x1
a
+
-
GUARDIN (0-3)/
SW 14
DUTGND (0-3)
a
b
DUTGND
MEASURE
VOLTAGE
IN AMP
When using the EXTFOHx outputs for current ranges up to
64mA, there is no switch in series with the EXTFOHx line,
ensuring minimum capacitance presented at the output of the
force amplifier. This is also an important feature if using a Pin
electronics driver to provide high current ranges.
Figure 11. Using the DUTGND per channel Feature
HIGH CURRENT RANGES
With the use of an external high current amplifier, one high
current range in excess of 64mA is possible. The high current
amplifier simply buffers the force output and provides the drive
for the required current.
Rev. PrL | Page ±ꢀ of 45
AD5522
Preliminary Technical Data
GUARD AMPLIFER
COMPENSATION CAPACITORS
A Guard amplifier allows the user to bootstrap the shield of the
cable to the voltage applied to the DUT, ensuring minimal
drops across the cable. This is particularly important for
measurements requiring a high degree of accuracy and in
leakage current testing.
Each channel requires an external compensation capacitor
(CCOMP) to ensure stability into the maximum load capacitance
while ensuring settling time is optimized. In addition, one CFF
pin is provided to further optimize stability and settling time
performance when in Force voltage mode. When changing
from Force current to force voltage mode, the switch
connecting CFF capacitor is automatically closed. While the
force amplifier is designed to drive load capacitances up to
10nF, using larger compensation capacitor values, it is possible
to drive larger load at the expense of an increase in settling
time. If a wide range of load capacitance must be driven, then
an external multiplexer connected to the CCOMP pin will allow
optimization of settling time versus stability. The series
resistance of a switch placed on CCOMP, should typically be
<50Ω.
If not required, all four Guard Amplifiers may be disabled via
the serial interface (through the System Control Register), this
decreases the power consumption by 400uA per channel.
GUARDIN(0-3)
As described in the DUTGND section, the
/DUTGND(0-3) is a shared pin. It can function either as a
guard amplifier input per channel or as a DUTGND input per
channel as required by the end application. Refer to Figure 11.
A Guard alarm event occurs when the guard output moves
more than 100mV away from the Guard input voltage for more
than 200μs. In the event this happens, this will be flagged via
Similarly, connecting the CFF node to a multiplexer externally,
would cater for a wide range of CDUT in Force Voltage mode.
The series resistance of the multiplexer used should be such
that:
the
open drain output. As the guard and clamp alarm
CGALM
functions share the same alarm output
, the alarm
CGALM
information (alarm trigger and alarm channel) is available via
the serial interface (ALARM STATUS REGISTER).
1
⎛
⎜
⎞
⎟
>100kHz
2ΠRON ×CDUT
⎝
⎠
Alternatively, the serial interfaces allow the user to setup the
Table 9. Suggested Compensation Capacitor Selection
output to flag either the clamp status or the guard
CGALM
CLOAD
CCOMP
CFF
status. By default, this open drain alarm pin is an unlatched
output, but may be set to a latched output via the serial
interface, System Control Register.
≤1nF
100pF
220pF
1nF
≤10nF
≤100nF
100pF
CLOAD/100
CLOAD/10
Rev. PrL | Page ±8 of 45
Preliminary Technical Data
AD5522
SYSTEM FORCE SENSE SWITCHES
MEASURE OUTPUT (MEASOUT)
Each channel has switches to allow connection of the force
(FOHx) and sense (MEASVHx) lines to a central PMU for
calibration purposes. There is one set of SYS_FORCE and
SYS_SENSE pins per device.
The measured DUT voltage or current (voltage representation
of DUT current) is available on MEASOUT (0-3) with respect
to AGND. The default MEASOUT range is the forced voltage
range for voltage measure and current measure (nominally
11.25V, depends on reference voltage and offset DAC) and
includes some over range to allow for offset correction. The
serial interface allows the user to select another MEASOUT
range of VREF to AGND, allowing for a smaller input range ADC
to be used. Each PMU channel MEASOUT line may be made
high impedance via the serial interface.
TEMPERATURE SENSOR
An on board temperature sensor monitors temperatures and in
the event of the temperature exceeding a factory defined value,
(130°C) or a user programmable value, the device will protect
itself by shutting down all channels and will flag an alarm
through the latched open drain
pin. Alarm status
TMPALM
When using low supply voltages, ensure that there is sufficient
headroom and footroom for the required force voltage range.
may be readback from the Alarm Status Register or the PMU
registers where latched and unlatched bits tell if an alarm has
occurred and whether the temperature has dropped below the
set alarm temperature.
The Offset DAC also directly offsets the MEASURE output
voltage level, but only when GAIN1 = 0.
Table 10. MEASOUT Output Ranges
MEASOUT Function
MV
GAIN1 = “0”VREF = 5V
GAIN1 = “1”
MEASOUT Gain = 1
MEASOUT Gain = 1/5
±VDUT (up to ±±.25V)
4.5VREF
0 to
5
MI GAIN0 = “0” CURRENT MEAS GAIN = ±0 ±VRSENSE X ±0 = up to ±±±.25V 0 to 4.5V
GAIN0 = “1” CURRENT MEAS GAIN = 5
± VRSENSE X 5 = up to ±5.625 0 to 2.25V
Rev. PrL | Page ±9 of 45
AD5522
Preliminary Technical Data
Therefore, depending on headroom available, the input to the
Force Amplifier may be unipolar positive, or bipolar, either
symmetrical or asymmetrical about DUTGND but always
within a voltage span of 22.5V.
DAC LEVELS
Each channel contains five dedicated DAC levels : one for the
force amplifier, one each for the clamp high and low levels and
one each for the comparator high and low levels.
The offset DAC offsets all DAC functions. It also centers the
current range, such that zero current always flows at midscale
code irrespective of offset DAC setting.
The architecture of a single DAC channel consists of a 16-bit
resistor-string DAC followed by an output buffer amplifier. This
resistor-string architecture guarantees DAC monotonicity. The
16-bit binary digital code loaded to the DAC register
determines at what node on the string the voltage is tapped off
before being fed to the output amplifier.
Rearranging the transfer function for the DAC output gives the
following equation to determine what Offset DAC code is
required for a given reference and output voltage range.
16
⎛
⎞
2 (VOUT − DUTGND)
3.5VREF
4.5× DACCODE
⎛
⎞
⎟
⎜
⎜
⎟
⎟
OFFSETDAC⋅CODE =
−
⎜
The transfer function for DAC outputs is:
3.5
⎝
⎠
⎝
⎠
DACCODE
OFFSETDAC ⋅CODE
⎛
⎜
⎞
⎟
⎛
⎜
⎞
⎟
VOUT = 4.5VREF
− 3.5V
+ DUTGND
REF
216
216
⎝
⎠
⎝
⎠
OFFSET AND GAIN REGISTERS
Where the voltage range must be take into account the +/-4V
headroom and footroom requirements for the amplifier and
sense resistor and must be within the range -16.25V to 22.5V
(22V range + 500mV overrange to allow for correction).
Each DAC level contains independent offset and gain control
registers that allow the user to digitally trim offset and gain.
These registers give the user the ability to calibrate out errors in
the complete signal chain, including the DAC, using the
internal m and c registers, which hold the correction factors. All
registers in the AD5522 are volatile, so need to be loaded on
power on during a calibration cycle.
OFFSET DAC
The device is capable of forcing a 22.5V (4.5 × VREF) voltage
range. Included on chip is one 16 Bit offset DAC (one for all
four channels) which allows for adjustment of the voltage range.
The digital input transfer function for each DAC can be
represented as
The useable range is -16.25V to 22.5V. Zero scale gives a full-
scale range of 0V to +22.5V, mid scale gives 11.25V, while the
most negative useful range is in a range of -16.25V to 6.25V.
Full scale loaded to the Offset DAC does not give a useful
output voltage range as the output amplifiers are limited by
available footroom. The following table shows the effect of the
Offset DAC on the other DACs in the device.
x2 = [(m + 1)/ 2n × x1] + (c – 2n – 1
)
where:
x2 = the data-word loaded to the resistor string DAC.
x1 = the 16-bit data-word written to the DAC input register.
m = code in gain register (default code = 216 – 1.)
c = code in offset register (default code = 215)
n = DAC resolution (n = 16).
The calibration engine is only engaged when data is written to
the x1 register. This has the advantage of minimizing the setup
time of the device.
Table 11. OFFSET DAC Relationship with other DACs with
VREF = 5V
Offset DAC
DAC Code
DAC Output Voltage Range
Code
0
0
0
0
0.00 V
CACHED X2 REGISTERS
32ꢀ68
65535
±±.25 V
22.50 V
Each DAC has a number of cached x2 values. These registers
store the result of an offset and gain calibration in advance of a
mode change. This enables the user to preload registers; allow
the calibration engine to calculate the appropriate x2 value and
store until ready to change modes. As the data is ready and held
in the appropriate register, this enables mode changing be as
time efficient as possible. If an update occurs to a DAC register
set that is currently part of the operating PMU mode, the DAC
32ꢀ68
32ꢀ68
32ꢀ68
0
-8.ꢀ5 V
2.50 V
32ꢀ68
65535
±3.ꢀ5 V
42±30
42±30
42±30
0
-±±.25 V
0.00 V
32ꢀ68
65535
±±.25 V
output will update immediately (depending on
LOAD
condition).
60855
60855
60855
0
-±6.25
-5.00
6.25
32ꢀ68
65535
65535
-
Footroom Limitations
Rev. PrL | Page 20 of 45
Preliminary Technical Data
AD5522
VREF
Offset and Gain registers for the FIN DAC
One buffered analog input supplies all 20 DACs with the
necessary reference voltage to generate the required DC levels.
The FIN (force amplifier input) DAC level contains
independent offset and gain control registers that allow the user
to digitally trim offset and gain. There are six sets of x1, m and c
registers, one set (x1, m and c) for the force voltage range, and
one set for each of the force current ranges (4 internal current
ranges and 1 external current range). Six x2 registers store
calculated DAC values ready to load to the DAC register on a
mode change.
REFERENCE SELECTION
The voltage applied to the VREF pin determines the output
voltage range and span applied to the force amplifier, clamp and
comparator inputs. This device can be used with a reference
input ranging from 2V to 5V, however, for most applications, a
reference input of 5V or 2.5V will be sufficient to meet all
voltage range requirements. The DAC amplifier gain is 4.5,
which gives a DAC output span of 22.5V. The DACs have offset
and gain registers which can be used to calibrate out system
errors.
OFFSET DAC
VREF
16
16
16
FIN
16-Bit
16 FIN DAC
X1 REG
M REG
C REG
X2 REG
*6
Serial I/F
In addition, the gain register can be used to reduce the DAC
output range to the desired force voltage range. The Force DAC
will retain 16 bit resolution even with a gain register setting of
quarter scale (0x4000). Therefore, from a single 5V reference, it
is possible to get a voltage span as high as 22.5V or as low as
5.625V all from one 5V reference.
Figure 12. FIN DAC Registers
Offset and Gain registers for the COMPARATOR DACs
The Comparator DAC levels contain independent offset and
gain control registers that allow the user to digitally trim offset
and gain. There are six sets of (x1, m and c) registers, one set for
the voltage mode, and one set for each of the four internal
current ranges and one set for the external current range. In this
way, x1 may also be preprogrammed, so switching different
modes, allows for efficient switching into the required compare
mode. Six x2 registers store cached calculated DAC values ready
to load to the DAC register on a mode change.
When using the offset and gain registers, the chosen output
range should take into account the system offset and gain errors
that need to be trimmed out. Therefore, the chosen output
range should be larger than the actual, required range.
When using low supply voltages, ensure that there is sufficient
headroom and footroom for the required force voltage range.
Also, note that with a supply differential of less than 18V and a
full scale current range requirement, it is necessary to reduce
the current measure in amp gain to 5 so the feedback path can
swing through the full range.
16
16
X1 REG
M REG
C REG
16
CPH
16-Bit
CPH DAC
16
X2 REG
X2 REG
*6
VREF
16
16
16
CPL
16-Bit
CPL DAC
X1 REG
M REG
C REG
16
Serial I/F
*6
Also, the forced current range will only be the quoted full scale
range with an applied reference of 5V or 2.5V (with ISENSE
AMP gain = 5).
Figure 13. Comparator Registers
Offset and Gain registers for the Clamp DACs
For other voltage/current ranges, the required reference level
can be calculated as follows:
The clamp DAC levels contain independent offset and gain
control registers that allow the user to digitally trim offset and
gain. There are just two sets of registers, one for the voltage
mode and another register set (x1, m and c) for all five current
ranges. Two x2 registers store cached calculated DAC values
ready to load to the DAC register on a PMU mode change.
1. Identify the nominal range required
2. Identify the maximum offset span and the maximum
gain required on the full output signal range.
VREF
16-Bit
CLH DAC
3. Calculate the new maximum output range including
the expected maximum offset and gain errors.
16
16
16
16
CLH
X1 REG
M REG
C REG
X2 REG
4. Choose the new required VOUTmax and VOUTmin
,
16-Bit
CLL DAC
16
16
CLL
X1 REG
M REG
C REG
16
16
X2 REG
keeping the VOUT limits centered on the nominal
values. Note that AVDD and AVSS must provide
sufficient headroom.
Serial I/F
5. Calculate the value of VREF as follows:
Figure 14. Clamp Registers
V
REF = (VOUTMAX – VOUTMIN)/4.5
Rev. PrL | Page 2± of 45
AD5522
Preliminary Technical Data
12/12.26× 65535 = 64145
Reference Selection Example
Nominal Output Range = 10V (-2V to +8V)
Offset Error = 100mV
Gain Error = 0.5%
Example 1: Gain Error = +0.5%, Offset Error = +100mV
1) Gain Error (0.5%) Calibration: 63937 × 0.995 = 63617
=> Load Code “0b1111 1000 1000 0001” to m register
REFGND = AGND = 0V
2) Offset Error (100mV) Calibration:
LSB Size = 10.25/65535 = 156 µV;
Offset Coefficient for 100mV Offset = 100/0.156 = 641 LSBs
=> Load Code “0b0111 1101 0111 1111” to c register
1) Gain Error = 0.5%
=> Maximum Positive Gain Error = +0.5%
=> Output Range incl. Gain Error
= 10 + 0.005(10)=10.05V
2) Offset Error = 100mV
SYSTEM LEVEL CALIBRATION
=> Maximum Offset Error Span = 2(100mV)=0.2V
=> Output Range including Gain Error and Offset Error =
10.05V + 0.2V = 10.25V
There are many ways to calibrate the device on power on. The
following gives an example of how to calibrate the FIN DAC of
the device without a DUT or DUT board connected.
Calibration Procedure for Force and Measure circuitry:
3) VREF Calculation
Actual Output Range = 10.25V, that is -2.125V to +8.125V
(centered);
1) Calibrate Force Voltage (2 point)
Write zero scale to the Force DAC (FIN), connect
SYS_FORCE to FOHx and SYS_SENSE to MEASVHx,
close the internal Force/Sense Switch (SW 7). Using the
System PMU, measure the error between voltage at FOHx,
MEASVHx and desired value.
V
REF = (8.125V + 2.125V)/4.5 = 2.28V
If the solution yields an inconvenient reference level, the user
can adopt one of the following approaches:
1. Use a resistor divider to divide down a convenient,
higher reference level to the required level.
Similarly, load Full scale to the Force DAC, and measure
the error between FOHx , MEASVH and the desired value.
Work out m and c values. Load these values to appropriate
m and c registers for Force DAC.
2. Select a convenient reference level above VREF and
modify the Gain and Offset registers to digitally
downsize the reference. In this way the user can use
almost any convenient reference level.
2) Calibrate Measure Voltage (2 point)
Connect SYS_FORCE to FOH, SYS_SENSE to MEASVHx
Close Internal Force/Sense switch (SW 7). Force voltage on
FOH via SYS_FORCE and measure voltage at MEASOUT.
The difference is the error between the actual forced
voltage and the voltage at MEASOUT.
3. Use a combination of these two approaches
In this case, the optimum reference to choose is a 2.5V
reference, then use the m and c registers and the OFFSET DAC
to achieve the required -2V to +8V range. The ISENSE
amplifier gain should be changed to a gain of 5. This ensures a
full scale current range of the specified values and also allows
optimization of power supplies and minimizes power
consumption within the device.
3) Calibrate Force current (2 point)
In Force current mode, write zero and fullscale to the Force
DAC. Connect SYS_FORCE to external ammeter and to
FOH pin. Measure error on zero and fullscale current and
calculate m and c values.
CALIBRATION
4) Calibrate Measure Current (2 Point)
The user can perform a system calibration by overwriting the
default values in the m and c registers for any individual DAC
channels as follows:
Write zero scale to the Force DAC in Force Current mode.
Connect SYS_FORCE to an external ammeter and to the
FOH pin. Measure the error between ammeter reading and
MEASOUT reading. Repeat with Full scale loaded to the
Force DAC.
Calculate the nominal offset and gain coefficients for the new
output range (see previous example)
5) Repeat for all four channels.
Calculate the new m and c values for each channel based on
the specified offset and gain errors
Similarly, calibrate the comparators and clamp DACs and load
the appropriate gain and offset registers. Calibrating these
DACs will require some successive approximation to find where
the comparator trips or the clamps engage.
Calibration Example
Nominal Offset Coefficient = 32768
Nominal Gain Coefficient = 10/10.25x 65535 = 63937
Rev. PrL | Page 22 of 45
Preliminary Technical Data
AD5522
CIRCUIT OPERATION
FORCE VOLTAGE, FV
Most PMU measurements are performed while in force voltage
and measure current mode, for example, when the device is
used as a device power supply, or in continuity or leakage
testing. In the force voltage mode, the voltage forced is mapped
directly to the DUT. The voltage measure amplifier completes
the loop giving negative feedback to the forcing amplifier. See
Figure 15.
Forced Voltage at DUT = VFIN
Where:
VFIN = Voltage of the FIN DAC, See VOUT for DAC levels.
EXTFOH
C
FF
INTERNAL RANGE SELECT
(5uA, 20uA, 200uA, 2mA)
FIN
DAC
+
FOH
-
Rsense
EXTMEASIH
EXTMEASIL
OFFSET DAC
BIAS TO
CENTER
+
-
IRANGE
Rsense
up to
(64mA)
10kΩ
+
x5 or x10
+
-
x1/x0.2
MEASOUT
-
MEASVH
DUTGND
AGND
+
-
DUT
+
x1
+
-
-
Figure 15. Forcing voltage, measuring current
Rev. PrL | Page 23 of 45
AD5522
Preliminary Technical Data
FORCE CURRENT, FI
In the force current mode, the voltage at FIN is now converted
to a current and applied to the DUT. The feedback path is now
the current measure amplifier, feeding back the voltage
measured across the sense resistor and MEASOUT reflects the
voltage measured across the DUT. See Figure 16.
For the suggested current ranges, the maximum voltage drop
across the sense resistors is 1V, however, to allow for
correction of errors, there is some over range available in the
current ranges. The maximum full-scale voltage range that can
be loaded to the FIN DAC is 11.5V; the forced current may be
calculated as follows:
VFIN
FI =
RSENSE ×Gain
Where:
FI = Forced Current
VFIN = Voltage of the FIN DAC, See VOUT for DAC levels.
RSENSE = Selected Sense Resistor
Gain of Current Measure Instrumentation amplifier, it may be
set (via the serial interface) to 5 or 10.
The ISENSE amplifier is biased by the Offset DAC output
voltage, in such as way as to center the Measure current output
irrespective of the voltage span used.
Using the 5kΩ sense resistor and ISENSE gain of 10, the
maximum current range possible is 225μA. Similarly for the
other current ranges, there is an over range of 12.5% to allow for
correction.
EXTFOH
C
FF
INTERNAL RANGE SELECT
(5uA, 20uA, 200uA, 2mA)
FIN
DAC
+
FOH
-
Rsense
EXTMEASIH
OFFSET DAC
BIAS TO
CENTER
+
-
IRANGE
Rsense
up to
(64mA)
10kΩ
+
x5 or x10
EXTMEASIL
x1/x0.2
+
-
-
MEASOUT
MEASVH
DUTGND
AGND
+
-
DUT
+
x1
+
-
-
Figure 16. .Forcing current, measuring voltage
Rev. PrL | Page 24 of 45
Preliminary Technical Data
SERIAL INTERFACE
The AD5522 contains two high-speed serial interfaces, an SPI
compatible, interface operating at clock frequencies up to
50MHz, and an EIA-644-compliant, LVDS interface. To
minimize both the power consumption of the device and on-
chip digital noise, the interface powers up fully only when the
AD5522
the section Power On Default). This sequence takes approx
300µs. The falling edge of initiates the reset process;
RESET
goes low for the duration, returning high when
is
BUSY
complete. While
RESET
is low, all interfaces are disabled. When
returns high, normal operation resumes and the status of
BUSY
BUSY
the
pin is ignored until it goes low again. The SDO
output will be high impedance during a power on reset or a
RESET
.
RESET
device is being written to, that is, on the falling edge of
.
SYNC
Power on reset follows the same function as
.
RESET
SPI INTERFACE
The serial interface operates over a 2.3V to 5.25V DVCC supply
range. The serial interface is controlled by four pin, as follows:
AND
FUNCTION
LOAD
BUSY
is an open drain output that indicates the status of the
AD5522 interface. When writing to any of the registers
goes low and stays low until the command completes.
BUSY
Frame synchronization input.
SYNC
BUSY
SDI Serial data input pin.
Writing to a DAC register drives the
signal low for longer
BUSY
SCLK Clocks data in and out of the device.
SDO Serial data output pin for data readback purposes.
than a simple PMU or System Control Register write. For the
DACs, the value of the internal cached (x2) data is calculated
and stored each time the user writes new data to the
There is also an
/LVDS select pin, which must be held low
SPI
corresponding x1 register. During this write and calculation, the
for SPI interface and high for LVDS interface.
output is driven low. While
is low, the user can
BUSY
BUSY
continue writing new data to the x1, m, or c registers, but no
output updates can take place.
LVDS INTERFACE
The LVDS interface uses the same input pins as the SPI
interface with the same designations. In addition, three other
pins are provided for the complementary signals needed for
differential operation, thus:
X2 values are stored and held until a PMU word is written that
calls the appropriate cached x2 register. Only then does a DAC
output update.
SYNC/
Differential frame synchronization signal.
SYNC
The DAC outputs and PMU modes are updated by taking the
input low. If
goes low while is active, the
LOAD
LOAD
LOAD
event is stored and the DAC outputs or PMU modes
goes high. A user can also hold
BUSY
SDI/
SDI
Differential serial data input.
update immediately after
BUSY
SCLK/
Differential clock input.
SCLK
the
input permanently low. In this case, the change in
LOAD
SDO/
Serial data output pin for data readback
SDO
DAC outputs or PMU modes update immediately after
goes high.
BUSY
SERIAL INTERFACE WRITE MODE
The
pin is bidirectional and has a 50 kΩ internal pullup
BUSY
resistor. Where multiple AD5522 devices may be used in one
system, the pins can be tied together. This is useful where
The AD5522 allows writing of data via the serial interface to
every register directly accessible to the serial interface, which is
all registers except the DAC registers.
BUSY
it is required that no DAC or PMU in any device is updated
until all others are ready. When each device has finished
The serial word is 29 bits long. The serial interface works with
both a continuous and a burst (gated) serial clock. Serial data
applied to SDI is clocked into the AD5522 by clock pulses
updating the x2 registers, it will release the
pin. If
BUSY
another device has not finished updating its x2 registers, it will
hold low, thus delaying the effect of going low.
applied to SCLK. The first falling edge of
starts the write
SYNC
cycle. At least 29 falling clock edges must be applied to SCLK to
clock in 29 bits of data, before is taken high again.
BUSY
As there is only one multiplier shared between four channels,
this task must be done sequentially, so the length of the
LOAD
SYNC
The input register addressed is updated on the rising edge of
BUSY
pulse will vary according to the number of channels being
updated.
. In order for another serial transfer to take place,
SYNC
SYNC
must be taken low again.
FUNCTION
RESET
Bringing the level sensitive
line low resets the contents
RESET
of all internal registers to their power-on reset state (detailed in
Rev. PrL | Page 25 of 45
AD5522
Preliminary Technical Data
Table 12.
Action
Pulse Width
BUSY
REGISTER UPDATE RATES
Pulse Width
(μs max)
BUSY
As mentioned previously the value of the X2 register is
calculated each time the user writes new data to the
corresponding X1 register. The calculation is performed by a
three stage process. The first two stages take 500ns each and the
third stage takes 250ns. When the writes to one of the X1
registers is complete the calculation process begins. If the write
operation involves the update of a single DAC channel the user
is free to write to another register provided that the write
operation doesn’t finish until the first stage calculation is
complete, i.e. 500ns after the completion of the first write
operation.
Loading data to PMU, System Control
Register or Readback
0.15
Loading x1 to any 1 PMU DAC Channel
Loading x1 to any 2 PMU DAC Channels
Loading x1 to any 3 PMU DAC Channels
Loading x1 to any 4 PMU DAC Channels
1.25
1.75
2.25
2.75
BUSY
Pulse Width = ((Number of channels +1) × 500ns) + 250ns
Calibration Engine Time
500ns
250ns
~600ns
500ns
also goes low during power-on reset and when a falling
BUSY
3rd
STAGE
1st
STAGE
2nd
STAGE
WRITE
#1
edge is detected on the
pin.
RESET
3rd
STAGE
1st
STAGE
2nd
STAGE
WRITE
#2
Calibration Engine Time
500ns
250ns
~600ns
500ns
3rd
STAGE
3rd
STAGE
1st
STAGE
2nd
STAGE
1st
STAGE
2nd
STAGE
WRITE
#1
WRITE
#3
3rd
STAGE
e.g. WRITE TO
3 FIN DAC REGISTERS
1st
STAGE
2nd
STAGE
Figure 18. Multiple Single Channel writes engaging calibration engine
3rd
1st
2nd
STAGE
STAGE
STAGE
3rd
STAGE
1st
STAGE
2nd
STAGE
WRITE
#2
Figure 17. Multiple writes to DAC x1 registers
Writing data to the System control register, PMU control
register, m or c registers do not involve the digital calibration
engine, thus speeding up configuration of the device on power
on.
Rev. PrL | Page 26 of 45
Preliminary Technical Data
AD5522
PMU Address Bits, PMU3, PMU2, PMU1, PMU0
REGISTER SELECTION
Bits PMU3 through PMU0 address each of the PMU channels
on chip. This allows individual control of each PMU channel or
any manner of combined addressing in addition to multi
channel programming. PMU bits also allow access to write
registers such as the System Control Register and the many
DAC registers, in addition to reading from all the registers.
The serial word assignment consists of 29 bits. Bits 28 through
to 22 are common to all registers, whether writing to or reading
from the device. PMU3 to PMU0 data bits address each PMU
channel (or associated DAC register). When PMU3 to PMU0
are all zeros, the System Control Register is addressed. Mode
Bits MODE0 and MODE1 address the different sets of DAC
registers and the PMU register.
Table 13. Mode Bits
B23
B22
WRITE FUNCTION
Readback Control, RD/
WR
MODE± MODE0 Action
0
0
±
±
0
±
0
±
System Control Register or PMU Register
DAC Gain (m) Register
The R/ bit set high initiates a readback sequence of PMU,
W
Alarm, Comparator, System Control Register or DAC
information as determined by address bits.
DAC Offset (c) Register
DAC Input Data Register, (x±)
Table 14. Read and Write Functions of the AD5522
B28
B27
B26
B25
B24
B23
B22
B21 to B0
SELECTED REGISTER
WR PMU3 PMU2 PMU± PMU0 MODE±
RD/
WRITE FUNCTIONS
MODE0
DATA BITS
CH3
CH2
CH±
CH0
0
0
0
0
0
0
0
DATA BITS
Write to System Control Register (Table ±6)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
±
±
±
±
0
±
±
DATA BITS
DATA BITS
RESERVED
RESERVED
±± ±±±± ±±±± ±±±± ±±±± ±±±±b NOP (No Operation)
DATA BITS other than all ±’s
DATA BITS
RESERVED
WRITE ADDRESSED DAC OR PMU REGISTER
0
0
0
0
0
0
0
0
0
0
0
0
0
-
0
0
0
±
-
0
±
±
0
-
±
0
±
0
-
Select DAC or PMU Registers.
See Table ±3
×
×
×
CHO
×
×
CH±
CH±
×
×
×
×
CH0
×
CH2
-
×
-
-
-
±
-
0
-
0
-
0
-
CH3
-
×
×
×
-
-
-
±
±
±
±
±
±
0
±
CH3
CH3
CH2
CH2
CH±
CH±
×
CH0
READ FUNCTIONS
±
±
±
±
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
±
±
0
±
0
±
All zeros
All zeros
X
Read from System Control Register
Read from Comparator Status Registers
Reserved
All zeros
Read from Alarm Status Register
READ ADDRESSED DAC or PMU REGISTER – Can only read one PMU or DAC register at one time.
±
±
±
±
0
0
0
±
0
0
±
0
0
±
0
0
±
0
0
0
PMU/.DAC REGISTER ADDRESS DAC ADDRESS SEE
×
×
×
CH0
×
×
×
CH±
×
SEE Table ±3
Table 2±
×
CH2
×
×
CH3
×
×
NOP (No Operation)
If a NOP (No Operation) command is loaded, no change is made to DAC or PMU registers. This code is useful when performing a read
back of a register within the device (via the SDO pin) where a change of DAC code or PMU function may not be required
Reserved Commands
Any bit combination that is not described in the Register address tables for the PMU, DAC and System Control Registers are Reserved
commands. These commands are unassigned commands; they are reserved for factory use. To ensure correct operation of the device, do
not used reserved commands.
Rev. PrL | Page 2ꢀ of 45
AD5522
Preliminary Technical Data
WRITE SYSTEM CONTROL REGISTER
The System Control Register is accessed when the PMU channel address PMU3-PMU0 and Mode Bits, MODE1 and MODE0 are all
zeros. It allows quick setup of different functions within the device. The System Control Register operates on a per device basis.
Table 15. System Control Register Bits
B28
B27
B26
B25
B24
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1/0
Table 16. System Control Register Functions
Bit
Bit name
Description
28
WR
RD/
WR
bit is set high, this initiates a readback sequence
When low, a write function takes place to the selected register, while if the RD/
(MSB)
of PMU, Alarm, Comparator, System Control or DAC register as determined by address bits.
2ꢀ
26
25
24
PMU3
PMU2
PMU±
PMU0
Bits PMU3 through PMU0 address each of the PMU channels in the device. If all four of this bits are set to zero, the System Control
Register is addressed.
B27
B26
B25
B24
B23
B22
MODE0
0
SELECTED REGISTER
CH3 CH2 CH±
Write to System Control Register
PMU3 PMU2 PMU± PMU0 MODE±
CH0
0
0
0
0
0
-
0
0
0
0
±
-
0
0
±
±
0
-
0
±
0
±
0
-
0
×
×
×
CHO
Select DAC or PMU Registers.
See below
×
×
CH±
CH±
×
×
×
×
CH0
×
CH2
-
×
-
-
-
CH3
-
×
×
×
±
-
0
-
0
-
0
-
-
-
-
CH3
CH3
CH2
CH2
CH±
CH±
×
±
±
±
±
±
±
0
±
CH0
23
22
MODE±
MODE0
Mode Bits, MODE0 and MODE± allow addressing of the PMU register or the DAC gain (m), offset (c ) or input register (x±). Set to
Zero to access the System Control Register.
MODE1 MODE0 Action
0
0
±
±
0
±
0
±
System Control Register or PMU Register
DAC Gain (m) Register
DAC Offset (c) Register
DAC Input Data Register, (x±)
SYSTEM CONTROL REGISTER SPECIFIC BITS
2±
20
±9
±8
±ꢀ
±6
±5
±4
CL3
Clamp Enable. Bits CL3 through CL0 enable and disable the clamp function per channel. A “0” disables, while a “±” enables. The
clamp enable function is also available in the PMU register on a per channel basis. This dual functionality allows flexible enable or
disabling of this function. When reading back information on the status of the clamp enable function, what was most recently
written to the clamp register is available in the readback word from either PMU or System Control Registers.
CL2
CL±
CL0
CPOLH3
CPOLH2
CPOLH±
CPOLH0
Comparator Output Enable. By default the comparator outputs are hi-Z on power on. A “±” in each bit position enables the
comparator output for the selected channel. The CPBIASEN (Bit ±3) must be enabled to power on the comparator functions. The
comparator enable function is also available in the PMU register on a per channel basis. This dual functionality allows flexible
enable or disabling of this function. When reading back information on the status of the comparator enable function, what was
most recently written to the comparator register is available in the readback word from either PMU or System Control Registers.
±3
CPBIASEN
Comparator Enable. By default the comparators are powered down on power on. To enable the comparator function for all
channels, write a “±” to the CPBIASEN bit. A “0” disabled the comparators and shuts them down. Comparator Output Enables bits
(CPOLHx) allow the user to switch on each comparator output individually, enabling bussing of comparator outputs.
±2
DUTGND/CH
GUARDIN(0-3)
/DUTGND(0-3) pins are shared pin functions and may be configured to enable a
DUTGND per channel enable. The
DUTGND per PMU channel or GUARD input per PMU channel. Setting this bit to “±” enables DUTGND per channel. In this mode, this
pin now functions as a DUTGND pin on a per channel basis. The guard inputs are disconnected from this pin and instead connected
directly to the MEASVH line by an internal connection. Default power on condition is GUARDIN(0-3).
±±
±0
GUARD ALM
CLAMP ALM
CGALM
CGALM
alarm pin. By default, the
Clamp and Guard Alarm Function share one open drain
pin is disabled. Bits GUARD ALM
CGALM
and CLAMP ALM allow the user to choose if they only wish to have both or either information flagged to the
enable either alarm function.
pin. Set high to
9
INT±0K
Internal Sense Short, INT±0K. Setting this bit high allows the user to connect in an internal sense short resistor of ±0kΩ between the
FOH and the MEASVH lines, (closes SW ꢀ), it also closes SW ±5, connecting another ±0 kΩ resistor between DUTGND and AGND.
Rev. PrL | Page 28 of 45
Preliminary Technical Data
AD5522
8
GUARD EN
Guard enable. The Guard Amplifier is disabled on power on; write a “±” to enable it. Disabling the guard function if not in use saves
power (typically 400μA per Channel).
ꢀ
6
GAIN±
GAIN0
MEASOUT Output Range. The MEASOUT range defaults to the voltage force span for voltage and current measurements, this is
±±±.25V, which includes some over range to allow for offset correction. The MEASOUT range may be reduced by using the GAIN0
and GAIN± data bits. This allows for use of asymmetrical supplies and also for use of a smaller input range ADC.
MEASOUT Function
GAIN1 = “0”VREF = 5V
GAIN1 = “1”
MEASOUT Gain = 1
MEASOUT Gain = 1/5
MV
±VDUT (up to ±±.25V)
4.5VREF
0 to
5
MI GAIN0 = “0” CURRENT MEAS GAIN = ±0 ±VRSENSE X ±0 = up to ±±±.25V 0 to 4.5V
GAIN0 = “1” CURRENT MEAS GAIN = 5
± VRSENSE X 5 = up to ±5.625 0 to 2.25V
TMP ENABLE Thermal Shutdown Function, TMP ENABLE, TMP±, TMP0
5
4
3
To disable the Thermal Shutdown feature, write a “0” to the TMP ENABLE bit (enabled by default). Bits TMP± and TMP0 allow the
user to program the thermal shutdown temperature of operation.
TMP±
TMP0
TMP ENABLE TMP1 TMP0 Action
0
±
±
X
X
0
X
X
0
Thermal Shutdown Disabled
Thermal Shutdown Enabled
Shutdown at Junction Temp of ±30°C
(Power On Default)
±
±
±
0
±
±
±
Shutdown at Junction Temp of ±20°C
Shutdown at Junction Temp of ±±0°C
Shutdown at Junction Temp of ±00°C
0
±
2
±
LATCHED
CGALM
as a latched or unlatched output pin. When high, this bit sets the alarm output as latched
outputs allowing it to drive a controller I/O without having to poll the line constantly. Default condition on power on is unlatched.
CGALM
Configure open drain
0
0
Unused bits. Set to 0.
0
(LSB)
Rev. PrL | Page 29 of 45
AD5522
Preliminary Technical Data
WRITE PMU REGISTER
To address PMU functions, set Mode bits MODE1, MODE0 low, this selects the PMU register as outlined in Table 13 and Table 14. The
AD5522 has very flexible addressing, in that it allows writing of data to a single PMU channel, any combination of them or all PMU
channels. This enables multi pin broadcasting to similar pins on a DUT. Bits 27 to 24 select which PMU or group of PMUs is addressed.
Table 17. PMU Register Bits
B28
WR
B27
B26
B25
B24
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5 to B0
PMU3
PMU2
PMU±
PMU0
MODE±
MODE0
CH
EN
FORCE±
FORCE0
X
C2
C±
C0
MEAS±
MEAS0
FIN
SF0
SF0
CL
CPOLH
COMPARE
V/I
CLEAR
UNUSED
DATA
BITS
RD/
Table 18. PMU Register Functions
Bit
Bit name
Description
28
WR
RD/
WR
When low, a write function takes place to the selected register, while if the RD/
bit is set high, this initiates a readback
(MSB)
sequence of PMU, Alarm, Comparator, System Control or DAC register as determined by address bits.
2ꢀ
26
25
24
PMU3
PMU2
PMU±
PMU0
Bits PMU3 through PMU0 address each of the PMU channels in the device. This allows individual control of each PMU channel
or any manner of combined addressing in addition to multi-channel programming.
B27
B26
B25
B24
B23
B22
MODE0
0
SELECTED REGISTER
CH3 CH2 CH±
Write to System Control Register
PMU3 PMU2 PMU± PMU0 MODE±
CH0
0
0
0
0
0
-
0
0
0
0
1
-
0
0
1
1
0
-
0
1
0
1
0
-
0
×
×
×
CHO
Select DAC or PMU Registers.
See below
×
×
CH1
CH1
×
×
×
×
CH0
×
CH2
-
×
-
-
-
CH3
-
×
×
×
1
-
0
-
0
-
0
-
-
-
-
CH3
CH3
CH2
CH2
CH1
CH1
×
1
1
1
1
1
1
0
1
CH0
23
22
MODE±
MODE0
Mode Bits, MODE0 and MODE± allow addressing of the PMU register or the DAC gain (m), offset (c ) or input register (x±). Set
to zero to access the PMU Register.
MODE1 MODE0 Action
0
0
±
±
0
±
0
±
System Control Register or PMU Register
DAC Gain (m) Register
DAC Offset (c) Register
DAC Input Data Register, (x±)
PMU REGISTER SPECIFIC BITS
2±
CH EN
Channel Enable, Set high to enable the selected channel, similarly, set low to disable a selected channel or group of channels.
When disabled, SW 2 is closed, SW 5 open.
20
±9
FORCE±
FORCE0
Bits FORCE± and FORCE0 address the force function for each of the PMU channels (in association with P3-P0). All
combinations of forcing and measuring (using MEAS0 and MEAS±) are available. The Hi-Z (voltage and current) modes allows
user to optimize glitch response during mode changes. While in these modes, with PMU Hi-Z, new x± codes loaded to the FIN
DAC register and the Clamp DAC register will be calibrated, stored in x2 register and loaded directly to the DAC outputs.
FORCE1 FORCE0 Action
0
0
±
±
0
±
0
±
FV & Current Clamp (if clamp enabled)
FI & Voltage Clamp (if clamp enabled)
Hi-Z FOH Voltage (pre load FIN DAC & Clamp DAC)
Hi-Z FOH Current (pre load FIN DAC & Clamp DAC)
±8
±ꢀ
±6
±5
RESERVED
0
C2
C±
C0
Bits C2 through C0 address allow selection of the required current range.
C2 C1 C0 Action
0
0
0
0
±
±
±
±
0
0
±
±
0
0
±
±
0
±
0
±
0
±
0
±
±5µA current range
±20µA current range
±200µA current range
±2mA current range
±external current range
NOP
NOP
NOP
Rev. PrL | Page 30 of 45
Preliminary Technical Data
AD5522
±4
±3
MEAS±
MEAS0
Bits MEAS± and MEAS0 allow selection of the required measure mode, allowing the measout line to be disabled, connected
to the temperature sensor or enabled for measurement or current or voltage.
MEAS1 MEAS0 Action
0
0
±
±
0
±
0
±
MEASOUT connected to I SENSE
MEASOUT connected to V SENSE
MEASOUT connected to Temperature Sensor
MEASOUT Hi-Z (SW ±2 Open)
±2
±±
±0
FIN
Bit FIN = 0 switches the input of the force amplifier to GND, while FIN = ± connects it to FIN DAC output.
SFO
SSO
Bits SF0 through SS0 address each of the different combinations of switching the system force and sense lines to the force
and sense at the DUT. Selection of which channel the system force and sense lines are connected to as per P3 to P0
addressing.
SF0 SS0 Action
0
0
±
±
0
±
0
±
SYS_FORCE and SYS_SENSE Hi-Z
SYS_FORCE Hi-Z, SYS_SENSE connected to MEASVHx
SYS_FORCE connected to FOHx, SYS_SENSE Hi-Z
SYS_FORCE connected to FOHx, SYS_SENSE connected to MEASVHx
9
8
CL
Per PMU clamp enable bit. A logic high enables the clamp function for the selected PMU. The clamp enable function is also
available in the System control register. This dual functionality allows flexible enable or disabling of this function. When
reading back information on the status of the clamp enable function on a per channel basis, what was most recently written
to the clamp register is available in the readback word from either PMU or System Control Registers.
CPOLH
Comparator output enable bit. A logic high enables the comparator output for the selected PMU, the comparator function
CPBIASEN must be enabled in the SYSTEM CONTROL REGISTER. The comparator output enable function is also available in
the System control register. This dual functionality allows flexible enable or disabling of this function.
ꢀ
6
COMPARE V/I
CLEAR
A logic high selects compare voltage function, while logic low, current function.
To clear or reset a latched alarm bit and pin (temperature, guard or clamp), load a “±” to the Clear bit position. This bit applies
to latched alarm (clamp and guard) conditions on all four PMU channels.
5
0
Unused bits. Set to 0.
4
3
2
±
0 (LSB)
Rev. PrL | Page 3± of 45
AD5522
Preliminary Technical Data
WRITE DAC REGISTER
The DAC input, gain and offset registers are addressed through a combination of PMU bits (Bits 27 through 24) and MODE bits (Bits 23
and 22). Bits A5 through A0 address each of the DAC levels on chip. D15 through D0 are the DAC data Bits when writing to these
registers. PMU address bits allow addressing to DAC across any combination of PMU channels.
Table 19. DAC Register Bits
B28
B27
B26
B25
B24
B23
B22
B21 B20 B19 B18 B17 B16 B15 to B0
A4 A3 A2 A± A0 DATA BITS D±5 (MSB to D0 (LSB)
WR PMU3 PMU2 PMU± PMU0 MODE± MODE0 A5
RD/
Table 20. DAC Register Functions
Bit
Bit name
Description
When low, a write function takes place to the selected register, while if the RD/
28 (MSB)
WR
RD/
WR
bit is set high, this initiates a
readback sequence of PMU, Alarm, Comparator, System Control or DAC register as determined by address bits.
2ꢀ
26
25
24
PMU3
PMU2
PMU±
PMU0
Bits PMU3 through PMU0 address each of the PMU and DAC channels in the device. This allows individual
control of each DAC channel or any manner of combined addressing in addition to multi-channel programming.
B27
B26
B25
B24
B23
B22
MODE0
0
SELECTED REGISTER
CH3 CH2 CH±
Write to System Control Register
PMU3 PMU2 PMU± PMU0 MODE±
CH0
0
0
0
0
0
-
0
0
0
0
1
-
0
0
1
1
0
-
0
1
0
1
0
-
0
×
×
×
CHO
Select DAC or PMU Registers.
See below
×
×
CH1
CH1
×
×
×
×
CH0
×
CH2
-
×
-
-
-
CH3
-
×
×
×
1
-
0
-
0
-
0
-
-
-
-
CH3
CH3
CH2
CH2
CH1
CH1
×
1
1
1
1
1
1
0
1
CH0
23
22
MODE±
MODE0
Mode Bits, MODE0 and MODE± allow addressing of the DAC gain (m), offset (c ) or input register (x±)
MODE1 MODE0 Action
0
0
1
1
0
1
0
1
System Control Register or PMU Register
DAC Gain (m) Register
DAC Offset (c) Register
DAC Input Data Register, (x1)
DAC REGISTER SPECIFIC BITS
2±,20,±9
A5,A4,A3
DAC Address Bits. A5 to A3 select which register set is addressed. See Table 2±
DAC Address Bits, A2 to A0 select which DAC is addressed. See Table 2±
±6 DAC Data bits. D±5 MSB.
±8,±ꢀ,±6
A2,A±,A0
±5 to 0(LSB)
D±5 (MSB) to D0(LSB)
Rev. PrL | Page 32 of 45
Preliminary Technical Data
AD5522
DAC Addressing
For the FIN and Comparator (CPH & CPL) DACs, there are sets of x1, m and c registers for each current range and for the voltage range,
but only two sets for the Clamp function (CLL and CLH).
When calibrating the device, m and c registers allow volatile storage of offset and gain coefficients. Calculation of the corresponding DAC
x2 register only occurs when x1 data is loaded (no internal calculation occurs on m or c updates).
There is one Offset DAC per all four channels in the device, it is addressed through any PMU0-3 address. The Offset DAC only has an
input register associated with it; there are no m or c registers for this DAC. When writing to this DAC, set both Mode bits high to address
the DAC input register (x1).
This address table is also used for readback of a particular DAC address.
Table 21. DAC Register Addressing
Address bits A5 to A3 (DAC ADDRESS Register)
Register Set
000
001
010
011
100
101
110
111
A2 to A0
MODE1 MODE0
(REGISTER
ADDRESS)
0
±
0
±
RESERVED
±
RESERVED
000 ±5µA I range
001 ±20µA I range
010 ±200µA I range
011 ±2mA I range
100 ±external I range
101 Voltage range
FIN
FIN
FIN
FIN
FIN
FIN
RESERVED RESERVED CPL
CPH
CPH
CPH
CPH
CPH
CPH
RESERVED RESERVED
RESERVED RESERVED
RESERVED RESERVED
RESERVED RESERVED
RESERVED RESERVED
RESERVED RESERVED
±
OFFSET DAC
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED RESERVED
RESERVED RESERVED
RESERVED RESERVED
CPL
CPL
CPL
CPL
CPL
CLL I1
CLL V2
CLH I1
CLH V2
RESERVED
RESERVED
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
110
111
± CLL I = Clamp Level Low Current register. CLH I = Clamp Level High Current Register. When forcing a voltage, current clamps are engaged, so this register set will be
loaded to the Clamp DAC.
2 CLL V = Clamp Level Low Voltage register. CLH V = Clamp Level High Voltage Register. When forcing a current, voltage clamps are engaged, so this register set will be
loaded to the Clamp DAC.
Rev. PrL | Page 33 of 45
AD5522
Preliminary Technical Data
READ REGISTERS
Readback of all the registers in the device is possible via the both SPI and LVDS interfaces. In order to readback data from a register, it is
first necessary to write a “readback” command to tell the device which register is required to readback. See Table 22 to address the
appropriate channel.
Table 22. Read Functions of the AD5522
B28
B27
B26
B25
B24
B23
B22
B21 to B0
SELECTED REGISTER
CH2 CH±
WR PMU3 PMU2 PMU± PMU0 MODE± MODE0
RD/
READ FUNCTIONS
DATA BITS
CH3
CH0
±
±
±
±
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
±
±
0
±
0
±
All zeros
All zeros
X
Read from System Control Register
Read from Comparator Status Registers
Reserved
All zeros
Read from Alarm Status Register
READ ADDRESSED PMU REGISTER – ONLY ONE PMU REGISTER CAN BE READ AT ONE TIME
±
±
±
±
0
0
0
±
0
0
±
0
0
±
0
0
±
0
0
0
0
0
0
0
0
0
0
0
All zeros
×
×
×
×
×
CH±
×
CH0
×
×
CH2
×
×
CH3
×
×
READ ADDRESSED DAC “m” Register – ONLY ONE DAC REGISTER CAN BE READ AT ONE TIME
±
±
±
±
0
0
0
±
0
0
±
0
0
±
0
0
±
0
0
0
0
0
0
0
±
±
±
±
DAC ADDRESS
SEE Table 2±
×
×
×
×
×
CH±
×
CH0
×
×
CH2
×
×
CH3
×
×
READ ADDRESSED DAC “c” Register – ONLY ONE DAC REGISTER CAN BE READ AT ONE TIME
±
±
±
±
0
0
0
±
0
0
±
0
0
±
0
0
±
0
0
0
±
±
±
±
0
0
0
0
DAC ADDRESS
SEE Table 2±
×
×
×
×
×
CH±
×
CH0
×
×
CH2
×
×
CH3
×
×
READ ADDRESSED DAC “x1” Register – ONLY ONE DAC REGISTER CAN BE READ AT ONE TIME
±
±
±
±
0
0
0
±
0
0
±
0
0
±
0
0
±
0
0
0
±
±
±
±
±
±
±
±
DAC ADDRESS
SEE Table 2±
×
×
×
×
×
CH±
×
CH0
×
×
CH2
×
×
CH3
×
×
Once the required channel has been addressed, the device will load the 24 bit Readback data into the MSB positions of the 29 Bit serial
SYNC
shift register, the five LSB bits will be filled with zeros. SCLK rising edges clock this readback data out on SDO(framed by the
signal).
A minimum of 24 clock rising edges are required to shift the readback data out of the shift register. If writing a 24-bit word to shift data
out of the device, user must ensure that the 24 bit write is effectively a NOP (No Operation) command. The last 5 bits in the shift register
will always be 00000b, these five bits will become the MSBs of the shift register when the 24 bit write is loaded. To ensure the device
receives a NOP command as outlined in Table 14, the recommended flush command is 0xFFFFFF and no change will be made to any
register within the device.
Readback data may also be shifted out by writing another 29 bit write or read command. If writing a 29-bit command, the readback data
will be MSB data available on SDO, followed by 00000b.
Rev. PrL | Page 34 of 45
Preliminary Technical Data
AD5522
READBACK OF SYSTEM CONTROL REGISTER
The readback function is a 24 bit word, mode, address and System Control Register data bits as shown in the following table.
Table 23. Readback System Control Register Data
Bit
Bit name
MODE±
MODE0
Description
23 (MSB)
22
0
0
SYSTEM CONTROL REGISTER SPECIFIC READBACK BITS
2±
20
±9
±8
CL3
CL2
CL±
CL0
Readback the status of the individual Clamp Enable bits. A “0” means the clamp is disabled, while a “±” enabled.
The clamp enable function is also available in the System Control Register. This dual functionality allows flexible
enable or disabling of this function. When reading back information on the status of the clamp enable function,
what was most recently written to the clamp register from either System Control register or PMU register will be
available in the readback word.
±ꢀ
±6
±5
±4
CPOLH3
CPOLH2
CPOLH±
CPOLH0
Readback information on the Comparator Output Enable status. A “±” signifies the function is enabled, while a
“0” disabled. A logic high indicates that the PMU comparator output is enabled, while if low, it’s disabled. The
comparator output enable function is also available in the PMU Register. This dual functionality allows flexible
enable or disabling of this function. When reading back information on the status of the comparator output
enable function, what was most recently written to the comparator register from either System Control register
or PMU register will be available in the readback word.
±3
±2
CPBIASEN
This readback bit tells the status of the Comparator Enable function. A “±” in this bit position means the
Comparator functions are enabled, while a “0” disabled.
DUTGND/CH
DUTGND per channel enable. If this bit is set at “±”, DUTGND per channel is enabled, while if “0”, individual
guard inputs are available per channel.
±±
±0
9
GUARD ALM
CLAMP ALM
INT±0K
CGALM
These bits give status on which of these alarm bits trigger the pin.
If this bit is set high, the internal ±0k resistor is connected between FOH and MEASVH, and between DUTGND
and AGND. If low, they are disconnected.
8
ꢀ
6
5
4
3
2
GUARD EN
GAIN±
Readback status of the Guard amplifies. If high, Amplifiers are enabled.
Status of the selected MEASOUT Output Range.
GAIN0
TMP ENABLE
TMP±
Information is available on the status of the setting for Thermal shutdown function. Refer to System control
write register.
TMP0
LATCHED
This bit tells of the status of the open drain outputs. When high, the open drain alarm outputs are latched
outputs, while if low, they are unlatched.
±
Unused Readback bits
Will be loaded with zeros.
0 (LSB)
Rev. PrL | Page 35 of 45
AD5522
Preliminary Technical Data
READBACK OF PMU REGISTER
The PMU readback function is a 24 bit word, mode, address and PMU data bits.
Table 24. Readback PMU Register (Only one PMU register may be read back at any one time).
Bit
Bit name
MODE±
MODE0
Description
23 (MSB)
22
0
0
PMU REGISTER SPECIFIC BITS
2±
20
±9
±8
±ꢀ
±6
±5
±4
±3
±2
±±
±0
9
CH EN
FORCE±
FORCE0
RESERVED
C2
Channel Enable, If high selected channel is enabled, otherwise disabled.
These bits tell what force and measure mode the selected channel is in.
0
These three bits tell what forced or measured current range is set for the selected channel.
C±
C0
MEAS±
MEAS0
FIN
Bits MEAS± and MEAS0 tell which measure mode is selected, voltage, current, temperature sensor or Hi-
Z.
This bit shows the status of the Force input amplifier.
SFO
The system force and sense lines may be connected to any of the four PMU channels. Reading back these
bits tell if they are switched in or not.
SSO
CL
A logic high in this readback position tells if the Per PMU clamp is enabled, while if low, the clamp is
disabled. The clamp enable function is also available in the System Control Register. This dual
functionality allows flexible enable or disabling of this function. When reading back information on the
status of the clamp enable function, what was most recently written to the clamp register from either
System Control register or PMU register will be available in the readback word.
8
ꢀ
CPOLH
A logic high indicates that the PMU comparator output is enabled, while if low, it’s disabled. The
comparator output enable function is also available in the System Control Register. This dual
functionality allows flexible enable or disabling of this function. When reading back information on the
status of the comparator output enable function, what was most recently written to the comparator
register from either System Control register or PMU register will be available in the readback word.
COMPARE V/I
A logic high selects indicates the selected channel is comparing voltage function, while logic low, current
function.
6
5
LTMPALM
TMPALM
TMPALM
TMPALM
output pin which flags the user of a temperature event
corresponds to the open drain
exceeding the default or user programmed level. The temperature alarm is a per device alarm, and latched
LTMPALM TMPALM
(
) and unlatched ( ) bits tell a temperature event occurred and if the alarm still exists (if
the junction temperature still exceeds the programmed alarm level). To reset an alarm event, the user
must write to the CLEAR bit in the PMU register.
4, 3, 2, ±, 0 (LSB)
Unused Readback bits
Will be loaded with zeros.
READBACK OF COMPARATOR STATUS REGISTER
The Comparator output status Register is a read only register giving access to the output status of each of the comparators on the chip.
Table 25 shows the format of the comparator readback word.
Table 25. Comparator Status Readback Register
Bit
Bit name
MODE±
MODE0
Description
23 (MSB)
22
0
±
COMPARATOR STATUS REGISTER SPECIFIC BITS
2±
CP0L0
Comparator output conditions per channel corresponding to the comparator output pins.
20
CP0H0
±9
CP0L±
±8
CP0H±
±ꢀ
CP0L2
±6
CP0H2
±5
CP0L3
±4
CP0H3
±3 to 0 (LSB)
Unused Readback bits
Will be loaded with zeros.
Rev. PrL | Page 36 of 45
Preliminary Technical Data
AD5522
READBACK OF ALARM STATUS REGISTER
The Alarm Status register is a READ only register that gives information on temperature, clamp and guard alarm events. In the event the
Guard and Clamp alarm functions are not used, (the alarm function may be switched off in the System Control Register). In this case, the
Temperature alarm status is also available in the contents of any of the four PMU readback registers.
Table 26. Alarm Status Readback Register
Bit
Bit name
MODE±
MODE0
Description
23 (MSB)
22
±
±
ALARM STATUS READBACK REGISTER SPECIFIC BITS
2±
20
LTMPALM
TMPALM
TMPALM
TMPALM
output pin which flags the user of a temperature event
corresponds to the open drain
exceeding the default or user programmed level. The temperature alarm is a per device alarm, and latched
LTMPALM TMPALM
(
) and unlatched ( ) bits tell a temperature event occurred and if the alarm still exists (if
the junction temperature still exceeds the programmed alarm level). To reset an alarm event, the user
must write to the CLEAR bit in the PMU register.
±9
LG0
LGx
Gx
is the per channel latched Guard Alarm bit and is an unlatched alarm bit. These bits give
CGALM
information on which channel flagged an alarm on the open drain alarm
condition still exists.
pin and if the alarm
±8
G0
±ꢀ
LG±
±6
G±
±5
LG2
±4
G2
±3
LG3
±2
G3
±±
LC0
LCx
Cx
is a per channel latched Clamp alarm bit and is the unlatched alarm bit. These bits give
CGALM
information on which channel flagged an alarm on the open drain alarm
condition still exists.
pin and if the alarm
±0
C0
9
LC±
8
C±
ꢀ
LC2
6
C2
5
LC3
4
C3
3 to 0 (LSB)
Unused Readback bits
Will be loaded with zeros.
READBACK OF DAC REGISTER
The DAC readback function is a 24 bit word, mode, address and DAC data bits.
Table 27. DAC Register Readback
Bit
Bit name
MODE±
MODE0
Description
23 (MSB)
22
0
0
DAC READBACK REGISTER SPECIFIC BITS
2± to ±6
A5, A4, A3, A2, A±
D±5 to D0
Address Bits indicating the DAC register that is read.
Contents of the addressed DAC register (x±, m or c).
±5 to 0 (LSB)
Rev. PrL | Page 3ꢀ of 45
AD5522
Preliminary Technical Data
POWER ON DEFAULT
The power on default for all DAC channels is that the contents of each m register is set to full-scale (0xFFFF) and c register to
midscale(0x8000). The contents of the DAC registers are :
Offset DAC: 0xA492, FIN DACs: 0x8000, CLL DACs: 0x0000, CLH DACs: 0xFFFF, CPL DACs: 0x0000, CPH DACs: 0xFFFF
The power on defaults of the PMU register and the System Control Register are shown below.
Table 28. Power on Default for System Control Register and PMU Register
SYSTEM CONTROL REGISTER POWER ON DEFAULT
PMU REGISTER POWER ON DEFAULT
Bit
Bit name
Description
Bit name
CH EN
Description
2± (MSB) CL3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
±
0
0
0
0
0
0
0
0
0
0
±
±
±
±
0
0
0
0
0
0
±
±
0
0
0
0
0
20
±9
±8
±ꢀ
±6
±5
±4
±3
±2
±±
±0
9
CL2
FORCE±
FORCE0
RESERVED
C2
CL±
CL0
CPOLH3
CPOLH2
CPOLH±
CPOLH0
CPBIASEN
DUTGND/CH
GUARD ALM
CLAMP ALM
INT±0K
C±
C0
MEAS±
MEAS0
FIN
SFO
SSO
CL
8
GUARD EN
GAIN±
CPOLH
COMPARE V/I
LTMPALM
TMPALM
Unused Data Bits
ꢀ
6
GAIN0
5
TMP ENABLE
TMP±
4
3
TMP0
2
LATCHED
Unused Data Bits
±
0 (LSB)
Rev. PrL | Page 38 of 45
Preliminary Technical Data
AD5522
SETTING UP THE DEVICE ON POWER ON
CHANGING MODES
On power on, default conditions are recalled from the power on
reset register ensuring each PMU and DAC channel is powered
up to a known condition. To operate the device, the user must:
There are different ways of handling a mode change:
1) Load any DAC x1 values that are required to change.
Remember that x1 registers are available per voltage and
current range (for Force Amplifier and Comparator
DACs), so you can preload these and may not need to
make changes. The calibration engine will calculate the x2
values and store them.
1) Configure the device by writing to the System Control
register to set up different functions as required.
2) Calibrate out errors and load required calibration values to
(Gain) m and (Offset) c registers, and load codes to each
DAC input register (x1). Once x1 values are loaded to the
individual DACs, the calibration engine calculates the
appropriate x2 value and stores it ready for the PMU
address to call it.
2) Now change into the new PMU mode. This will load the
new switch conditions in the PMU circuitry and load the
DAC register with the stored x2 data.
or
3) Load the required PMU channel with the required force
mode, current range etc. Loading the PMU channel
configures the switches around the Force Amplifier,
Measure function, clamps and comparators and also acts as
a load signal for the DACs, loading the DAC register with
the appropriate stored x2 value.
1) Use the Hi-Z V or Hi-Z I mode in the PMU register, this
makes the amplifier high impedance.
2) Now load any DAC x1 values that need to be loaded.
Remember that x1 registers are available per voltage and
current range, so you can preload these and may not need
to make changes.
4) As the voltage and current ranges have individual DAC
registers associated with them, each PMU register mode of
operation calls a particular x2 register. Hence, only updates
(changes to x1 register) to DACs associated with the
selected mode of operation are reflected to the output of
the PMU. If there is a change to the x1 value associated
with a different PMU mode of operation, then this x1 value
and it’s m and c coefficients are used to calculate a
3) When the Hi-Z (V or I) modes are used, the relevant DAC
outputs are automatically updated (FIN, CLL, CLH DACs).
For example, when selecting Hi-Z V (Voltage), the FIN
Voltage x2 result is loaded, offset and gain corrected,
cached and loaded to the FIN DAC. When forcing a
voltage, current clamps are engaged, so the CLL I (Current)
register can be loaded, gain and offset corrected and loaded
to the DAC register. Similarly, for the CLH I register.
corresponding x2 value which is stored in the correct x2
register, but it does not get loaded to the DAC.
4) Now change into the new PMU mode (FI/FV). This will
load the new switch conditions in the PMU circuitry. As
the DAC outputs are already loaded, transients when
changing current or voltage mode will be minimized.
Rev. PrL | Page 39 of 45
AD5522
Preliminary Technical Data
REQUIRED EXTERNAL COMPONENTS
The minimum required external components are shown in the
block diagram below. Decoupling will be very dependent on the
type of supplies used, other decoupling on the board and the
noise in the system. It is possible more or less decoupling may
be required as a result.
AV
DV
AV
SS
CC
DD
REF
10µF
10µF
10µF
0.1µF
0.1µF
0.1µF
0.1µF
AV
SS
AV
VREF
C
DV
DD
COMP(0-3)
CC
EXTFOH0
EXTFOH3
C
FF3
C
FF0
FOH3
FOH0
MEASVH3
MEASVH0
EXTMEASIH3
EXTMEASIH0
EXTMEASIL0
up to
64mA
up to
64mA
EXTMEASIL3
DUT
DUT
EXTFOH1
EXTFOH2
C
C
FF1
FF2
FOH2
FOH1
MEASVH2
MEASVH1
EXTMEASIH2
EXTMEASIL2
EXTMEASIH1
EXTMEASIL1
up to
64mA
up to
64mA
DUTGND
DUT
DUT
Figure 19. External components required for use with this PMU device.
Rev. PrL | Page 40 of 45
Preliminary Technical Data
AD5522
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful
consideration of the power supply and ground return layout
helps to ensure the rated performance. The printed circuit
board on which the AD5522 is mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5522 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
For supplies with multiple pins (AVSS, AVDD, VCC), it is
recommended to tie these pins together and to decouple each
supply once.
The AD5522 should have ample supply decoupling of 10 µF in
parallel with 0.1 µF on each supply located as close to the
package as possible, ideally right up against the device. The
10µF capacitors are the tantalum bead type. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching.
Digital lines running under the device should be avoided,
because these couple noise onto the device. The analog ground
plane should be allowed to run under the AD5522 to avoid
noise coupling (only with the package with paddle up).. The
power supply lines of the AD5522 should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching digital
signals should be shielded with digital ground to avoid
radiating noise to other parts of the board, and should never be
run near the reference inputs. It is essential to minimize noise
on all VREF lines. Avoid crossover of digital and analog signals.
Traces on opposite sides of the board should run at right angles
to each other. This reduces the effects of feedthrough through
the board. As is the case for all thin packages, care must be
taken to avoid flexing the package and to avoid a point load on
the surface of this package during the assembly process.
Also note that the exposed paddle of the AD5522 is connected
to the negative supply AVSS.
Rev. PrL | Page 4± of 45
AD5522
Preliminary Technical Data
.
TYPICAL APPLICATION FOR THE AD5522
Figure 20 shows the AD5522 as used in an ATE system. This
device can used as a per pin parametric unit in order to speed
up the rate at which testing can be done.
The central PMU shown in the block diagram is usually a
highly accurate PMU, and is shared among a number of pins in
the tester. In general, many discrete levels are required in an
ATE system for the pin drivers, comparators, clamps, and active
loads. DAC devices, such as the AD5379, offer a highly
integrated solution for a number of these levels. The AD5379 is
a dense 40-channel DAC designed with high channel
requirements, such as ATE
Driven Shield
DAC
Guard Amp
Central PMU
ADC
AD5522
DAC
VCH
DAC
PPMU
ADC
Vterm
DAC
Timing Data
Memory
VH
DUT
DAC
Relays
50 Coax
Ω
Timing
Generator
DLL,Logic
Formatter
De-Skew
Driver
DAC
VL
VCL
DAC
Guard Amp
DAC
GND Sense
VTH
VTL
Compare
Memory
Formatter
De-Skew
Comp
DAC
ADC
Device Power supply
DAC
Active Load
IOL
DAC
VCOM
DAC
IOH
DAC
Figure 20. Typical Applications Circuit using the AD5522 as a per pin parametric unit.
Rev. PrL | Page 42 of 45
Preliminary Technical Data
OUTLINE DIMENSIONS
AD5522
14.20
14.00 SQ
13.80
12.20
1.20
MAX
12.00 SQ
11.80
0.75
0.60
0.45
61
80
80
61
1
60
1
60
PIN 1
EXPOSED
PAD
9.50
BSC SQ
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
(PINS UP)
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
20
41
41
20
40
40
21
21
3.5°
0°
VIEW A
0.15
0.05
0.50 BSC
LEAD PITCH
0.27
0.22
0.17
SEATING
PLANE
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD
Figure 21. 80 lead TQFP/EP with exposed pad on bottom
14.20
14.00 SQ
12.20
13.80
1.20
MAX
12.00 SQ
11.80
0.75
0.60
0.45
61
80
80
61
1
60
1
60
PIN 1
EXPOSED
PAD
9.50
BSC
BOTTOM VIEW
(PINS UP)
0° MIN
TOP VIEW
(PINS DOWN)
1.05
1.00
0.95
0.20
0.09
7°
20
41
41
20
21
40
40
21
3.5°
0°
VIEW A
6.50
BSC
0.15
0.05
0.50 BSC
LEAD PITCH
0.27
0.22
0.17
SEATING
PLANE
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HU
Figure 22. 80 lead TQFP/EP with exposed pad on top
Rev. PrL | Page 43 of 45
AD5522
Preliminary Technical Data
ORDERING GUIDE
Model
Function
Package Description1
Package
Options
AD5522JSVDZ2
Quad PMU with 4 internal current ranges, full
comparator function, ± external current range, SPI and
LVDS serial interfaces.
80 Lead TQFP with exposed pad on bottom
80 Lead TQFP with exposed pad on top
SV-80
SV-80
CP-64
AD5522JSVUZError! Quad PMU with 4 internal current ranges, full
Bookmark not defined.
comparator function, ± external current range, SPI and
LVDS serial interfaces.
AD5523JCPZError!
Quad PMU, 4 internal current ranges, window
comparator function, SPI interface.
64 Lead LFCSP with exposed pad on bottom
9mm x 9mm
Bookmark not defined.,3
± Exposed pad is tied to AVSS.
2 Lead Free.
3 Reduced functionality. Contact factory for AD5523 datasheet and more details..
Rev. PrL | Page 44 of 45
Preliminary Technical Data
NOTES
AD5522
©
2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A.
PR06197-0-9/06(PrL)
Rev. PrL | Page 45 of 45
相关型号：
AD5530BRUZ-REEL
SERIAL INPUT LOADING, 20us SETTLING TIME, 12-BIT DAC, PDSO16, LEAD FREE, MO-153AB, TSSOP-16
ADI
©2020 ICPDF网 联系我们和版权申明