AD5453WBCPZ-RL [ADI]
8-/10-/12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface; 8位/ 10位/ 12位/ 14位，高带宽乘法数模转换器，串行接口
| 型号： | AD5453WBCPZ-RL |
| 厂家： | 
ADI |
| 描述： | 8-/10-/12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface |
| 文件： | 总28页 (文件大小：725K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-/10-/12-/14-Bit High Bandwidth
Multiplying DACs with Serial Interface
Data Sheet
AD5450/AD5451/AD5452/AD5453
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
REF
12 MHz multiplying bandwidth
INL of 0.25 LSB at 8-bit
DD
R
FB
8-lead TSOT and MSOP packages
2.5 V to 5.5 V supply operation
Pin-compatible 8-/10-/12-/14-bit current output DACs
10 V reference input
R
AD5450/
AD5451/
AD5452/
AD5453
8-/10-/12-/14-BIT REF
R-2R DAC
I
1
OUT
50 MHz serial interface
DAC REGISTER
INPUT LATCH
2.7 MSPS update rate
Extended temperature range: –40°C to +125°C
4-quadrant multiplication
POWER-ON
RESET
Power-on reset with brownout detect
<0.4 µA typical current consumption
Guaranteed monotonic
SYNC
SCLK
SDIN
CONTROL LOGIC
AND INPUT SHIFT
REGISTER
Qualified for automotive applications
GND
APPLICATIONS
Figure 1.
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
GENERAL DESCRIPTION
The AD5450/AD5451/AD5452/AD54531 are CMOS 8-/10-/12-/
14-bit current output digital-to-analog converters, respectively.
These devices operate from a 2.5 V to 5.5 V power supply,
making them suited to several applications, including battery-
powered applications.
The applied external reference input voltage (VREF) determines
the full-scale output current. These parts can handle 10 V
inputs on the reference, despite operating from a single-supply
power supply of 2.5 V to 5.5 V. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage
precision amplifier.
As a result of manufacture on a CMOS submicron process,
these DACs offer excellent 4-quadrant multiplication
characteristics of up to 12 MHz.
The AD5450/AD5451/AD5452/AD5453 DACs are available in
small 8-lead TSOT, and the AD5452/AD5453 are also available
in MSOP packages. The AD5453 also comes in 8-lead LFCSP.
These DACs use a double-buffered, 3-wire serial interface that
is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP
interface standards. Upon power-up, the internal shift register
and latches are filled with 0s, and the DAC output is at zero scale.
The EV-AD5443/46/53SDZ evaluation board is available for
evaluating DAC performance. For more information, see the UG-
327 evaluation board user guide.
1 U.S. Patent Number 5,689,257.
Rev. G
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5450/AD5451/AD5452/AD5453
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
DAC Section................................................................................ 16
Circuit Operation....................................................................... 16
Single-Supply Applications ....................................................... 18
Adding Gain................................................................................ 18
Divider or Programmable Gain Element................................ 19
Reference Selection .................................................................... 19
Amplifier Selection .................................................................... 19
Serial Interface............................................................................ 21
Microprocessor Interfacing....................................................... 22
PCB Layout and Power Supply Decoupling ........................... 24
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 27
Automotive Products................................................................. 27
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 15
General Description....................................................................... 16
REVISION HISTORY
1/10—Rev. B to Rev. C
6/13—Rev. F to Rev. G
Changes to DAC Control Bits C1, C0.......................................... 21
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide.......................................................... 28
Change to General Description Section........................................ 1
Change to Figure 56 and Figure 57 .............................................. 22
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide .......................................................... 27
3/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Features ..........................................................................1
Changes to General Description .....................................................1
Changes to Specifications.................................................................4
Changes to Figure 27 and Figure 28............................................. 11
Change to Table 9 ........................................................................... 20
Changes to Table 12 ....................................................................... 26
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide.......................................................... 28
4/12—Rev. E to Rev. F
Changes to General Description Section ...................................... 1
Deleted Evaluation Board for the DAC Section, Power Supplies
for the Evaluation Board Section, and Figure 64;
Renumbered Sequentially.............................................................. 25
Deleted Figure 65 and Figure 66................................................... 26
Deleted Figure 67............................................................................ 27
Changes to Ordering Guide .......................................................... 27
3/11—Rev. D to Rev. E
7/05—Rev. 0 to Rev. A
Changes to
Function Section ............................................ 21
SYNC
Added AD5453 ...................................................................Universal
Changes to Specifications.................................................................4
Change to Figure 21 ....................................................................... 10
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide.......................................................... 28
Added Figure 54 (Renumbered Sequentially) ............................ 21
Added Figure 55 and Table 11 ..................................................... 22
2/11—Rev. C to Rev. D
Added 8-Lead LFCSP.........................................................Universal
Changes to Features Section............................................................ 1
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide .......................................................... 28
Added Automotive Products Section .......................................... 28
1/05—Revision 0: Initial Version
Rev. G | Page 2 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise
noted. DC performance measured with OP177 and ac performance measured with AD8038, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions
STATIC PERFORMANCE
AD5450
Resolution
8
Bits
LSB
LSB
LSB
LSB
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error
Gain Error
0.25
0.5
0.5
0.25
Guaranteed monotonic
AD5451
Resolution
10
0.25
0.5
0.5
0.25
Bits
LSB
LSB
LSB
LSB
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error
Gain Error
Guaranteed monotonic
Guaranteed monotonic
AD5452
Resolution
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error
Gain Error
12
0.5
1
1
0.5
Bits
LSB
LSB
LSB
LSB
AD5453
Resolution
14
Bits
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error
Gain Error
2
LSB
LSB
LSB
LSB
ppm FSR/°C
nA
−1/+2
4
2.5
Guaranteed monotonic
Gain Error Temperature Coefficient1
2
Output Leakage Current
1
Data = 0x0000, TA = 25°C, IOUT1
10
nA
Data = 0x0000, TA = −40°C to +125°C, IOUT1
REFERENCE INPUT1
Reference Input Range
VREF Input Resistance
RFB Feedback Resistance
Input Capacitance
10
9
9
V
kΩ
kΩ
7
7
11
11
Input resistance, TC = −50 ppm/°C
Input resistance, TC = −50 ppm/°C
Zero-Scale Code
Full-Scale Code
18
18
22
22
pF
pF
DIGITAL INPUTS/OUTPUTS1
Input High Voltage, VIH
2.0
1.7
V
V
VDD = 3.6 V to 5 V
VDD = 2.5 V to 3.6 V
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
Input Leakage Current, IIL
Input Capacitance
0.8
0.7
V
V
V
V
V
V
nA
nA
pF
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
VDD − 1
VDD − 0.5
VDD = 4.5 V to 5 V, ISOURCE = 200 µA
VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA
VDD = 4.5 V to 5 V, ISINK = 200 µA
VDD = 2.5 V to 3.6 V, ISINK = 200 µA
TA = 25°C
0.4
0.4
1
10
10
TA = −40°C to +125°C
Rev. G | Page 3 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions
DYNAMIC PERFORMANCE1
Reference-Multiplying BW
Multiplying Feedthrough Error
12
MHz
VREF
VREF
=
=
3.5 V, DAC loaded with all 1s
3.5 V, DAC loaded with all 0s
72
64
44
dB
dB
dB
100 kHz
1 MHz
10 MHz
Output Voltage Settling Time
VREF = 10 V, RLOAD = 100 Ω; DAC latch alternately
loaded with 0s and 1s
Measured to 1 mV of FS
Measured to 4 mV of FS
Measured to 16 mV of FS
Digital Delay
10% to 90% Settling Time
Digital-to-Analog Glitch Impulse
Output Capacitance
100
24
16
20
10
2
110
40
33
40
30
ns
ns
ns
ns
ns
nV-s
Interface delay time
Rise and fall times, VREF = 10 V, RLOAD = 100 Ω
1 LSB change around major carry, VREF = 0 V
IOUT
1
13
28
18
5
pF
pF
pF
pF
DAC latches loaded with all 0s
DAC latches loaded with all 1s
DAC latches loaded with all 0s
DAC latches loaded with all 1s
IOUT
2
Digital Feedthrough
0.5
nV-s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
VREF = 3.5 V p-p, all 1s loaded, f = 1 kHz
Clock = 1 MHz, VREF = 3.5 V
Analog THD
Digital THD
83
dB
50 kHz fOUT
20 kHz fOUT
Output Noise Spectral Density
SFDR Performance (Wide Band)
50 kHz fOUT
71
77
25
dB
dB
nV/√Hz
@ 1 kHz
Clock = 1 MHz, VREF = 3.5 V
78
74
dB
dB
20 kHz fOUT
SFDR Performance (Narrow Band)
50 kHz fOUT
20 kHz fOUT
Intermodulation Distortion
POWER REQUIREMENTS
Power Supply Range
IDD
Clock = 1 MHz, VREF = 3.5 V
87
85
79
dB
dB
dB
f1 = 20 kHz, f2 = 25 kHz, clock = 1 MHz, VREF = 3.5 V
2.5
5.5
10
0.6
0.001
V
0.4
µA
µA
%/%
TA = −40°C to +125°C, logic inputs = 0 V or VDD
TA = 25°C, logic inputs = 0 V or VDD
∆VDD = 5%
Power Supply Sensitivity1
1 Guaranteed by design and characterization, not subject to production test.
Rev. G | Page 4 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
REF = 10 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
V
Table 2.
Parameter1
VDD = 2.5 V to 5.5 V
Unit
Description
fSCLK
t1
t2
t3
50
20
8
8
8
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK active edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK active edge
Minimum SYNC high time
t4
t5
t6
t7
5
4.5
5
t8
30
2.7
Update Rate
Consists of cycle time, SYNC high time, data setup, and
output voltage settling time
1 Guaranteed by design and characterization, not subject to production test.
t1
SCLK
t2
t3
t8
t7
t4
SYNC
t6
t5
DIN
DB15
DB0
Figure 2. Timing Diagram
Rev. G | Page 5 of 28
AD5450/AD5451/AD5452/AD5453
ABSOLUTE MAXIMUM RATINGS
Data Sheet
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
VDD to GND
VREF, RFB to GND
IOUT1 to GND
Input Current to Any Pin Except Supplies
Logic Inputs and Output1
−0.3 V to +7 V
−12 V to +12 V
−0.3 V to +7 V
10 mA
−0.3 V to VDD + 0.3 V
−40°C to +125°C
ESD CAUTION
Operating Temperature Range, Extended
(Y Version)
Storage Temperature Range
Junction Temperature
−65°C to +150°C
150°C
θJA Thermal Impedance
8-Lead MSOP
8-Lead TSOT
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (<20 sec)
206°C/W
211°C/W
300°C
235°C
1 Overvoltages at SCLK,
, and SDIN are clamped by internal diodes.
SYNC
Rev. G | Page 6 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
I
1
1
2
3
4
8
7
6
5
R
FB
R
1
2
3
4
8
7
6
5
I
1
OUT
FB
OUT
AD5450/
AD5451/
AD5452/
AD5453
AD5453
V
GND
REF
GND
V
V
REF
DD
TOP VIEW
(Not to Scale)
V
SCLK
SDIN
DD
SCLK
SDIN
SYNC
SYNC
Figure 3. 8-Lead TSOT Pin Configuration
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND.
I
1
1
2
3
4
8
7
6
5
R
FB
OUT
GND
V
V
REF
DD
AD5452/
AD5453
Figure 5. 8-Lead LFCSP Pin Configuration
SCLK
SDIN
SYNC
Figure 4. 8-Lead MSOP Pin Configuration
Table 4. Pin Function Descriptions
Pin No1
TSOT MSOP LFCSP Mnemonic Description
1
8
8
RFB
DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external
amplifier output.
2
3
4
7
6
5
7
6
5
VREF
VDD
SYNC
DAC Reference Voltage Input.
Positive Power Supply Input. These parts can operate from a supply of 2.5 V to 5.5 V.
Active Low Control Input. This is the frame synchronization signal for the input data. Data is
loaded to the shift register upon the active edge of the following clocks.
5
6
4
3
4
3
SDIN
SCLK
GND
Serial Data Input. Data is clocked into the 16-bit input register upon the active edge of the serial
clock input. By default, in power-up mode data is clocked into the shift register upon the falling
edge of SCLK. The control bits allow the user to change the active edge to a rising edge.
Serial Clock Input. By default, data is clocked into the input shift register upon the falling edge
of the serial clock input. Alternatively, by means of the serial control bits, the device can be
configured such that data is clocked into the shift register upon the rising edge of SCLK.
7
2
2
Ground Pin.
8
1
1
IOUT
1
DAC Current Output.
N/A
N/A
EPAD
EPAD
Exposed pad must be connected to ground.
1 N/A = not applicable.
Rev. G | Page 7 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.25
2.0
1.6
T
= 25°C
T = 25°C
A
A
V
= 10V
V
V
= 10V
0.20
0.15
0.10
0.05
0
REF
= 5V
REF
= 5V
DD
V
DD
1.2
0.8
0.4
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.4
–0.8
–1.2
–1.6
–2.0
0
32
64
96
128
160
192
224
256
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
CODE
Figure 6. INL vs. Code (8-Bit DAC)
Figure 9. INL vs. Code (14-Bit DAC)
0.25
0.20
0.15
0.10
0.05
0
0.5
0.4
T
V
V
= 25°C
T = 25°C
A
A
= 10V
V
V
= 10V
REF
= 5V
REF
= 5V
DD
DD
0.3
0.2
0.1
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.1
–0.2
–0.3
–0.4
–0.5
0
128
256
384
512
640
768
896
1024
0
32
64
96
128
160
192
224
256
CODE
CODE
Figure 7. INL vs. Code (10-Bit DAC)
Figure 10. DNL vs. Code (8-Bit DAC)
0.5
0.4
0.5
0.4
T
V
V
= 25°C
T = 25°C
A
A
= 10V
V
V
= 10V
REF
= 5V
REF
= 5V
DD
DD
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0
512
1024
1536
2048
2560
3072
2584
4096
0
128
256
384
512
640
768
896
1024
CODE
CODE
Figure 8. INL vs. Code (12-Bit DAC)
Figure 11. DNL vs. Code (10-Bit DAC)
Rev. G | Page 8 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
2.0
1.5
1.0
T
V
V
= 25°C
A
T
= 25°C
A
= 10V
0.8
0.6
REF
= 5V
V
= 5V
DD
AD5452
DD
1.0
0.4
MAX DNL
MIN DNL
0.5
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
0
512
1024
1536
2048
2560
3072
2584
4096
2
3
4
5
6
7
8
9
10
REFERENCE VOLTAGE (V)
CODE
Figure 12. DNL vs. Code (12-Bit DAC)
Figure 15. DNL vs. Reference Voltage
2.0
1.6
0.5
T
V
V
= 25°C
REF
T
V
V
= 25°C
A
A
= 10V
= 10V
0.4
0.3
REF
= 5V
= 5V
DD
DD
AD5450
1.2
0.8
0.2
0.4
0.1
0
0
–0.4
–0.8
–1.2
–1.6
–2.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
0
32
64
96
128
160
192
224
256
CODE
Figure 13. DNL vs. Code (14-Bit DAC)
Figure 16. TUE vs. Code (8-Bit DAC)
1.00
0.75
0.50
0.25
0
0.25
0.20
0.15
0.10
0.05
0
T
V
V
= 25°C
A
T
= 25°C
A
= 10V
REF
= 5V
V
= 5V
DD
AD5452
DD
AD5451
MAX INL
–0.05
–0.10
–0.15
–0.20
–0.25
MIN INL
–0.25
–0.50
–0.75
–1.00
2
3
4
5
6
7
8
9
10
0
128
256
384
512
640
768
896
1024
REFERENCE VOLTAGE (V)
CODE
Figure 14. INL vs. Reference Voltage
Figure 17. TUE vs. Code (10-Bit DAC)
Rev. G | Page 9 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
1.0
0.3
0.2
T
V
V
= 25°C
A
= 10V
0.8
0.6
REF
= 5V
DD
0.4
0.1
V
= 3V
= 5V
DD
0.2
V
0
0
DD
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.2
–0.3
0
512
1024
1536
2048
2560
3072
2584
4096
–60 –40 –20
0
20
40
60
80
100 120 140
CODE
TEMPERATURE (°C)
Figure 18. TUE vs. Code (12-Bit DAC)
Figure 21. Gain Error (LSB) vs. Temperature
2.0
1.6
2.0
1.5
T
V
V
= 25°C
T
V
= 25°C
DD
A
A
= 10V
= 5V
REF
= 5V
AD5452
DD
1.2
1.0
0.8
0.5
0.4
0
0
–0.4
–0.8
–1.2
–1.6
–2.0
–0.5
–1.0
–1.5
–2.0
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
2
3
4
5
6
7
8
9
10
REFERENCE VOLTAGE (V)
Figure 19. TUE vs. Code (14-Bit DAC)
Figure 22. Gain Error (LSB) vs. Reference Voltage
2.0
1.5
1.0
0.5
0
2.0
T
= 25°C
= 5V
A
V
I
1 V = 5V
DD
DD
AD5452
OUT
1.6
1.2
0.8
0.4
0
I
1 V = 3V
DD
OUT
MAX TUE
MIN TUE
–0.5
–1.0
–1.5
–2.0
2
3
4
5
6
7
8
9
10
–40
–20
0
20
40
60
80
100
120
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
Figure 20. TUE vs. Reference Voltage
Figure 23. IOUT1 Leakage Current vs. Temperature
Rev. G | Page 10 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.5
T
= 25°C
A
T
= 25°C
A
V
IH
V
IL
2.0
1.5
1.0
0.5
0
V
= 5V
DD
V
= 3V
DD
0
1
2
3
4
5
2.5
3.0
3.5
4.0
VOLTAGE (V)
4.5
5.0
5.5
INPUT VOLTAGE (V)
Figure 24. Supply Current vs. Logic Input Voltage
Figure 27. Threshold Voltage vs. Supply Voltage
10
0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
T
= 25°C
A
ALL 1s
ALL 0s
LOADING
ZS TO FS
ALL ON
DB13
–10
–20
–30
–40
–50
–60
–70
–80
DB12
DB11
DB10
V
DD
= 5V
DB9
DB8
DB7
DB6
DB5
DB4
DB3
V
= 3V
DD
V
V
C
= 5V
DD
= ±3.5V
REF
DB2
= 1.8pF
COMP
AD8038 AMPLIFIER
10k
100k
1M
10M 100M
–40
–20
0
20
40
60
80
100
120
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 25. Supply Current vs. Temperature
Figure 28. Reference Multiplying Bandwidth vs. Frequency and Code
0.6
0.4
6
5
4
3
2
1
0
T
= 25°C
A
AD5452
LOADING 010101010101
0.2
0
–0.2
–0.4
–0.6
V
= 5V
DD
T
V
= 25°C
= 5V
–0.8
–1.0
–1.2
A
DD
V
= ±3.5V
REF
C
= 1.8pF
COMP
AD8038 AMPLIFIER
V
= 3V
DD
1
10
100
1k
10k
100k
1M
10M
10k 100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 26. Supply Current vs. Update Rate
Figure 29. Reference Multiplying Bandwidth—All 1s Loaded
Rev. G | Page 11 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
3
10
0
T
V
= 25°C
DD
T
V
= 25°C
= 5V
A
A
= 3V
DD
AD8038 AMPLIFIER
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–3
–6
–9
FULL SCALE
ZERO SCALE
V
V
V
V
V
= ±2V, AD8038 C
= ±2V, AD8038 C
= ±15V, AD8038 C
= ±15V, AD8038 C
= ±15V, AD8038 C
= 1pF
= 1.5pF
REF
REF
REF
REF
REF
COMP
COMP
= 1pF
= 1.5pF
= 1.8pF
COMP
COMP
COMP
10k
100k
1M
10M
100M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 30. Reference Multiplying Bandwidth vs. Frequency and
Compensation Capacitor
Figure 33. Power Supply Rejection Ratio vs. Frequency
0.08
–60
–65
–70
–75
–80
–85
–90
T
V
= 25°C
DD
T = 25°C
A
V
= 5V
A
DD
= 0V
V
= 5V
0x7FF TO 0x800
NRG = 2.154nVs
DD
AD8038 AMPLIFIER
C
0.06
0.04
0.02
0
V
= ±3.5V
REF
= 1.8pF
COMP
V
= 3V
DD
0x7FF TO 0x800
NRG = 1.794nVs
V
= 5V
DD
–0.02
–0.04
–0.06
0x800 TO 0x7FF
NRG = 0.694nVs
V
= 5V
0x800 TO 0x7FF
NRG = 0.694nVs
DD
50
75
100
125
150
175
200
225
250
100
1k
10k
100k
FREQUENCY (Hz)
TIME (ns)
Figure 34. THD + Noise vs. Frequency
Figure 31. Midscale Transition, VREF = 0 V
100
80
60
40
20
0
–1.66
–1.68
–1.70
–1.72
–1.74
T
V
= 25°C
DD
V
= 5V
A
DD
MCLK = 200kHz
= 3.5V
0x7FF TO 0x800
NRG = 2.154nVs
MCLK = 500kHz
AD8038 AMPLIFIER
C
= 1.8pF
COMP
V
= 3V
MCLK = 1MHz
DD
0x7FF TO 0x800
NRG = 1.794nVs
–1.76
V
= 5V
DD
0x800 TO 0x7FF
NRG = 0.694nVs
= 5V
T
V
= 25°C
A
–1.78
–1.80
V
DD
= ±3.5V
REF
0x800 TO 0x7FF
NRG = 0.694nVs
AD8038 AMPLIFIER
0
10
20
fOUT (kHz)
30
40
50
50
75
100
125
150
175
200
225
250
TIME (ns)
Figure 32. Midscale Transition, VREF = 3.5 V
Figure 35. Wideband SFDR vs. fOUT Frequency
Rev. G | Page 12 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
0
0
–20
T
V
V
= 25°C
A
T
V
V
= 25°C
A
= 5V
DD
= 5V
DD
= 3.5V
REF
= 3.5V
–20
REF
AD8038 AMPLIFIER
AD8038 AMPLIFIER
–40
–40
–60
–60
–80
–80
–100
–100
–120
0
–120
10k
15k
20k
25k
30k
100k
200k
300k
400k
500k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 36. Wideband SFDR, fOUT = 20 kHz, Clock = 1 MHz
Figure 38. Narrow-Band SFDR, fOUT = 20 kHz, Clock = 1 MHz
0
–20
0
T
V
V
= 25°C
A
T
V
V
= 25°C
A
= 5V
DD
= 5V
DD
= 3.5V
REF
= 3.5V
–20
–40
REF
AD8038 AMPLIFIER
AD8038 AMPLIFIER
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
100k
200k
300k
400k
500k
30k
40k
50k
60k
70k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 37. Wideband SFDR, fOUT = 50 kHz, Clock = 1 MHz
Figure 39. Narrow-Band SFDR , fOUT = 50 kHz, Clock = 1 MHz
Rev. G | Page 13 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
80
70
60
50
40
30
20
10
0
0
T
= 25°C
A
T
V
= 25°C
A
AD8038 AMPLIFIER
= 3.5V
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
REF
AD8038 AMPLIFIER
FULL SCALE
LOADED TO DAC
MIDSCALE
LOADED TO DAC
ZERO SCALE
LOADED TO DAC
100
1k
10k
100k
1M
10k
15k
20k
25k
30k
35k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 42. Output Noise Spectral Density
Figure 40. Narrow-Band IMD, fOUT = 20 kHz, 25 kHz, Clock = 1 MHz
0
T
V
= 25°C
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
= 3.5V
REF
AD8038 AMPLIFIER
0
100k
200k
300k
400k
500k
FREQUENCY (Hz)
Figure 41. Wideband IMD, fOUT = 20 kHz, 25 kHz, Clock = 1 MHz
Rev. G | Page 14 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
Digital Feedthrough
A measure of the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is mea-
sured after adjusting for zero and full scale and is normally
expressed in LSBs or as a percentage of the full-scale reading.
When the device is not selected, high frequency logic activity
on the device’s digital inputs may be capacitively coupled
through the device and produce noise on the IOUT pins. This
noise is coupled from the outputs of the device onto follow-on
circuitry. This noise is digital feedthrough.
Differential Nonlinearity
The difference between the measured change and the ideal 1 LSB
change between any two adjacent codes. A specified differential
nonlinearity of −1 LSB maximum over the operating temperature
range ensures monotonicity.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal when all 0s are
loaded to the DAC.
Gain Error (Full-Scale Error)
Total Harmonic Distortion (THD)
A measure of the output error between an ideal DAC and the
actual device output. For these DACs, ideal maximum output is
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics, such as
second to fifth, are included.
V
REF − 1 LSB. Gain error of the DACs is adjustable to zero with
external resistance.
2
2
2
2
V2 +V3 +V4 +V5
Output Leakage Current
THD = 20 log
The current that flows into the DAC ladder switches when it is
turned off. For the IOUT1 terminal, it can be measured by loading
all 0s to the DAC and measuring the IOUT1 current.
V1
Digital Intermodulation Distortion (IMD)
Second-order intermodulation measurements are the relative
magnitudes of the fa and fb tones generated digitally by the
DAC and the second-order products at 2fa − fb and 2fb − fa.
Output Capacitance
Capacitance from IOUT1 to AGND.
Output Current Settling Time
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
The amount of time it takes for the output to settle to a specified
level for a full-scale input change. For these devices, it is specified
with a 100 Ω resistor to ground. The settling time specification
Spurious-Free Dynamic Range (SFDR)
includes the digital delay from the
rising edge to the full-
SYNC
The usable dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental
and the largest harmonically or nonharmonically related spur
from dc to full Nyquist bandwidth (half the DAC sampling rate
or fS/2). Narrow-band SFDR is a measure of SFDR over an
arbitrary window size, in this case 50% of the fundamental.
Digital SFDR is a measure of the usable dynamic range of the
DAC when the signal is a digitally generated sine wave.
scale output change.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s, depending
on whether the glitch is measured as a current or voltage signal.
Rev. G | Page 15 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
GENERAL DESCRIPTION
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages.
DAC SECTION
The AD5450/AD5451/AD5452/AD5453 are 8-/10-/12-/14-bit
current output DACs, respectively, consisting of a segmented
(4-bit) inverting R-2R ladder configuration. A simplified
diagram for the 12-bit AD5452 is shown in Figure 43.
V
DD
R2
C1
V
R
FB
DD
AD5450/
AD5451/
AD5452/
AD5453
R
R
R
I
1
OUT
V
V
REF
V
REF
REF
A1
R1
GND
2R
S2
2R
S3
2R
2R
V
= 0 TO –V
REF
2R
S1
OUT
SYNC SCLK SDIN
R
S12
R
FB
AGND
I
1
OUT
µCONTROLLER
DAC DATA LATCHES
AND DRIVERS
NOTES
AGND
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 43. AD5452 Simplified Ladder
Figure 44. Unipolar Mode Operation
The feedback resistor, RFB, has a value of R. The value of R is
typically 9 kΩ (with a minimum value of 7 kΩ and a maximum
value of 11 kΩ). If IOUT1 is kept at the same potential as GND, a
constant current flows in each ladder leg, regardless of digital
input code. Therefore, the input resistance presented at VREF is
always constant and nominally of value R. The DAC output
(IOUT1) is code-dependent, producing various resistances and
capacitances. When choosing the external amplifier, take into
account the variation in impedance generated by the DAC on
the amplifier’s inverting input node.
These DACs are designed to operate with either negative or
positive reference voltages. The VDD power pin is only used by
the internal digital logic to drive the on and off states of the
DAC switches.
These DACs are designed to accommodate ac reference input
signals in the range of −10 V to +10 V.
With a fixed 10 V reference, the circuit shown in Figure 44 gives
a unipolar 0 V to −10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
Access is provided to the VREF, RFB, and IOUT1 terminals of the
DAC, making the device extremely versatile and allowing it to be
configured in several operating modes; for example, it can provide
a unipolar output or can provide 4-quadrant multiplication in
bipolar mode. Note that a matching switch is used in series with
the internal RFB feedback resistor. If users attempt to measure
RFB, power must be applied to VDD to achieve continuity.
Table 5 shows the relationship between the digital code and
the expected output voltage for a unipolar operation using the
8-bit AD5450.
Table 5. Unipolar Code Table for the AD5450
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
Analog Output (V)
−VREF (255/256)
−VREF (128/256) = −VREF/2
−VREF (1/256)
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, these devices can easily be configured to
provide a 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 44. When an output amplifier
is connected in unipolar mode, the output voltage is given by
−VREF (0/256) = 0
D
VOUT = −
×VREF
2n
where:
D is the fractional representation of the digital word loaded to
the DAC.
D
= 0 to 255 (8-bit AD5450).
= 0 to 1023 (10-bit AD5451).
= 0 to 4095 (12-bit AD5452).
= 0 to 16,383 (14-bit AD5453).
n is the number of bits.
Rev. G | Page 16 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
Bipolar Mode
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication. Table 6 shows the relationship between the
digital code and the expected output voltage for a bipolar
operation using the 8-bit AD5450.
In some applications, it may be necessary to generate a full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and some external resistors, as shown in Figure 45. In
this circuit, the second amplifier, A2, provides a gain of 2.
Biasing the external amplifier with an offset from the reference
voltage results in full 4-quadrant multiplying operation. The
transfer function of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from Code 0 (VOUT = − VREF) to midscale
(VOUT − 0 V ) to full scale (VOUT = +VREF).
Table 6. Bipolar Code Table for the AD5450
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
Analog Output (V)
+VREF (127/128)
0
−VREF (127/128)
−VREF (128/128)
D
VOUT = V
×
−V
REF
REF
2n−1
where:
D is the fractional representation of the digital word loaded to
the DAC.
D
= 0 to 255 (8-bit AD5450).
= 0 to 1023 (10-bit AD5451).
= 0 to 4095 (12-bit AD5452).
n is the resolution of the DAC.
R3
20kΩ
V
V
DD
R5
20kΩ
R2
C1
R
DD
FB
AD5450/
AD5451/
AD5452/
AD5453
R4
10kΩ
I
1
OUT
V
±10V
REF
V
REF
A1
R1
GND
A2
V
=
–V
REF
TO +V
REF
OUT
SYNC SCLK SDIN
AGND
µCONTROLLER
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR V = 0V WITH CODE 10000000 LOADED TO DAC.
OUT
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R3 AND R4.
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
Figure 45. Bipolar Mode Operation (4-Quadrant Multiplication)
Rev. G | Page 17 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
Stability
Positive Output Voltage
In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited gain bandwidth
product (GBP) and there is excessive parasitic capacitance at the
inverting node. This parasitic capacitance introduces a pole into
the open-loop response, which can cause ringing or instability
in the closed-loop applications circuit.
The output voltage polarity is opposite to the VREF polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier
because of the resistors’ tolerance errors. To generate a negative
reference, the reference can be level-shifted by an op amp such
that the VOUT and GND pins of the reference become the virtual
ground and −2.5 V, respectively, as shown in Figure 47.
V
= +5V
DD
ADR03
V
V
An optional compensation capacitor, C1, can be added in parallel
with RFB for stability, as shown in Figure 44 and Figure 45. Too
small a value of C1 can produce ringing at the output, and too
large a value can adversely affect the settling time. C1 should be
found empirically, but 1 pF to 2 pF is generally adequate for the
compensation.
OUT
IN
GND
+5V
C1
V
R
FB
DD
I
1
–2.5V
OUT
V
V
= 0V TO +2.5V
OUT
REF
GND
–5V
SINGLE-SUPPLY APPLICATIONS
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
Voltage-Switching Mode
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 46 shows these DACs operating in the voltage-switching
mode. The reference voltage, VIN, is applied to the IOUT1 pin, and
the output voltage is available at the VREF terminal. In this
configuration, a positive reference voltage results in a positive
output voltage, making single-supply operation possible. The
output from the DAC is voltage at a constant impedance (the
DAC ladder resistance); therefore, an op amp is necessary to
buffer the output voltage. The reference input no longer sees
constant input impedance, but one that varies with code;
therefore, the voltage input should be driven from a low
impedance source.
Figure 47. Positive Output Voltage with Minimum Components
ADDING GAIN
In applications in which the output voltage is required to be
greater than VIN, gain can be added with an additional external
amplifier, or it can be achieved in a single stage. It is important
to consider the effect of the temperature coefficients of the
DAC’s thin film resistors. Simply placing a resistor in series
with the RFB resistor causes mismatches in the temperature
coefficients and results in larger gain temperature coefficient
errors. Instead, increase the gain of the circuit by using the
recommended configuration shown in Figure 48. R1, R2, and
R3 should have similar temperature coefficients, but they need
not match the temperature coefficients of the DAC. This
approach is recommended in circuits where gains greater than 1
are required.
R1
R2
V
DD
R
V
FB
DD
V
OUT
V
I
1
V
REF
IN
OUT
GND
V
DD
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
C1
V
R
DD
FB
I
1
R1
OUT
Figure 46. Single-Supply Voltage-Switching Mode
V
IN
V
REF
V
OUT
R3
R2
It is important to note that with this configuration VIN is limited
to low voltages because the switches in the DAC ladder do not
have the same source-drain drive voltage. As a result, their on
resistance differs, which degrades the integral linearity of the
DAC. Also, VIN must not go negative by more than 0.3 V, or an
internal diode turns on, causing the device to exceed the
maximum ratings. In this type of application, the full range of
multiplying capability of the DAC is lost.
GND
R2 + R3
R2
GAIN =
R2R3
R2 + R3
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
R1 =
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 48. Increasing Gain of Current-Output DAC
Rev. G | Page 18 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
REFERENCE SELECTION
Current-steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp and RFB is used as the input
resistor as shown in Figure 49, the output voltage is inversely
proportional to the digital input fraction, D.
When selecting a reference for use with this series of current-
output DACs, pay attention to the reference’s output voltage
temperature coefficient specification. This parameter not only
affects the full-scale error, but also may affect the linearity (INL
and DNL) performance. The reference temperature coefficient
should be consistent with the system accuracy specifications.
For example, an 8-bit system is required to hold its overall
specification to within 1 LSB over the temperature range 0°C to
50°C, and the system’s maximum temperature drift should be
less than 78 ppm/°C.
For D = 1 − 2−n, the output voltage is
−VIN
D
−VIN
VOUT
=
=
1−2−n
As D is reduced, the output voltage increases. For small values
of the digital fraction, D, it is important to ensure that the
amplifier does not saturate and that the required accuracy is
met. For example, an 8-bit DAC driven with the binary code
0x10 (00010000), that is, 16 decimal, in the circuit of Figure 49
should cause the output voltage to be 16 times VIN.
A 12-bit system within 2 LSB accuracy requires a maximum
drift of 10 ppm/°C. Choosing a precision reference with a low
output temperature coefficient minimizes this error source.
Table 7 lists some dc references available from Analog Devices
that are suitable for use with this range of current-output DACs.
V
DD
AMPLIFIER SELECTION
V
IN
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
The input offset voltage of an op amp is multiplied by the variable
gain of the circuit due to the code-dependent output resistance of
the DAC. A change in this noise gain between two adjacent digital
fractions produces a step change in the output voltage due to the
offset voltage of the amplifier’s input. This output voltage change
is superimposed on the desired change in output between the two
codes and gives rise to a differential linearity error, which if
large enough, could cause the DAC to be nonmonotonic.
R
V
FB
DD
I
1
V
REF
OUT
GND
V
OUT
NOTE
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 49. Current-Steering DAC Used as a Divider or
Programmable Gain Element
The input bias current of an op amp generates an offset at the
voltage output as a result of the bias current flowing in the
feedback resistor, RFB. Most op amps have input bias currents
low enough to prevent significant errors in 12-bit applications.
However, for 14-bit applications, some consideration should be
given to selecting an appropriate amplifier.
However, if the DAC has a linearity specification of 0.5 LSB, D
can have weight anywhere in the range of 15.5/256 to 16.5/256.
Therefore, the possible output voltage is in the range of 15.5 VIN
to 16.5 VIN—an error of 3%, even though the DAC itself has a
maximum error of 0.2%.
Common-mode rejection of the op amp is important in voltage-
switching circuits because it produces a code-dependent error
at the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-, 10-, and 12-bit resolutions.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction, D, of the current in the VREF terminal is
routed to the IOUT1 terminal, the output voltage changes as follows:
Provided that the DAC switches are driven from true wideband
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage-
switching DAC circuit is determined largely by the output op
amp. To obtain minimum settling time in this configuration, it
is important to minimize capacitance at the VREF node (the voltage
output node in this application) of the DAC. This is done by using
low input-capacitance buffer amplifiers and careful board design.
Output Error Voltage Dueto Leakage = (Leakage × R)/D
where R is the DAC resistance at the VREF terminal.
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain
(that is, 1/D) of 16, the error voltage is 1.6 mV.
Most single-supply circuits include ground as part of the analog
signal range, which in turn requires an amplifier that can handle
rail-to-rail signals. There is a large range of single-supply amplifiers
available from Analog Devices.
Rev. G | Page 19 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
Table 7. Suitable ADI Precision References
Part No. Output Voltage (V)
Initial Tolerance (%)
Temp Drift (ppm/°C)
ISS (mA)
Output Noise (µV p-p) Package
ADR01
ADR01
ADR02
ADR02
ADR03
ADR03
ADR06
ADR06
ADR431
ADR435
ADR391
ADR395
10
10
5
0.05
0.05
0.06
0.06
0.10
0.10
0.10
0.10
0.04
0.04
0.16
0.10
3
9
3
9
3
9
3
9
3
3
9
9
1
1
1
1
1
1
1
1
0.8
0.8
0.12
0.12
20
20
10
10
6
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
SOIC-8
TSOT-23
TSOT-23
5
2.5
2.5
3
3
2.5
5
6
10
10
3.5
8
5
8
2.5
5
Table 8. Suitable ADI Precision Op Amps
0.1 Hz to 10 Hz
Noise (µV p-p)
Part No.
OP97
OP1177
AD8551
AD8603
AD8628
Supply Voltage (V)
2 to 20
2.5 to 15
2.7 to 5
1.8 to 6
2.7 to 6
VOS (Max) (µV)
IB (Max) (nA)
Supply Current (µA)
Package
25
60
5
50
5
0.1
2
0.05
0.001
0.1
0.5
0.4
1
2.3
0.5
600
500
975
50
SOIC-8
MSOP, SOIC-8
MSOP, SOIC-8
TSOT
850
TSOT, SOIC-8
Table 9. Suitable ADI High Speed Op Amps
Part No.
AD8065
AD8021
AD8038
AD9631
Supply Voltage (V)
BW @ ACL (MHz)
Slew Rate (V/µs)
VOS (Max) (µV) IB (Max) (nA)
Package
5 to 24
2.5 to 12
3 to 12
145
490
350
320
180
120
425
1300
1500
1000
3000
10000
0.006
10500
750
SOIC-8, SOT-23, MSOP
SOIC-8, MSOP
SOIC-8, SC70-5
SOIC-8
3 to
6
7000
Rev. G | Page 20 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
SERIAL INTERFACE
The serial interface to the AD5450 uses a 16-bit shift register.
Take care to avoid incomplete data sequences as these will be
latched to update the DAC output.
The AD5450/AD5451/AD5452/AD5453 have an easy-to-use
3-wire interface that is compatible with SPI, QSPI, MICROWIRE,
and most DSP interface standards. Data is written to the device in
16-bit words. This 16-bit word consists of two control bits and 8,
10, 12, or 14 data bits, as shown in Figure 50, Figure 51, Figure 52,
and Figure 53. The AD5453 uses all 14 bits of DAC data, the
AD5452 uses 12 bits and ignores the two LSBs, the AD5451 uses
10 bits and ignores the four LSBs, and the AD5450 uses 8 bits
and ignores the six LSBs.
For example,
•
•
Loading 0x3FFF (a complete data sequence) will update
the output to 10 V (full scale).
User intends to write 0x3200 but after 12 active edges
SYNC
goes high (incomplete write sequence). This will
actually update the following code: 0xF200.
SYNC
DAC Control Bits C1, C0
•
The user expects an output of 5.6 V. However, if
goes high after 12 valid clock edges then an incomplete
data sequence of 12 bits is loaded. To complete the shift
register the 4 LSBs from the previous sequence are taken
and used as the 4 MSBs missing. The addition of these
4 bits will put the part in rising edge mode and the output
will show no change. Figure 54, Figure 55, and Table 11
show the data frames for this example.
Control Bits C1 and C0 allow the user to load and update the
new DAC code and to change the active clock edge. By default,
the shift register clocks data upon the falling edge; this can be
changed via the control bits. If changed, the DAC core is
inoperative until the next data frame, and a power recycle is
required to return it to active on the falling edge. A power cycle
resets the core to default condition. On-chip power-on reset
circuitry ensures that the device powers on with zero scale
loaded to the DAC register and IOUT line.
Also note that if more then 16-bits are loaded to the part before
SYNC
goes high the last 16-bits will be latched.
DB15 (MSB)
DB0 (LSB)
Table 10. DAC Control Bits
C1 C0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
X
X
X
X
X
C1
C0
Function Implemented
Load and update (power-on default)
Reserved
DATA BITS
0
0
CONTROL BITS
0
1
Figure 50. AD5450 8-Bit Input Shift Register Contents
1
0
Reserved
1
1
Clock data to shift register upon rising edge
DB15 (MSB)
C1
DB0 (LSB)
Function
SYNC
C0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
X
X
X
is an edge-triggered input that acts as a frame-
SYNC
DATA BITS
CONTROL BITS
synchronization signal and chip enable. Data can only be
transferred to the device while is low. To start the serial
Figure 51. AD5451 10-Bit Input Shift Register Contents
SYNC
should be taken low, observing the
data transfer,
SYNC
falling to SCLK falling edge setup time, t4. To
minimum
SYNC
DB15 (MSB)
C1 C0
DB0 (LSB)
DB9 DB8 DB7 DB6 DB5 DB4
DATA BITS
DB1 DB0
DB3 DB2
X
DB11 DB10
X
minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
CONTROL BITS
upon the falling edge of
. The SCLK and SDIN input
SYNC
Figure 52. AD5452 12-Bit Input Shift Register Contents
buffers are powered down upon the rising edge of
.
SYNC
After the falling edge of the 16th SCLK pulse, bring
to transfer data from the input shift register to the DAC register.
high
DB15 (MSB)
SYNC
DB0 (LSB)
DB3 DB2 DB1 DB0
DB5 DB4
C1
C0
DB11 DB10 DB9 DB8 DB7 DB6
DATA BITS
DB13 DB12
CONTROL BITS
Figure 53. AD5453 14-Bit Input Shift Register Contents
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DATA BITS
CONTROL BITS
Figure 54. AD5453 First Write, Complete Data Sequence (0x3FFF)
Rev. G | Page 21 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
DATA BITS
DATA BITS
CONTROL BITS
CONTROL BITS
INTENDED DATA FRAME
ACTUAL DATA FRAME
Figure 55. AD5453 Second Write, Incomplete Data Sequence (0x3200) and Subsequent Additional Bits (0xF200)
Table 11.
Writing
Sequence
Data Write in
Shift Register
Data Transfer to
the Device
Action Expected
Action Carried Out
1
0x3FFF
Load and update 0x3FFF
0x3FFF
Load and update 0x3FFF
2
0x3200
Load and update 0x3200
0xF200
Clock data to shift register upon rising edge (0xF200)
MICROPROCESSOR INTERFACING
AD5450/AD5451/
AD5452/AD5453*
ADSP-2101/
ADSP-2191M*
Microprocessor interfacing to a AD5450/AD5451/AD5452
/AD5453 DAC is through a serial bus that uses standard protocol
and is compatible with microcontrollers and DSP processors.
The communication channel is a 3-wire interface consisting of
a clock signal, a data signal, and a synchronization signal. The
AD5450/AD5451/AD5452/AD5453 require a 16-bit word, with
the default being data valid upon the falling edge of SCLK, but
this is changeable using the control bits in the data-word.
TFS
SYNC
DT
SDIN
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 57. ADSP-2101/ADSP-2191M-
to-AD5450/AD5451/AD5452/AD5453 Interface
Communication between two devices at a given clock speed is
possible when the following specifications are compatible:
ADSP-21xx-to-AD5450/AD5451/AD5452/AD5453
Interface
frame
delay and frame
setup-and-hold, data delay
SYNC
and data setup-and-hold, and SCLK width. The DAC interface
expects a t4 ( falling edge to SCLK falling edge setup time)
SYNC
The ADSP-21xx family of DSPs is easily interfaced to a AD5450/
AD5451/AD5452/AD5453 DAC without the need for extra glue
logic. Figure 56 is an example of an SPI interface between the DAC
and the ADSP-2191M. SCK of the DSP drives the serial data line,
SYNC
of 13 ns minimum. See the ADSP-21xx User Manual for infor-
mation on clock and frame frequencies for the SPORT
SYNC
SDIN.
is driven from one of the port lines, in this case
SYNC
register. Table 12 shows the setup for the SPORT control register.
.
SPIxSEL
Table 12. SPORT Control Register Setup
AD5450/AD5451/
ADSP-2191M*
AD5452/AD5453*
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
Setting
Description
SYNC
SDIN
SPIxSEL
1
1
00
1
1
Alternate framing
Active low frame signal
Right justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
MOSI
SCK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
ITFS
1
Figure 56. ADSP-2191M SPI-to-AD5450/AD5451/AD5452/AD5453 Interface
SLEN
1111
A serial interface between the DAC and DSP SPORT is shown
in Figure 57. In this example, SPORT0 is used to transfer data to
the DAC shift register. Transmission is initiated by writing a
word to the Tx register after the SPORT has been enabled. In a
write sequence, data is clocked out upon each rising edge of the
DSP’s serial clock and clocked into the DAC input shift register
upon the falling edge of its SCLK. The update of the DAC
ADSP-BF5xx-to-AD5450/AD5451/AD5452/AD5453
Interface
The ADSP-BF5xx family of processors has an SPI-compatible
port that enables the processor to communicate with SPI-
compatible devices. A serial interface between the BlackFin®
processor and the AD5450/AD5451/AD5452/AD5453 DAC is
shown in Figure 58. In this configuration, data is transferred
output takes place upon the rising edge of the
signal.
SYNC
through the MOSI (master output, slave input) pin.
is
SYNC
driven by the
pin, which is a reconfigured
SPIxSEL
programmable flag pin.
Rev. G | Page 22 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
AD5450/AD5451/
AD5452/AD5453*
AD5450/AD5451/
AD5452/AD5453*
ADSP-BF5xx*
8051*
TxD
RxD
P1.1
SCLK
SDIN
SYNC
SYNC
SDIN
SPIxSEL
MOSI
SCK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 60. 80C51/80L51-to-AD5450/AD5451/AD5452/AD5453 Interface
Figure 58. ADSP-BF5xx-to-AD5450/AD5451/AD5452/AD5453 Interface
MC68HC11-to-AD5450/AD5451/AD5452/AD5453
Interface
The ADSP-BF5xx processor incorporates channel synchronous
serial ports (SPORT). A serial interface between the DAC and
the DSP SPORT is shown in Figure 59. When the SPORT is
enabled, initiate transmission by writing a word to the Tx register.
The data is clocked out upon each rising edge of the DSP’s serial
clock and clocked into the DAC’s input shift register upon the
falling edge its SCLK. The DAC output is updated by using the
Figure 61 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR); see the 68HC11 User Manual. SCK
of the 68HC11 drives the SCLK of the DAC interface; the MOSI
output drives the serial data line (SDIN) of the DAC.
transmit frame synchronization (TFS) line to provide a
SYNC
signal.
The
signal is derived from a port line (PC7). When data
SYNC
is being transmitted to the AD5450/AD5451/AD5452/AD5453,
the line is taken low (PC7). Data appearing on the MOSI
AD5450/AD5451/
AD5452/AD5453*
ADSP-BF5xx*
TFS
DT
SYNC
SYNC
SDIN
output is valid upon the falling edge of SCK. Serial data from the
68HC11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
first. To load data to the DAC, PC7 is left low after the first eight
bits are transferred, and a second serial write operation is performed
to the DAC. PC7 is taken high at the end of this procedure.
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 59. ADSP-BF5xx SPORT-to-AD5450/AD5451/AD5452/AD5453 Interface
80C51/80L51-to-AD5450/AD5451/AD5452/AD5453
Interface
MC68HC11*
AD5450/AD5451/
AD5452/AD5453*
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 60. TxD of the 80C51/80L51 drives SCLK of
the DAC serial interface, and RxD drives the serial data line,
SDIN. P1.1 is a bit-programmable pin on the serial port and is used
PC7
SCK
SYNC
SCLK
SDIN
MOSI
to drive
. As data is transmitted to the switch, P1.1 is taken
*ADDITIONAL PINS OMITTED FOR CLARITY
SYNC
low. The 80C51/80L51 transmit data only in 8-bit bytes; there-
fore, only eight falling clock edges occur in the transmit cycle.
Figure 61. MC68HC11-to-AD5450/AD5451/AD5452/AD5453 Interface
If the user wants to verify the data previously written to the
input shift register, the SDO line can be connected to MISO of
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and a second write cycle is initiated to
transmit the second byte of data. Data on RxD is clocked out of
the microcontroller upon the rising edge of TxD and is valid upon
the falling edge. As a result, no glue logic is required between the
DAC and microcontroller interface. P1.1 is taken high following
the completion of this cycle. The 80C51/80L51 provide the LSB
of its SBUF register as the first bit in the data stream. The DAC
input register acquires its data with the MSB as the first bit received.
The transmit routine should take this into account.
the MC68HC11. In this configuration with
low, the shift
SYNC
register clocks data out upon the rising edges of SCLK.
Rev. G | Page 23 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
MICROWIRE-to-AD5450/AD5451/AD5452/AD5453
Interface
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which a
AD5450/AD5451/AD5452/AD5453 DAC is mounted should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. If the DAC is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device.
Figure 62 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out
upon the falling edge of the serial clock, SK, and is clocked into
the DAC input shift register upon the rising edge of SK, which
corresponds to the falling edge of the DAC’s SCLK.
MICROWIRE*
AD5450/AD5451/
AD5452/AD5453*
SK
SO
CS
SCLK
SDIN
SYNC
These DACs should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on the supply located as close to the package
as possible, ideally right up against the device. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), like the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 62. MICROWIRE-to-AD5450/AD5451/AD5452/AD5453 Interface
PIC16C6x/PIC16C7x-to-
AD5450/AD5451/AD5452/AD5453 Interface
The PIC16C6x/PIC16C7x synchronous serial port (SSP) is
configured as an SPI master with the clock polarity bit (CKP) = 0.
This is done by writing to the synchronous serial port control
register (SSPCON); see the PIC16/PIC17 Microcontroller
User Manual.
Components, such as clocks, that produce fast switching signals
should be shielded with a digital ground to avoid radiating noise
to other parts of the board, and they should never be run near
the reference inputs.
In this example, I/O Port RA1 is used to provide a
signal
SYNC
and enable the serial port of the DAC. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, two consecutive write operations are
required. Figure 63 shows the connection diagram.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is the best solution, but its use is not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane and signal
traces are placed on the solder side.
AD5450/AD5451/
AD5452/AD5453*
PIC16C6x/PIC16C7x*
SCK/RC3
SDI/RC4
RA1
SCLK
SDIN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
Figure 63. PIC16C6x/7x-to-AD5450/AD5451/AD5452/AD5453 Interface
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error. To optimize high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
Rev. G | Page 24 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
Table 13. Overview of AD54xx and AD55xx Devices
Part No.
AD5424
AD5426
AD5428
AD5429
AD5450
AD5432
AD5433
AD5439
AD5440
AD5451
AD5443
AD5444
AD5415
AD5405
AD5445
AD5447
AD5449
AD5452
AD5446
AD5453
AD5553
AD5556
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
Resolution
No. DACs
INL (LSB)
Interface
Parallel
Serial
Parallel
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Serial
Serial
Serial
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Parallel
Serial
Parallel
Package1
Features
8
1
1
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
1
1
2
2
0.25
0.25
0.25
0.25
0.25
0.5
0.5
0.5
0.5
0.25
1
RU-16, CP-20
RM-10
RU-20
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
12 MHZ BW, 50 MHz serial interface
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
12 MHz BW, 50 MHz serial interface
10 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial interface
12 MHz BW, 50 MHz serial
8
8
8
8
RU-10
UJ-8
RM-10
RU-20, CP-20
RU-16
10
10
10
10
10
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
RU-24
UJ-8
RM-10
RM-10
RU-24
0.5
1
1
CP-40
1
RU-20, CP-20
RU-24
1
1
0.5
1
2
1
RU-16
UJ-8, RM-8
RM-10
UJ-8, RM-8
RM-8
12 MHz BW, 50 MHz serial
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 n WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
1
RU-28
1
1
RM-8
RU-38
2
2
RM-8
RU-28
2
2
RU-16
RU-38
1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
Rev. G | Page 25 of 28
AD5450/AD5451/AD5452/AD5453
OUTLINE DIMENSIONS
Data Sheet
2.90 BSC
8
1
7
2
6
3
5
4
1.60 BSC
2.80 BSC
PIN 1
INDICATOR
0.65 BSC
1.95
BSC
*
0.90
0.87
0.84
*
0.20
0.08
1.00 MAX
0.60
0.45
0.30
8°
4°
0°
0.38
0.22
0.10 MAX
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-193-BA WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 64. 8-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-8)
Dimensions shown in millimeters
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 65. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. G | Page 26 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
3.10
3.00 SQ
2.90
0.35
0.30
0.25
0.65 BSC
8
5
PIN 1 INDEX
AREA
EXPOSED
PAD
1.74
1.64
1.49
0.50
0.40
0.30
1
4
0.20 MIN
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
(R 0.2)
2.48
2.38
2.23
0.80 MAX
0.55 NOM
0.80
0.75
0.70
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SEATING
PLANE
0.20 REF
SECTION OF THIS DATA SHEET.
Figure 66. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Resolution
INL
0.25
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead TSOT
8-Lead TSOT
Package Option
UJ-8
UJ-8
Branding
D6Y
D6Y
D6Z
D6Z
D70
AD5450YUJZ-REEL
AD5450YUJZ-REEL7
AD5451YUJZ-REEL
AD5451YUJZ-REEL7
AD5452YUJZ-REEL
AD5452YUJZ-REEL7
AD5452YRM
8
8
0.25
0.25
0.25
0.5
0.5
0.5
0.5
0.5
0.5
0.5
2
2
2
2
2
2
2
2
2
10
10
12
12
12
12
12
12
12
14
14
14
14
14
14
14
14
14
8-Lead TSOT
8-Lead TSOT
UJ-8
UJ-8
8-Lead TSOT
8-Lead TSOT
UJ-8
UJ-8
D70
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead LFCSP_WD
8-Lead TSOT
RM-8
RM-8
RM-8
RM-8
RM-8
CP-8-3
UJ-8
D1Z
D1Z
D70
D70
D70
AD5452YRM-REEL
AD5452YRMZ
AD5452YRMZ-REEL
AD5452YRMZ-REEL7
AD5453WBCPZ-RL
AD5453YUJZ-REEL
AD5453YUJZ-REEL7
AD5453YRM
AD5453YRM-REEL
AD5453YRM-REEL7
AD5453YRMZ
DG3
DAH
DAH
D26
D26
D26
DAH
DAH
DAH
8-Lead TSOT
UJ-8
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Evaluation Board
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
AD5453YRMZ-REEL
AD5453YRMZ-REEL7
EV-AD5443/46/53SDZ
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD5453WBCPZ-RL model is available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models.
Rev. G | Page 27 of 28
AD5450/AD5451/AD5452/AD5453
NOTES
Data Sheet
©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04587-0-6/13(G)
Rev. G | Page 28 of 28
相关型号：
AD5453YRMREEL7
IC SERIAL INPUT LOADING, 14-BIT DAC, PDSO8, MO-187AA, MSOP-8, Digital to Analog Converter
ADI
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