AD5313ARUZ-REEL7 [ADI]
2.5 V to 5.5 V, 230 µA, Dual Rail-to-Rail Voltage Output 10-Bit DAC;型号: | AD5313ARUZ-REEL7 |
厂家: | ADI |
描述: | 2.5 V to 5.5 V, 230 µA, Dual Rail-to-Rail Voltage Output 10-Bit DAC 光电二极管 转换器 |
文件: | 总28页 (文件大小:488K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail
Voltage Output 8-/10-/12-Bit DACs
AD5303/AD5313/AD5323
GENERAꢀ DESCRIPTION
FEATURES
AD5303: 2 buffered 8-bit DACs in 1 package
A version: 1 ꢀSB INꢀ, B version: 0.5 ꢀSB INꢀ
AD5313: 2 buffered 10-bit DACs in 1 package
A version: 4 ꢀSB INꢀ, B version: 2 ꢀSB INꢀ
AD5323: 2 buffered 12-bit DACs in 1 package
A version: 16 ꢀSB INꢀ, B version: 8 ꢀSB INꢀ
16-lead TSSOP package
Micropower operation: 300 μA @ 5 V (including reference
current)
Power-down to 200 nA @ 5 V, 50 nA @ 3 V
2.5 V to 5.5 V power supply
The AD5303/AD5313/AD5323 are dual 8-/10-/12-bit buffered
voltage output DACs in a 16-lead TSSOP package that operate
from a single 2.5 V to 5.5 V supply, consuming 230 μA at 3 V.
Their on-chip output amplifiers allow the outputs to swing rail-to-
rail with a slew rate of 0.7 V/μs. The AD5303/AD5313/AD5323
utilize a versatile 3-wire serial interface that operates at clock
rates up to 30 MHz and is compatible with standard SPI, QSPI™,
MICROWIRE™, and DSP interface standards.
The references for the two DACs are derived from two reference
pins (one per DAC). These reference inputs may be configured
as buffered or unbuffered inputs. The parts incorporate a power-
on reset circuit, which ensures that the DAC outputs power up
to 0 V and remain there until a valid write to the device takes
Double-buffered input logic
Guaranteed monotonic by design over all codes
Buffered/unbuffered reference input options
Output range: 0 V to VREF or 0 V to 2 VREF
Power-on-reset to 0 V
CLR
place. There is also an asynchronous active low
clears both DACs to 0 V. The outputs of both DACs may be
LDAC
pin that
updated simultaneously using the asynchronous
input.
SDO daisy-chaining option
The parts contain a power-down feature that reduces the
current consumption of the devices to 200 nA at 5 V (50 nA
at 3 V) and provides software-selectable output loads while
in power-down mode. The parts may also be used in daisy-
chaining applications using the SDO pin.
ꢀDAC
Simultaneous update of DAC outputs via
CꢀR
pin
Asynchronous
facility
ꢀow power serial interface with Schmitt-triggered inputs
On-chip rail-to-rail output buffer amplifiers
APPꢀICATIONS
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip-
ment. The power consumption is 1.5 mW at 5 V and 0.7 mW at
3 V, reducing to 1 μW in power-down mode.
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAꢀ BꢀOCK DIAGRAM
V
V
A
DD
BUF A
REF
AD5303/AD5313/AD5323
POWER-ON
RESET
DAC
REGISTER
INPUT
REGISTER
STRING
DAC
V
OUT
A
BUFFER
SYNC
SCLK
DIN
INTERFACE
LOGIC
POWER-DOWN
LOGIC
RESISTOR
NETWORK
DAC
REGISTER
INPUT
REGISTER
STRING
DAC
V
OUT
B
BUFFER
SDO
GAIN-SELECT
LOGIC
RESISTOR
NETWORK
V B
REF
GND
DCEN
BUF B
LDAC
CLR
PD
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1999–2007 Analog Devices, Inc. All rights reserved.
AD5303/AD5313/AD5323
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Shift Register .................................................................... 17
Low Power Serial Interface ....................................................... 17
Double-Buffered Interface ........................................................ 17
Power-Down Modes ...................................................................... 19
Microprocesser Interfacing ........................................................... 20
AD5303/AD5313/AD5323 to ADSP-2101 Interface............. 20
AD5303/AD5313/AD5323 to 68HC11/68L11 Interface ...... 20
AD5303/AD5313/AD5323 to 80C51/80L51 Interface.......... 20
AD5303/AD5313/AD5323 to MICROWIRE Interface ........ 20
Applications Information.............................................................. 21
Typical Application Circuit....................................................... 21
Bipolar Operation Using the AD5303/AD5313/AD5323..... 21
Opto-Isolated Interface for Process Control Applications ... 22
Decoding Multiple AD5303/AD5313/AD5323s.................... 22
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 6
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 10
Typical Performance Characteristics ........................................... 11
Functional Description.................................................................. 15
Digital-to-Analog ....................................................................... 15
Resistor String............................................................................. 15
DAC Reference Inputs ............................................................... 15
Output Amplifier........................................................................ 15
Power-On Reset .............................................................................. 16
AD5303/AD5313/AD5323 as a Digitally Programmable
Window Detector....................................................................... 22
Coarse and Fine Adjustment Using the
AD5303/AD5313/AD5323 ....................................................... 23
Daisy-Chain Mode..................................................................... 23
Power Supply Bypassing and Grounding................................ 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
CLR
Clear Function (
) ................................................................ 16
Serial Interface ................................................................................ 17
REVISION HISTORY
6/07—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Table 4............................................................................ 8
Changes to the Ordering Guide.................................................... 25
8/03—Rev. 0 to Rev. A
Added A Version.................................................................Universal
Changes to Features.......................................................................... 1
Changes to Specifications................................................................ 2
Changes to Absolute Maximum Ratings....................................... 5
Changes to Ordering Guide ............................................................ 5
Updated Outline Dimensions....................................................... 18
4/99—Revision 0: Initial Version
Rev. B | Page 2 of 28
AD5303/AD5313/AD5323
SPECIFICATIONS
VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
A Version1
Min Typ
B Version1
Min Typ
Parameter2
DC PERFORMANCE3, 4
Max
Max
Unit
Conditions/Comments
AD5303
Resolution
8
8
Bits
LSB
Relative Accuracy
Differential Nonlinearity
0.15
0.02
1
0.15
0.02
0.5
0.25
0.25 LSB
Guaranteed monotonic by design over
all codes
AD5313
Resolution
10
0.5
0.05
10
0.5
0.05
Bits
Relative Accuracy
Differential Nonlinearity
4
2
LSB
LSB
0.5
0.5
Guaranteed monotonic by design over
all codes
AD5323
Resolution
12
12
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
2
1ꢀ
1
2
8
1
0.2
0.2
Guaranteed monotonic by design over
all codes
Offset Error
0.4
3
1
0.4
3
1
% of FSR
% of FSR
mV
See Figure 2 and Figure 3
See Figure 2 and Figure 3
See Figure 2 and Figure 3
Gain Error
0.15
0.15
Lower Dead Band
Offset Error Drift5
Gain Error Drift5
Power Supply Rejection Ratio5
DC Crosstalk5
10
ꢀ0
10
ꢀ0
−12
−5
−12
−5
ppm of FSR/°C
ppm of FSR/°C
dB
−ꢀ0
30
−ꢀ0
30
ΔVDD = 10%
μV
DAC REFERENCE INPUTS5
VREF Input Range
1
0
VDD
VDD
1
0
VDD
VDD
V
Buffered reference mode
Unbuffered reference mode
Buffered reference mode
Unbuffered reference mode
V
VREF Input Impedance
>10
180
>10
180
MΩ
kΩ
0 V to VREF output range, input
impedance = RDAC
90
90
kΩ
Unbuffered reference mode
0 V to 2 VREF output range, input
impedance = RDAC
Reference Feedthrough
−90
−80
−90
−80
dB
dB
Frequency = 10 kHz
Frequency = 10 kHz
Channel-to-Channel Isolation
OUTPUT CHARACTERISTICS5
Minimum Output Voltageꢀ
Maximum Output Voltageꢀ
0.001
0.001
V min
V max
This is a measure of the minimum and
maximum drive capability of the output
amplifier
VDD − 0.001
VDD − 0.001
DC Output Impedance
Short-Circuit Current
0.5
50
0.5
50
Ω
mA
mA
μs
VDD = 5 V
VDD = 3 V
20
20
Power-Up Time
2.5
2.5
Coming out of power-down mode;
VDD = 5 V
5
5
μs
Coming out of power-down mode;
VDD = 3 V
Rev. B | Page 3 of 28
AD5303/AD5313/AD5323
A Version1
Min Typ
B Version1
Min Typ
Parameter2
Max
Max
Unit
Conditions/Comments
LOGIC INPUTS5
Input Current
1
1
μA
Input Low Voltage, VIL
Input High Voltage, VIH
Pin Capacitance
0.8
0.ꢀ
0.5
0.8
0.ꢀ
0.5
V
VDD = 5 V 10%
VDD = 3 V 10%
VDD = 2.5 V
V
V
2.4
2.1
2.0
2.4
2.1
2.0
V
VDD = 5 V 10%
VDD = 3 V 10%
VDD = 2.5 V
V
V
2
3.5
0.4
2
3.5
0.4
pF
LOGIC OUTPUT (SDO)5
VDD = 5 V 10%
Output Low Voltage
Output High Voltage
VDD = 3 V 10%
V
V
ISINK = 2 mA
4.0
2.4
4.0
2.4
ISOURCE = 2 mA
Output Low Voltage
Output High Voltage
Floating-State Leakage Current
0.4
1
0.4
1
V
ISINK = 2 mA
V
ISOURCE = 2 mA
DCEN = GND
DCEN = GND
μA
pF
Floating-State Output
Capacitance
3
3
POWER REQUIREMENTS
VDD
2.5
5.5
2.5
5.5
V
IDD specification is valid for all DAC codes
IDD (Normal Mode)
Both DACs active and excluding load
currents
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.ꢀ V
300
230
450
350
300
230
450
350
μA
μA
Both DACs in unbuffered mode;
VIH = VDD and VIL = GND; in buffered
mode, extra current is typically x μA
per DAC, where x = 5 μA + VREF/RDAC
IDD (Full Power-Down)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.ꢀ V
0.2
1
1
0.2
1
1
μA
μA
0.05
0.05
1 Temperature range for Version A, Version B: −40°C to +105°C.
2 See the Terminology section.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range: AD5303 (Code 8 to Code 248); AD5313 (Code 28 to Code 995); AD5323 (Code 115 to Code 3981).
5 Guaranteed by design and characterization, not production tested.
ꢀ In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage, VREF = VDD
and offset plus gain error must be positive.
Rev. B | Page 4 of 28
AD5303/AD5313/AD5323
GAIN ERROR
PLUS
OFFSET ERROR
GAIN ERROR
PLUS
OFFSET ERROR
OUTPUT
VOLTAGE
ACTUAL
OUTPUT
VOLTAGE
IDEAL
ACTUAL
IDEAL
POSITIVE
OFFSET
ERROR
POSITIVE
OFFSET
ERROR
DAC CODE
DAC CODE
Figure 3. Transfer Function with Positive Offset
DEAD BAND
AMPLIFIER
FOOTROOM
(1mV)
NEGATIVE
OFFSET
ERROR
Figure 2. Transfer Function with Negative Offset
Rev. B | Page 5 of 28
AD5303/AD5313/AD5323
AC CHARACTERISTICS1
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A, B Version3
Parameter2
Unit
Conditions/Comments
Min
Typ
Max
Output Voltage Settling Time
VREF = VDD = 5 V
AD5303
AD5313
AD5323
ꢀ
7
8
8
9
10
μs
μs
μs
¼ scale to ¾ scale change (0x40 to 0xc0)
¼ scale to ¾ scale change (0x100 to 0x300)
¼ scale to ¾ scale change (0x400 to 0xc00)
Slew Rate
Major-Code Transition Glitch Energy
0.7
12
V/μs
nV-s
1 LSB change around major carry
(011 . . . 11 to 100 . . . 00)
Digital Feedthrough
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
0.10
0.01
0.01
200
−70
nV-s
nV-s
nV-s
kHz
dB
VREF = 2 V 0.1 V p-p, unbuffered mode
VREF = 2.5 V 0.1 V p-p, frequency = 10 kHz
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range for Version A and Version B: −40°C to +105°C.
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Limit at TMIN, TMAX
Parameter1, 2, 3
Unit
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK rising edge setup time
Data setup time
(A, B Version)
t1
t2
t3
t4
t5
tꢀ
t7
t8
t9
t10
t11
33
13
13
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
5
4.5
0
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
LDAC pulse width
100
20
20
20
5
SCLK falling edge to LDAC rising edge
CLR pulse width
4, 5
t12
SCLK falling edge to SDO invalid
SCLK falling edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
4, 5
t13
5
20
0
t14
5
t15
10
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 See Figure 4 and Figure 5.
4 These are measured with the load circuit of Figure 4.
5 Daisy-chain mode only (see Figure 47).
Rev. B | Page ꢀ of 28
AD5303/AD5313/AD5323
2mA
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
2mA
I
OH
Figure 4. Load Circuit for Digital Output (SDO) Timing Specifications
t1
SCLK
SYNC
t2
t3
t7
t8
t4
t6
t5
DIN*
DB15
DB0
t9
LDAC
t10
LDAC
t11
CLR
*
SEE THE INPUT SHIFT REGISTER SECTION.
Figure 5. Serial Interface Timing Diagram
Rev. B | Page 7 of 28
AD5303/AD5313/AD5323
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
Digital Input Voltage to GND
Digital Output Voltage to GND
Reference Input Voltage to GND
VOUTA, VOUTB to GND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
ESD CAUTION
Operating Temperature Range
Industrial (A, B Version)
Storage Temperature Range
Junction Temperature (TJ Max)
1ꢀ-Lead TSSOP Package
Power Dissipation
θJA Thermal Impedance
Lead Temperature
Soldering
−40°C to +105°C
−ꢀ5°C to +150°C
150°C
(TJ max − TA)/θJA
1ꢀ0°C/W
JEDEC Industry Standard
J-STD-020
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. B | Page 8 of 28
AD5303/AD5313/AD5323
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
SDO
GND
DIN
LDAC
AD5303/
AD5313/
AD5323
TOP VIEW
(Not to Scale)
V
DD
V
B
A
SCLK
SYNC
REF
V
REF
OUT
V
A
V
B
OUT
BUF A
BUF B
PD
DCEN
Figure 6. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
CLR
Active Low Control Input. Loads all zeros to both input and DAC registers.
LDAC
Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing
this pin low allows either or both DAC registers to be updated if the input registers have new data. This allows
the simultaneous update of both DAC outputs.
3
4
VDD
VREF
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND.
Reference Input Pin for DAC B. It may be configured as a buffered or an unbuffered input, depending on the state
of the BUF B pin. It has an input range from 0 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode.
B
5
VREF
A
Reference Input Pin for DAC A. It may be configured as a buffered or an unbuffered input depending on the state
of the BUF A pin. It has an input range from 0 to VDD in unbuffered mode and from 1 V to VDD in buffered mode.
ꢀ
7
VOUT
A
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Control Pin. Controls whether the reference input for DAC A is unbuffered or buffered. If this pin is tied low, the
reference input is unbuffered. If it is tied high, the reference input is buffered.
Control Pin. Controls whether the reference input for DAC B is unbuffered or buffered. If this pin is tied low, the
reference input is unbuffered. If it is tied high, the reference input is buffered.
This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a daisy
chain. The pin should be tied low if it is being used in standalone mode.
BUF A
BUF B
DCEN
PD
8
9
10
Active Low Control Input. Acts as a hardware power-down option. This pin overrides any software power-down
option. Both DACs go into power-down mode when this pin is tied low. The DAC outputs go into a high
impedance state and the current consumption of the part drops to 200 nA @ 5 V (50 nA @ 3 V).
11
12
VOUT
SYNC
B
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling
edges of the following 1ꢀ clocks. If SYNC is taken high before the 1ꢀth falling edge, the rising edge of SYNC acts
as an interrupt and the write sequence is ignored by the device.
13
14
SCLK
DIN
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
Serial Data Input. This device has a 1ꢀ-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input. The DIN input buffer is powered down after each write cycle.
15
1ꢀ
GND
SDO
Ground Reference Point for All Circuitry on the Part.
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the
data in the shift register for diagnostic purposes. The serial data output is valid on the falling edge of the clock.
Rev. B | Page 9 of 28
AD5303/AD5313/AD5323
TERMINOLOGY
DAC-to-DAC Crosstalk
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measure of the maximum deviation, in LSB, from a straight
line passing through the actual endpoints of the DAC transfer
function. A typical INL error vs. code plot can be seen in
Figure 7, Figure 8, and Figure 9.
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
the other DAC. This includes both digital and analog crosstalk.
It is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) while keeping
and monitoring the output of the other DAC. The area of the
glitch is expressed in nV-s.
LDAC
low
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified DNL of 1 LSB maximum ensures monotonic-
ity. This DAC is guaranteed monotonic by design. A typical
DNL error vs. code plot can be seen in Figure 10, Figure 11, and
Figure 12.
DC Crosstalk
This is the dc change in the output level of one DAC in response
to a change in the output of the other DAC. It is measured with
a full-scale output change on one DAC while monitoring the
other DAC. It is expressed in microvolts.
Power Supply Rejection Ratio (PSRR)
Offset Error
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in decibels. VREF is held at 2 V and VDD is varied 10ꢀ.
This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
Gain Error
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
Reference Feedthrough
This is the ratio of the amplitude of the signal at the DAC output to
the reference input when the DAC output is not being updated
Offset Error Drift
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
LDAC
(that is,
is high). It is expressed in decibels.
Total Harmonic Distortion (THD)
This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as
the reference for the DAC and the THD is a measure of the
harmonics present on the DAC output. It is measured in
decibels.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Major-Code Transition Glitch Energy
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC register
changes state. It is normally specified as the area of the glitch in
nV-s and is measured when the digital code is changed by 1 LSB
at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . .
00 to 011 . . . 11).
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Digital Feedthrough
Channel-To-Channel Isolation
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
This is a ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference input of the other DAC. It
is measured in decibels.
SYNC
(
held high). It is specified in nV-s and is measured with a
full-scale change on the digital input pins, that is, from all 0s to
all 1s and vice versa.
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of the other DAC. It is measured
by loading one of the input registers with a full-scale code
LDAC
change (all 0s to all 1s and vice versa) while keeping
LDAC
high. Then pulse
low and monitor the output of the
DAC whose digital code was not changed. The area of the
glitch is expressed in nV-s.
Rev. B | Page 10 of 28
AD5303/AD5313/AD5323
TYPICAL PERFORMANCE CHARACTERISTICS
0.3
0.2
1.0
T
V
= 25°C
= 5V
T
V
= 25°C
= 5V
A
A
DD
DD
0.5
0
0.1
0
–0.1
–0.2
–0.3
–0.5
–1.0
0
0
0
50
100
150
200
250
1000
4000
0
50
100
150
200
250
1000
4000
CODE
CODE
Figure 7. AD5303 Typical INL Plot
Figure 10. AD5303 Typical DNL Plot
3
2
0.6
0.4
T
V
= 25°C
= 5V
T
V
= 25°C
A
A
= 5V
DD
DD
1
0.2
0
0
–1
–2
–3
–0.2
–0.4
–0.6
200
400
600
800
0
200
400
600
800
CODE
CODE
Figure 8. AD5313 Typical INL Plot
Figure 11. AD5313 Typical DNL Plot
12
8
1.0
0.5
T
V
= 25°C
A
T = 25°C
A
= 5V
DD
V
= 5V
DD
4
0
0
–4
–8
–12
–0.5
–1.0
0
1000
2000
3000
1000
2000
3000
CODE
CODE
Figure 9. AD5323 Typical INL Plot
Figure 12. AD5323 Typical DNL Plot
Rev. B | Page 11 of 28
AD5303/AD5313/AD5323
1.00
0.75
0.50
T
V
= 25°C
A
= 5V
DD
V
= 5V
DD
V
= 3V
DD
0.25
MAX INL
MAX DNL
0
MIN DNL
–0.25
–0.50
–0.75
–1.00
MIN INL
0
100
150
200
250
(µA)
300
350
400
2
3
4
5
I
DD
V
(V)
REF
Figure 13. AD5303 INL and DNL Error vs. VREF
Figure 16. IDD Histogram with VDD = 3 V and VDD = 5 V
5
4
1.00
0.75
0.50
0.25
0
V
V
= 5V
DD
= 3V
REF
5V SOURCE
MAX DNL
MAX INL
3V SOURCE
3
2
–0.25
–0.50
–0.75
–1.00
MIN INL
MIN DNL
3V SINK
5V SINK
1
–0
–40
0
40
TEMPERATURE (°C)
80
120
0
1
2
3
4
5
6
SINK/SOURCE CURRENT (mA)
Figure 14. AD5303 INL Error and DNL Error vs. Temperature
Figure 17. Source and Sink Current Capability
1.0
600
500
400
300
200
100
0
T
V
= 25°C
= 5V
V
V
= 5V
=2V
A
DD
DD
REF
0.5
GAIN ERROR
0
OFFSET ERROR
–0.5
–1.0
–40
0
40
80
120
ZERO SCALE
FULL SCALE
TEMPERATURE (°C)
Figure 15. Offset Error and Gain Error vs. Temperature
Figure 18. Supply Current vs. Code
Rev. B | Page 12 of 28
AD5303/AD5313/AD5323
600
500
400
300
200
100
0
V
T
= 5V
DD
= 25°C
BOTH DACS IN GAIN-OF-TWO MODE
REFERENCE INPUTS BUFFERED
A
CLK
CH2
–40°C
+105°C
+25°C
CH1
V
OUT
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
CH1 1V, CH2 5V, TIME BASE = 5µs/DIV
V
DD
Figure 19. Supply Current vs. Supply Voltage
Figure 22. Half-Scale Settling (¼ to ¾ Scale Code Change)
1.0
0.9
0.8
T
= 25°C
A
BOTH DACS IN
THREE-STATE CONDITION
V
DD
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
+25°C
–40°C
CH1
CH2
V
A
OUT
+105°C
4.7 5.2
CH1 1V, CH2 1V, TIME BASE = 20µs/DIV
2.7
3.2
3.7
4.2
(V)
V
DD
Figure 20. Power-Down Current vs. Supply Voltage
Figure 23. Power-On Reset to 0 V
700
600
500
400
300
200
100
T
= 25°C
T
= 25°C
A
A
V
OUT
CH1
CH3
V
= 5V
DD
CLK
V
= 3V
DD
CH1 1V, CH3 5V, TIME BASE = 1µs/DIV
0
0.5
1.0
1.5
2.0
2.5
3.0
(V)
3.5
4.0
4.5
5.0
V
LOGIC
Figure 21. Supply Current vs. Logic Input Voltage
Figure 24. Exiting Power-Down to Midscale
Rev. B | Page 13 of 28
AD5303/AD5313/AD5323
2.50
2.49
2.48
2.47
500ns/DIV
1µs/DIV
Figure 27. DAC-to-DAC Crosstalk
Figure 25. AD5323 Major-Code Transition
10
0
0.10
0.05
0
T
V
= 25°C
A
= 5V
DD
–10
–20
–30
–40
–50
–60
–0.05
–0.10
0
1
2
3
4
5
10
100
1k
10k
100k
1M
10M
V
(V)
FREQUENCY(Hz)
REF
Figure 28. Full-Scale Error vs. VREF (Buffered)
Figure 26. Multiplying Bandwidth (Small-Signal Frequency Response)
Rev. B | Page 14 of 28
AD5303/AD5313/AD5323
FUNCTIONAL DESCRIPTION
The AD5303/AD5313/AD5323 are dual resistor-string DACs
fabricated on a CMOS process with resolutions of 8-/10-/12-bits
respectively. They contain reference buffers and output buffer
amplifiers, and are written to via a 3-wire serial interface. They
operate from single supplies of 2.5 V to 5.5 V and the output
buffer amplifiers provide rail-to-rail output swing with a slew
rate of 0.7 V/μs. Each DAC is provided with a separate reference
input, which may be buffered to draw virtually no current from
the reference source, or unbuffered to give a reference input
range from GND to VDD. The devices have three programmable
power-down modes, in which one or both DACs may be turned
off completely with a high impedance output, or the output may
be pulled low by an on-chip resistor.
RESISTOR STRING
The resistor string section of the AD5303/AD5313/AD5323
is shown in Figure 30. It is simply a string of resistors, each of
value R. The digital code loaded to the DAC register determines
at what node on the string the voltage is tapped off to be fed
into the output amplifier. The voltage is tapped off by closing
one of the switches connecting the string to the amplifier.
Because it is a string of resistors, it is guaranteed monotonic.
R
R
TO OUTPUT
R
AMPLIFIER
DIGITAL-TO-ANALOG
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the VREF pin provides the reference
voltage for the DAC. Figure 29 shows a block diagram of the
DAC architecture. Because the input coding to the DAC is
straight binary, the ideal output voltage is given by
R
R
Figure 30. Resistor String
DAC REFERENCE INPUTS
VREF × D
There is a reference input pin for each of the two DACs. The
reference inputs are buffered, but can also be configured as
unbuffered. The advantage with the buffered input is the high
impedance it presents to the voltage source driving it. However,
if the unbuffered mode is used, the user can have a reference
voltage as low as GND and as high as VDD since there is no
restriction due to headroom and footroom of the reference
amplifier.
VOUT
where:
=
2N
D is the decimal equivalent of the binary code, which is loaded
to the DAC register:
0 to 255 for AD5303 (8 bits)
0 to 1023 for AD5313 (10 bits)
0 to 4095 for AD5323 (12 bits)
N is the DAC resolution.
If there is a buffered reference in the circuit (for example,
REF192), there is no need to use the on-chip buffers of the
AD5303/AD5313/AD5323. In unbuffered mode, the input
impedance is still large at typically 180 kΩ per reference input
for 0 V to VREF mode and 90 kΩ for 0 V to 2 VREF mode.
V
A
REF
SWITCH
CONTROLLED
BY CONTROL
LOGIC
REFERENCE
BUFFER
The buffered/unbuffered option is controlled by the BUF A
and BUF B pins. If a BUF pin is tied high, the reference input
is buffered; if tied low, it is unbuffered.
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V
A
OUT
OUTPUT BUFFER
AMPLIFIER
OUTPUT AMPLIFIER
Figure 29. Single DAC Channel Architecture
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail, which gives an output
range of 0.001 V to VDD − 0.001 V when the reference is VDD.
It is capable of driving a load of 2 kΩ in parallel with 500 pF to
GND and VDD. The source and sink capabilities of the output
amplifier can be seen in Figure 17.
The slew rate is 0.7 V/μs with a half-scale settling time to
0.5 LSB (at eight bits) of 6 μs.
Rev. B | Page 15 of 28
AD5303/AD5313/AD5323
POWER-ON RESET
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
The AD5303/AD5313/AD5323 are provided with a power-on
reset function, so that they power up in a defined state. The
power-on state is with 0V to VREF output range and the output
set to 0 V.
CLEAR FUNCTION (CLR)
CLR
The
pin is an active low input that, when pulled low, loads
Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
all zeros to both input registers and both DAC registers. This
enables both analog outputs to be cleared to 0 V.
Rev. B | Page 1ꢀ of 28
AD5303/AD5313/AD5323
SERIAL INTERFACE
After the end of serial data transfer, data is automatically
transferred from the input shift register to the input register
The AD5303/AD5313/AD5323 are controlled over a versatile,
3-wire serial interface, which operates at clock rates up to
30 MHz and is compatible with SPI, QSPI, MICROWIRE,
and DSP interface standards.
SYNC
of the selected DAC. If
is taken high before the 16th
falling edge of SCLK, the data transfer is aborted and the input
registers are not updated.
INPUT SHIFT REGISTER
When data has been transferred into both input registers, the
DAC registers of both DACs may be simultaneously updated,
The input shift register is 16 bits wide. Data is loaded into
the device as a 16-bit word under the control of a serial clock
input, SCLK. The timing diagram for this operation is shown in
Figure 5. The 16-bit word consists of four control bits followed
by 8 /10 /12 bits of DAC data, depending on the device type.
The first bit loaded is the MSB (Bit 15), which determines whether
the data is for DAC A or DAC B. Bit 14 determines the output
range (0 V to VREF or 0 V to 2 VREF). Bit 13 and Bit 12 control the
operating mode of the DAC.
LDAC
CLR
by taking
low.
is an active low, asynchronous clear
that clears the input and DAC registers of both DACs to all 0s.
LOW POWER SERIAL INTERFACE
To reduce the power consumption of the device even further,
the interface only powers up fully when the device is being
written to. As soon as the 16-bit control word has been written
to the part, the SCLK and DIN input buffers are powered down.
SYNC
They only power up again following a falling edge of
.
Table 6. Control Bits
DOUBLE-BUFFERED INTERFACE
Power-On
Default
Bit Name Function
The DACs all have double-buffered interfaces consisting of two
banks of registers—input registers and DAC registers. The input
register is connected directly to the input shift register and the
digital code is transferred to the relevant input register on com-
pletion of a valid write sequence. The DAC register contains the
digital code used by the resistor string.
15 A/B
0: data written to DAC A
1: data written to DAC B
N/A
14 GAIN
0: output range of 0 V to VREF
1: output range of 0 V to 2 VREF
0
13 PD1
12 PD0
Mode bit
Mode bit
0
0
LDAC
Access to the DAC register is controlled by the
function.
is high, the DAC register is latched and the input
register may change state without affecting the contents of the
LDAC
LDAC
When
The remaining bits are DAC data bits, starting with the MSB
and ending with the LSB. The AD5323 uses all 12 bits of DAC
data; the AD5313 uses 10 bits and ignores the 2 LSBs. The
AD5303 uses eight bits and ignores the last four bits. The data
format is straight binary, with all 0s corresponding to 0 V output,
and all 1s corresponding to full-scale output (VREF − 1 LSB).
DAC register. However, when
is brought low, the DAC
register becomes transparent and the contents of the input reg-
ister are transferred to it.
This is useful if the user requires simultaneous updating of
both DAC outputs. The user may write to both input registers
SYNC
The
synchronization signal and chip enable. Data can be transferred
SYNC
input is a level-triggered input that acts as a frame
LDAC
individually and then, by pulsing the
outputs update simultaneously.
input low, both
into the device only while
is low. To start the serial data
SYNC
transfer,
SYNC
should be taken low, observing the minimum
These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
SYNC
to SCLK rising edge setup time, t4. After
goes low,
LDAC
LDAC
the last time that
was brought low. Normally, when
serial data is shifted into the device’s input shift register on the
falling edges of SCLK for 16 clock pulses. Any data and clock
pulses after the 16th are ignored, and no further serial data
is brought low, the DAC registers are filled with the contents of
the input registers. In the case of the AD5303/AD5313/AD5323,
the part only updates the DAC register if the input register has
been changed since the last time the DAC register was updated,
thereby removing unnecessary digital crosstalk.
SYNC
transfer occurs until
is taken high and low again.
SYNC
may be taken high after the falling edge of the 16th SCLK
pulse, observing the minimum SCLK falling edge to
rising edge time, t7.
SYNC
Rev. B | Page 17 of 28
AD5303/AD5313/AD5323
DB15 (MSB)
DB0 (LSB)
A/B GAIN PD1 PD0 D7
D6
D5
D4
D3
D2
D1 D0
X
X
X
X
DATA BITS
Figure 31. AD5303 Input Shift Register Contents
DB15 (MSB)
DB0 (LSB)
A/B GAIN PD1 PD0
D7
D6
D5
D4
D3 D2
D1
D0
X
X
D9
D8
DATA BITS
Figure 32. AD5313 Input Shift Register Contents
DB15 (MSB)
DB0 (LSB)
D1 D0
A/B GAIN PD1 PD0
D7
D6
D5
D4
D3
D2
D11 D10 D9
D8
DATA BITS
Figure 33. AD5323 Input Shift Register Contents
Rev. B | Page 18 of 28
AD5303/AD5313/AD5323
POWER-DOWN MODES
There are three different power-down options. The output is
connected internally to GND through either a 1 kΩ resistor or
a 100 kΩ resistor, or it is left in a high impedance state (three-
state). The output stage is illustrated in Figure 34.
The AD5303/AD5313/AD5323 have very low power consump-
tion, dissipating only 0.7 mW with a 3 V supply and 1.5 mW
with a 5 V supply. Power consumption can be further reduced
when the DACs are not in use by putting them into one of three
power-down modes, which are selected by Bit 13 and Bit 12
(PD1 and PD0) of the control word. Table 7 shows how the
state of the bits corresponds to the mode of operation of that
particular DAC.
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 μs for VDD = 5 V and 5 μs when
Table 7. PD1/PD0 Operating Modes
V
DD = 3 V (see Figure 24 for a plot).
The software power-down modes programmed by PD0 and
PD
PD1
PD0
Operating Mode
0
0
1
1
0
1
0
1
Normal operation
PD1 are overridden by the
pin. Taking this pin low puts
Power-down (1 kΩ load to GND)
Power-down (100 kΩ load to GND)
Power-down (high impedance output)
both DACs into power-down mode simultaneously and both
PD
outputs are put into a high impedance state. If
it should be tied high.
is not used,
AMPLIFIER
When both bits are set to 0, the DACs work normally with their
normal power consumption of 300 μA at 5 V. However, for the
three power-down modes, the supply current falls to 200 nA at
5 V (50 nA at 3 V) when both DACs are powered down. Not
only does the supply current drop, but the output stage is also
internally switched from the output of the amplifier to a resistor
network of known values. This has the advantage that the
output impedance of the part is known while the part is in
power-down mode and provides a defined input condition
for whatever is connected to the output of the DAC amplifier.
RESISTOR
STRING DAC
V
OUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 34. Output Stage During Power-Down
Rev. B | Page 19 of 28
AD5303/AD5313/AD5323
MICROPROCESSER INTERFACING
AD5303/AD5313/AD5323 TO ADSP-2101
INTERFACE
AD5303/AD5313/AD5323 TO 80C51/80L51
INTERFACE
Figure 35 shows a serial interface between the AD5303/AD5313/
AD5323 and the ADSP-2101. The ADSP-2101 should be set up
to operate in the SPORT transmit alternate framing mode. The
ADSP-2101 sport is programmed through the SPORT control
register and should be configured as follows: internal clock
operation, active-low framing, 16-bit word length. Transmission
is initiated by writing a word to the Tx register after the SPORT
has been enabled.
Figure 37 shows a serial interface between the AD5303/
AD5313/AD5323 and the 80C51/80L51 microcontroller. The
setup for the interface is as follows: TXD of the 80C51/80L51
drives SCLK of the AD5303/AD5313/AD5323, while RXD
SYNC
drives the serial data line of the part. The
signal is again
derived from a bit programmable pin on the port. In this case,
port line P3.3 is used. When data is to be transmitted to the
AD5303/AD5313/AD5323, P3.3 is taken low. The 80C51/80L51
transmits data only in 8-bit bytes; thus only eight falling clock
edges occur in the transmit cycle. To load data to the DAC, P3.3
is left low after the first eight bits are transmitted and a second
write cycle is initiated to transmit the second byte of data. P3.3
is taken high following the completion of this cycle. The 80C51/
80L51 output the serial data in a format that has the LSB first.
The AD5303/AD5313/AD5323 require data with MSB as the
first bit received. The 80C51/80L51 transmit routine should
take this into account.
ADSP-2101
AD5303/
AD5313/
AD5323*
SYNC
TFS
DT
DIN
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 35. AD5303/AD5313/AD5323 to ADSP-2101 Interface
AD5303/AD5313/AD5323 TO 68HC11/68L11
INTERFACE
80C51/80L51*
AD5303/
AD5313/
AD5323*
Figure 36 shows a serial interface between the AD5303/
AD5313/AD5323 and the 68HC11/68L11 microcontroller.
SCK of the 68HC11/68L11 drives the SCLK of the AD5303/
AD5313/AD5323, while the MOSI output drives the serial data
SYNC
P3.3
TXD
RXD
SCLK
DIN
SYNC
line (DIN) of the DAC. The
signal is derived from a port
*ADDITIONAL PINS OMITTED FOR CLARITY.
line (PC7). The setup conditions for correct operation of this
interface are as follows: the 68HC11/68L11 should be con-
figured so that its CPOL bit is a 0 and its CPHA bit is a 1.
Figure 37. AD5303/AD5313/AD5323 to 80C51/80L51 Interface
AD5303/AD5313/AD5323 TO MICROWIRE
INTERFACE
SYNC
When data is being transmitted to the DAC, the
line
Figure 38 shows an interface between the AD5303/AD5313/
AD5323 and any MICROWIRE-compatible device. Serial
data is shifted out on the falling edge of the serial clock and
is clocked into the AD5303/AD5313/AD5323 on the rising
edge of the SK.
is taken low (PC7). When the 68HC11/68L11 is configured
as previously mentioned, data appearing on the MOSI output
is valid on the falling edge of SCK. Serial data from the 68HC11/
68L11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
first. To load data to the AD5303/AD5313/ AD5323, PC7 is left
low after the first eight bits are transferred and a second serial
write operation is performed to the DAC; PC7 is taken high at
the end of this procedure.
AD5303/
AD5313/
AD5323*
MICROWIRE*
CS
SYNC
SK
SO
SCLK
DIN
68HC11/68L11*
AD5303/
AD5313/
AD5323*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
PC7
SCK
Figure 38. AD5303/AD5313/AD5323 to MICROWIRE Interface
SCLK
DIN
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 36. AD5303/AD5313/AD5323 to 68HC11/68L11 Interface
Rev. B | Page 20 of 28
AD5303/AD5313/AD5323
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
15V
V
S
0.1µF
10µF
The AD5303/AD5313/AD5323 can be used with a wide range
of reference voltages, especially if the reference inputs are con-
figured to be unbuffered, in which case the devices offer a full,
one-quadrant multiplying capability over a reference range of
0 V to VDD.
REF195
OUTPUT
GND
V
DD
V
A
OUT
1µF
V
V
A
B
REF
REF
AD5303/AD5313/
AD5323
SCLK
More typically, the AD5303/AD5313/AD5323 may be used
with a fixed precision reference voltage. Figure 39 shows a
typical setup for the AD5303/AD5313/AD5323 when using
an external reference. If the reference inputs are unbuffered,
the reference input range is from 0 V to VDD, but if the on-chip
reference buffers are used, the reference range is reduced. Suit-
able references for 5 V operation are the AD780 and REF192
(2.5 V references). For 2.5 V operation, a suitable external
reference is the REF191, a 2.048 V reference.
DIN
V
B
OUT
SYNC
GND BUF A BUF B
SERIAL
INTERFACE
Figure 40. Using an REF195 as Power and Reference to the
AD5303/AD5313/AD5323
BIPOLAR OPERATION USING THE AD5303/
AD5313/AD5323
V
= 2.5V to 5.5V
DD
The AD5303/AD5313/AD5323 have been designed for single-
supply operation, but bipolar operation is also achievable using
the circuit shown in Figure 41. The circuit shown has been con-
figured to achieve an output voltage range of −5 V < VOUT < +5 V.
Rail-to-rail operation at the amplifier output is achievable using
an AD820 or OP295 as the output amplifier.
V
DD
EXT
REF
V
OUT
V
V
A
B
V
A
REF
OUT
1µF
REF
AD780/REF192
WITH V = 5V
OR REF191 WITH
AD5303/AD5313/
DD
AD5323
V
= 2.5V
DD
SCLK
DIN
V
B
6V to 16V
OUT
SYNC
R2
10kΩ
GND BUF A BUF B
V
= 5V
DD
0.1µF
10µF
SERIAL
INTERFACE
+5V
R1
10kΩ
V
S
Figure 39. AD5303/AD5313/AD5323 Using External Reference
±5V
REF195
OUTPUT
GND
V
DD
AD820/
OP295
If an output range of 0 V to VDD is required when the reference
inputs are configured as unbuffered (for example, 0 V to 5 V),
the simplest solution is to connect the reference inputs to VDD.
As this supply may not be very accurate and may be noisy, the
AD5303/AD5313/AD5323 can be powered from the reference
voltage, for example, using a 5 V reference such as the REF195,
as shown in Figure 40. The REF195 outputs a steady supply
voltage for the AD5303/AD5313/AD5323. The supply current
required from the REF195 is 300 μA and approximately 30 μA
or 60 μA into each of the reference inputs (if unbuffered). This
is with no load on the DAC outputs. When the DAC outputs are
loaded, the REF195 also needs to supply the current to the
loads. The total current required (with a 10 kΩ load on each
output) is
V
A/B
REF
–5V
1µF
AD5303/AD5313/
AD5323
SCLK
DIN
V
A/B
OUT
SYNC
GND BUF A BUF B
SERIAL
INTERFACE
Figure 41. Bipolar Operation Using the AD5303/AD5313/AD5323
The output voltage for any input code can be calculated as
follows:
VOUT
=
(VREF ) × (D / 2N ) × (R1 + R2)/ R1 − VREF × (R2 / R1)
]
where:
360 μA + 2(5 V/10 kΩ) = 1.36 mA
D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
The load regulation of the REF195 is typically 2 ppm/mA, which
results in an error of 2.7 ppm (13.5 μV) for the 1.36 mA current
drawn from it. This corresponds to a 0.0007 LSB error at eight
bits and 0.011 LSB error at 12 bits.
V
REF is the reference voltage input, and gain bit = 0, with
REF = 5 V
V
R1 = R2 = 10 kΩ and VDD = 5 V,
VOUT = (10 × D /2N ) − 5V
Rev. B | Page 21 of 28
AD5303/AD5313/AD5323
SCLK
DIN
OPTO-ISOLATED INTERFACE FOR PROCESS
CONTROL APPLICATIONS
AD5303/
SYNC AD5313/
DIN
SCLK
AD5323
V
V
DD
The AD5303/AD5313/AD5323 has a versatile 3-wire serial
interface making it ideal for generating accurate voltages in
process control and industrial applications. Due to noise, safety
requirements, or distance, it may be necessary to isolate the
AD5303/AD5313/AD5323 from the controller. This can easily
be achieved by using opto-isolators, which provides isolation
in excess of 3 kV. The serial loading structure of the AD5303/
AD5313/AD5323 makes it ideally suited for use in opto-isolated
applications. Figure 42 shows an opto-isolated interface to the
CC
1G
1A
1B
ENABLE
1Y0
1Y1
1Y2
1Y3
AD5303/
SYNC AD5313/
74HC139
CODED
ADDRESS
DIN
SCLK
AD5323
DGND
AD5303/
SYNC AD5313/
DIN
SCLK
AD5323
SYNC
AD5303/AD5313/AD5323 where DIN, SCLK, and
are
driven from opto-couplers. The power supply to the part also
needs to be isolated. This is done by using a transformer. On the
DAC side of the transformer, a 5 V regulator provides the 5 V
supply required for the AD5303/AD5313/AD5323.
AD5303/
SYNC AD5313/
DIN
SCLK
AD5323
Figure 43. Decoding Multiple AD5303/AD5313/AD5323 Devices in a System
5V
REGULATOR
10µF
0.1µF
POWER
AD5303/AD5313/AD5323 AS A DIGITALLY
PROGRAMMABLE WINDOW DETECTOR
V
DD
DD
DD
A digitally programmable upper/lower limit detector using
the two DACs in the AD5303/AD5313/AD5323 is shown in
Figure 44. The upper and lower limits for the test are loaded
to DAC A and DAC B, which, in turn, set the limits on the
CMP04. If the signal at the VIN input is not within the pro-
grammed window, an LED indicates the fail condition.
5V
10kΩ
V
DD
SCLK
SCLK
V
A
REF
V
B
REF
AD5303/AD5313/
AD5323
V
10kΩ
V
A
OUT
SYNC
0.1µF
10µF
SYNC
V
IN
1kΩ
1kΩ
V
B
OUT
FAIL
PASS
V
DD
V
V
V
A
REF
REF
V
V
A
OUT
B
REF
10kΩ
AD5303/AD5313/
1/2
CMP04
PASS/FAIL
1/6 74HC05
AD5323
DIN
DIN
GND BUF A BUF B
SYNC
SYNC
DIN
DIN
V
B
SCLK
SCLK
OUT
GND
Figure 42. AD5303/AD5313/AD5323 in an Opto-Isolated Interface
Figure 44. Window Detector Using AD5303/AD5313/AD5323
DECODING MULTIPLE AD5303/AD5313/AD5323s
SYNC
The
pin on the AD5303/AD5313/AD5323 can be used
in applications to decode a number of DACs. In this application,
all the DACs in the system receive the same serial clock and
SYNC
serial data, but only the
to one of the devices is active at
any one time, allowing access to two channels in this 8-channel
system. The 74HC139 is used as a 2-to-4 line decoder to address
any of the DACs in the system. To prevent timing errors from
occurring, the enable input should be brought to its inactive
state while the coded address inputs are changing state.
Figure 43 shows a diagram of a typical setup for decoding
multiple AD5303/AD5313/AD5323 devices in a system.
Rev. B | Page 22 of 28
AD5303/AD5313/AD5323
A continuous SCLK source may be used if it can be arranged
COARSE AND FINE ADJUSTMENT USING THE
AD5303/AD5313/AD5323
SYNC
that
is held low for the correct number of clock cycles.
Alternatively, a burst clock containing the exact number of
The DACs in the AD5303/AD5313/AD5323 can be paired
together to form a coarse and fine adjustment function, as
shown in Figure 45. DAC A provides the coarse adjustment
while DAC B provides the fine adjustment. Varying the ratio
of R1 and R2 changes the relative effect of the coarse and fine
adjustments. With the resistor values and external reference
shown, the output amplifier has unity gain for the DAC A
output, so the output range is 0 V to 2.5 V − 1 LSB. For
DAC B, the amplifier has a gain of 7.6 × 10–3, giving DAC B
a range equal to 19 mV.
SYNC
clock cycles may be used and
time later.
may be taken high some
When the transfer to all input registers is complete, a common
LDAC
signal updates all DAC registers and all analog outputs
are updated simultaneously.
AD5303/
AD5313/
AD53231
(DAC 1)
68HC111
MOSI
SCK
DIN
SCLK
The circuit is shown with a 2.5 V reference, but reference
voltages up to VDD may be used. The op amps indicated allow
a rail-to-rail output swing.
SYNC
LDAC
PC7
PC6
MISO
SDO
DIN
V
= 5V
DD
R3
R4
AD5303/
AD5313/
AD53231
(DAC 2)
51.2kΩ
900Ω
+5V
0.1µF
1µF
10µF
V
IN
SCLK
SYNC
LDAC
EXT 2.5V
REF
V
DD
V
OUT
R1
V
OUT
V
A
V
A
OUT
REF
AD820/
OP295
390Ω
GND
SDO
AD5303/AD5313/
AD5323
AD780/REF192
WITH V = 5V
DIN
DD
R2
AD5303/
AD5313/
AD53231
(DAC N)
V
B
V
B
OUT
REF
51.2kΩ
GND
SCLK
SYNC
LDAC
Figure 45. Coarse and Fine Adjustment
SDO
DAISY-CHAIN MODE
1
ADDITIONAL PINS OMITTED FOR CLARITY.
This mode is used for updating serially connected or standalone
SYNC
Figure 46. Daisy-Chain Mode
devices on the rising edge of
. For systems that contain
several DACs, or where the user wishes to read back the DAC
contents for diagnostic purposes, the SDO pin may be used to
daisy-chain several devices together and provide serial readback.
By connecting the daisy-chain enable (DCEN) pin high, the
daisy-chain mode is enabled. It is tied low in standalone mode.
In daisy-chain mode, the internal gating on SCLK is disabled.
The SCLK is continuously applied to the input shift register
SYNC
when
is low. If more than 16 clock pulses are applied,
the data ripples out of the shift register and appears on the SDO
line. This data is clocked out after the falling edge of SCLK and
is valid on the subsequent rising and falling edges. By connect-
ing this line to the DIN input on the next DAC in the chain, a
multiDAC interface is constructed. Sixteen clock pulses are
required for each DAC in the system. Therefore, the total
number of clock cycles must equal 16N, where N is the total
number of devices in the chain. When the serial transfer to all
SYNC
devices is complete,
should be taken high. This prevents
any further data from being clocked into the input shift register.
Rev. B | Page 23 of 28
AD5303/AD5313/AD5323
t1
SCLK
t2
t14
t3
t8
t4
t6
SYNC
t15
t5
DIN
DB15
DB0
DB15
DB15
DB0
DB0
INPUT WORD FOR DAC N
UNDEFINED
INPUT WORD FOR DAC (N+1)
INPUT WORD FOR DAC N
SDO
SCLK
SDO
t13
V
IH
V
IL
t12
Figure 47. Daisy-Chaining Timing Diagram
(ESI), like the common ceramic types that provide a low
impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
POWER SUPPLY BYPASSING AND GROUNDING
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5303/AD5313/AD5323 are mounted should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. If the AD5303/
AD5313/AD5323 are in a system where multiple devices
require an AGND-to-DGND connection, the connection
should be made at one point only. The star ground point
should be established as close as possible to the AD5303/
AD5313/AD5323. The AD5303/AD5313/AD5323 should
have ample supply bypassing of 10 μF in parallel with 0.1 μF
on the supply located as close to the package as possible, ideally
right up against the device. Use 10 μF capacitors that are of the
tantalum bead type. The 0.1 μF capacitor should have low
effective series resistance (ESR) and effective series inductance
The power supply lines of the AD5303/AD5313/AD5323 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Fast
switching signals such as clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board, and
should never be run near the reference inputs. Avoid crossover
of digital and analog signals. Traces on opposite sides of the
board should run at right angles to each other. This reduces
the effects of feedthrough through the board. A microstrip
technique is by far the best, but is not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to the ground plane while signal traces
are placed on the solder side.
Rev. B | Page 24 of 28
AD5303/AD5313/AD5323
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 48. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5303ARU
AD5303ARU-REEL7
AD5303ARUZ1
AD5303BRU
Temperature Range
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
Package Description
Package Option
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
RU-1ꢀ
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
1ꢀ-Lead Thin Shrink Small Outline Package (TSSOP)
AD5303BRU-REEL
AD5303BRU-REEL7
AD5303BRUZ1
AD5303BRUZ-REEL71
AD5313ARU
AD5313ARU-REEL7
AD5313ARUZ1
AD5313BRU
AD5313BRU-REEL
AD5313BRU-REEL7
AD5313BRUZ1
AD5323ARU
AD5323ARU-REEL7
AD5323ARUZ1
AD5323ARUZ-REEL71
AD5323BRU
AD5323BRU-REEL
AD5323BRU-REEL7
AD5323BRUZ1
AD5323BRUZ-REEL1
AD5323BRUZ-REEL71
1 Z = RoHS Compliant Part.
Rev. B | Page 25 of 28
AD5303/AD5313/AD5323
NOTES
Rev. B | Page 2ꢀ of 28
AD5303/AD5313/AD5323
NOTES
Rev. B | Page 27 of 28
AD5303/AD5313/AD5323
NOTES
©1999–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00472-0-6/07(B)
Rev. B | Page 28 of 28
相关型号:
AD5313BRU-REEL
SERIAL INPUT LOADING, 7us SETTLING TIME, 10-BIT DAC, PDSO16, MO-153AB, TSSOP-16
ROCHESTER
AD5313BRU-REEL7
SERIAL INPUT LOADING, 7us SETTLING TIME, 10-BIT DAC, PDSO16, MO-153AB, TSSOP-16
ROCHESTER
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