AD5300* [ADI]

+2.7 V to +5.5 V. 140 uA. Rail-to-Rail Output 8-Bit DAC in an SOT-23 ; +2.7 V至+5.5 V. 140微安。轨至轨输出8位DAC采用SOT -23\n
AD5300*
型号: AD5300*
厂家: ADI    ADI
描述:

+2.7 V to +5.5 V. 140 uA. Rail-to-Rail Output 8-Bit DAC in an SOT-23
+2.7 V至+5.5 V. 140微安。轨至轨输出8位DAC采用SOT -23\n

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a+2.7 V to +5.5 V, 140 A, Rail-to-Rail Output  
8-Bit DAC in an SOT-23  
AD5300*  
FEATURES  
Single 8-Bit DAC  
FUNCTIONAL BLOCK DIAGRAM  
V
GND  
DD  
6-Lead SOT-23 and 8-Lead SOIC Packages  
Micropower Operation: 140 A @ 5 V  
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V  
+2.7 V to +5.5 V Power Supply  
Guaranteed Monotonic by Design  
Reference Derived from Power Supply  
Power-On-Reset to Zero Volts  
Three Power-Down Functions  
Low Power Serial Interface with Schmitt-Triggered  
Inputs  
POWER-ON  
RESET  
AD5300  
REF(+) REF(–)  
DAC  
REGISTER  
OUTPUT  
BUFFER  
V
8-BIT  
DAC  
OUT  
INPUT  
CONTROL  
LOGIC  
POWER-DOWN  
CONTROL LOGIC  
RESISTOR  
NETWORK  
On-Chip Output Buffer Amplifier, Rail-to-Rail  
Operation  
SYNC Interrupt Facility  
DIN  
SYNC SCLK  
APPLICATIONS  
Portable Battery Powered Instruments  
Digital Gain and Offset Adjustment  
Programmable Voltage and Current Sources  
Programmable Attenuators  
GENERAL DESCRIPTION  
PRODUCT HIGHLIGHTS  
The AD5300 is a single, 8-bit buffered voltage out DAC that  
operates from a single +2.7 V to +5.5 V supply consuming  
115 µA at 3 V. Its on-chip precision output amplifier allows  
rail-to-rail output swing to be achieved. The AD5300 utilizes a  
versatile three-wire serial interface that operates at clock rates up  
to 30 MHz and is compatible with standard SPI™, QSPI™,  
MICROWIRE™ and DSP interface standards.  
1. Available in 6-lead SOT-23 and 8-lead µSOIC packages.  
2. Low power, single supply operation. This part operates from  
a single +2.7 V to +5.5 V supply and typically consumes  
0.35 mW at 3 V and 0.7 mW at 5 V, making it ideal for  
battery powered applications.  
3. The on-chip output buffer amplifier allows the output of the  
DAC to swing rail-to-rail with a slew rate of 1 V/µs.  
The reference for AD5300 is derived from the power supply  
inputs and thus gives the widest dynamic output range. The part  
incorporates a power-on-reset circuit that ensures that the DAC  
output powers up to zero volts and remains there until a valid  
write takes place to the device. The part contains a power-down  
feature that reduces the current consumption of the device to  
200 nA at 5 V and provides software selectable output loads  
while in power-down mode. The part is put into power-down  
mode over the serial interface.  
4. Reference derived from the power supply.  
5. High speed serial interface with clock speeds up to 30 MHz.  
Designed for very low power consumption. The interface  
only powers up during a write cycle.  
6. Power-down capability. When powered down the DAC  
typically consumes 50 nA at 3 V and 200 nA at 5 V.  
The low power consumption of this part in normal operation  
makes it ideally suited to portable battery operated equipment.  
The power consumption is 0.7 mW at 5 V reducing to 1 µW in  
power-down mode.  
The AD5300 is one of a family of pin-compatible DACs. The  
AD5310 is the 10-bit version and the AD5320 is the 12-bit  
version. The AD5300/AD5310/AD5320 are available in 6-lead  
SOT-23 packages and 8-lead µSOIC packages.  
SPI and QSPI are trademarks of Motorola, Inc.  
MICROWIRE is a trademark of National Semiconductor Corporation.  
*Patent pending; protected by U.S. Patent No. 5684481.  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 1999  
(VDD = +2.7 V to +5.5 V; RL = 2 kto GND; CL = 500 pF to GND; all specifications  
MIN to TMAX unless otherwise noted)  
B Version1  
T
AD5300–SPECIFICATIONS  
Parameter  
Min  
Typ  
Max  
Units  
Conditions/Comments  
STATIC PERFORMANCE2  
Resolution  
8
Bits  
Relative Accuracy  
±1  
LSB  
See Figure 2.  
Differential Nonlinearity  
Zero Code Error  
Full-Scale Error  
Gain Error  
Zero Code Error Drift  
Gain Temperature Coefficient  
±0.25  
+3.5  
–3.5  
±1.25  
LSB  
LSB  
LSB  
% of FSR  
µV/°C  
ppm of FSR/°C  
Guaranteed Monotonic by Design. See Figure 3.  
All Zeros Loaded to DAC Register. See Figure 6.  
All Ones Loaded to DAC Register. See Figure 6.  
+0.5  
–0.5  
–20  
–5  
OUTPUT CHARACTERISTICS3  
Output Voltage Range  
Output Voltage Settling Time  
0
VDD  
6
V
µs  
4
1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex).  
RL = 2 k; 0 pF < CL < 500 pF. See Figure 16.  
Slew Rate  
Capacitive Load Stability  
1
V/µs  
pF  
pF  
nV-s  
nV-s  
mA  
mA  
µs  
470  
1000  
20  
0.5  
1
50  
20  
2.5  
5
RL =  
RL = 2 kΩ  
Digital-to-Analog Glitch Impulse  
Digital Feedthrough  
DC Output Impedance  
Short Circuit Current  
1 LSB Change Around Major Carry. See Figure 19.  
V
V
DD = +5 V  
DD = +3 V  
Power-Up Time  
Coming Out of Power-Down Mode. VDD = +5 V  
Coming Out of Power-Down Mode. VDD = +3 V  
µs  
LOGIC INPUTS3  
Input Current  
±1  
0.8  
0.6  
µA  
V
V
V
V
V
V
V
V
INL, Input Low Voltage  
INL, Input Low Voltage  
INH, Input High Voltage  
INH, Input High Voltage  
VDD = +5 V  
VDD = +3 V  
VDD = +5 V  
VDD = +3 V  
2.4  
2.1  
Pin Capacitance  
3
pF  
POWER REQUIREMENTS  
VDD  
2.7  
5.5  
V
I
DD (Normal Mode)  
DAC Active and Excluding Load Current  
VIH = VDD and VIL = GND  
VIH = VDD and VIL = GND  
V
V
DD = +4.5 V to +5.5 V  
DD = +2.7 V to +3.6 V  
140  
115  
250  
200  
µA  
µA  
I
DD (All Power-Down Modes)  
DD = +4.5 V to +5.5 V  
VDD = +2.7 V to +3.6 V  
V
0.2  
0.05  
1
1
µA  
µA  
VIH = VDD and VIL = GND  
VIH = VDD and VIL = GND  
POWER EFFICIENCY  
IOUT/IDD  
93  
%
ILOAD = 2 mA. VDD = +5 V  
NOTES  
1Temperature ranges are as follows: B Version: –40°C to +105°C.  
2Linearity calculated using a reduced code range of 4 to 251. Output unloaded.  
3Guaranteed by design and characterization, not production tested.  
Specifications subject to change without notice.  
–2–  
REV. A  
AD5300  
TIMING CHARACTERISTICS1, 2  
(VDD = +2.7 V to +5.5 V; all specifications TMIN to TMAX unless otherwise noted)  
Limit at TMIN, TMAX  
VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V  
Parameter  
Units  
Conditions/Comments  
3
t1  
50  
13  
22.5  
0
5
4.5  
33  
13  
13  
0
5
4.5  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
SCLK Cycle Time  
SCLK High Time  
SCLK Low Time  
SYNC to SCLK Rising Edge Setup Time  
Data Setup Time  
Data Hold Time  
SCLK Falling Edge to SYNC Rising Edge  
Minimum SYNC High Time  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
0
50  
0
33  
NOTES  
1All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.  
2See Figure 1.  
3Maximum SCLK frequency is 30 MHz at VDD = +3.6 V to +5.5 V and 20 MHz at VDD = +2.7 V to +3.6 V.  
Specifications subject to change without notice.  
t1  
SCLK  
t8  
t2  
t7  
t3  
t4  
SYNC  
t6  
t5  
DB0  
DIN  
DB15  
Figure 1. Serial Write Operation  
*Stresses above those listed under Absolute Maximum Ratings may cause perma-  
ABSOLUTE MAXIMUM RATINGS*  
nent damage to the device. This is a stress rating only; functional operation of the  
device at these or any other conditions above those listed in the operational sections  
of this specification is not implied. Exposure to absolute maximum rating condi-  
tions for extended periods may affect device reliability.  
(TA = +25°C unless otherwise noted)  
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V  
Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V  
VOUT to GND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V  
Operating Temperature Range  
ORDERING GUIDE  
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C  
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C  
Junction Temperature (TJ Max) . . . . . . . . . . . . . . . . .+150°C  
SOT-23 Package  
Power Dissipation . . . . . . . . . . . . . . . . . . . (TJ Max–TA)/θJA  
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 240°C/W  
Lead Temperature, Soldering  
Temperature  
Range  
Branding  
Information Options*  
Package  
Model  
AD5300BRT –40°C to +105°C  
AD5300BRM –40°C to +105°C  
D2B  
D2B  
RT-6  
RM-8  
*RT = SOT-23; RM = µSOIC.  
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C  
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C  
µSOIC Package  
Power Dissipation . . . . . . . . . . . . . . . . . . . (TJ Max–TA)/θJA  
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W  
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W  
Lead Temperature, Soldering  
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C  
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C  
CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection.  
Although the AD5300 features proprietary ESD protection circuitry, permanent damage may  
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD  
precautions are recommended to avoid performance degradation or loss of functionality.  
WARNING!  
ESD SENSITIVE DEVICE  
REV. A  
–3–  
AD5300  
PIN CONFIGURATIONS  
SOT-23  
SOIC  
1
2
3
1
8
7
6
5
V
GND  
DIN  
6
5
4
SYNC  
SCLK  
DIN  
V
OUT  
DD  
AD5300  
TOP VIEW  
(Not to Scale)  
2
3
4
GND  
NC  
NC  
AD5300  
TOP VIEW  
(Not to Scale)  
V
SCLK  
SYNC  
DD  
V
OUT  
NC = NO CONNECT  
PIN FUNCTION DESCRIPTIONS  
SOT-23 Pin Numbers  
Pin  
No.  
Mnemonic  
Function  
1
2
3
VOUT  
GND  
VDD  
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.  
Ground reference point for all circuitry on the part.  
Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and VDD should be de-  
coupled to GND.  
4
5
6
DIN  
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the  
falling edge of the serial clock input.  
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock  
input. Data can be transferred at rates up to 30 MHz.  
Level triggered control input (active low). This is the frame synchronization signal for the input  
data. When SYNC goes low, it enables the input shift register and data is transferred in on the fall-  
ing edges of the following clocks. The DAC is updated following the 16th clock cycle unless SYNC  
is taken high before this edge in which case the rising edge of SYNC acts as an interrupt and the  
write sequence is ignored by the DAC.  
SCLK  
SYNC  
–4–  
REV. A  
AD5300  
TERMINOLOGY  
Gain Error  
Relative Accuracy  
This is a measure of the span error of the DAC. It is the devia-  
tion in slope of the DAC transfer characteristic from ideal ex-  
pressed as a percent of the full-scale range.  
For the DAC, relative accuracy or Integral Nonlinearity (INL)  
is a measure of the maximum deviation, in LSBs, from a straight  
line passing through the endpoints of the DAC transfer func-  
tion. A typical INL vs. code plot can be seen in Figure 2.  
Total Unadjusted Error  
Total Unadjusted Error (TUE) is a measure of the output error  
taking into account all the various errors. A typical TUE vs.  
code plot can be seen in Figure 4.  
Differential Nonlinearity  
Differential Nonlinearity (DNL) is the difference between the  
measured change and the ideal 1 LSB change between any two  
adjacent codes. A specified differential nonlinearity of ±1 LSB  
maximum ensures monotonicity. This DAC is guaranteed  
monotonic by design. A typical DNL vs. code plot can be seen  
in Figure 3.  
Zero-Code Error Drift  
This is a measure of the change in zero-code error with a  
change in temperature. It is expressed in µV/°C.  
Gain Error Drift  
This is a measure of the change in gain error with changes in  
temperature. It is expressed in (ppm of full-scale range)/°C.  
Zero-Code Error  
Zero-code error is a measure of the output error when zero code  
(00 Hex) is loaded to the DAC register. Ideally the output  
should be 0 V. The zero-code error is always positive in the  
AD5300 because the output of the DAC cannot go below 0 V.  
It is due to a combination of the offset errors in the DAC and  
output amplifier. Zero-code error is expressed in LSBs. A plot  
of zero-code error vs. temperature can be seen in Figure 6.  
Digital-to-Analog Glitch Impulse  
Digital-to-analog glitch impulse is the impulse injected into the  
analog output when the input code in the DAC register changes  
state. It is normally specified as the area of the glitch in nV secs  
and is measured when the digital input code is changed by  
1 LSB at the major carry transition (7F Hex to 80 Hex). See  
Figure 19.  
Full-Scale Error  
Digital Feedthrough  
Full-scale error is a measure of the output error when full-scale  
code (FF Hex) is loaded to the DAC register. Ideally the output  
should be VDD – 1 LSB. Full-scale error is expressed in LSBs. A  
plot of full-scale error vs. temperature can be seen in Figure 6.  
Digital feedthrough is a measure of the impulse injected into the  
analog output of the DAC from the digital inputs of the DAC,  
but is measured when the DAC output is not updated. It is  
specified in nV secs and is measured with a full-scale code  
change on the data bus, i.e., from all 0s to all 1s and vice versa.  
REV. A  
–5–  
AD5300–Typical Performance Characteristics  
0.5  
1
0.5  
0
1.0  
0.5  
0
T
= +25؇C  
A
0.4  
TUE @ 3V  
T
= +25؇C  
A
0.3  
INL @ 3V  
0.2  
DNL @ 5V  
DNL @ 3V  
0.1  
INL @ 5V  
TUE @ 5V  
0
–0.1  
–0.2  
–0.3  
–0.4  
–0.5  
–0.5  
–1  
–0.5  
–1.0  
T
= +25؇C  
A
0
50  
100  
150  
200  
250  
50  
100  
150  
CODE  
200  
250  
0
50  
100  
150  
200  
250  
0
CODE  
CODE  
Figure 2. Typical INL Plot  
Figure 3. Typical DNL Plot  
Figure 4. Typical Total Unadjusted  
Error Plot  
3
2
1
1
2500  
V
= +5V  
DD  
V
= +5V  
DD  
V
= +5V  
DD  
2000  
1500  
0.5  
0
V
= +3V  
DD  
MAX INL  
ZS ERROR  
FS ERROR  
MAX DNL  
0
MIN DNL  
MIN INL  
1000  
500  
0
–1  
–0.5  
–2  
–3  
–1  
100 110 120 130 140 150 160 170 180190  
50 60 70 80 90  
–40  
0
40  
80  
120  
–40  
0
40  
80  
120  
I
A  
DD  
TEMPERATURE – ؇C  
TEMPERATURE – ؇C  
Figure 5. INL Error and DNL Error  
vs. Temperature  
Figure 7. IDD Histogram with  
Figure 6. Zero-Scale Error and Full-  
Scale Error vs. Temperature  
VDD = 3 V and VDD = 5 V  
5
3
500  
400  
300  
200  
100  
0
T
= +25؇C  
A
DAC LOADED WITH FF HEX  
4
DAC LOADED WITH FF HEX  
2
1
0
3
T
= +25؇C  
A
2
1
0
V
V
= +5V  
= +3V  
DD  
DAC LOADED WITH 00 HEX  
DD  
DAC LOADED WITH 00 HEX  
0
0
5
10  
– mA  
15  
5
10  
15  
0
50  
100  
150  
200  
250  
I
I
– mA  
CODE  
SOURCE/SINK  
SOURCE/SINK  
Figure 8. Source and Sink Current  
Capability with VDD = 3 V  
Figure 9. Source and Sink Current  
Capability with VDD = 5 V  
Figure 10. Supply Current vs. Code  
REV. A  
–6–  
AD5300  
300  
250  
1.0  
0.9  
300  
250  
200  
150  
100  
50  
THREE–STATE  
CONDITION  
V
= +5V  
DD  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
200  
150  
100  
50  
+105؇C  
+25؇C  
–40؇C  
0
2.7  
0
2.7  
3.2  
3.7  
4.2  
– V  
4.7  
5.2  
3.2  
3.7  
4.2  
– V  
4.7  
5.2  
–40  
0
40  
80  
120  
V
V
DD  
TEMPERATURE – ؇C  
DD  
Figure 11. Supply Current vs.  
Temperature  
Figure 12. Supply Current vs. Supply  
Voltage  
Figure 13. Power-Down Current vs.  
Supply Voltage  
800  
T
= +25؇C  
A
CH 2  
CLK  
600  
CH 2  
CLK  
400  
200  
V
OUT  
V
OUT  
V
= +5V  
V
= +5V  
DD  
DD  
FULL-SCALE CODE CHANGE  
00 HEX – FF HEX  
CH 1  
HALF-SCALE CODE CHANGE  
40 HEX – C0 HEX  
CH1  
V
= +5V  
DD  
T
= +25؇C  
T
= +25؇C  
A
A
OUTPUT LOADED WITH  
OUTPUT LOADED WITH  
2kAND 200pF TO GND  
2kAND 200pF TO GND  
V
= +3V  
DD  
CH1 1V, CH 2 5V, TIME BASE = 1s/DIV  
CH1 1V, CH2 5V, TIME BASE = 1s/DIV  
0
0
1
2
3
4
5
V
– V  
LOGIC  
Figure 14. Supply Current vs. Logic  
Input Voltage  
Figure 15. Full-Scale Settling Time  
Figure 16. Half-Scale Settling Time  
2.54  
LOADED WITH 2k⍀  
AND 200pF TO GND  
V
= +5V  
DD  
2kLOAD  
CH2  
TO V  
DD  
CLK  
CODE CHANGE:  
80 HEX TO 7F HEX  
2.52  
2.50  
2.48  
2.46  
V
DD  
CH1  
CH2  
V
OUT  
V
OUT  
CH1  
CH1 1V, CH2 1V, TIME BASE = 20s/DIV  
CH1 1V, CH2 5V, TIME BASE = 5s/DIV  
500ns/DIV  
Figure 17. Power-On Reset to 0 V  
Figure 18. Exiting Power-Down  
(7F Hex Loaded)  
Figure 19. Digital-to-Analog Glitch  
Impulse  
REV. A  
–7–  
AD5300  
GENERAL DESCRIPTION  
D/A Section  
register determines at which node on the string the voltage is  
tapped off to be fed into the output amplifier. The voltage is  
tapped off by closing one of the switches connecting the string  
to the amplifier. Because it is a string of resistors, it is guaran-  
teed monotonic.  
The AD5300 DAC is fabricated on a CMOS process. The archi-  
tecture consists of a string DAC followed by an output buffer  
amplifier. Since there is no reference input pin, the power  
supply (VDD) acts as the reference. Figure 20 shows a block  
diagram of the DAC architecture.  
Output Amplifier  
The output buffer amplifier is capable of generating rail-to-rail  
voltages on its output which gives an output range of 0 V to  
VDD. It is capable of driving a load of 2 kin parallel with  
1000 pF to GND. The source and sink capabilities of the output  
amplifier can be seen in Figures 8 and 9. The slew rate is 1 V/µs  
with a half-scale settling time of 4 µs with the output loaded.  
V
DD  
REF (+)  
RESISTOR  
STRING  
DAC REGISTER  
V
OUT  
REF (–)  
OUTPUT  
AMPLIFIER  
SERIAL INTERFACE  
GND  
The AD5300 has a three-wire serial interface (SYNC, SCLK  
and DIN), which is compatible with SPI, QSPI and MICROWIRE  
interface standards as well as most DSPs. See Figure 1 for a  
timing diagram of a typical write sequence.  
Figure 20. DAC Architecture  
Since the input coding to the DAC is straight binary, the ideal  
output voltage is given by:  
The write sequence begins by bringing the SYNC line low. Data  
from the DIN line is clocked into the 16-bit shift register on the  
falling edge of SCLK. The serial clock frequency can be as high  
as 30 MHz, making the AD5300 compatible with high-speed  
DSPs. On the sixteenth falling clock edge, the last data bit is  
clocked in and the programmed function is executed (i.e., a  
change in DAC register contents and/or a change in the mode of  
operation). At this stage, the SYNC line may be kept low or be  
brought high. In either case, it must be brought high for a mini-  
mum of 33 ns before the next write sequence so that a falling  
edge of SYNC can initiate the next write sequence. Since the  
SYNC buffer draws more current when VIN = 2.4 V than it does  
when VIN = 0.8 V, SYNC should be idled low between write  
sequences for even lower power operation of the part. As is  
mentioned above, however, it must be brought high again just  
before the next write sequence.  
D
256  
VOUT =VDD  
×
where D = decimal equivalent of the binary code that is loaded  
to the DAC register; it can range from 0 to 255.  
Resistor String  
The resistor string section is shown in Figure 21. It is simply a  
string of resistors, each of value R. The code loaded to the DAC  
R
R
TO OUTPUT  
AMPLIFIER  
R
Input Shift Register  
The input shift register is 16 bits wide (see Figure 22). The first  
two bits are “don’t cares.” The next two are control bits that  
control which mode of operation the part is in (normal mode or  
any one of three power-down modes). There is a more complete  
description of the various modes in the Power-Down Modes  
section. The next eight bits are the data bits. These are trans-  
ferred to the DAC register on the sixteenth falling edge of SCLK.  
Finally, the last four bits are “don’t cares.”  
R
R
Figure 21. Resistor String  
DB15 (MSB)  
DB0 (LSB)  
X
X
PD1  
PD 0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
X
X
X
X
DATA BITS  
0
0
1
1
0
NORMAL OPERATION  
1kTO GND  
1
0
1
100kTO GND  
POWER-DOWN MODES  
THREE-STATE  
Figure 22. Input Register Contents  
–8–  
REV. A  
AD5300  
SCLK  
SYNC  
DB0  
DB0  
DB15  
DB15  
DIN  
VALID WRITE SEQUENCE, OUTPUT UPDATES  
INVALID WRITE SEQUENCE:  
 SYNC HIGH BEFORE 16 FALLING EDGE  
TH  
TH  
ON THE 16 FALLING EDGE  
Figure 23. SYNC Interrupt Facility  
SYNC Interrupt  
In a normal write sequence, the SYNC line is kept low for at  
least 16 falling edges of SCLK and the DAC is updated on the  
16th falling edge. However, if SYNC is brought high before the  
16th falling edge this acts as an interrupt to the write sequence.  
The shift register is reset and the write sequence is seen as  
invalid. Neither an update of the DAC register contents or a  
change in the operating mode occurs—see Figure 23.  
RESISTOR  
AMPLIFIER  
STRING DAC  
V
OUT  
POWER-DOWN  
CIRCUITRY  
RESISTOR  
NETWORK  
Power-On-Reset  
The AD5300 contains a power-on-reset circuit which controls  
the output voltage during power-up. The DAC register is filled  
with zeros and the output voltage is 0 V. It remains there until  
a valid write sequence is made to the DAC. This is useful in  
applications where it is important to know the state of the out-  
put of the DAC while it is in the process of powering up.  
Figure 24. Output Stage During Power-Down  
The bias generator, the output amplifier, the resistor string and  
other associated linear circuitry are all shut down when the  
power-down mode is activated. However, the contents of the  
DAC register are unaffected when in power-down. The time to  
exit power-down is typically 2.5 µs for VDD = 5 V and 5 µs for  
VDD = 3 V. See Figure 18 for a plot.  
Power-Down Modes  
The AD5300 contains four separate modes of operation. These  
modes are software-programmable by setting two bits (DB13  
and DB12) in the control register. Table I shows how the state  
of the bits corresponds to the mode of operation of the device.  
MICROPROCESSOR INTERFACING  
AD5300 to ADSP-2101/ADSP-2103 Interface  
Figure 25 shows a serial interface between the AD5300 and the  
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should  
be set up to operate in the SPORT Transmit Alternate Framing  
Mode. The ADSP-2101/ADSP-2103 SPORT is programmed  
through the SPORT control register and should be configured  
as follows: Internal Clock Operation, Active Low Framing, 16-  
Bit Word Length. Transmission is initiated by writing a word to  
the Tx register after the SPORT has been enabled.  
Table I. Modes of Operation for the AD5300  
DB13  
DB12  
Operating Mode  
0
0
Normal Operation  
Power-Down Modes  
1 kto GND  
100 kto GND  
Three-State  
0
1
1
1
0
1
ADSP-2101/  
AD5300*  
ADSP-2103*  
When both bits are set to 0, the part works normally with its  
normal power consumption of 140 µA at 5 V. However, for the  
three power-down modes, the supply current falls to 200 nA at  
5 V (50 nA at 3 V). Not only does the supply current fall but  
the output stage is also internally switched from the output of  
the amplifier to a resistor network of known values. This has the  
advantage that the output impedance of the part is known while  
the part is in power-down mode. There are three different options.  
The output is connected internally to GND through a 1 kresis-  
tor, a 100 kresistor or it is left open-circuited (Three-State).  
The output stage is illustrated in Figure 24.  
SYNC  
DIN  
TFS  
DT  
SCLK  
SCLK  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 25. AD5300 to ADSP-2101/ADSP-2103 Interface  
REV. A  
–9–  
AD5300  
AD5300 to 68HC11/68L11 Interface  
Figure 26 shows a serial interface between the AD5300 and the  
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11  
drives the SCLK of the AD5300, while the MOSI output drives  
the serial data line of the DAC. The SYNC signal is derived  
from a port line (PC7). The setup conditions for correct opera-  
tion of this interface are as follows: the 68HC11/68L11 should  
be configured so that its CPOL bit is a 0 and its CPHA bit is a  
1. When data is being transmitted to the DAC, the SYNC line is  
taken low (PC7). When the 68HC11/68L11 is configured as  
above, data appearing on the MOSI output is valid on the falling  
edge of SCK. Serial data from the 68HC11/68L11 is transmit-  
ted in 8-bit bytes with only eight falling clock edges occurring in  
the transmit cycle. Data is transmitted MSB first. In order to  
load data to the AD5300, PC7 is left low after the first eight bits  
are transferred, and a second serial write operation is performed  
to the DAC and PC7 is taken high at the end of this procedure.  
MICROWIRE*  
AD5300*  
CS  
SK  
SYNC  
SCLK  
DIN  
SO  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 28. AD5300 to MICROWIRE Interface  
APPLICATIONS  
Using REF19x as a Power Supply for AD5300  
Because the supply current required by the AD5300 is extremely  
low, an alternative option is to use a REF19x voltage reference  
(REF195 for 5 V or REF193 for 3 V) to supply the required  
voltage to the part—see Figure 29. This is especially useful if  
your power supply is quite noisy or if the system supply voltages  
are at some value other than 5 V or 3 V (e.g., 15 V). The REF19x  
will output a steady supply voltage for the AD5300. If the low  
dropout REF195 is used, the current it needs to supply to the  
AD5300 is 140 µA. This is with no load on the output of the  
DAC. When the DAC output is loaded, the REF195 also needs to  
supply the current to the load. The total current required (with  
a 5 kload on the DAC output) is:  
68HC11/68L11*  
AD5300*  
PC7  
SYNC  
SCLK  
DIN  
SCK  
MOSI  
140 µA + (5 V/5 k) = 1.14 mA  
*ADDITIONAL PINS OMITTED FOR CLARITY  
The load regulation of the REF195 is typically 2 ppm/mA,  
which results in an error of 2.3 ppm (11.5 µV) for the 1.14 mA  
current drawn from it. This corresponds to a 0.0006 LSB error.  
Figure 26. AD5300 to 68HC11/68L11 Interface  
AD5300 to 80C51/80L51 Interface  
Figure 27 shows a serial interface between the AD5300 and the  
80C51/80L51 microcontroller. The setup for the interface is as  
follows: TXD of the 80C51/80L51 drives SCLK of the AD5300,  
while RXD drives the serial data line of the part. The SYNC  
signal is again derived from a bit programmable pin on the port.  
In this case port line P3.3 is used. When data is to be transmit-  
ted to the AD5300, P3.3 is taken low. The 80C51/80L51 trans-  
mits data only in 8-bit bytes; thus only eight falling clock edges  
occur in the transmit cycle. To load data to the DAC, P3.3 is  
left low after the first eight bits are transmitted, and a second  
write cycle is initiated to transmit the second byte of data. P3.3  
is taken high following the completion of this cycle. The 80C51/  
80L51 outputs the serial data in a format which has the LSB  
first. The AD5300 requires its data with the MSB as the first bit  
received. The 80C51/80L51 transmit routine should take this  
into account.  
+15V  
+5V  
REF195  
140A  
SYNC  
SCLK  
DIN  
THREE-WIRE  
SERIAL  
INTERFACE  
V
= 0V TO 5V  
OUT  
AD5300  
Figure 29. REF195 as Power Supply to AD5300  
Bipolar Operation Using the AD5300  
The AD5300 has been designed for single-supply operation, but  
a bipolar output range is also possible using the circuit in Figure  
30. The circuit below will give an output voltage range of ±5 V.  
Rail-to-rail operation at the amplifier output is achievable using  
an AD820 or an OP295 as the output amplifier.  
The output voltage for any input code can be calculated as  
follows:  
AD5300*  
80C51/80L51*  
P3.3  
SYNC  
D
256  
R1+ R2  
R1  
R2  
R1  
TXD  
RXD  
SCLK  
DIN  
VO = VDD  
×
×
VDD ×  
where D represents the input code in decimal (0–255).  
With VDD = 5 V, R1 = R2 = 10 k:  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 27. AD5300 to 80C51/80L51 Interface  
AD5300 to Microwire Interface  
Figure 28 shows an interface between the AD5300 and any  
microwire compatible device. Serial data is shifted out on the  
falling edge of the serial clock and is clocked into the AD5300  
on the rising edge of the SK.  
10 × D  
VO  
=
5V  
256  
This is an output voltage range of ±5 V with 00 Hex corresponding  
to a –5 V output and FF Hex corresponding to a +5 V output.  
–10–  
REV. A  
AD5300  
R2 = 10k⍀  
+5V  
REGULATOR  
0.1F  
10F  
+5V  
POWER  
SCLK  
+5V  
R1 = 10k⍀  
V
V
V
DD  
AD820/  
OP295  
؎5V  
10k⍀  
V
DD  
V
V
OUT  
DD  
SCLK  
10F  
0.1F  
AD5300  
–5V  
DD  
AD5300  
10k⍀  
THREE-WIRE  
SERIAL  
INTERFACE  
SYNC  
DATA  
V
SYNC  
OUT  
DD  
Figure 30. Bipolar Operation with the AD5300  
10k⍀  
DIN  
Two 8-Bit AD5300s Together Make One 15-Bit DAC  
By using the configuration below in Figure 31, it can be seen  
that one 15-bit DAC can be made with two 8-bit AD5300s.  
Because of the low supply current the AD5300 requires, the  
output of one DAC may be directed into the supply pin of the  
second DAC. The first DAC has no problem sourcing the re-  
quired 140 µA of current for the second DAC.  
GND  
Figure 32. AD5300 with an Opto-Isolated Interface  
Power Supply Bypassing and Grounding  
When accuracy is important in a circuit it is helpful to carefully  
consider the power supply and ground return layout on the  
board. The printed circuit board containing the AD5300 should  
have separate analog and digital sections, each having its own  
area of the board. If the AD5300 is in a system where other  
devices require an AGND to DGND connection, the connec-  
tion should be made at one point only. This ground point should  
be as close as possible to the AD5300.  
Since the AD5300 works on any supply voltage between 2.5 V  
and 5.5 V, the output of the first DAC can be anywhere above  
2.5 V. For a VDD of 5 V this allows the first DAC to use half of  
its output range (2.5 V to 5 V), which gives 7-bit resolution on  
the output voltage. This output then becomes the supply and  
reference for the second DAC. The second DAC has 8-bit reso-  
lution on the output range, which gives an overall resolution for  
the system of 15 bits.  
The power supply to the AD5300 should be bypassed with  
10 µF and 0.1 µF capacitors. The capacitors should be physi-  
cally as close as possible to the device with the 0.1 µF capacitor  
ideally right up against the device. The 10 µF capacitors are the  
tantalum bead type. It is important that the 0.1 µF capacitor has  
low Effective Series Resistance (ESR) and Effective Series In-  
ductance (ESI), e.g., common ceramic types of capacitors. This  
0.1 µF capacitor provides a low impedance path to ground for  
high frequencies caused by transient currents due to internal  
logic switching.  
A level-shifter is required to ensure that the logic input voltages  
do not exceed the supply voltage of the part. The microcontroller  
outputs 5 V signals which need to be level-shifted down to 2.5 V  
in the case of the second DAC having a supply of only 2.5 V.  
+5V  
V
DD  
SYNC  
V
= 2.5V TO 5V  
OUT  
SCLK  
AD5300  
DIN  
The power supply line itself should have as large a trace as pos-  
sible to provide a low impedance path and reduce glitch effects  
on the supply line. Clocks and other fast switching digital signals  
should be shielded from other parts of the board by digital  
ground. Avoid crossover of digital and analog signals if possible.  
When traces cross on opposite sides of the board, ensure that  
they run at right angles to each other to reduce feedthrough  
effects through the board. The best board layout technique is  
the microstrip technique where the component side of the board  
is dedicated to the ground plane only and the signal traces are  
placed on the solder side. However, this is not always possible  
with a two-layer board.  
MICRO-  
CONTROLLER  
V
DD  
SYNC  
LEVEL  
SHIFTER  
V
= 0V TO 5V  
SCLK AD5300  
DIN  
OUT  
15-BIT  
RESOLUTION  
Figure 31. 15-Bit DAC Using Two AD5300s  
Using AD5300 with an Opto-Isolated Interface  
In process-control applications in industrial environments it is  
often necessary to use an opto-isolated interface to protect and  
isolate the controlling circuitry from any hazardous common-  
mode voltages that may occur in the area where the DAC is  
functioning. Opto-isolators provide isolation in excess of 3 kV.  
Because the AD5300 uses a three-wire serial logic interface, it  
requires only three opto-isolators to provide the required isola-  
tion (see Figure 32). The power supply to the part also needs to  
be isolated. This is done by using a transformer. On the DAC  
side of the transformer, a +5 V regulator provides the +5 V  
supply required for the AD5300.  
REV. A  
–11–  
AD5300  
OUTLINE DIMENSIONS  
Dimensions shown in inches and (mm).  
6-Lead SOT-23  
(RT-6)  
0.122 (3.10)  
0.106 (2.70)  
6
1
5
2
4
3
0.071 (1.80)  
0.059 (1.50)  
0.118 (3.00)  
0.098 (2.50)  
PIN 1  
0.037 (0.95) BSC  
0.075 (1.90)  
BSC  
0.051 (1.30)  
0.035 (0.90)  
0.057 (1.45)  
0.035 (0.90)  
10°  
0°  
0.020 (0.50)  
0.010 (0.25)  
0.006 (0.15)  
0.000 (0.00)  
0.022 (0.55)  
0.014 (0.35)  
SEATING  
PLANE  
0.009 (0.23)  
0.003 (0.08)  
8-Lead SOIC  
(RM-8)  
0.122 (3.10)  
0.114 (2.90)  
8
1
5
4
0.199 (5.05)  
0.187 (4.75)  
0.122 (3.10)  
0.114 (2.90)  
PIN 1  
0.0256 (0.65) BSC  
0.120 (3.05)  
0.120 (3.05)  
0.112 (2.84)  
0.112 (2.84)  
0.043 (1.09)  
0.037 (0.94)  
0.006 (0.15)  
0.002 (0.05)  
33°  
27°  
0.018 (0.46)  
0.011 (0.28)  
0.003 (0.08)  
0.028 (0.71)  
0.016 (0.41)  
SEATING  
PLANE  
0.008 (0.20)  
–12–  
REV. A  

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