AD5282 [ADI]

+15V, I2C Compatible Digital Potentiometers; + 15V ， I2C兼容数字电位器


型号：	AD5282
厂家：	ADI
描述：	+15V, I2C Compatible Digital Potentiometers + 15V ， I2C兼容数字电位器电位器
文件：	总10页 (文件大小：154K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY TECHNICAL DATA

+15V, I2C Compatible

Digital Potentiometers

FEATURES

256 Position

Preliminary Technical Data

AD5280/AD5282

A₁

W₁

B₁

A₂

W₂

B₂

O₁

AD5280 – 1-Channel

AD5282 – 2-Channel (Independently Programmable)

Potentiometer Replacement

OUTPUT

SHDN

20K, 50K, 200K Ohm with TC < 50ppm/ºC

Internal Power ON Mid-Scale Preset

+5 to +15V Single-Supply; ±5.5V Dual-Supply Operation

I²C Compatible Interface

V_DD

V_SS

RDAC1 REGISTER

RDAC2 REGISTER

V_L

APPLICATIONS

ADDRESS

DECODE

PWR ON

RESET

Multi-Media, Video & Audio

Communications

AD5282

Mechanical Potentiometer Replacement

Instrumentation: Gain, Offset Adjustment

Programmable Voltage to Current Conversion

Line Impedance Matching

SCL

SDA

GND

SERIAL INPUT REGISTER

AD0

AD1

GENERAL DESCRIPTION

The AD5280/AD5282 provides a single/dual channel, 256 position

digitally-controlled variable resistor (VR) device. These devices

perform the same electronic adjustment function as a

potentiometer, trimmer or variable resistor. Each VR offers a

completely programmable value of resistance, between the A

terminal and the wiper, or the B terminal and the wiper. The fixed

A-to-B terminal resistance of 20, 50 or 200K ohms has a 1%

channel-to-channel matching tolerance with a nominal temperature

coefficient of 30 ppm/°C.

The AD5280/AD5282 are available in ultra compact surface mount

thin TSSOP-14/-16 packages. All parts are guaranteed to operate

over the extended industrial temperature range of -40°C to +85°C.

For 3-wire, SPI compatible interface applications, see

AD5203/AD5204/AD5206/AD7376/AD8400/AD8402/AD8403/

AD5260/AD5262/AD5200/AD5201 products.

ORDERING GUIDE

Kilo

Ohms

Package

Description Option

Package

Wiper Position programming defaults to midscale at system power

ON. Once powered the VR wiper position is programmed by a I²C

compatible 2-wire serial data interface. Both parts have two

programmable logic outputs available to drive digital loads, gates,

LED drivers, analog switches, etc.

Model

Temp

AD5280BRU20

AD5280BRU50

-40/+85°C

TSSOP-14

RU-14

AD5280BRU200 200

FUNCTIONAL BLOCK DIAGRAMS

AD5282BRU20

AD5282BRU50

-40/+85°C

TSSOP-16

RU-16

A₁

W₁

B₁

O₁

O₂

AD5282BRU200 200

The AD5280/AD5282 die size is 75 mil X 120 mil, 9,000 sq. mil.

Contains xxx transistors. Patent Number xxx applies.

SHDN

V_DD

V_SS

RDAC1 REGISTER

RDAC2 REGISTER

V_L

ADDRESS

DECODE

PWR ON

RESET

AD5280

SCL

SDA

GND

SERIAL INPUT REGISTER

AD0

AD1

REV PrE 12 MAR 02

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use; nor for any infringements of patents

or other rights of third parties which may result from its use. No license is granted by

implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

©Analog Devices, Inc., 2002

PRELIMINARY TECHNICAL DATA

AD5280/AD5282

ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION ^(V_DD= +5V, V_SS= -5V, V_LOGIC= +5V,

_A= +V_DD, V_B= 0V, -40°C < T_A< +85°C unless otherwise noted.)

Parameter Symbol Conditions

Min

Typ¹

Max

Units

DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs

Resistor Differential NL²

Resistor Nonlinearity²

Nominal resistor tolerance³

R-DNL

R-INL

R_WB, V_A=NC

-1

±0.4

±0.5

LSB

∆R

T_A= 25°C

-30

Resistance Temperature Coefficient

R_AB/∆T

V_AB= V_DD, Wiper = No Connect

ppm/°C

Wiper Resistance

R_W

I_W= V_DD/R, V_DD= +3V or +5V

100

Ω

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs

Resolution

Bits

LSB

Integral Nonlinearity⁴

Differential Nonlinearity⁴

INL

DNL

R_AB=20KΩ, 50KΩ

R_AB=200KΩ

–1

–2

–1

±0.5

±0.4

-0.5

+0.5

LSB

Voltage Divider Temperature Coefficient ∆V_W/∆T

Full-Scale Error

Zero-Scale Error

Code = 80_H

Code = FF_H

Code = 00_H

ppm/°C

V_WFSE

V_WZSE

–1

LSB

RESISTOR TERMINALS

Voltage Range⁵

Capacitance⁶A, B

Capacitance⁶W

V_A,B,W

C_A,B

C_W

V_SS

V_DD

f = 1 MHz, measured to GND, Code = 80_H

V_A= V_B= V_W

Common Mode Leakage

I_CM

DIGITAL INPUTS

Input Logic High

Input Logic Low

Input Logic High

Input Logic Low

Input Logic High

Input Logic Low

Input Current

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

I_IL

SDA & SCL

AD0 & AD1

0.7V_LOGIC

V_LOGIC+0.5

0.3V_LOGIC

V_LOGIC

0.8

V_LOGIC

0.6

µA

-0.5

2.4

2.1

AD0 & AD1

V_LOGIC= +3V, AD0 & AD1

V_IN= 0V or +5V

±1

Input Capacitance⁶

C_IL

DIGITAL Output

O1, O2

SDA

V_OH

V_OL

I_OZ

I_OH=0.4mA

I_OL=-1.6mA

I_OL= -6mA

I_OL= -3mA

V_IN= 0V or +5V

2.4

5.5

0.4

0.6

0.4

±1

µA

SDA

Three-State Leakage Current

Output Capacitance⁶

C_OZ

POWER SUPPLIES

Logic Supply

V_LOGIC

+2.7

±4.5

+5.5

+15

±5.5

Power Single-Supply Range

Power Dual-Supply Range

Logic Supply Current

Positive Supply Current

Negative Supply Current

V_{DD RANGE}

V_{DD/SS RANGE}

I_LOGIC

I_DD

I_SS

V_SS= 0V

V_LOGIC= +5V

V_IH= +5V or V_IL= 0V

µA

Power Dissipation¹⁰

P_DISS

PSS

V_IH= +5V or V_IL= 0V, V_DD= +5V, V_SS= -5V

0.2

0.05

0.6

Power Supply Sensitivity

0.015

%/%

REV PrE 12 MAR 02

Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final

product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com

PRELIMINARY TECHNICAL DATA

AD5280/AD5282

ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION ^(V_DD= +5V, V_SS= -5V, V_LOGIC= +5V,

_A= +V_DD, V_B= 0V, -40°C < T_A< +85°C unless otherwise noted.)

Parameter

Symbol

Conditions

Min

Typ¹

Max

Units

DYNAMIC CHARACTERISTICS^6,9,11

Bandwidth –3dB

BW_20K

BW_50K

R_AB= 20KΩ, Code = 80_H

R_AB= 50KΩ, Code = 80_H

650

142

0.005

kHz

BW_200K R_AB= 200KΩ, Code = 80_H

THD_W

t_S

Total Harmonic Distortion

V_WSettling Time

V_A=1Vrms + 2V dc, V_B= 2V DC, f=1KHz

V_A= V_DD, V_B=0V, ±1 LSB error band

µs

Resistor Noise Voltage

e_{N_WB}

R_WB= 10KΩ, f = 1KHz

nV√Hz

INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)

SCL Clock Frequency

f_SCL

400

0.9

KHz

µs

t_BUFBus free time between STOP & START

t_HD;STAHold Time (repeated START)

t_LOWLow Period of SCL Clock

t_HIGHHigh Period of SCL Clock

t_SU;STASetup Time For START Condition t5

t_HD;DATData Hold Time

t_SU;DATData Setup Time

t_FFall Time of both SDA & SCL signals

t_RRise Time of both SDA & SCL signals t9

1.3

0.6

1.3

0.6

After this period the first clock pulse is generated

100

300

t_SU;STOSetup time for STOP Condition

t10

0.6

µs

NOTES:

Typicals represent average readings at +25°C, V_DD= +5V, V_SS= -5V.

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the

relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

V_AB= V_DD, Wiper (V_W) = No connect

INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V_A= V_DDand V_B= 0V.

DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.

Resistor terminals A,B,W have no limitations on polarity with respect to each other.

Guaranteed by design and not subject to production test.

Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value

result in the minimum overall power consumption.

10.

is calculated from (I x V ). CMOS logic level inputs result in minimum power dissipation.

DISS

DD DD

11. All dynamic characteristics use V_DD= +5V.

12. See timing diagram for location of measured values.

REV PrE 12 MAR 02

Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final

product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com

PRELIMINARY TECHNICAL DATA

AD5280/AD5282

ABSOLUTE MAXIMUM RATINGS (T_A= +25°C, unless

TABLE 1: AD5280 PIN Function Descriptions

otherwise noted)

Name

V_DD

Description

Resistor terminal A

Wiper terminal W

Resistor terminal B

Positive power supply, specified for

_DDto GND .............................................................-0.3, +15V

V_SSto GND .................................................................. 0V, -7V

V_DDto V_SS...................................................................... +15V

V_A, V_B, V_Wto GND...................................................V_SS, V_DD

A_X– B_X, A_X– W_X, B_X– W_X.........................................±20mA

operation from +5 to +15V.

SHDN

Active Low, Asynchronous connection of

the wiper W to terminal B, and open

circuit of terminal A. RDAC register

contents unchanged.

Serial Clock Input

Serial Data Input/Output

Programmable address bit for multiple

package decoding. Bits AD0 & AD1

provide 4 possible addresses.

Programmable address bit for multiple

package decoding. Bits AD0 & AD1

provide 4 possible addresses.

Digital Input Voltage to GND.........................................0V, 7V

Operating Temperature Range ...........................-40°C to +85°C

Thermal Resistance^*θ_JA,

TSSOP-14 ........................................................206°C/W

TSSOP-16 ........................................................180°C/W

Maximum Junction Temperature (T_JMAX) .................... +150°C

SCL

SDA

AD0

Storage Temperature ........................................-65°C to +150°C

Lead Temperature

RU-14, RU-16 (Vapor Phase, 60 sec) ....................... +215°C

RU-14, RU-16 (Infrared, 15 sec) .............................. +220°C

AD1

^*Package Power Dissipation (T MAX - T ) / θ

GND

V_SS

Common Ground

Negative power supply, specified for

AD5280 PIN CONFIGURATION

operation from 0 to -5V

V_L

Logic Output terminal O2

Logic Supply Voltage, needs to be same

voltage as the digital logic controlling the

AD5280.

V_L

Logic Output terminal O1

V_DD

SHDN

SCL

SDA

V_SS

GND

AD1

AD0

AD5282 PIN CONFIGURATION

V_L

V_DD

V_SS

GND

AD1

AD0

SHDN

SCL

SDA

REV PrE 12 MAR 02

Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final

product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com

PRELIMINARY TECHNICAL DATA

AD5280/AD5282

AD0

Programmable address bit for multiple

package decoding. Bits AD0 & AD1

provide 4 possible addresses.

TABLE 2: AD5282 PIN Function Descriptions

Name

A₁

Description

Logic Output terminal O1

Resistor terminal A₁

Wiper terminal W₁

AD1

Programmable address bit for multiple

package decoding. Bits AD0 & AD1

provide 4 possible addresses.

Common Ground

Negative power supply, specified for

W₁

B₁

V_DD

Resistor terminal B₁

Positive power supply, specified for

GND

V_SS

operation from +5 to +15V.

Active Low, Asynchronous connection of

the wiper W to terminal B, and open

circuit of terminal A. RDAC register

contents unchanged.

operation from 0 to -5V

Logic Supply Voltage, needs to be same

voltage as the digital logic controlling the

AD5282.

Resistor terminal B₂

Wiper terminal W₂

SHDN

V_L

B₂

W₂

A₂

SCL

SDA

Serial Clock Input

Serial Data Input/Output

Resistor terminal A₂

t₈

SDA

t₁

t₆

t₈

t₉

SCL

t₂

t₃

t₄

t₅

t₇

t₁₀

Figure 1. Detail Timing Diagram

Data of AD5280/AD5282 is accepted from the I²C bus in the following serial format:

Slave Address Byte

Instruction Byte

Data Byte

Where:

S = Start Condition

P = Stop Condition

A = Acknowledge

X = Don’t Care

R/W= Read Enable at High and Write Enable at Low

A/B = RDAC sub address select. “Zero” for RDAC1 and “One” for RDAC2

SD = Shutdown, same as SHDN pin operation except inverse logic

O2, O1 = Output logic pin latched values

AD1, AD0 = Package pin programmable address bits

D7,D6,D5,D4,D3,D2,D1,D0 = Data Bits

SCL

SDA

AD1

AD0

R/W

A/B

ACK. BY

AD5280

ACK. BY

AD5280

ACK. BY

AD5280

START BY

MASTER

FRAME 1

Slave Address Byte

FRAME

Instruction Byte

FRAME 3

Data Byte

Figure 2. Writing to the RDAC Register

REV PrE 12 MAR 02

Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final

product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com

PRELIMINARY TECHNICAL DATA

AD5280/AD5282

SCL

AD1

AD0

R/W

SDA

NO ACK.

BY MASTER

ACK. BY

AD5280

START BY

MASTER

FRAME 2

STOP BY

MASTER

FRAME 1

Slave Address Byte

Data From Select ed

RDAC Register

Figure 3. Reading Data from a Previously Selected RDAC Register

for data 02_Hand so on. Each LSB data value increase moves the

OPERATION

The AD5280/AD5282 provides a single/dual channel, 256-

position digitally-controlled variable resistor (VR) device. The

terms VR and RDAC are used interchangeably throughout this

documentation. To program the VR settings, refer to the Digital

Interface section. Both parts have an internal power ON preset

that places the wiper in mid scale during power on, which

simplifies the fault condition recovery at power up. In addition,

the shutdown SHDN pin of AD5280/AD5282 places the RDAC

in a zero power consumption state where terminal A is open

circuited and the wiper W is connected to terminal B, resulting

in only leakage currents being consumed in the VR structure. In

shutdown mode the VR latch settings are maintained, so that,

returning to operational mode from power shutdown, the VR

settings return to their previous resistance values.

wiper up the resistor ladder until the last tap point is reached at

19982Ω [R_AB–1LSB+R_W]. The wiper does not directly connect

to the B terminal. See Figure 4 for a simplified diagram of the

equivalent RDAC circuit.

The general equation determining the digitally programmed

output resistance between W and B is:

R_WB(D) =

R_AB+R_W

eqn.1

256

where D is the decimal equivalent of the binary code which is

loaded in the 8-bit RDAC register, and R_ABis the nominal end-

to-end resistance.

SHDN

For example, R_AB=20KΩ, when V_B= 0V and A–terminal is open

circuit, the following output resistance values R_WBwill be set for

the following RDAC latch codes. Result will be the same if

terminal A is tied to W:

R_WB

Output State

(DEC) (Ω)

256

128

19982Ω Full-Scale (R_AB- 1LSB + R_W)

10060Ω Mid-Scale

RDAC

LATCH

DECODER

138Ω

60Ω

1 LSB

Zero-Scale (Wiper contact resistance)

Note that in the zero-scale condition a finite wiper resistance of

60Ω is present. Care should be taken to limit the current flow

between W and B in this state to a maximum current of no more

than 5mA. Otherwise, degradation or possible destruction of the

internal switch contact can occur.

Figure 4. AD5280/AD5282 Equivalent RDAC Circuit

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance of the RDAC between terminals A and B

are available in 20KΩ, 50KΩ, and 200KΩ. The final three

digits of the part number determine the nominal resistance

value, e.g. 20KΩ = 20; 50KΩ = 50; 200KΩ = 200. The

nominal resistance (R_AB) of the VR has 256 contact points

Similar to the mechanical potentiometer, the resistance of the

RDAC between the wiper W and terminal A also produces a

digitally controlled resistance R_WA. When these terminals are

used the B–terminal should be let open or tied to the wiper

terminal. Setting the resistance value for R_WAstarts at a

accessed by the wiper terminal, plus the B terminal contact. The

eight bit data in the RDAC latch is decoded to select one of the

256 possible settings. Assume a 20KΩ part is used, the wiper's

first connection starts at the B terminal for data 00_H. Since there

maximum value of resistance and decreases as the data loaded in

the latch is increased in value. The general equation for this

operation is:

is a 60Ω wiper contact resistance, such connection yields a

minimum of 60Ω resistance between terminals W and B. The

second connection is the first tap point corresponds to 138Ω

(R_WB= R_AB/256 + R_W= 78Ω+60Ω) for data 01_H. The third

256 − D

R_WA(D) =

R_AB+ R_W

eqn.2

256

connection is the next tap point representing 216Ω (78x2+60)

REV PrE 12 MAR 02

Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final

product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com

PRELIMINARY TECHNICAL DATA

AD5280/AD5282

For example, R_AB=20KΩ, when V_A= 0V and B–terminal is open

2 bits are determined by the state of the AD0 and AD1 pins of

the device. AD0 and AD1 allow the user to use up to four of

these devices on one bus.

circuit, the following output resistance R_WAwill be set for the

following RDAC latch codes. Result will be the same if terminal

B is tied to W:

The 2-wire I²C serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high, Figure 2. The

following byte is the Slave Address Byte which consists of

the 7-bit slave address followed by an R/W bit (this bit

determines whether data will be read from or written to the

slave device).

R_WA

Output State

(DEC) (Ω)

256

128

Full-Scale

10060 Mid-Scale

19982 1 LSB

20060 Zero-Scale

The slave whose address corresponds to the transmitted

address responds by pulling the SDA line low during the

ninth clock pulse (this is termed the Acknowledge bit). At

this stage, all other devices on the bus remain idle while the

selected device waits for data to be written to or read from

its serial register. If the R/W bit is high, the master will read

from the slave device. On the other hand, if the R/W bit is

low, the master will write to the slave device.

The typical distribution of the nominal resistance R_ABfrom

channel-to-channel matches within ±1%. Device to device

matching is process lot dependent and is possible to have ±30%

variation. Since the resistance element is processed in thin film

technology, the change in R_ABwith temperature has a 30

ppm/°C temperature coefficient.

2. A Write operation contains an extra Instruction Byte more

than the Read operation. Such Instruction Byte in Write

mode follows the Slave Address Byte. The MSB of the

Instruction Byte labeled A/B is the RDAC sub-address

select. A “low” select RDAC1 and a “high” selects RDAC2

for dual channel AD5282. The 2^ndMSB RS is the Mid-

scale reset. A logic high of this bit moves the wiper of a

selected RDAC to the center tap where R_WA=R_WB. The 3^rd

MSB SD is a shutdown bit. A logic high causes the RDAC

open circuit at terminal A while shorting wiper to terminal

B. This operation yields almost a zero Ohm in rheostat

mode or zero volt in potentiometer mode. This SD bit

serves the same function as the SHDN pin except it reacts in

active low. The following two bits are O2 and O1. They are

extra programmable logic output that users can make use of

them by driving other digital loads, logic gates, LED

drivers, and analog switches, etc. The 3 LSBs are DON’T

CARE. See Figure 2.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates output voltages at

wiper-to-B and wiper-to-A to be proportional to the input

voltage at A-to-B. Let’s ignore the effect of the wiper resistance

at the moment. For example connecting A–terminal to +5V and

B–terminal to ground produces an output voltage at the wiper-

to-B starting at zero volts up to 1 LSB less than +5V. Each LSB

of voltage is equal to the voltage applied across terminal AB

divided by the 256 position of the potentiometer divider. Since

AD5280/AD5282 can be supplied by dual supplies, the general

equation defining the output voltage at V_Wwith respect to

ground for any given input voltage applied to terminals AB is:

256 − D

V_W(D) =

V_A

V_B

eqn.3

256

3. After acknowledged the Instruction Byte, the last byte in

Write mode is the Data Byte. Data is transmitted over the

serial bus in sequences of nine clock pulses (eight data bits

followed by an “Acknowledge” bit). The transitions on the

SDA line must occur during the low period of SCL and

remain stable during the high period of SCL, Figure 1.

where D is decimal equivalent of the binary code which is

loaded in the 8-bit RDAC register.

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

the rheostat mode, the output voltage is dependent on the ratio

of the internal resistors R_WAand R_WBand not the absolute values,

therefore, the temperature drift reduces to 5ppm/°C.

4. In Read mode, the Data Byte goes right after the

acknowledgment of the Slave Address Byte. Data is

transmitted over the serial bus in sequences of nine clock

pulses (slight difference with the Write mode, there are

eight data bits followed by a “No Acknowledge” bit).

Similarly, the transitions on the SDA line must occur

during the low period of SCL and remain stable during the

high period of SCL.

DIGITAL INTERFACE

2-WIRE SERIAL BUS

The AD5280/AD5282 are controlled via an I²C compatible

serial bus. The RDACs are connected to this bus as slave

devices.

5. When all data bits have been read or written, a STOP

condition is established by the master. A STOP condition is

defined as a low-to-high transition on the SDA line while

SCL is high. In Write mode, the master will pull the SDA

line high during the 10^thclock pulse to establish a STOP

Referring from Figures 2 and 3, the first byte of

AD5280/AD5282 is a Slave Address Byte. It has a 7-bit slave

address and a R/W bit. The 5 MSBs are 01011 and the following

REV PrE 12 MAR 02

Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final

product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com

PRELIMINARY TECHNICAL DATA

AD5280/AD5282

= 3.3V

= 5V

DD2

DD1

condition, Figure 2. In Read mode, the master will issue a

No Acknowledge for the 9^thclock pulse (i.e., the SDA line

remains high). The master will then bring the SDA line low

before the 10^thclock pulse which goes high to establish a

STOP condition, Figure 3.

SDA1

SCL1

SDA2

SCL2

A repeated Write function gives the user flexibility to update the

RDAC output a number of times after addressing and instructing

the part only once. During the Write cycle, each Data byte will

update the RDAC output. For example, after the RDAC has

acknowledged its Slave Address and Instruction Bytes, the

RDAC output will update after these two bytes. If another byte

is written to the RDAC while it is still addressed to a specific

slave device with the same instruction, this byte will update the

output of the selected slave device. If different instructions are

needed, the Write mode has to start with a new Slave Address,

Instruction, and Data Bytes again. Similarly, a repeated Read

function of the RDAC is also allowed.

3.3V

AD5282

PROM

Figure 6. Level Shift for different potential operation.

All digital inputs are protected with a series input resistor and

parallel Zener ESD structures shown in figure 7. Applies to

digital input pins SDA, SCL, and SHDN.

MULTIPLE DEVICES ON ONE BUS

340

Ω

Figure 5 shows four AD5282 devices on the same serial bus.

Each has a different slave address sine the state of their AD0 and

AD1 pins are different. This allows each RDAC within each

device to be written to or read from independently. The master

device output bus line drivers are open-drain pull downs in a

fully I²C compatible interface.

LOGIC

V_SS

Figure 7. ESD Protection of digital pins

A,B,W

+5V

SDA

SCL

Figure 8. ESD Protection of Resistor Terminals

MASTER

VDD

SDA SCL

AD1

SDA SCL

AD1

SDA SCL

AD1

SDA SCL

AD1

AD0

AD5282

Figure 5. Multiple AD5282 Devices on One Bus

LEVEL SHIFT FOR BI-DIRECTIONAL INTERFACE

While most old systems may be operated at one voltage, a new

component may be optimized at another. When two systems

operate the same signal at two different voltages, proper method

of level shifting is needed. For instance, one can use a 3.3V

E²PROM to interface with a 5V digital potentiometer. A level

shift scheme is needed in order to enable a bi-directional

communication so that the setting of the digital potentiometer

can be stored to and retrieved from the E²PROM. Figure 6

shows one of the techniques. M1 and M2 can be N-Ch FETs

2N7002 or low threshold FDV301N if V_DDfalls below 2.5V.

REV PrE 12 MAR 02

Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final

product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com

PRELIMINARY TECHNICAL DATA

AD5280/AD5282

TEST CIRCUITS

Figures 9 to 17 define the test conditions used in product specification

table.

Figure 14. Non-Inverting Gain test circuit

Figure 9. Potentiometer Divider Nonlinearity error test circuit

(INL, DNL)

Figure 15. Gain Vs Frequency test circuit

Figure 10. Resistor Position Nonlinearity Error (Rheostat

Operation; R-INL, R-DNL)

Figure 16. Incremental ON Resistance Test Circuit

Figure 11. Wiper Resistance test Circuit

Figure 17. Common Mode Leakage current test circuit

Figure 12. Power supply sensitivity test circuit (PSS, PSSR)

Figure 13. Inverting Gain test Circuit

REV PrE 12 MAR 02

Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final

product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com

PRELIMINARY TECHNICAL DATA

AD5280/AD5282

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm)

REV PrE 12 MAR 02

Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final

product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com

AD5282 [ADI]

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